Computing unit in alignment Flash memory and array structure

Abstract

The invention discloses an alignment Flash in-memory computing unit and an array structure, and belongs to the technical field of integrated circuits. The counterpoint Flash in-memory computing unit comprises a metal oxide semiconductor (MOS) type gate tube and two Flash type weight tubes, and the MOS type gate tube and the two Flash type weight tubes are sequentially connected in series. In-memory calculation can be realized by applying an in-memory calculation array formed by the alignment Flash in-memory calculation unit. The alignment Flash in-memory computing unit and array obtained by the invention are compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process, wide in weight configuration range, high in reliability, small in area and suitable for a storage and computing integrated architecture circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a bit-aligned Flash in-memory computing unit and an array structure. Background Art

[0002] With the rapid development of technologies such as artificial intelligence (AI), the Internet of Things (IoT), and edge computing, the bottlenecks of traditional computing architecture (von Neumann architecture) are becoming increasingly prominent. In traditional computing systems, data needs to be frequently moved between processors and memory, resulting in high energy consumption, high latency, and low energy efficiency. This problem is particularly severe in data-intensive tasks such as deep learning and real-time signal processing. At the same time, the slowdown of Moore's Law has made it increasingly difficult for technology routes that rely on process technology to increase chip computing power to meet current development needs.

[0003] As an emerging computing paradigm, the "storage-computing-in-one" architecture embeds computing tasks directly into storage units, enabling the fusion of storage and computing, fundamentally resolving the "storage wall" and "power consumption wall" problems. Device technology routes for the "storage-computing-in-one" computing paradigm are divided into volatile (SRAM, DRAM) and non-volatile (RRAM, MRAM, PCM, Flash) memory devices. The former suffers from large computing unit areas, high power consumption, and complex designs. The latter, including new devices like RRAM, MRAM, and PCM, have low process maturity and struggle to meet the demands of large-scale production. Flash devices, on the other hand, offer mature manufacturing processes that are highly compatible with the existing semiconductor industry chain, offering significant advantages in the industrialization of storage-computing-in-one chips. However, building a storage-computing-in-one crossbar array using Flash devices still requires addressing issues such as high integration and highly reliable multi-weight configuration. Summary of the Invention

[0004] The object of the present invention is to provide a Flash in-memory computing unit and an array structure to solve the problems in the background technology.

[0005] To solve the above technical problems, the present invention provides a Flash in-memory computing unit and array structure, comprising:

[0006] 1 MOS type gate tube and the first Flash type weight tube and the second Flash type weight tube;

[0007] The drain end of the MOS type gate tube is connected to the bit line, the source end is connected to the drain end of the first Flash type weight tube, the source end of the first Flash type weight tube is connected to the drain end of the second Flash type weight tube, and the source end of the second Flash type weight tube is connected to the source line;

[0008] The gate end of the MOS type gate tube is connected to the selection gate word line, the gate end of the first Flash type weight tube is connected to the first control gate word line, and the gate end of the second Flash type weight tube is connected to the second control gate word line. The selection gate word line, the first control gate word line, and the second control gate word line are independently controlled and applied with different potentials.

[0009] In one embodiment, when the first Flash type weight tube is programmed, a voltage is applied to the selection gate word line to turn on the MOS type selection tube, an over-control voltage is applied to the second control gate word line to turn on the second Flash type weight tube, a voltage is applied to the bit line, and a band-to-band tunneling method at the drain end is used to charge the floating gate polycrystalline layer of the first Flash type weight tube.

[0010] In one embodiment, when the first Flash type weight tube performs a read operation, a voltage is applied to the selection gate word line to turn on the MOS type selection tube, an over-control voltage is applied to the second control gate word line to turn on the second Flash type weight tube, voltages are applied to the bit line and source line respectively, and current is read from the source line to obtain the conductance state of the first Flash type weight tube, which is the weight.

[0011] In one embodiment, the second control gate word line super-control voltage for opening the second Flash type weight tube needs to be greater than the maximum threshold voltage of the second Flash type weight tube. Regardless of whether the floating gate polycrystalline layer of the second Flash type weight tube is charged with charge, the second Flash type weight tube remains open.

[0012] In one embodiment, when the second Flash type weight tube performs a programming operation, a voltage is applied to the selection gate word line to turn on the MOS type selection tube, an over-control voltage is applied to the first control gate word line to turn on the first Flash type weight tube, a voltage is applied to the bit line, and the floating gate polycrystalline layer of the second Flash type weight tube is charged using a band-to-band tunneling method at the drain end.

[0013] In one embodiment, when the second Flash type weight tube performs a read operation, a voltage is applied to the selection gate word line to turn on the MOS type selection tube, an over-control voltage is applied to the first control gate word line to turn on the first Flash type weight tube, voltages are applied to the bit line and source line respectively, and current is read from the source line to obtain the conductance state of the second Flash type weight tube, which is the weight.

[0014] In one embodiment, the super-control voltage of the first control gate word line for opening the first Flash type weight tube needs to be greater than the maximum threshold voltage of the first Flash type weight tube. Regardless of whether the floating gate polycrystalline layer of the first Flash type weight tube is charged with charge, the first Flash type weight tube remains open.

[0015] In one embodiment, when the first Flash-type weight transistor and the second Flash-type weight transistor perform an erase operation, a source-end FN tunneling method or a full-channel uniform FN tunneling method is used to simultaneously remove charges on the floating gate polycrystalline layer.

[0016] In one embodiment, the MOS-type gate tube is a p-channel MOS tube or an n-channel MOS tube, and the two Flash-type weight tubes are p-channel Flash tubes or n-channel Flash tubes; the MOS-type gate tube and the two Flash-type weight tubes are both p-channel MOS tubes or both n-channel MOS tubes.

[0017] The present invention also provides an array structure based on the above-mentioned aligned Flash in-memory computing unit, the aligned Flash in-memory computing array structure includes n rows of aligned Flash in-memory computing units and m columns of aligned Flash in-memory computing units, wherein m and n are positive integers with a minimum value of 1;

[0018] The gate end of the MOS-type gate transistor in the i-th row is connected in series to the selection gate word line in the i-th row, the control gate of the first Flash-type weight transistor in the i-th row is connected in series to the first control gate word line in the i-th row, the control gate of the second Flash-type weight transistor in the i-th row is connected in series to the second control gate word line in the i-th row, the source end of the second Flash-type weight transistor in the i-th row is connected in series to the source line in the i-th row, the source line in the i-th row is connected to the multiplexer in the i-th row, and the positive source line and the negative source line output by the multiplexer in the i-th row are output to the output port after passing through the difference circuit in the i-th row;

[0019] The drain end of the MOS type gate transistor in the jth column is connected in series to the bit line in the jth column; wherein, i is a positive integer not greater than m, and j is a positive integer not greater than n.

[0020] In one embodiment, the current read out from the source line of the i-th row in the in-memory calculation array structure of the Flash memory is decoded and selected by the multiplexer of the i-th row to complete the two-step current reading:

[0021] Step 1: Add the readout currents of the first Flash-type weight transistors of the Flash memory calculation units in the i-th row, output them to the positive source line of the i-th row, and store the charges in the first storage capacitors of the i-th row;

[0022] Step 2: sum the currents read out of the second Flash-type weight transistors of the Flash memory calculation units in the i-th row, output them to the negative source line of the i-th row, and store the charges in the second storage capacitors in the i-th row;

[0023] After the two-step current reading, the current on the positive source line and the negative source line in the i-th row are subtracted through the difference circuit in the i-th row and output to the output port in the i-th row.

[0024] The present invention provides a pair of Flash in-memory computing units and an array structure. Subtracting the weights of the pair of Flash in-memory computing units helps further improve the weight configuration range of the in-memory computing units. A BTBT (Band-to-band tunneling) programming method with high electron injection efficiency can effectively increase the programming rate. Furthermore, compared with CHHE (Channel hot-hole induced hot-electron injection) and FN (Fowler-Nordheim) programming methods, the BTBT programming method can reduce damage to the tunnel oxide layer of the Flash device during programming operations, thereby improving the reliability and service life of the in-memory computing device structure. A MOS-type gate transistor can resolve the problem of weight configuration interference of the Flash units in the in-memory computing array, enhancing the configuration reliability of the Flash array. Controlling the switching of the pair of Flash in-memory computing units through a single MOS-type gate transistor helps reduce the area of ​​the in-memory computing array. The in-memory calculation unit and array obtained by the present invention are compatible with CMOS technology, have a wide range of weight configuration, high reliability, and a small area, and are suitable for storage and calculation integrated architecture circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the structure of the in-memory calculation unit of the Flash provided by the present invention;

[0026] Figure 2 A schematic diagram of the programming operation of the in-memory calculation unit of the Flash memory provided by the present invention;

[0027] Figure 3 A schematic diagram of the erase operation of the in-memory calculation unit of the Flash provided by the present invention;

[0028] Figure 4 A schematic diagram of the transfer characteristic curve of the Flash-type weight tube during charging and discharging on the floating gate polycrystalline layer of the in-place Flash memory computing unit provided by the present invention;

[0029] Figure 5 A schematic diagram of the read operation of the in-memory calculation unit of the Flash provided by the present invention;

[0030] Figure 6 This is a schematic diagram of the in-memory calculation array structure of the aligned Flash provided by the present invention. DETAILED DESCRIPTION

[0031] The following is a detailed description of the in-memory Flash computing unit and array structure proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0032] The present invention provides a bit-aligned Flash in-memory computing unit, comprising a MOS-type gating tube T1 and two Flash-type weight tubes (i.e., a first Flash-type weight tube T2 and a second Flash-type weight tube T3).

[0033] In the present invention, the MOS type gate tube is described using a p-channel MOS tube as a typical example. The MOS type gate tube in the present invention can also be selected but not limited to an n-channel MOS tube to achieve the same effect and purpose; in the present invention, the two Flash type weight tubes are described using a p-channel Flash tube as a typical example. The two Flash type weight tubes in the present invention can also be selected but not limited to an n-channel Flash tube to achieve the same effect and purpose.

[0034] like Figure 1 As shown, the drain end of the MOS type gate tube T1 is connected to the bit line BL, the source end is connected to the drain end of the first Flash type weight tube T2, the source end of the first Flash type weight tube T2 is connected to the drain end of the second Flash type weight tube T3, and the source end of the second Flash type weight tube T3 is connected to the source line SL, that is, the MOS type gate tube T1, the first Flash type weight tube T2 and the second Flash type weight tube T3 are in a series relationship.

[0035] The gate end of the MOS-type gate tube T1 is connected to the selection gate word line sgWL, the gate end of the first Flash-type weight tube T2 is connected to the first control gate word line cgWLP, and the gate end of the second Flash-type weight tube T3 is connected to the second control gate word line cgWLN; the selection gate word line sgWL, the first control gate word line cgWLP, and the second control gate word line cgWLN can be independently controlled and applied with different potentials.

[0036] like Figure 2As shown, when the programming operation is performed on the first Flash type weight tube T2, a voltage is applied to the selection gate word line sgWL to turn on the MOS type selection tube T1, an over-control voltage is applied to the second control gate word line cgWLN to turn on the second Flash type weight tube T3, a voltage is applied to the bit line BL, and the floating gate polycrystalline layer of the first Flash type weight tube T2 is charged with charge using the BTBT method at the drain end, wherein the over-control voltage of the second control gate word line cgWLN that turns on the second Flash type weight tube T3 needs to be greater than the maximum threshold voltage of the second Flash type weight tube T3. Regardless of whether the floating gate polycrystalline layer of the second Flash type weight tube T3 is charged with charge, the second Flash type weight tube T3 remains turned on. At the same time, the over-control voltage cannot be too large, and should be less than half of the erase voltage applied to the second control gate word line cgWLN when the second Flash type weight tube T3 is erased, so as to prevent the second Flash type weight tube T3 from being erased due to FN tunneling.

[0037] When programming the second Flash type weight tube T3, a voltage is applied to the selection gate word line sgWL to turn on the MOS type selection tube T1, an over-control voltage is applied to the first control gate word line cgWLP to turn on the first Flash type weight tube T2, a voltage is applied to the bit line BL, and the floating gate polycrystalline layer of the second Flash type weight tube T3 is charged with charge using the BTBT method at the drain end, wherein the over-control voltage of the first control gate word line cgWLP that turns on the first Flash type weight tube T2 needs to be greater than the maximum threshold voltage of the first Flash type weight tube T2. Regardless of whether the floating gate polycrystalline layer of the first Flash type weight tube T2 is charged, the first Flash type weight tube T2 remains turned on. At the same time, the over-control voltage cannot be too large, and should be less than half of the erase voltage applied to the first control gate word line cgWLP when performing an erase operation on the first Flash type weight tube T2, so as to prevent the first Flash type weight tube T2 from being erased due to FN tunneling.

[0038] like Figure 3 As shown, when the first Flash type weight transistor T2 and the second Flash type weight transistor T3 are erased, the charge on the floating gate polycrystalline layer is removed simultaneously by using the source end FN tunneling method or the full channel uniform FN tunneling method.

[0039] Through the above-mentioned programming and erasing operations on the first Flash type weight tube T2 and the second Flash type weight tube T3, the conductance state (i.e., weight) of the first Flash type weight tube T2 and the second Flash type weight tube T3 can be controlled respectively. That is, when the floating gate polycrystalline layer of the first Flash type weight tube T2 or the second Flash type weight tube T3 is charged with electrons, the transfer characteristic curve of the first Flash type weight tube T2 or the second Flash type weight tube T3 is as follows: Figure 4As shown, when the potential of the first control gate word line cgWLP or the second control gate word line cgWLN is 0V, the change in the amount of charge charged on the floating gate polycrystalline layer of the first Flash type weight tube T2 or the second Flash type weight tube T3 causes the conductance state of the second Flash type weight tube T3 to change; when the electrons in the floating gate polycrystalline layer of the first Flash type weight tube T2 or the second Flash type weight tube T3 are completely removed, the transfer characteristic curve of the first Flash type weight tube T2 or the second Flash type weight tube T3 is as shown in FIG. Figure 4 As shown, when the potential of the first control gate word line cgWLP or the second control gate word line cgWLN is 0V, the first Flash type weight transistor T2 or the second Flash type weight transistor T3 is in the off state.

[0040] like Figure 5 As shown, when the first Flash type weight transistor T2 is read, a voltage is applied to the selection gate word line sgWL to turn on the MOS type gate transistor T1, an over-control voltage is applied to the second control gate word line cgWLN to turn on the second Flash type weight transistor T3, voltages are applied to the bit line BL and the source line SL respectively, and the current is read from the source line SL to obtain the conductance state (i.e., weight) of the first Flash type weight transistor T2, wherein the over-control voltage of the second control gate word line cgWLN that turns on the second Flash type weight transistor T3 is within the same range as the aforementioned programming operation;

[0041] When performing a read operation on the second Flash type weight tube T3, a voltage is applied to the selection gate word line sgWL to turn on the MOS type selection tube T1, and an over-control voltage is applied to the first control gate word line cgWLP to turn on the first Flash type weight tube T2. Voltages are applied to the bit line BL and the source line SL respectively, and the current is read from the source line SL to obtain the conductivity state (i.e., weight) of the second Flash type weight tube T3. The over-control voltage of the first control gate word line cgWLP that turns on the first Flash type weight tube T2 is the same as the range requirements during the aforementioned programming operation.

[0042] The present invention also provides a Flash in-memory computing array structure, the array structure is as follows Figure 6 As shown, it includes n rows of aligned Flash in-memory computing units and m columns of aligned Flash in-memory computing units, where m and n are positive integers with a minimum value of 1.

[0043] According to the above-mentioned programming operation of the in-place Flash memory computing unit, the weight configuration of any in-place Flash memory computing unit in the in-place Flash memory computing array can be completed, so that the conductance of the first Flash type weight tube or the second Flash type weight tube reaches the target value; according to the above-mentioned reading operation of the in-place Flash memory computing unit, the weight reading of any in-place Flash memory computing unit in the in-place Flash memory computing array can be completed.

[0044] The gate end of the MOS type gate transistor T1 in the i-th row is connected in series to the selection gate word line sgWL in the i-th row. The control gate of the first Flash weight transistor T2 in the i-th row is connected in series to the first control gate word line cgWLP in the i-th row. The control gate of the second Flash weight transistor T3 in the i-th row is connected in series to the second control gate word line cgWLN in the i-th row. The source end of the second Flash weight transistor T3 in the i-th row is connected in series to the source line SL in the i-th row. , the source line SL of the i-th row Multiplexer MP connected to row i , the multiplexer MP of row i Output positive power line SLP and negative source line SLN The difference circuit DC in row i Then output to the output port OUT ;

[0045] The drain end of the MOS type gate transistor T1 in the jth column is connected in series to the bit line BL in the jth column. <j>.

[0046] According to the above programming operation, the weight configuration of any aligned Flash in-memory computing unit in the aligned Flash in-memory computing array can be completed. Taking the aligned Flash in-memory computing unit 110 in the first row and the first column as an example:

[0047] The select gate word line sgWL in row 1 <1> Apply voltage to open the MOS gate tube 111, and the second control gate word line cgWLN in the first row <1> Applying an over-control voltage to turn on the second Flash weight transistor 113, the bit line BL in the first column <1> A voltage is applied to the floating gate polycrystalline layer of the first Flash type weight tube 112 by using the BTBT method at the drain end until the conductance of the first Flash type weight tube 112 reaches the target value, wherein the second control gate word line cgWLN that turns on the second Flash type weight tube 113 is turned on. <1> The over-control voltage is the same as the range requirements during the above programming operation;

[0048] The select gate word line sgWL in row 1 <1> Apply voltage to open the MOS gate transistor 111, and the first control gate word line cgWLP in the first row <1> Applying an over-control voltage to turn on the first Flash weight transistor 112, the bit line BL in the first column <1> A voltage is applied to the floating gate polycrystalline layer of the second Flash type weight tube 113 by using the BTBT method at the drain end until the conductance of the second Flash type weight tube 113 reaches the target value, wherein the first control gate word line cgWLP that turns on the first Flash type weight tube 112 is turned on. <1> The over-control voltage is the same as the range requirements during the above programming operation.

[0049] According to the above read operation, the weight reading of any one of the aligned Flash memory calculation units in the aligned Flash memory calculation array can be completed. Taking the aligned Flash memory calculation unit 110 in the first row and the first column as an example:

[0050] The select gate word line sgWL in row 1 <1> Apply voltage to open the MOS gate tube 111, and the second control gate word line cgWLN in the first row <1> Applying an over-control voltage to turn on the second Flash weight transistor 113, the bit line BL in the first column <1> and the source line SL of row 1 <1> Voltage is applied to the source line SL in row 1. <1> Read the current to obtain the conductance state (ie, weight) of the first Flash type weight tube 112, wherein the second control gate word line cgWLN that turns on the second Flash type weight tube 113 is <1> The over-control voltage is the same as the range requirements during the above programming operation;

[0051] The select gate word line sgWL in row 1 <1> Apply voltage to open the MOS gate transistor T1, and the first control gate word line cgWLP in row 1 <1> Applying an over-control voltage to turn on the first Flash weight transistor 112, the first bit line BL <1> and the source line SL of row 1 <1> Voltage is applied to the source line SL in row 1. <1> Read the current to obtain the conductance state (ie, weight) of the second Flash type weight tube 113, wherein the first control gate word line cgWLP that turns on the first Flash type weight tube 112 is <1> The over-control voltage is the same as the range requirements during the above programming operation.

[0052] Source line SL of row i The read current passes through the multiplexer MP of row i Perform decoding selection and complete two-step current reading;

[0053] The first step is to sum the read currents of the first Flash type weight tube T2 of the calculation unit in the Flash memory of the i-th row and output it to the positive source line SLP of the i-th row. and stores the charge in the first storage capacitor CP of the i-th row middle;

[0054] The second step is to add the read current of the second Flash type weight tube T3 of the calculation unit in the Flash memory of the i-th row and output it to the negative source line SLN of the i-th row. and stores the charge in the second storage capacitor CN of the i-th row middle;

[0055] After the two-step current reading, the difference circuit DC of the i-th row The positive source line SLP of row i and negative source line SLN The current on the ith row is subtracted and output to the output port OUT of the ith row. .

[0056] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims. < / j>

Claims

1. A Flash in-memory computing unit, characterized in that: include: 1 MOS type gate tube and the first Flash type weight tube and the second Flash type weight tube; The drain end of the MOS type gate tube is connected to the bit line, the source end is connected to the drain end of the first Flash type weight tube, the source end of the first Flash type weight tube is connected to the drain end of the second Flash type weight tube, and the source end of the second Flash type weight tube is connected to the source line; The gate end of the MOS type gate tube is connected to the selection gate word line, the gate end of the first Flash type weight tube is connected to the first control gate word line, and the gate end of the second Flash type weight tube is connected to the second control gate word line. The selection gate word line, the first control gate word line, and the second control gate word line are independently controlled and applied with different potentials.

2. The in-memory calculation unit for Flash memory according to claim 1, wherein: When the first Flash type weight tube is programmed, a voltage is applied to the selection gate word line to turn on the MOS type selection tube, an over-control voltage is applied to the second control gate word line to turn on the second Flash type weight tube, a voltage is applied to the bit line, and the band-to-band tunneling method at the drain end is used to charge the floating gate polycrystalline layer of the first Flash type weight tube.

3. The in-memory calculation unit for Flash memory according to claim 1, wherein: When the first Flash type weight tube performs a read operation, a voltage is applied to the selection gate word line to turn on the MOS type selection tube, an over-control voltage is applied to the second control gate word line to turn on the second Flash type weight tube, voltages are applied to the bit line and source line respectively, and current is read from the source line to obtain the conductivity state of the first Flash type weight tube, which is the weight.

4. The in-memory calculation unit for Flash memory according to claim 2 or 3, wherein: The second control gate word line super-control voltage of the second Flash type weight tube to open must be greater than the maximum threshold voltage of the second Flash type weight tube. Regardless of whether the floating gate polycrystalline layer of the second Flash type weight tube is charged with charge, the second Flash type weight tube remains open.

5. The in-memory calculation unit for Flash memory according to claim 1, wherein: When the second Flash type weight tube is programmed, a voltage is applied to the selection gate word line to turn on the MOS type selection tube, an over-control voltage is applied to the first control gate word line to turn on the first Flash type weight tube, a voltage is applied to the bit line, and the band-to-band tunneling method at the drain end is used to charge the floating gate polycrystalline layer of the second Flash type weight tube.

6. The in-memory calculation unit for Flash memory according to claim 1, wherein: When the second Flash type weight tube performs a read operation, a voltage is applied to the selection gate word line to open the MOS type selection tube, an over-control voltage is applied to the first control gate word line to open the first Flash type weight tube, and voltages are applied to the bit line and source line respectively. The current is read from the source line to obtain the conductance state of the second Flash type weight tube, which is the weight.

7. The in-memory Flash computing unit according to claim 5 or 6, wherein: The first control gate word line super-control voltage for opening the first Flash type weight tube needs to be greater than the maximum threshold voltage of the first Flash type weight tube. Regardless of whether the floating gate polycrystalline layer of the first Flash type weight tube is charged with charge, the first Flash type weight tube remains open.

8. The in-memory calculation unit for Flash memory according to claim 1, wherein: When the first Flash type weight tube and the second Flash type weight tube perform an erase operation, a source-end FN tunneling method or a full-channel uniform FN tunneling method is adopted to simultaneously remove the charge on the floating gate polycrystalline layer.

9. The in-memory calculation unit for Flash memory according to claim 1, wherein: The MOS type gate tube is a p-channel MOS tube or an n-channel MOS tube, and the two Flash type weight tubes are p-channel Flash tubes or n-channel Flash tubes; the MOS type gate tube and the two Flash type weight tubes are both p-channel MOS tubes or both n-channel MOS tubes.

10. An array structure of the aligned Flash in-memory computing unit according to any one of claims 1 to 9, characterized in that: The in-place Flash memory calculation array structure includes n rows of in-place Flash memory calculation units and m columns of in-place Flash memory calculation units, where m and n are positive integers with a minimum value of 1; The gate end of the MOS-type gate transistor in the i-th row is connected in series to the selection gate word line in the i-th row, the control gate of the first Flash-type weight transistor in the i-th row is connected in series to the first control gate word line in the i-th row, the control gate of the second Flash-type weight transistor in the i-th row is connected in series to the second control gate word line in the i-th row, the source end of the second Flash-type weight transistor in the i-th row is connected in series to the source line in the i-th row, the source line in the i-th row is connected to the multiplexer in the i-th row, and the positive source line and the negative source line output by the multiplexer in the i-th row are output to the output port after passing through the difference circuit in the i-th row; The drain end of the MOS type gate transistor in the jth column is connected in series to the bit line in the jth column; wherein, i is a positive integer not greater than m, and j is a positive integer not greater than n.

11. The in-memory calculation unit for Flash memory according to claim 10, wherein: The current read out from the source line in the i-th row of the in-bit Flash memory calculation array structure is decoded and selected by the multiplexer in the i-th row, completing a two-step current reading: Step 1: Add the readout currents of the first Flash-type weight transistors of the Flash memory calculation units in the i-th row, output them to the positive source line of the i-th row, and store the charges in the first storage capacitors of the i-th row; Step 2: sum the currents read out of the second Flash-type weight transistors of the Flash memory calculation units in the i-th row, output them to the negative source line of the i-th row, and store the charges in the second storage capacitors in the i-th row; After the two-step current reading, the current on the positive source line and the negative source line in the i-th row are subtracted through the difference circuit in the i-th row and output to the output port in the i-th row.

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