A control method of a phase change memory and a phase change memory

Abstract

This application proposes a control method for a phase-change memory (PCM) and a PCM itself. The method includes: obtaining the number of memory cells; and, if the number of memory cells is less than a threshold value, performing a first reset operation on a first target memory cell among the multiple memory cells. The first reset operation includes: applying a first word line voltage to a first word line coupled to the first target memory cell during a first time period, and applying a first word line voltage and a first current to the first bit line coupled to the first target memory cell; applying a second word line voltage to the first word line during a second time period, and applying a first word line voltage and a first current to the first bit line, wherein the second word line voltage is greater than the first word line voltage; and applying the second word line voltage to the first word line during a third time period, and applying a first word line voltage and a second current to the first bit line, wherein the second current is greater than the first current. This method can reduce overcharge current in the PCM.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a control method for a phase-change memory and a phase-change memory. Background Technology

[0002] Phase-change memory includes a memory cell array, which comprises multiple memory cells arranged in an array. In the prior art, when resetting a target memory cell in the memory cell array, it is generally divided into two stages. In the first stage, a small word line voltage is applied, and in the second stage, both the word line voltage and the current on the bit line are increased simultaneously. Because the word line voltage and the current on the bit line increase simultaneously, it can lead to excessive overcharge current.

[0003] Overcharging current can lead to excessive heat, which in turn causes thermal crosstalk in the memory cell array, affecting the state of memory cells near the target memory cell. It can also reduce the cycling characteristics of the target memory cell, causing it to fail faster.

[0004] Therefore, excessive overcharging current in phase-change memory is one of the problems that urgently needs to be solved. Summary of the Invention

[0005] This application proposes a control method for phase-change memory and a phase-change memory to solve the technical problem of excessive overcharge current in existing phase-change memories.

[0006] In a first aspect, embodiments of this application propose a control method for a phase-change memory, wherein the memory cell array includes multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and the multiple word lines, the method comprising:

[0007] Obtain the number of the storage units;

[0008] When the number of storage cells is less than a number threshold, a first reset operation is performed on the first target storage cell among the plurality of storage cells. The first reset operation includes: applying a first word line voltage to the first word line coupled to the first target storage cell in a first time period, and applying a first word line voltage and a first current to the first bit line coupled to the first target storage cell.

[0009] During the second time period, a second word line voltage is applied to the first word line, and the first bit line is applied with the first bit line voltage and the first current, wherein the second word line voltage is greater than the first word line voltage;

[0010] During the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and a second current are applied to the first bit line, wherein the second current is greater than the first current.

[0011] In some embodiments, the method further includes:

[0012] When the number of storage cells is greater than or equal to a number threshold, a second reset operation is performed on the first target storage cell among the plurality of storage cells. The second reset operation includes: during the first time period, applying a first word line voltage to the first word line, applying a second bit line voltage and the first current to the first bit line, wherein the second bit line voltage is greater than the first bit line voltage.

[0013] During the second time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line;

[0014] If it is determined that the first target memory cell is in a non-conducting state during the second time period, in the third time period, a third word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line to adjust the first target memory cell to a conducting state, wherein the third word line voltage is greater than the second word line voltage.

[0015] In some embodiments, after applying the second word line voltage to the first word line, applying the first bit line voltage to the first bit line, and applying the first current, the method further includes:

[0016] If it is determined that the first target memory cell is in the on state during the second time period, during the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

[0017] In some embodiments, the method further includes:

[0018] When the number of storage cells is greater than or equal to a number threshold, a third reset operation is performed on the first target storage cell among the plurality of storage cells. The third reset operation includes: applying a first word line voltage to the first word line, applying a second bit line voltage and the first current to the first bit line during the first time period.

[0019] If it is determined that the first target storage cell is in the on state during the first time period, it is detected whether the line resistance of the first target storage cell is greater than the resistance threshold.

[0020] If it is determined that the line resistance of the first target memory cell is greater than the resistance threshold, during the second time period, a third word line voltage or a second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line.

[0021] During the third time period, the third word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

[0022] In some embodiments, after detecting whether the line resistance of the first target memory cell is greater than a resistance threshold, the method further includes:

[0023] If it is determined that the line resistance of the first target memory cell is less than or equal to the resistance threshold, during the second time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line.

[0024] During the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

[0025] In some embodiments, after detecting whether the line resistance of the first target memory cell is greater than a resistance threshold, the method further includes:

[0026] If the line resistance of the first target memory cell is determined to be greater than the resistance threshold, a memory cell connected in series with the first target memory cell on the first word line is determined as the second target memory cell.

[0027] When the third word line voltage is applied to the first word line, a bias voltage is applied to the second bit line coupled to the second target memory cell.

[0028] In some embodiments, after applying the first word line voltage to the first word line, applying the second bit line voltage to the first bit line, and applying the first current, the method further includes:

[0029] If it is determined that the first target memory cell is in a non-conducting state during the first time period, the voltage applied to the first word line is set to 0, and the voltage and current applied to the first bit line are set to 0.

[0030] In some embodiments, the range of the first word line voltage Vp1 is 0V < Vp1 ≤ 4V.

[0031] In some embodiments, the range of the first current I1 is 20A≤I1≤80A.

[0032] Secondly, embodiments of this application propose a phase-change memory, comprising:

[0033] A memory cell array includes multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and the multiple word lines;

[0034] The peripheral circuitry coupled to the memory cell array is configured to control the memory cell array using the method described in any of the above embodiments.

[0035] The technical solution of this application can achieve the following beneficial effects: Based on the phase-change memory control method proposed in the embodiments of this application, only the voltage of the first word line is changed in the second time period while the first current is maintained, and only the current of the first word line is changed in the third time period while the voltage of the second word line is maintained. That is, the voltage and current are increased separately in different time periods, rather than the voltage and current are increased synchronously. Therefore, the overcharge current from the second time period to the third time period is suppressed. Furthermore, applying a small first current to the first word line in the first time period and increasing the voltage from the first word line voltage to the second word line voltage under the condition of a small first current can also suppress the overcharge current. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0037] Figure 1 A schematic flowchart illustrating a control method for a phase-change memory provided in an embodiment of this application;

[0038] Figure 2 A schematic diagram of a phase-change memory provided for an embodiment of this application;

[0039] Figure 3 A partial structural schematic diagram of a phase-change memory provided for an embodiment of this application;

[0040] Figure 4 A timing diagram of current and voltage provided for an embodiment of this application;

[0041] Figure 5 A timing diagram of current and voltage provided for an embodiment of this application;

[0042] Figure 6 A timing diagram of current and voltage provided for an embodiment of this application;

[0043] Figure 7 A timing diagram of current and voltage provided for an embodiment of this application;

[0044] Figure 8A timing diagram of current and voltage provided for an embodiment of this application;

[0045] Figure 9 A timing diagram of current and voltage provided for an embodiment of this application;

[0046] Figure 10 A timing diagram of current and voltage provided for an embodiment of this application;

[0047] Figure 11 A timing diagram of current and voltage in a simulation experiment is provided for an embodiment of this application;

[0048] Figure 12 This is a timing diagram of current and voltage in the prior art;

[0049] Figure 13 This is a timing diagram of current and voltage in the prior art. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0051] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document, unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0052] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0053] Phase-change memory (PCM) includes a memory cell array, which comprises multiple memory cells arranged in an array. In the prior art, there are two methods for resetting a target memory cell in the memory cell array. Method one can be found in [reference needed]. Figure 12 As shown, the process is divided into two stages. In the first stage, a small word line voltage is applied along with a relatively large bit line current. In the second stage, the word line voltage is increased while maintaining a relatively large bit line current. A large overcharge current will be generated at the moment the word line voltage suddenly increases. Method two can be found in [reference needed]. Figure 13 As shown, the process is divided into two stages. In the first stage, a small word line voltage and a small bit line current are applied. In the second stage, both the word line voltage and bit line current are increased simultaneously. This simultaneous increase in word line voltage and bit line current leads to a larger overcharge current. The large overcharge current causes excessive heat, which in turn causes thermal crosstalk in the memory cell array, affecting the state of memory cells near the target memory cell. It also reduces the cycling characteristics of the target memory cell, causing it to fail more quickly.

[0054] To address the technical problem of large overcharge current generated during the reset process of existing phase-change memory, this application proposes a control method and a phase-change memory to overcome the above-mentioned problem.

[0055] The following description, in conjunction with the accompanying drawings, introduces a control method for a phase-change memory and the phase-change memory provided in this application.

[0056] See Figure 1 As shown in the figure, this application proposes a control method for a phase-change memory. The phase-change memory includes a memory cell array, which includes multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and the multiple word lines. The method includes:

[0057] S101: Obtain the number of the storage units;

[0058] When the number of storage cells is less than a threshold, a first reset operation is performed on a first target storage cell among the plurality of storage cells. The first reset operation includes:

[0059] S102: In the first time period, a first word line voltage is applied to the first word line coupled to the first target memory cell, and a first word line voltage and a first current are applied to the first bit line coupled to the first target memory cell.

[0060] S103: In the second time period, a second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line, wherein the second word line voltage is greater than the first word line voltage;

[0061] S104: During the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and a second current are applied to the first bit line, wherein the second current is greater than the first current.

[0062] The phase-change memory and its control method will be described below with reference to the accompanying drawings.

[0063] Please refer to Figure 2 The phase-change memory (PCM) includes a memory cell array, which includes multiple bit lines, multiple word lines, and multiple memory cells located between the bit lines and word lines. The PCM also includes peripheral circuitry coupled to the memory cell array. The memory cell array further includes bit line power supply terminals and word line power supply terminals, with the bit line power supply terminals coupled to the multiple bit lines and the word line power supply terminals coupled to the multiple word lines.

[0064] The storage unit includes a phase-change storage unit; the phase-change storage unit includes a phase-change element and a gating element connected in series with the phase-change element. The phase-change element includes a phase-change material (PCM) cell. The gating element includes a material with bidirectional threshold switch (OTS) properties.

[0065] The voltage across a memory cell is equal to the voltage across the word line minus the voltage across the bit line. Current can be applied to the memory cell through the bit line. If the phase-change element is crystalline (low-resistance state), the memory cell has a first threshold voltage (a smaller value). When the voltage across the memory cell is greater than the first threshold voltage, the selection element is turned on, and the memory cell as a whole exhibits a low-resistance state. If the phase-change element is amorphous (high-resistance state), the memory cell has a second threshold voltage (a larger value), which is greater than the first threshold voltage. When the voltage across the memory cell is greater than the second threshold voltage, the selection element is turned on.

[0066] The phase-change element (PCE) transitions from a high-resistivity amorphous state to a low-resistivity crystalline state; this process is called a set operation. Before the set operation, a suitable voltage needs to be applied to activate the gating element in the memory cell. If the PCE is amorphous, the applied voltage must be greater than a second voltage threshold. After the gating element is activated, the voltage and current across the memory cell are adjusted to meet the conditions for the set operation.

[0067] The phase-change element (PCE) transitions from a low-resistance crystalline state to a high-resistance amorphous state; this process is called a reset operation. Before the reset operation, a suitable voltage needs to be applied to turn on the gating element in the memory cell. If the PCE is crystalline, the applied voltage must be greater than a first voltage threshold. After the gating element turns on, the voltage and current across the memory cell are adjusted to meet the conditions for the reset operation.

[0068] WL1, WL2, WL3, and WL4 represent four different word lines, and BL1, BL2, BL3, and BL4 represent four different bit lines. The connection points between the word lines and bit lines are connected in series with memory cells. One memory cell is selected from the multiple memory cells as the first target memory cell. The word line coupled to the first target memory cell is designated as the first word line (WL2 in this embodiment), and the bit line coupled to the first target memory cell is designated as the first bit line (BL2 in this embodiment). The voltage applied to the first word line is denoted as the word line voltage Vp, which includes: the first word line voltage Vp1, the second word line voltage Vp2, and the third word line voltage Vp3. The voltage applied to the first bit line is denoted as the bit line voltage Vn, which includes: the first bit line voltage Vn1 and the second bit line voltage Vn2. The voltage across the first target memory cell is equal to Vp - Vn. A portion of the memory cells and the first target memory cell are connected in series on the first bit line. This portion of the memory cells is denoted as the second target memory cell, and the bit lines coupled to the second target memory cell are denoted as the second bit lines (BL1, BL3, and BL4 in this embodiment). The voltage applied to the second bit lines is denoted as the bias voltage Vbias. The voltage across the second target memory cell is equal to Vp - Vbias.

[0069] Please refer to Figure 3A word line voltage Vp can be applied to the first word line through the first transistor Q1 and the second transistor Q2. The third transistor Q3 acts as a switch, and its on / off state can be controlled by an external circuit (not shown). The fourth transistor Q4 acts as a switch to control the on / off state of the first current source A1. The fifth transistor Q5 acts as a switch to control the on / off state of the second current source A2. The first current source A1 and the second current source A2 are current mirror structures. A bit line voltage Vn can be applied to the first bit line through the fourth transistor Q4 and the fifth transistor Q5. The fourth transistor Q4 is connected to the first current source A1, and the fifth transistor Q5 is connected to the second current source A2. The first current source A1 and the second current source A2 can apply current to the first target memory cell through the first bit line. Specifically, the first word line voltage is applied through the first transistor Q1, the second word line voltage is applied through the second transistor Q2, the first bit line voltage is applied through the fourth transistor Q4, the second bit line voltage is applied through the fifth transistor Q5, the first current is applied through the first current source A1, and the second current is applied through the second current source A2. It should be noted that this embodiment uses two current sources (first current source A1 and second current source A2) as an example for illustrative purposes. Other numbers of current sources can be provided as needed. This application does not limit the specific number of current sources. Multiple current sources connected in parallel can apply different current values ​​to the first target memory cell by controlling the on / off state of different current sources. This embodiment also uses two transistors (first transistor Q1 and second transistor Q2) connected to the word line power supply terminal as an example for illustrative purposes. Other numbers of transistors can be connected to the word line power supply terminal as needed. This application does not limit the specific number of transistors. By controlling the on / off state of the transistors connected to the word line power supply terminal, different word line voltages can be applied to the first target memory cell. Other circuit elements with switching functions (e.g., microswitches, thyristors) can also be used to replace transistors Q1 to Q5.

[0070] Please refer to Figure 1 and Figure 2 Execute step S101 to obtain the number of storage units.

[0071] After obtaining the number of storage cells, it is checked whether the number of storage cells is less than a quantity threshold. If the number of storage cells is less than the quantity threshold, a first reset operation is performed on the first target storage cell among the plurality of storage cells. If the number of storage cells is greater than or equal to the quantity threshold, a second reset operation or a third reset operation is performed on the first target storage cell among the plurality of storage cells. The quantity threshold can be 30Gb.

[0072] When the number of storage cells is less than the number threshold, it indicates that the scale of the storage cell array is small and the physical location difference between each storage cell is small. Due to the small difference in physical location, the characteristics of each storage cell are similar, which is reflected in the small difference in the voltage threshold of each storage cell (the threshold voltage includes: the first voltage threshold, the second voltage threshold, and the voltage threshold that satisfies the reset operation). Therefore, when the number of storage cells is less than the number threshold, the distribution range of the voltage threshold of the storage cell array is small, which is suitable for the first reset operation with a simple control method.

[0073] When the number of storage cells is greater than or equal to the number threshold, it indicates that the scale of the storage cell array is large and the physical location of each storage cell is different. Due to the large difference in physical location, the characteristics of each storage cell are different, which is manifested in the large difference in the voltage threshold of each storage cell (the threshold voltage includes: the first voltage threshold, the second voltage threshold, and the voltage threshold that satisfies the reset operation). Therefore, when the number of storage cells is greater than or equal to the number threshold, the distribution range of the voltage threshold of the storage cell array is large, which is suitable for the second reset operation or the third reset operation with complex control methods.

[0074] In some embodiments, a first reset operation may also be performed when the number of storage cells is less than 30Gb; when the number of storage cells is in the range of 30Gb to 80Gb, one of the first reset operation, the second reset operation, and the third reset operation may be selected; when the number of storage cells is greater than 80Gb, one of the second reset operation and the third reset operation may be selected.

[0075] Please refer to Figure 1 , Figure 2 , Figure 4 Step S102 is executed. When the number of storage cells is less than the number threshold, a first reset operation is performed on the first target storage cell among the multiple storage cells. The first reset operation includes: applying a first word line voltage to the first word line coupled to the first target storage cell in a first time period, and applying a first bit line voltage and a first current to the first bit line coupled to the first target storage cell.

[0076] The timing sequence is divided into a start phase, a first time period, a second time period, a third time period, and a termination phase. Specifically, during the start and termination phases, the voltage applied to the first word line is set to 0, and the voltage and current applied to the first bit line are also set to 0.

[0077] The current applied to the first bit line includes: a first current I1 and a second current I2. The voltage applied to the first bit line includes: the first bit line voltage Vn1. The voltage applied to the first word line includes: the first word line voltage Vp1 and the second word line voltage Vp2.

[0078] Please refer to Figure 1 , Figure 2 , Figure 4 In step S103, during the second time period, a second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line, wherein the second word line voltage is greater than the first word line voltage.

[0079] Please refer to Figure 1 , Figure 2 , Figure 4 In step S104, during the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and a second current are applied to the first bit line, wherein the second current is greater than the first current.

[0080] In some embodiments, the range of the first word line voltage Vp1 is 0V < Vp1 ≤ 4V. The range of the second word line voltage Vp2 is Vp1 < Vp2 ≤ 5V, and Vp2 ≥ 3V.

[0081] In some embodiments, the range of the first current I1 is 20A ≤ I1 ≤ 80A. The range of the second current I2 is I1 < I2 ≤ 200A, and I2 ≥ 60A.

[0082] In some embodiments, the first line voltage Vn1 is negative, and the range of the first line voltage Vn1 is -5V≤Vn1<0V.

[0083] Under the combined action of the first line voltage, the second current, and the second word line voltage, the first target memory cell can be reset.

[0084] Based on the above embodiments, in the second time period, only the voltage of the first word line is changed while the first current is maintained; in the third time period, only the current of the first word line is changed while the voltage of the second word line is maintained. That is, the voltage and current are increased separately in different time periods, rather than simultaneously. Therefore, the overcharge current from the second time period to the third time period is suppressed. Furthermore, applying a small first current to the first word line in the first time period, and then increasing the voltage from the first word line voltage to the second word line voltage under a small first current, can also suppress the overcharge current.

[0085] In some embodiments, the magnitude of the overcharge current can also be controlled by adjusting the length of the second time period. A longer second time period results in better suppression of the overcharge current. A shorter second time period leads to a larger overcharge current.

[0086] In some embodiments, see Figure 5 As shown, the method further includes:

[0087] S201: When the number of storage cells is greater than or equal to a number threshold, a second reset operation is performed on the first target storage cell among the plurality of storage cells. The second reset operation includes: during the first time period, applying a first word line voltage to the first word line, applying a second bit line voltage and the first current to the first bit line, wherein the second bit line voltage is greater than the first bit line voltage.

[0088] S202: During the second time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line;

[0089] S203: If it is determined that the first target memory cell is in a non-conducting state during the second time period, in the third time period, a third word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line to adjust the first target memory cell to a conducting state, wherein the third word line voltage is greater than the second word line voltage.

[0090] In some embodiments, after S202, the method further includes: detecting the state of the first target storage cell to determine whether the first target storage cell is in a non-conducting state or a conducting state.

[0091] In some embodiments, detecting the state of the first target storage unit specifically includes:

[0092] S1: Detect whether the current passing through the first target storage unit is greater than a current threshold; the current threshold is a small value, such as 1uA or 10uA;

[0093] S2: If the current through the first target memory cell is less than or equal to the current threshold, it means that the gating element in the first target memory cell is turned off, and the first target memory cell is "in a non-conducting state".

[0094] S3: If the current through the first target memory cell is greater than the current threshold, it means that the gating element in the first target memory cell is turned on, and the first target memory cell is "in the on state".

[0095] The voltage applied to the first word line also includes: the second word line voltage Vn2. The voltage applied to the first word line also includes: the third word line voltage Vp3.

[0096] If the first target memory cell is "in a non-conducting state", then the second word line voltage needs to be increased to the third word line voltage in the third time period so that the first target memory cell is "in a conducting state". Then, the reset operation is achieved by using the combined effect of the third word line voltage, the first word line voltage and the second current.

[0097] In some embodiments, the range of the third word line voltage Vp3 is Vp2<Vp3≤5V, and Vp3≥3V.

[0098] In some embodiments, the range of the second bit line voltage Vn2 is -5V≤Vn2<0, Vn2>Vn1.

[0099] In some embodiments, see Figure 6 As shown, after S202, the method further includes:

[0100] S204: If it is determined that the first target memory cell is in the on state during the second time period, during the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

[0101] If the first target memory cell is "in the on state", then it is not necessary to increase the voltage of the first word line in the third time period. The reset operation is achieved by the combined effect of the second word line voltage, the first word line voltage, and the second current.

[0102] Based on the aforementioned second reset operation, regardless of whether the first target memory cell has completed the reset operation, the first target memory cell is reset again. If the reset operation is repeated, the first target memory cell will still be in an amorphous state after the repeated reset operation. In this embodiment, the absolute value of the second bit line voltage is set to a small value in the first time period, which can suppress the overcharge current in the first time period (i.e., when the first target memory cell is turned on). In the second time period, with the current of the first bit line unchanged, the voltage of the first word line is increased and decreased, and the overcharge current can also be suppressed. In the second time period, a fast read operation is performed, that is, the state of the first target memory cell is detected to determine whether the first target memory cell is in a non-conducting state or a conducting state, so as to determine whether the voltage of the first word line needs to be further increased. If the first target memory cell is in a conducting state, the voltage of the first word line does not need to be increased, ensuring a small overcharge current and avoiding applying an excessively high voltage of the first word line to the first target memory cell, which would affect the cell performance. If the first target memory cell is in a non-conducting state, the voltage of the first word line is increased to ensure that it is in a conducting state before the reset operation is performed.

[0103] In some embodiments, see Figure 7 , Figure 8 As shown, Figure 7 and Figure 8 The difference is that, Figure 7 In the second time period, the voltage of the first word line is directly increased to a relatively large voltage of the third word line. Figure 8The method further includes: increasing the voltage of the first word line to the voltage of the second word line in a second time period, and then increasing the voltage of the second word line to the voltage of the third word line in a third time period.

[0104] S301: When the number of storage cells is greater than or equal to a number threshold, a third reset operation is performed on the first target storage cell among the plurality of storage cells. The third reset operation includes: applying the first word line voltage to the first word line, applying the second bit line voltage and the first current to the first bit line during the first time period.

[0105] S302: When it is determined that the first target storage cell is in the on state during the first time period, detect whether the line resistance of the first target storage cell is greater than the resistance threshold.

[0106] S303: When it is determined that the line resistance of the first target memory cell is greater than the resistance threshold, during the second time period, a third word line voltage or a second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line.

[0107] S304: During the third time period, the third word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

[0108] In some embodiments, after S301, the method further includes: detecting the state of the first target memory cell to determine whether the first target memory cell is in a non-conducting state or a conducting state.

[0109] In some embodiments, the line resistance of the first target memory cell refers to the sum of the line resistance of the first target memory cell from the first word line to the word line power supply terminal and the line resistance of the first target memory cell from the first bit line to the bit line power supply terminal. The resistance threshold can be set to 10kΩ. If the line resistance of the first target memory cell is greater than the resistance threshold, it indicates that the first target memory cell is far from the two power supply terminals, resulting in a large line resistance. This line resistance will cause voltage division. Therefore, it is necessary to boost the first word line voltage to a relatively large third word line voltage to compensate for the voltage division caused by the line resistance. The reset operation is achieved by utilizing the combined effect of the third word line voltage, the first bit line voltage, and the second current.

[0110] In some embodiments, see Figure 9 As shown, after detecting whether the line resistance of the first target memory cell is greater than the resistance threshold, the method further includes:

[0111] S305: If it is determined that the line resistance of the first target memory cell is less than or equal to the resistance threshold, during the second time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line.

[0112] S306: During the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

[0113] If the line resistance of the first target memory cell is less than or equal to the resistance threshold, it means that the first target memory cell is close to the two power supply terminals and has a small line resistance. The effect of the line resistance voltage division can be ignored. Therefore, it is only necessary to increase the first word line voltage to the second word line voltage and use the combined effect of the second word line voltage, the first word line voltage and the second current to achieve the reset operation. Furthermore, since the second word line voltage is less than the third word line voltage, overcharging current can also be suppressed.

[0114] In some embodiments, see Figure 10 As shown, after applying the first word line voltage to the first word line, the second bit line voltage to the first bit line, and the first current, the method further includes:

[0115] S307: When it is determined that the first target memory cell is in a non-conducting state during the first time period, the voltage applied to the first word line is set to 0, and the voltage and current applied to the first bit line are set to 0.

[0116] If the first target memory cell is in a non-conducting state during the first time period, it means that it has already undergone a reset operation and does not need to undergo a reset operation again. Therefore, the voltage applied to the first word line and the voltage and current applied to the first bit line are set to 0, which can protect the performance of the memory cell and reduce power consumption.

[0117] The difference between the second and third reset operations is that the second reset operation performs a reset again regardless of whether the first target memory cell has already undergone a reset operation. The third reset operation determines whether a reset operation is needed based on the state of the first target memory cell: if the first target memory cell is in a non-conductive state (amorphous, high-resistance state) during the first time period, it means it has already undergone a reset operation and does not need to be reset again; if the first target memory cell is in a conductive state (crystalline, low-resistance state) during the first time period, it means it needs to be reset, and the corresponding voltage and current are increased accordingly. The advantage of the third reset operation is that it effectively avoids resetting the first target memory cell that has already been reset, avoids unnecessary reset operations that generate overcharge current, and suppresses overcharge current during the reset operation of the crystalline first target memory cell.

[0118] In some embodiments, see Figure 7 , Figure 8 As shown, after detecting whether the line resistance of the first target memory cell is greater than the resistance threshold, the method further includes:

[0119] S308: If it is determined that the line resistance of the first target memory cell is greater than the resistance threshold, a memory cell connected in series with the first target memory cell on the first word line is identified as the second target memory cell.

[0120] S309: When the third word line voltage is applied to the first word line, a bias voltage is applied to the second bit line coupled to the second target memory cell.

[0121] When the third word line voltage is applied to the first word line, the voltage across the second target memory cell is also increased. Therefore, a bias voltage Vbias is applied to the second bit line coupled to the second target memory cell. The bias voltage Vbias is positive, and its range is 0 < Vbias ≤ 2V. The voltage across the second target memory cell is Vp3 - Vbias. By setting the bias voltage, the voltage across the second target memory cell can be reduced, preventing the second target memory cell, which is in a non-conducting state, from being mistakenly turned on.

[0122] See Figure 11 As shown, Figure 11 The diagram shows the simulation results. As can be seen from L4, there will be an overcharge current during voltage switching, but the absolute value is small. Only when the current source is switched later will there be a significant increase in the current value.

[0123] This application provides a phase-change memory, including:

[0124] A memory cell array includes multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and the multiple word lines;

[0125] The peripheral circuitry coupled to the memory cell array is configured to control the memory cell array using the method described in any of the above embodiments.

[0126] It should be noted that the above method, based on the description of the phase-change memory embodiment, may also include other implementation methods. For specific implementation methods, please refer to the description of the relevant phase-change memory control method embodiment, which will not be elaborated here.

[0127] The methods or embodiments of phase-change memory described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0128] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0129] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A control method for a phase-change memory, the phase-change memory comprising a memory cell array, the memory cell array comprising multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and the multiple word lines, characterized in that, The method includes: Obtain the number of the storage units; When the number of storage cells is less than a threshold, a first reset operation is performed on a first target storage cell among the plurality of storage cells. The first reset operation includes: In the first time period, a first word line voltage is applied to the first word line coupled to the first target memory cell, and a first word line voltage and a first current are applied to the first bit line coupled to the first target memory cell. During the second time period, a second word line voltage is applied to the first word line, and the first bit line is applied with the first bit line voltage and the first current, wherein the second word line voltage is greater than the first word line voltage; During the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and a second current are applied to the first bit line, wherein the second current is greater than the first current.

2. The method according to claim 1, characterized in that, The method further includes: When the number of storage cells is greater than or equal to a number threshold, a second reset operation is performed on the first target storage cell among the plurality of storage cells. The second reset operation includes: during the first time period, applying a first word line voltage to the first word line, applying a second bit line voltage and the first current to the first bit line, wherein the second bit line voltage is greater than the first bit line voltage. During the second time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line; If it is determined that the first target memory cell is in a non-conducting state during the second time period, in the third time period, a third word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line to adjust the first target memory cell to a conducting state, wherein the third word line voltage is greater than the second word line voltage.

3. The method according to claim 2, characterized in that, After applying the second word line voltage to the first word line, applying the first bit line voltage to the first bit line, and applying the first current, the method further includes: If it is determined that the first target memory cell is in the on state during the second time period, during the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

4. The method according to claim 1, characterized in that, The method further includes: When the number of storage cells is greater than or equal to a number threshold, a third reset operation is performed on the first target storage cell among the plurality of storage cells. The third reset operation includes: applying a first word line voltage to the first word line, applying a second bit line voltage and the first current to the first bit line during the first time period. If it is determined that the first target storage cell is in the on state during the first time period, it is detected whether the line resistance of the first target storage cell is greater than the resistance threshold. If it is determined that the line resistance of the first target memory cell is greater than the resistance threshold, during the second time period, a third word line voltage or a second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line. During the third time period, the third word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

5. The method according to claim 4, characterized in that, After detecting whether the line resistance of the first target memory cell is greater than a resistance threshold, the method further includes: If it is determined that the line resistance of the first target memory cell is less than or equal to the resistance threshold, during the second time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line. During the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

6. The method according to claim 4, characterized in that, After detecting whether the line resistance of the first target memory cell is greater than a resistance threshold, the method further includes: If the line resistance of the first target memory cell is determined to be greater than the resistance threshold, a memory cell connected in series with the first target memory cell on the first word line is determined as the second target memory cell. When the third word line voltage is applied to the first word line, a bias voltage is applied to the second bit line coupled to the second target memory cell.

7. The method according to claim 4, characterized in that, After applying the first word line voltage to the first word line, the second bit line voltage to the first bit line, and the first current, the method further includes: If it is determined that the first target memory cell is in a non-conducting state during the first time period, the voltage applied to the first word line is set to 0, and the voltage and current applied to the first bit line are set to 0.

8. The method according to claim 1, characterized in that, The range of the first word line voltage Vp1 is 0V < Vp1 ≤ 4V.

9. The method according to claim 1, characterized in that, The range of the first current I1 is 20A ≤ I1 ≤ 80A.

10. A phase-change memory, characterized in that, include: A memory cell array includes multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and the multiple word lines; The peripheral circuitry coupled to the memory cell array is configured to control the memory cell array using the method described in any one of claims 1 to 9.

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