Capacitor and operation control circuit thereof

Abstract

The invention discloses a capacitor and an operation control circuit thereof, which are used for a charging and discharging circuit, and relates to the technical field of capacitors. A plurality of controlled switches and a plurality of capacitor cores are connected to form a series and parallel combined capacitor structure; the charging and discharging monitoring module is used for monitoring the charging and discharging state of the capacitor and outputting a discharging ending signal when it is determined that discharging of the capacitor is completed; a state monitoring module is used for monitoring the working time length of each capacitor core and generating a working state signal; and the control module controls on and off of part of the plurality of controlled switches based on the working state signals and the discharge ending signals of the capacitor cores so as to adjust the capacitor structure, so that the capacitor cores in an idle state replace the capacitor cores in an alarm state to work, the capacitance of the capacitor is kept unchanged, and the alarm effect is improved. Therefore, long-time high-load work of the capacitor core is effectively avoided, heating is reduced, and the capacitance of the capacitor is kept stable.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitors, and in particular to a capacitor and an operation control circuit thereof. Background Art

[0002] In modern electronic devices, capacitors, as an important energy storage component, are widely used in various industries.

[0003] During operation, capacitors generate heat due to factors such as the flow of current and ambient temperature. If the capacitor core is subjected to high load for extended periods, its temperature will continue to rise. Excessive temperature can cause the electrochemical performance of the capacitor core to degrade, shortening the capacitor's service life and causing changes in capacitance.

[0004] Currently, heat dissipation is mostly achieved by adding heat sink fins or providing heat dissipation channels outside the capacitor, but its effectiveness is still not understood, especially in applications where the capacitor needs to operate for a long time. Summary of the Invention

[0005] The present invention provides a capacitor and an operation control circuit thereof, which can effectively prevent the capacitor core from working at a high load for a long time, thereby reducing heat generation and maintaining the capacitance of the capacitor stable.

[0006] In order to solve the above problems, from a first aspect, an embodiment of the present invention discloses a capacitor operation control circuit for a charging and discharging circuit, comprising: Multiple capacitor cores; A plurality of controlled switches are connected to a plurality of capacitor cores to form a capacitor structure combining series and parallel connections; The charge and discharge monitoring module is used to monitor the charge and discharge status of the capacitor and output a discharge end signal when it is determined that the capacitor has completed discharge; The status monitoring module includes monitoring units corresponding to multiple capacitor cores. Each monitoring unit is used to monitor the operating time of the corresponding capacitor core and generate an operating status signal. The operating status signal includes: idle state, alarm state and running state. Among them, the alarm state indicates that the capacitor core is in the running state and the operating time has exceeded its timing threshold. a control module, which generates a first control signal for controlling the opening and closing of some of the plurality of controlled switches based on the working state signal and the discharge completion signal of each capacitor core; The driving module adjusts the capacitor structure according to the first control signal so that the capacitor core in the idle state replaces the capacitor core in the alarm state to work and the capacitor maintains the current capacitance.

[0007] In one embodiment of the present invention, the plurality of capacitor cores include: m first capacitor cores Cx[0,m-1] and n second capacitor cores Cy[0,n-1], where m is a positive integer ≥2 and n is a positive integer ≥2; the plurality of controlled switches include: m+1 first switches K[0,m] and n second switches S[0,n-1]; wherein the positive electrode of each first capacitor core is connected to the positive power supply terminal of the capacitor through the corresponding first switch, and the negative electrode of each first capacitor core is connected to form a common end; each second capacitor core is connected in series with its corresponding second switch to form a series branch, and each series branch is connected in parallel to form a parallel circuit, and the parallel circuit is connected between the common end and the negative power supply terminal of the capacitor and is connected to the positive power supply terminal of the capacitor through the corresponding first switch.

[0008] In one embodiment of the present invention, the capacitance of the first capacitor core is greater than the capacitance of the second capacitor core; m is 2, and the value range of n is 2-6.

[0009] In one embodiment of the present invention, the capacitor structure maintains a series-parallel capacitor structure before and after adjustment.

[0010] In one embodiment of the present invention, a first storage module connected to the control module is further included; the first storage module is used to store the mapping relationship between the adjustment mode of the capacitor structure and the capacitance, wherein, except for the maximum capacity, the same capacitance corresponds to at least two adjustment modes, and the adjustment mode is characterized by the opening and closing control logic of multiple controlled switches; the control module generates a first control signal based on the discharge end signal, working status signal and mapping relationship of each capacitor core.

[0011] In one embodiment of the present invention, the monitoring unit includes: The current sensor is used to monitor whether there is current flowing through the capacitor core and send a timing start signal when current is detected; A timer, configured to start timing upon receiving a timing start signal and output a timing signal; The signal processor outputs a working status signal based on the timing signal and a timing threshold set for the capacitor core.

[0012] In one embodiment of the present invention, the monitoring unit includes: A first comparator, wherein a first input terminal is connected to a control terminal level signal of a controlled switch connected in series with a capacitor core corresponding to the monitoring unit, a second input terminal is based on a default level signal, and an output terminal outputs a first comparison signal; a timer, configured to time the first comparison signal and output a timing signal; The second comparator outputs a working state signal based on the timing signal and a timing threshold set for the capacitor core.

[0013] In one embodiment of the present invention, when the control module receives the working state signal indicating an alarm state, the control module sends a timing reset signal to the monitoring unit that sends the working state signal.

[0014] In one embodiment of the present invention, the load in the charge and discharge circuit is variable; The capacitor operation control circuit also includes: The load detection module is connected to the loads in the charge and discharge circuits respectively, and is used to detect the resistance value of the loads; A second storage module is used to store the corresponding relationship between the resistance value of different loads and the target capacitance; The control module is further configured to determine a target capacitance based on the load resistance detected by the load detection module and the corresponding relationship, and to generate a second control signal for controlling the opening and closing of some of the plurality of controlled switches; The driving module adjusts the capacitor structure according to the second control signal so that the capacitance of the capacitor is adjusted to the target capacitance.

[0015] An embodiment of the present invention further discloses a capacitor, comprising the capacitor operation control circuit as described in the first aspect of the embodiment of the present invention.

[0016] The embodiments of the present invention include the following advantages: In an embodiment of the present invention, multiple capacitor cores are connected through multiple controlled switches to form a switchable series and parallel capacitor structure. The control module switches the controlled switches through the driving module according to the working time of the capacitor core monitored by the monitoring unit. When the working time of the capacitor core reaches a certain timing threshold and the capacitor discharge is completed, the capacitor core in the idle state replaces the capacitor core in the alarm state to avoid a certain capacitor core working at high load for a long time, reduces heat, reduces the degree to which the capacitance is affected by temperature, ensures the stability of the capacitance, and extends the service life of the capacitor core. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 1 is a schematic structural diagram of a capacitor operation control circuit according to an embodiment of the present invention; Figure 2 is a schematic diagram of a capacitor structure according to an embodiment of the present invention; Figure 3This is a schematic structural diagram of a monitoring unit according to an embodiment of the present invention; Figure 4 1 is a schematic structural diagram of another monitoring unit according to an embodiment of the present invention; Figure 5 It is a structural schematic diagram of another capacitor operation control circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0020] The embodiment of the present invention provides a capacitor operation control circuit for a charge and discharge circuit, such as Figure 1 As shown, the control circuit includes: Multiple capacitor cores; A plurality of controlled switches are connected to a plurality of capacitor cores to form a capacitor structure combining series and parallel connections; A charge and discharge monitoring module, configured to monitor the charge and discharge status of the capacitor and output a discharge completion signal when it is determined that the capacitor has completed discharge; The status monitoring module includes monitoring units corresponding to multiple capacitor cores. Each monitoring unit is used to monitor the operating time of the corresponding capacitor core and generate an operating status signal. The operating status signal includes: idle state, alarm state and running state. Among them, the alarm state indicates that the capacitor core is in the running state and the operating time has exceeded its timing threshold. a control module, which generates a first control signal for controlling the opening and closing of some of the plurality of controlled switches based on the working state signal and the discharge end signal of each capacitor core; The driving module adjusts the capacitor structure according to the first control signal so that the capacitor core in the idle state replaces the capacitor core in the alarm state to work, and the capacitor maintains the current capacitance.

[0021] In an embodiment of the present invention, multiple controlled switches are connected to multiple capacitor cores to form a capacitor structure that combines series and parallel connections, improving voltage quality and increasing the capacitor's withstand voltage. In a series circuit, voltage can be distributed across multiple capacitor cores, reducing the withstand voltage of a single capacitor core; in a parallel circuit, capacitance can be increased, improving circuit stability and enhancing voltage quality.

[0022] The multiple capacitor cores in the capacitor of the present invention include capacitor cores in three states: idle state, alarm state and running state. A capacitor core in an idle state refers to a capacitor core that is not connected in series or in parallel in the capacitor structure, is not connected to the positive power supply terminal and the negative power supply terminal of the capacitor, and cannot participate in the work of the capacitor (such as charge and discharge control); a capacitor core in a running state refers to a capacitor core that is connected in series or in parallel in the capacitor structure, is connected to the positive power supply terminal and the negative power supply terminal of the capacitor, and can participate in the work of the capacitor. The capacitance of the capacitor is affected by the capacitor core in the running state. A capacitor core in an alarm state refers to a capacitor core that has been in operation for a long time and the working time has exceeded its timing threshold. The timing thresholds of different capacitor cores are different, so as to stagger the rest based on the regulation scheme conceived by the present invention.

[0023] If the capacitor core in the alarm state continues to operate for a long time, under the application of the charge and discharge circuit, the actual capacitance of the capacitor core will deviate from the rated capacitance due to factors such as its overly high temperature, affecting the effective capacitance of the entire capacitor and affecting the actual application of the capacitor, such as the charging and discharging speed. This not only affects the accuracy of the application, but also poses a safety hazard. In view of this, in an embodiment of the present invention, a switchable capacitor structure is formed by connecting multiple controlled switches to multiple capacitor cores. The control module is used to monitor the charging and discharging status of the capacitor according to the working time of the capacitor core monitored by the monitoring unit, and the charge and discharge monitoring module is used to monitor the charging and discharging status of the capacitor, and adjust the opening and closing of the controlled switch when it is determined that the capacitor is discharged, so that different capacitor cores work alternately. This avoids a certain capacitor core from working at a high load for a long time, reduces heat, and thus extends the service life of the capacitor core. The present invention cooperates with the control module, the charge and discharge monitoring module, and the status monitoring module to switch through the driving module when the working time of the capacitor core reaches a certain timing threshold and the capacitor discharge is completed, so that the capacitor core in the idle state replaces the capacitor core in the alarm state to work, so that the capacitor core works at a relatively low temperature, reduces the degree to which the capacitance is affected by temperature, and ensures the stability of the capacitance. The present invention realizes the backup operation of the capacitor core by adjusting the capacitor structure, and improves the reliability and stability of the capacitor. Among them, the embodiment of the present invention performs the switching action only when the capacitor discharge is completed, does not affect the normal operation of the capacitor, and does not cause the problem of the fully charged capacitor being replaced.

[0024] It is worth noting that when the control module receives a working status signal of an alarm state from a certain monitoring unit, it sends a timing reset signal to the monitoring unit to save power consumption and facilitate the subsequent re-addition of the capacitor structure. In various embodiments of the present invention, the timing threshold is a pre-set time value used to determine whether the capacitor core needs to be replaced. The setting of the timing threshold needs to be determined based on the performance parameters of the capacitor core and the actual application scenario. The timing threshold can be set and adjusted by software or hardware.

[0025] The embodiments of the present invention can change the capacitor structure and implement different adjustment methods by controlling the opening or closing of different controlled switches. This application does not limit the different adjustment methods, as long as the capacitor structure can be changed while the capacitance of the capacitor remains unchanged.

[0026] As for the capacitor structure combined in series and in parallel, the embodiment of the present invention provides the following optional capacitor structures, referring to Figure 2 , multiple capacitor cores include: m first capacitor cores Cx[0,m-1] and n second capacitor cores Cy[0,n-1], m is a positive integer ≥2, and n is a positive integer ≥2; multiple controlled switches include: m+1 first switches K[0,m] and n second switches S[0,n-1]; wherein, the positive electrode of each first capacitor core is connected to the positive power supply terminal of the capacitor through the first switch corresponding thereto, and the negative electrode of each first capacitor core is connected to form a common terminal; each second capacitor core is connected in series with its corresponding second switch to form a series branch, and each series branch is connected in parallel to form a parallel circuit, and the parallel circuit is connected between the common terminal and the negative power supply terminal of the capacitor and is connected to the positive power supply terminal of the capacitor through the first switch corresponding thereto. This embodiment adjusts Figure 2 The capacitor structure shown not only enables backup operation of the capacitor core, extending its service life, but also improves voltage quality and withstand voltage by combining series and parallel capacitors. The first switch described above is a controlled switch, and the second switch is also a controlled switch. The controlled switches can be implemented using MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices.

[0027] It is worth noting that if Figure 2As shown, the parallel circuit is connected between the common end and the negative power supply terminal of the capacitor and is connected to the positive power supply terminal of the capacitor through the corresponding first switch K[2]. When the first capacitor switch K[2] is closed, the entire capacitor structure becomes a parallel circuit. When the second switches S[1]-S[4] in the parallel circuit are all closed, the capacitance of the entire capacitor structure is maximum; when only K[0] is closed, and any of the second switches S[0]-S[3] is closed, and the other switches are open, the entire capacitor structure becomes a series circuit, and the capacitance is minimum.

[0028] Furthermore, since the first capacitor core is primarily used to increase the withstand voltage and the total capacitance of the series connection is minimal, in order to maintain the withstand voltage to accommodate high-voltage charge and discharge applications, the capacitor structure of this embodiment can be improved as follows: the capacitance of the first capacitor core can be greater than the capacitance of the second capacitor core, thereby achieving both increased withstand voltage and high capacitance. Optionally, the capacitance of the first capacitor core can be twice that of the second capacitor core to reduce computational complexity and circuit area.

[0029] Furthermore, m is 2, and the value range of n is 2-6. Limiting this value range not only provides adjustment of the capacitor structure based on the capacitance, but also does not make the volume of the entire capacitor too large, thus meeting actual needs.

[0030] In such Figure 2 During the adjustment process of the capacitor structure shown, the capacitor structure of series connection combined with parallel connection is maintained before and after the adjustment.

[0031] For example (not shown in the figure): Assume that m=2, n=2, that is, there are two first capacitor cores Cx[0] and Cx[1], and two second capacitor cores Cy[0] and Cy[1]. The capacitance of the first capacitor core is 2C, and the capacitance of the second capacitor core is C. The positive electrodes of the first capacitor cores Cx[0] and Cx[1] are connected to the positive power supply terminal of the capacitor through the first switches K[0] and K[1] respectively, and their negative electrodes are connected to form a common terminal; the second capacitor cores Cy[0] and Cy[1] are connected in series with the second switches S[0] and S[1] respectively to form two series branches. After being connected in parallel, the two series branches are connected between the common terminal and the negative power supply terminal of the capacitor, and are connected to the positive power supply terminal of the capacitor through the first switch K[2]. In the initial state, it is assumed that the first capacitor core Cx[0] and the second capacitor core Cy[0] are in operation, and the second capacitor core Cy[1] is in idle state. The status monitoring module detects that the working time of Cx[0] and Cy[0] is gradually increasing. The timing thresholds corresponding to Cx[0] and Cy[0] are different. When the working time of Cy[0] exceeds its timing threshold, the status monitoring module generates an alarm status signal. After the control module receives the alarm status signal, if it receives the discharge end signal, it generates a first control signal. The driving module controls the second switch S[0] to open according to the first control signal, and controls the second switch S[1] to close, so that the second capacitor core Cy[1] replaces Cy[0] and enters the operating state. At this time, the capacitance structure of the capacitor changes, but the total capacitance of the capacitor remains unchanged. Furthermore, after the control module generates the first control signal, it will also send a timing reset signal to the monitoring unit that monitors the second capacitor core Cy[0] to save power consumption and facilitate the subsequent re-addition of the capacitance structure.

[0032] When it is detected that the working time of Cx[0] exceeds its timing threshold, the status monitoring module generates an alarm status signal. After the control module receives the alarm status signal, if it receives a discharge end signal, it generates a first control signal. The driving module controls the first switch K[0] to disconnect according to the first control signal, and controls the first switch K[1] to close, so that the first capacitor core Cx[1] replaces Cx[0] and enters the operating state. At this time, the capacitance structure of the capacitor changes, but the total capacitance of the capacitor remains unchanged. Furthermore, after the control module generates the first control signal, it also sends a timing reset signal to the monitoring unit that monitors the first capacitor core Cx[0] to save power consumption and facilitate the subsequent re-addition of the capacitance structure.

[0033] For example: Figure 2As shown, assuming m=2, n=4, there are 2 first capacitor cores Cx[0], Cx[1] and 4 second capacitor cores Cy[0], Cy[1], Cy[2], Cy[3]. The capacitance of the first capacitor core is 2C, and the capacitance of the second capacitor core is C. The positive poles of the first capacitor cores Cx[0] and Cx[1] are connected to the positive power supply terminal of the capacitor through the first switches K[0], K[1] respectively, and their negative poles are connected to form a common terminal; the second capacitor cores Cy[0], Cy[1], Cy[2], Cy[3] are connected in series with the second switches S[0], S[1], S[2], S[3] respectively to form four series branches. These four series branches are connected in parallel between the common terminal and the negative power supply terminal of the capacitor, and are connected to the positive power supply terminal of the capacitor through the first switch K[2]. In the initial state, it is assumed that the first capacitor core Cx[0] and the second capacitor core Cy[0], Cy[1] are in the operating state, and the second capacitor core Cy[2], Cy[3] are in the idle state. The state monitoring module detects that the working time of Cx[0], Cy[0], Cy[1] gradually increases. When the working time of Cy[0] and Cy[1] exceeds their respective timing thresholds at the same time, the state monitoring module generates an alarm state signal for the two capacitor cores. After the control module receives the alarm state signal, if it receives the discharge end signal, it generates a first control signal. The driving module controls the second switches S[0] and S[1] to disconnect according to the first control signal, and controls the second switches S[2] and S[3] to close, so that the second capacitor cores Cy[2] and Cy[3] replace Cy[0] and Cy[1] and enter the operating state. At this time, the capacitance structure of the capacitor changes, but the current capacitance of the capacitor remains unchanged. In this process, since the switching time is extremely short, it does not affect the stability of the capacitor's operation. As can be seen from the above example, the first control signal includes control instructions for K[0], K[1], and S[0]~S[n] respectively to control the corresponding controlled switches to be closed or opened.

[0034] Through the above embodiment, the performance of the capacitor is further optimized. Since the capacitance of the first capacitor core is greater than the capacitance of the second capacitor core, and satisfies a specific capacitance relationship and quantity relationship, the capacitor can more flexibly achieve a wide range of capacitance selection when adjusting the capacitance structure. At the same time, this capacitance relationship and quantity relationship also makes the capacitor perform better in improving voltage quality and increasing voltage resistance. In a series circuit, the first capacitor core can bear a larger voltage distribution, and the second capacitor core can provide more capacitance options; in a parallel circuit, the parallel combination of the second capacitor cores can increase the capacitance and improve the stability of the circuit.

[0035] A charge-discharge monitoring module is configured to monitor the charge and discharge status of the capacitor and output a discharge completion signal when it determines that the capacitor has completed discharge. The charge-discharge monitoring module can be implemented using an existing voltage detection unit, a comparator, and a reference voltage source that provides a discharge threshold. The comparator outputs a discharge completion signal when it determines that the capacitor voltage detected by the voltage detection unit continues to decrease and is below the discharge threshold (this discharge voltage is generally set to a voltage close to zero).

[0036] The condition monitoring module plays an important role in the capacitor operation control circuit, especially in high-voltage circuits. It can effectively monitor the working status of the capacitor core, promptly detect capacitor cores with degraded performance, and make reasonable adjustments through the control module and drive module, thereby extending the service life of the capacitor and improving its reliability and stability. The following are some possible implementation methods: In one possible embodiment, reference Figure 3Each monitoring unit includes a current sensor, a timer, and a signal processing module. The current sensor monitors whether current is flowing through the capacitor core and issues a timing start signal when current is detected. The timer begins timing upon receiving the timing start signal and outputs a timing signal. The signal processor outputs an operating status signal based on the timing signal and a timing threshold set for the capacitor core. In this embodiment, if the capacitor core is not operating (not working), the current sensor detects no current flowing, indicating that the capacitor core is in an idle state. If the capacitor core is operating (working), the current sensor detects current flowing, indicating that the capacitor core is in an operating state. For a capacitor core in an operating state, if the signal processor determines that the capacitor core is in an operating state and the operating duration has exceeded its preset timing threshold, the capacitor core is in an alarm state. When the capacitor operation control circuit is activated, the status monitoring module initializes all monitoring units. The timer of each monitoring unit is reset, and the current sensor begins monitoring the corresponding capacitor core. The current sensor monitors the flow of current through the capacitor core in real time. If the current sensor detects current flow, the capacitor core is in operation and a timer starts counting. If no current is detected, the capacitor core is idle and the timer stops counting. While the capacitor core is in operation, the timer records the operating time of the capacitor core. The signal processor of each monitoring unit determines the operating state of the capacitor core based on the output signals of the current sensor and the timer. If the capacitor core is in idle state, the signal processor outputs an "idle state" operating state signal. If the capacitor core is in operation and the operating time does not exceed the timing threshold, the signal processor outputs an "operating state" operating state signal. If the capacitor core is in operation and the operating time exceeds the timing threshold, the signal processor outputs an "alarm state" operating state signal. The status monitoring module aggregates the operating state signals of all monitoring units and sends them to the control module. Based on these operating state signals, the control module determines whether the capacitor structure needs to be adjusted when the capacitor discharge is complete.

[0037] In one possible embodiment, reference Figure 4Each monitoring unit includes: a first comparator, a timer, and a second comparator, wherein the first input terminal of the first comparator is connected to the control terminal level signal of the controlled switch connected in series with the capacitor core corresponding to the monitoring unit, the second input terminal is based on a default level signal, and the output terminal outputs a first comparison signal; the timer is used to time the first comparison signal and output a timing signal; the second comparator outputs a working status signal based on the timing signal and a timing threshold set for the capacitor core. In this embodiment, since the corresponding capacitor core can be controlled to join or exit the capacitor structure by controlling the opening and closing of the controlled switch, the control terminal level signal of the controlled switch connected in series with the corresponding capacitor core can represent the working status of the capacitor core. For example, the controlled switch is implemented using N_MOSFET. If the control terminal level signal is high, the controlled switch is closed, the capacitor core is added to the capacitor structure, and is in the operating state; if the control terminal level signal is low, the controlled switch is disconnected, the capacitor core exits the capacitor structure, and is in the idle state. For a capacitor core in operation, the comparison result between the control terminal level signal of the controlled switch connected in series and the default level signal (i.e., the first comparison signal) can be used to determine whether the capacitor core is in operation. Thus, a timer begins timing when the capacitor core is in operation (i.e., when the level of the first comparison signal is valid). A second comparator compares the timing signal with a timing threshold set for the capacitor core. When the timing duration exceeds the timing threshold, a working status signal indicating that the capacitor core is in an alarm state is output. This embodiment is relatively simple to implement, does not require a separate current sensor, occupies less circuit area, and is less costly.

[0038] In the embodiment of the present invention, continue to refer to Figure 1 , also includes a first storage module connected to the control module; the first storage module is used to store the mapping relationship between the adjustment mode of the capacitor structure and the capacitance, wherein, except for the maximum capacity, the same capacitance corresponds to at least two adjustment modes, and the adjustment mode is characterized by the opening and closing control logic of multiple controlled switches; the control module generates a first control signal based on the discharge end signal, working status signal and the mapping relationship of each capacitor core, and adjusts the opening and closing of some of the controlled switches in the multiple controlled switches, so that the capacitor core in the idle state replaces the capacitor core in the alarm state to work, and the capacitor maintains the current capacitance.

[0039] The above describes in detail how to maintain a constant capacitance suitable for a given load in a charge-discharge circuit, assuming the load remains constant. However, in existing capacitor applications, the charge and discharge processes are typically simple, lacking detailed management of the capacitor core's operating state. Especially in scenarios with fluctuating loads, existing capacitor charge and discharge times are difficult to quickly adjust to match the load, resulting in inefficient circuits or even malfunctioning.

[0040] In view of this, in another embodiment of the present invention, the load in the charge and discharge circuit is variable; Figure 5 , the capacitor operation control circuit also includes: a load detection module and a second storage module, wherein the load detection module is connected to the load in the charge and discharge circuit, and the load detection module is used to detect the resistance of the load; the second storage module is used to store the correspondence between the resistance of different loads and the target capacitance; the control module is also used to determine the target capacitance based on the resistance of the load detected by the load detection module and the correspondence, and generate a second control signal for controlling the opening and closing of some of the controlled switches in the multiple controlled switches; the driving module adjusts the capacitor structure according to the second control signal to adjust the capacitance of the capacitor to the target capacitance. According to the charge and discharge formula T=RC, T is the charging time, R is the load resistance, and C is the capacitance. Based on the above structure, the embodiment of the present invention can dynamically adjust the capacitance of the capacitor according to the load change, so that the charge and discharge time of the capacitor meets the current load application in the charge and discharge circuit, thereby improving the overall adaptability and stability of the circuit.

[0041] The load detection module can detect the load resistance through a resistance measurement circuit. For example, a constant current source injects a known current into the load, measures the voltage across the load, and calculates the load resistance based on Ohm's law. The measured resistance signal is then converted into a digital signal and transmitted to the processing module.

[0042] The first and second storage modules can be implemented using non-volatile memory chips such as EEPROM and Flash. Of course, the first and second storage modules can also be the same module; the present invention distinguishes them only by the content stored therein. The second storage module is used to store pre-measured and calculated data on the correspondence between different load resistance values ​​and their target charging times. This data can be written to the storage chip via host computer programming and is read and used by the control module during circuit operation.

[0043] The control module can be implemented using a single-chip microcomputer or a programmable logic device such as an FPGA. The driver module typically consists of a power driver circuit, which converts the control signal output by the control module into a drive signal capable of actuating the controlled switch. For example, if a MOSFET is used as the controlled switch, the driver module can consist of a MOSFET driver chip, which converts the control signal into an appropriate voltage signal to drive the MOSFET gate, turning the MOSFET on (i.e., the switch is closed) and off (i.e., the switch is open). This, in turn, changes the connection between the capacitor cores, thereby adjusting the capacitor structure and capacitance.

[0044] Based on the above embodiments, the working process of the capacitor operation control circuit of the present invention is as follows: In the case of initialization after load switching, the capacitor has no charge. The control module determines a target capacitance based on the load resistance detected by the load detection module and the corresponding relationship. Based on the mapping relationship between the target capacitance and the capacitance adjustment method of the capacitance structure, the control module generates a second control signal for controlling the opening and closing of some of the multiple controlled switches. After adjustment by the driving module, the states of all controlled switches are initialized so that the capacitor cores are connected according to the preset capacitance structure. For example, some capacitor cores are connected in series and some capacitor cores are connected in parallel to form the initial capacitance structure.

[0045] After the initial capacitor structure is formed, the charge and discharge monitoring module monitors the charge and discharge status of the capacitor and outputs a discharge completion signal when it is determined that the capacitor has completed discharge.

[0046] Each monitoring unit in the status monitoring module begins monitoring the operating time of its corresponding capacitor core. For example, the monitoring unit determines whether the capacitor core is in operation by detecting the level signal at the control end of the controlled switch connected in series with the capacitor core, and then measures the operating time. When the monitoring unit detects that the operating time of the capacitor core has reached a preset timing threshold, it outputs an alarm operating status signal; if the operating time has not reached the threshold, it outputs an operating status signal for the running state; if the capacitor core is not operating, it outputs an idle operating status signal.

[0047] After the control module receives the working status signal and the discharge end signal, when it determines that the capacitor is in the discharge end state and a capacitor core is in the alarm state, it will generate a first control signal based on the mapping relationship between the adjustment method of the capacitor structure and the capacitance to adjust the opening and closing of the corresponding controlled switch. If a capacitor core is in the alarm state, the control module will turn off the controlled switch corresponding to the capacitor core, and turn on the controlled switches corresponding to other idle capacitor cores, so that the idle capacitor core replaces the alarm capacitor core to work, keeping the target capacitance corresponding to the load unchanged. When the control module receives the working status signal of the alarm state sent by a monitoring unit, it sends a timing reset signal to the monitoring unit, so that the monitoring unit restarts the timing, so as to monitor the working time of the replaced capacitor core.

[0048] An embodiment of the present invention further discloses a capacitor, comprising the capacitor operation control circuit according to the embodiment of the present invention.

[0049] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0050] Relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations, nor can they be understood as indicating or implying relative importance. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0051] The technical solutions provided by this application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of this application. The description of the above embodiments is only intended to help understand this application, and the contents of this specification should not be construed as limiting this application. At the same time, for those skilled in the art, according to this application, there may be various changes in the specific implementation methods and application scopes. It is not necessary and impossible to list all implementation methods here, and obvious changes or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A capacitor operation control circuit, characterized in that: For charging and discharging circuits, including: Multiple capacitor cores; A plurality of controlled switches are connected to the plurality of capacitor cores to form a capacitor structure combining series and parallel connections; A charge and discharge monitoring module, configured to monitor the charge and discharge status of the capacitor and output a discharge completion signal when it is determined that the capacitor has completed discharge; a state monitoring module, comprising monitoring units corresponding one to each of the plurality of capacitor cores, each monitoring unit being configured to monitor the operating time of the corresponding capacitor core and generate an operating state signal; the operating state signal comprising an idle state, an alarm state, and an operating state; wherein the alarm state indicates that the capacitor core is in an operating state and the operating time has exceeded a timing threshold; a control module, which generates a first control signal for controlling the opening and closing of some of the plurality of controlled switches based on the working state signal and the discharge end signal of each capacitor core; The driving module adjusts the capacitor structure according to the first control signal, so that the capacitor core in the idle state replaces the capacitor core in the alarm state to work, and the capacitor maintains the current capacitance.

2. The capacitor operation control circuit according to claim 1, characterized in that: The plurality of capacitor cores include: m first capacitor cores Cx[0,m-1] and n second capacitor cores Cy[0,n-1], where m is a positive integer ≥2 and n is a positive integer ≥2; The plurality of controlled switches include: m+1 first switches K[0,m] and n second switches S[0,n-1]; The positive electrode of each first capacitor core is connected to the positive power supply terminal of the capacitor through the corresponding first switch, and the negative electrodes of each first capacitor core are connected to form a common terminal; Each second capacitor core is connected in series with its corresponding second switch to form a series branch, and each series branch is connected in parallel to form a parallel circuit. The parallel circuit is connected between the common end and the negative power supply terminal of the capacitor and is connected to the positive power supply terminal of the capacitor through the corresponding first switch.

3. The capacitor operation control circuit according to claim 2, characterized in that: The capacitance of the first capacitor core is greater than the capacitance of the second capacitor core; The m is 2, and the value range of n is 2-6.

4. The capacitor operation control circuit according to claim 2 or 3, characterized in that: in, The capacitor structure of series connection combined with parallel connection is maintained before and after the capacitor structure is adjusted.

5. The capacitor operation control circuit according to any one of claims 1 to 3, characterized in that: Also included is a first storage module connected to the control module; The first storage module is used to store a mapping relationship between an adjustment mode of the capacitor structure and a capacitance, wherein, except for the maximum capacitance, the same capacitance corresponds to at least two adjustment modes, and the adjustment mode is characterized by the on-off control logic of multiple controlled switches; The control module generates the first control signal based on the discharge completion signal of each capacitor core, the working status signal and the mapping relationship.

6. The capacitor operation control circuit according to claim 1, characterized in that: The monitoring unit includes: The current sensor is used to monitor whether there is current flowing through the capacitor core and send a timing start signal when current is detected; A timer, configured to start timing upon receiving the timing start signal and output a timing signal; The signal processor outputs the working status signal based on the timing signal and a timing threshold set for the capacitor core.

7. The capacitor operation control circuit according to claim 1, characterized in that: The monitoring unit includes: a first comparator, wherein a first input terminal is connected to a control terminal level signal of a controlled switch connected in series with a capacitor core corresponding to the monitoring unit, a second input terminal is based on a default level signal, and an output terminal outputs a first comparison signal; a timer, configured to time the first comparison signal and output a timing signal; The second comparator outputs the working status signal based on the timing signal and a timing threshold set for the capacitor core.

8. The capacitor operation control circuit according to claim 1, 7 or 8, characterized in that: When the control module receives the working state signal of the alarm state, it sends a timing reset signal to the monitoring unit that sends the working state signal.

9. The capacitor operation control circuit according to claim 1, It is characterized by: Wherein, the load in the charging and discharging circuit is variable; The capacitor operation control circuit further includes: A load detection module, connected to each of the loads in the charge and discharge circuits, and configured to detect a resistance value of the load; A second storage module is used to store the corresponding relationship between the resistance value of different loads and the target capacitance; The control module is further configured to determine a target capacitance based on the load resistance detected by the load detection module and the corresponding relationship, and generate a second control signal for controlling the opening and closing of some of the plurality of controlled switches; The driving module adjusts the capacitor structure according to the second control signal so that the capacitance of the capacitor is adjusted to a target capacitance.

10. A capacitor, characterized in that: The method comprises the capacitor operation control circuit according to any one of claims 1 to 9.

Images