Wafer fragment testing method and wafer testing equipment
By performing image scanning, alignment and positioning on wafer fragments and using an automatic tester to perform wafer testing, the problem of fragments during wafer testing is solved, the scrap rate is reduced and costs are saved.
Patent Information
- Application Number
- CN202410225043.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-28
- Publication Date
- 2025-09-05
AI Technical Summary
Wafers that crack or chip before or after testing can result in costly scrap and affect sample wafer performance evaluation.
The wafer fragments are tiled and spliced along the preset direction according to the cutting path through the support structure, and the image is acquired and the position offset is calibrated according to the reference mark to perform position compensation for wafer testing.
It reduces the wafer scrap rate, saves costs, and quickly obtains test results during the wafer testing stage, reducing tape-out time.
Smart Images
Figure CN120600650A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a wafer fragment testing method and wafer testing equipment. Background Art
[0002] Semiconductor manufacturing involves numerous steps, with the majority of manufacturing processes completed between wafer tape-out and wafer testing. Cracks and fragments are more likely to appear during wafer thinning or wafer testing. The presence of cracks and fragments on a wafer does not necessarily indicate a problem with the product used on it. There are many causes, with human error or machine operation being the most common, rather than a manufacturing issue. Simply scrapping wafers with cracks and fragments would be prohibitively expensive. For example, a 12-inch silicon substrate wafer currently sells for around 30,000 RMB. If the undamaged die can be recycled and sold after wafer testing, this can significantly save costs and have a direct impact on reducing production costs.
[0003] In addition, if some sample wafers have cracks or fragments before or after wafer testing in the trial production stage, it will have a serious impact on the product performance of the sample wafers.
[0004] Therefore, how to deal with wafer fragments before and after wafer testing so that they can be tested normally and continue to be taped out is a very important issue for every major semiconductor manufacturer. Summary of the Invention
[0005] The object of the present invention is to provide a wafer fragment testing method and wafer testing equipment, so that the wafer fragments before and after the wafer test can be better tested normally and continue to be taped out.
[0006] To solve the above technical problems, the present invention provides a method for testing wafer fragments, wherein the wafer fragments are derived from the same wafer, comprising:
[0007] Providing a support structure and a plurality of wafer fragments, wherein the support structure is provided with a splicing area;
[0008] Laying and splicing a plurality of wafer fragments along their cutting paths in a preset direction in the splicing area;
[0009] Placing the support structure on a test table of a wafer testing device, acquiring an image of each wafer fragment, and acquiring offset data of each wafer fragment based on the image of each wafer fragment and a reference mark on the image of each wafer fragment, wherein the reference mark is used to calibrate a position offset between the wafer fragment and the testing device;
[0010] Position compensation is performed on the wafer fragments when wafer testing is performed based on the offset data.
[0011] Optionally, the support structure includes a film that is bonded to the wafer fragments and a frame surrounding the splicing area, and the frame is used to tighten the film.
[0012] Optionally, an angular deviation between the cutting path of each wafer fragment and the preset direction is less than or equal to a set value.
[0013] Optionally, the step of respectively acquiring the offset data of each wafer fragment according to the image of each wafer fragment and the reference mark on the image of each wafer fragment includes:
[0014] Acquire a first image in which a characteristic pattern on the wafer fragment is offset from the reference mark and a second image in which the characteristic pattern is aligned with the reference mark;
[0015] The offset data of the wafer fragments is obtained by the position offset between the characteristic pattern on the first image and the characteristic pattern on the second image, and the offset data includes plane offset data and angle offset data.
[0016] Optionally, the acquiring the offset data of each wafer fragment according to the image of each wafer fragment and the reference mark on the image of each wafer fragment further includes:
[0017] Scan the wafer fragments in the splicing area to obtain boundary information of each wafer fragment, and mark each wafer fragment in sequence as the first wafer fragment to the Nth wafer fragment, where N is an integer greater than or equal to 2, and obtain offset data from the first wafer fragment to the Nth wafer fragment respectively.
[0018] Optionally, the characteristic pattern includes a dicing line on the wafer fragment.
[0019] Optionally, the reference mark is a crosshair located at the center of the image of each wafer fragment.
[0020] Optionally, performing position compensation when performing wafer testing on the wafer fragments according to the offset data further includes:
[0021] The needle insertion position of each wafer fragment is determined, a test map including test information of a plurality of wafer fragments is obtained according to the needle insertion position, the offset data and the image of the wafer fragment, and the wafer fragment is tested according to the test map.
[0022] Optionally, testing the wafer fragments according to the test map includes:
[0023] Each of the wafer fragments is tested in sequence, and the movement of the wafer testing platform is controlled according to the offset data so that the probe card is aligned with the needle insertion position on each of the wafer fragments.
[0024] According to another aspect of the present invention, a wafer testing device is provided for performing wafer testing on wafer fragments, comprising:
[0025] A test table, used to support a support structure, wherein a plurality of wafer fragments are tiled and spliced in a splicing area of the support structure along a preset direction according to their cutting paths;
[0026] An image acquisition device, disposed above the test table, for acquiring images of each wafer fragment in the splicing area;
[0027] a position calculation module, configured to obtain offset data of each wafer fragment based on an image of each wafer fragment and a reference mark on the image of each wafer fragment to calibrate a position offset between the wafer fragment and the testing device;
[0028] The test execution module is used for performing position compensation when performing wafer testing on each of the wafer fragments according to the offset data of each of the wafer fragments.
[0029] In summary, the present invention uses a support structure to tile the cutting paths of several wafer fragments from the same product in a preset direction and splice them in their splicing area, places the support structure on the test bench of the wafer testing equipment, obtains the image of each wafer fragment, and obtains the offset data of each wafer fragment based on the image of each wafer fragment and the reference mark on the image of each wafer fragment. The reference mark is used to calibrate the position offset between the wafer fragment and the testing equipment, and then performs position compensation when the wafer fragment is subjected to wafer testing based on the offset data. Thus, the present invention performs image scanning, alignment and positioning on the wafer fragments after splicing, so that the wafer fragments in the splicing area can be automatically tested by an automatic testing machine, so that the wafers that are scrapped due to cracks in the factory can be retested and shipped, so as to reduce the wafer scrap rate, thereby saving costs and increasing shipments. Moreover, for the wafer fragments of the sample wafer, the method of the present invention can quickly obtain test results in the wafer testing stage, which is conducive to saving tape-out time. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.
[0031] Figure 1 This is a flow chart of the wafer fragment testing method provided in Example 1;
[0032] Figure 2A schematic diagram of splicing wafer fragments provided in Example 1;
[0033] Figure 3 A schematic diagram of the offset provided in Example 1;
[0034] Figure 4a A schematic diagram of a first image of a second wafer fragment provided in Example 1;
[0035] Figure 4b A schematic diagram of a second image of the first wafer fragment provided in Example 1;
[0036] Figure 4c A schematic diagram of fitting the first image and the second graph provided in Example 1;
[0037] Figure 4d A schematic diagram of extracting characteristic images of a first image and a second image provided in Example 1;
[0038] Figure 5 This is a schematic diagram of the test map provided in Example 1.
[0039] In the attached figure:
[0040] 10-wafer fragment; 11-frame; 12-joining area; 13-preset direction. DETAILED DESCRIPTION
[0041] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.
[0042] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.
[0043] Example 1
[0044] Embodiment 1 provides a method for testing wafer fragments.
[0045] Figure 1 This is a flow chart of the wafer fragment testing method provided in Example 1.
[0046] like Figure 1 As shown, the wafer fragment testing method provided in this embodiment includes:
[0047] S01: providing a support structure and a plurality of wafer fragments, wherein a splicing area is provided on the support structure;
[0048] S02: Laying and splicing a plurality of wafer fragments in the splicing area along a preset direction according to their cutting paths;
[0049] S03: placing the support structure on a test table of a wafer testing device, acquiring an image of each wafer fragment, and acquiring offset data of each wafer fragment based on the image of each wafer fragment and a reference mark on the image of each wafer fragment, wherein the reference mark is used to calibrate the position offset between the wafer fragment and the testing device;
[0050] S04: performing position compensation when performing wafer testing on the wafer fragments according to the offset data.
[0051] First, step S01 is performed to provide a support structure and a plurality of wafer fragments, wherein a splicing area is provided on the support structure.
[0052] The wafer fragments of this embodiment may come from wafers before or during wafer testing, such as wafers that are broken before wafer testing, wafers that are broken during wafer testing, and of course, wafers that are broken after wafer testing, such as wafers that are broken during wafer thinning after wafer testing, wafers that are broken during wafer cutting, etc., for re-inspection of wafer fragments. Among them, the several wafer fragments provided in this embodiment have the same device structure and film layer structure so that the same needle pressure parameters can be used for wafer testing, that is, the above-mentioned wafer fragments come from the same wafer. However, it can be understood that the above-mentioned wafer fragments may come from different wafers of the same product and the same process.
[0053] The support structure of this embodiment is used to carry the above-mentioned wafer fragments, and the support structure has a splicing area, and the splicing of the wafer fragments is completed on the splicing area. The shape and size of the splicing area can be the same as the shape and size of a normal wafer, so as to form a MAP diagram (test map) similar to a normal wafer. In one example, the support structure may include a film that fits the wafer fragments and a frame surrounding the wafer fragments. The surface of the film has a certain viscosity that can be used to fix the wafer fragments, and the frame can be used to tighten the film to make it flat. Preferably, the film can also be a film used to protect the wafer during wafer cutting, such as a blue film or a conductive film, to facilitate the subsequent wafer cutting process.
[0054] Next, please refer to Figure 2 , executing step S02 , laying out a plurality of wafer fragments 10 along a preset direction 13 along their cutting paths and splicing them in a splicing area 12 of the support structure.
[0055] The support structure can be placed on any suitable platform and fixed, and wafer fragments 10 with a larger area and the outer contour of the original wafer are preferentially selected for splicing along the edge of the splicing area, and then wafer fragments 10 of appropriate size are selected for splicing in the blank space of the splicing area, and they are spread as much as possible over the splicing area 12. Among them, when the above-mentioned wafer fragments 10 are flatly spliced in the splicing area 12, a certain interval needs to be retained between each wafer fragment 10 so that they can be distinguished during image recognition. In particular, when splicing wafer fragments 10, the cutting path direction (arrangement direction of the pads on the grains) on each wafer fragment needs to be unified (the arrangement direction of the pads on the grains is unified), that is, they are flatly spliced according to the preset direction 13, so as to facilitate subsequent wafer testing. The preset direction 13 can preferably be parallel to a straight edge of the frame 11 to facilitate splicing and fitting.
[0056] It should be noted that the angular deviation between the cutting paths of each wafer fragment in the splicing area and the preset direction 13 must be less than a set value to facilitate subsequent wafer testing and to allow for slight deviation during manual splicing of the wafer fragments. The set value can be less than or equal to the angular rotation range of the wafer test table during wafer testing, for example, less than or equal to 5°. The closer the cutting paths are to being parallel to the preset direction 13, the smaller the positional deviation of the wafer fragments during testing.
[0057] Next, execute step S03, place the support structure on the test table of the wafer testing equipment, obtain the image of each wafer fragment, and obtain the offset data of each wafer fragment based on the image of each wafer fragment and the reference mark on the image of each wafer fragment. The reference mark is used to calibrate the position offset between the wafer fragment and the testing equipment.
[0058] The support structure with the wafer fragments is placed on the test table of the wafer testing equipment. The image acquisition device and position calculation module are used to identify, align, and compensate for each wafer fragment in the splicing area. The image acquisition device can be located above the test table and includes a high-precision camera to capture images of the splicing area and each wafer fragment. The position calculation module processes and calculates the captured images accordingly and outputs the test position and needle insertion position of each wafer fragment, as well as a test map (MAP) constructed from all wafer fragments.
[0059] Specifically, first, the wafer fragments in the splicing area are image scanned to obtain the boundary information of each wafer fragment to distinguish each wafer fragment, and the wafer fragments are numbered in sequence, for example, numbered as the first wafer fragment to the Nth wafer fragment, where N is an integer greater than or equal to 2. When obtaining the boundary information of each wafer fragment, after identifying the outline of each wafer fragment, a boundary box can be used to confirm (box select) the boundary of each wafer fragment, and the center coordinates of the boundary box of each wafer fragment are used as the initial position of each wafer fragment. Subsequently, the numbering of each wafer fragment (first to Nth) can be used as the order of corresponding alignment and testing. In addition, when identifying the boundary information of each wafer fragment, the complete grains on each wafer fragment can also be synchronously identified to form the grain distribution on each wafer fragment (ignoring incomplete grains).
[0060] Next, a first image in which the characteristic pattern on each wafer fragment is offset from the reference mark and a second image in which the characteristic pattern is aligned with the reference mark are obtained; the offset data of the wafer fragment is obtained by the position offset between the characteristic pattern on the first image and the characteristic pattern on the second image, and the offset data includes plane offset data and angle offset data. Among them, the reference mark can be a cross mark located at the center of the field of view of the image acquisition device, that is, the cross mark can also appear on the image of the wafer fragment acquired by the image acquisition device. The characteristic pattern on the wafer fragment can be formed by extracting the common image feature points on the images of the two wafer fragments, and then connecting the respective common image feature points into a straight line. In this embodiment, the characteristic pattern on the wafer fragment can be the cutting path closest to the reference mark, and is preferably a pattern consisting of two mutually perpendicular cutting paths (cross cutting path pattern).
[0061] Taking the alignment and compensation of a first wafer fragment as an example, the process may include: moving the center of the first wafer fragment to the center of the lens field of view (which may also be, for example, below the probe), identifying a characteristic pattern in the field of view, and acquiring an image at this time as a first image. Moving the test platform (i.e., the first wafer fragment) so that the characteristic pattern is located at the center of the field of view, and rotating the test platform so that the characteristic pattern is (as far as possible) aligned with a reference mark, and acquiring an image at this time as a second image, or processing the first image by a computer to obtain a second image in which the reference mark and the characteristic pattern are aligned. The positional offset of the characteristic pattern (e.g., a cross-cut pattern) in the first and second images is used as offset data for the first wafer fragment. The offset data includes planar offset data and angular offset data. The planar offset data may be X-axis offset data (offset X) and Y-axis offset data (offset Y), and the angular offset data may be rotational angle offset data (β).
[0062] Among them, the process of obtaining offset data may include: performing position fitting on the first image and the second image, then extracting respective characteristic patterns (cross cutting road patterns) from the first image and the second image, and then normalizing the angular positions of the two characteristic patterns, that is, first obtaining the rotation angle offset data, performing angle offset compensation, and then performing translation so that the characteristic patterns in the first image and the second image coincide, and obtaining the X-axis offset data (offset X) and Y-axis offset data (offset Y) in the plane offset data. In addition, while obtaining the offset data of the first wafer fragment, the pinning position of the grain can also be confirmed based on the contact position of the pad of the grain near the characteristic pattern and the relative probe during wafer testing, and based on this, the pinning position data of all grains on the first wafer fragment can be obtained based on the array distribution of other grains. In one example, please refer to Figure 3 , the center (intersection point) of the characteristic pattern in the second image is A, the center of the characteristic pattern in the first image is C, and the characteristic pattern in the second image intersects with the characteristic pattern in the first image at B, wherein ∠ABC is the angle offset data of the characteristic pattern in the first image. The characteristic pattern in the first image is rotated counterclockwise around point C by ∠ABC, and translated along the X-axis by AC*COS (∠CAB), and offset along the Y-axis by AC*SIN (∠CAB) until it overlaps with the characteristic pattern in the second image. At this time, the angle offset data is a counterclockwise rotation of ∠ABC, and the plane offset data is a translation of AC*COS (∠CAB) along the X-axis and a translation of AC*SIN (∠CAB) along the Y-axis.
[0063] Then, similarly, the second to Nth wafer fragments are aligned and compensated in sequence, and images, offset data, and needle position data of the second to Nth wafer fragments thereon are obtained.
[0064] Next, step S04 is executed to perform position compensation when performing wafer testing on the wafer fragments according to the offset data.
[0065] Specifically, the position data, offset data and needle position data of the first to Nth wafer fragments can be used to generate test data of the automatic tester, and form a test map composed of the first to Nth wafer fragments. The test map can be as follows: Figure 5 As shown in the figure, since the dies within each wafer fragment are distributed in an array, the planar offset data and angular offset data of each wafer fragment can be used to compensate for the test position data of the corresponding die on each wafer fragment, thereby forming a test map and test data for each wafer fragment. The test maps of each wafer fragment are then integrated to form a test map for the spliced area.
[0066] During wafer testing, each wafer fragment can be tested sequentially according to the test sequence. The wafer test table movement (translation and rotation) is controlled based on the offset data to align the probe card with the needle position on each wafer fragment, without the need for additional manual adjustment. Compared to cutting the wafer fragments into dies and then performing automatic or manual testing, this embodiment directly tests several wafer fragments in the splicing area at the same time, which can achieve higher testing efficiency and is convenient for daily operation on the production line. It also helps to eliminate defective products during wafer testing, which is more conducive to cost savings.
[0067] Example 2
[0068] Embodiment 2 provides a method for testing wafer fragments.
[0069] Figure 1 This is a flow chart of the wafer fragment testing method provided in Example 2.
[0070] like Figure 1 As shown, the wafer fragment testing method provided in this embodiment includes:
[0071] S01: providing a support structure and a plurality of wafer fragments, wherein a splicing area is provided on the support structure;
[0072] S02: Laying and splicing a plurality of wafer fragments in the splicing area along a preset direction according to their cutting paths;
[0073] S03: placing the support structure on a test table of a wafer testing device, acquiring an image of each wafer fragment, and acquiring offset data of each wafer fragment based on the image of each wafer fragment and a reference mark on the image of each wafer fragment, wherein the reference mark is used to calibrate the position offset between the wafer fragment and the testing device;
[0074] S04: performing position compensation when performing wafer testing on the wafer fragments according to the offset data.
[0075] The test method provided in Example 2 is basically the same as the test method provided in Example 1 in terms of test principles and test steps. The only difference is that the method of obtaining offset data for each wafer fragment is different: in Example 2, the position offset of the characteristic pattern in the first image of each wafer fragment relative to the reference mark can be directly used as offset data to perform position compensation on each wafer fragment during wafer testing.
[0076] Example 3
[0077] Embodiment 3 provides a wafer testing device.
[0078] The wafer testing equipment provided in this embodiment is used to perform wafer testing on wafer fragments, and includes a test bench, an image acquisition device, a position calculation module, and a test execution module. The test bench is used to support a support structure, and a plurality of wafer fragments are tiled and spliced on a splicing area of the support structure in a preset direction. The image acquisition device is provided above the test bench and is used to acquire images of each wafer fragment in the splicing area; the position calculation module is used to acquire offset data of each wafer fragment based on the image of each wafer fragment and the reference mark on the image of each wafer fragment to calibrate the position offset between the wafer fragment and the test equipment; the test execution module is used to perform position compensation when performing wafer testing on each wafer fragment based on the offset data of each wafer fragment.
[0079] In summary, the present invention uses a support structure to tile the cutting paths of several wafer fragments from the same product in a preset direction and splice them in their splicing area, places the support structure on the test bench of the wafer testing equipment, obtains the image of each wafer fragment, and obtains the offset data of each wafer fragment based on the image of each wafer fragment and the reference mark on the image of each wafer fragment. The reference mark is used to calibrate the position offset between the wafer fragment and the testing equipment, and then performs position compensation when the wafer fragment is subjected to wafer testing based on the offset data. Thus, the present invention performs image scanning, alignment and positioning on the wafer fragments after splicing, so that the wafer fragments in the splicing area can be automatically tested by an automatic testing machine, so that the wafers that are scrapped due to cracks in the factory can be retested and shipped to reduce the wafer scrap rate, thereby saving costs and increasing shipments. Moreover, for the wafer fragments of the sample wafer, the method of the present invention can quickly obtain test results in the wafer testing stage, which is conducive to saving tape-out time.
[0080] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for testing wafer fragments, wherein the wafer fragments are derived from the same wafer, characterized in that: include: Providing a support structure and a plurality of wafer fragments, wherein the support structure is provided with a splicing area; Laying and splicing a plurality of wafer fragments along their cutting paths in a preset direction in the splicing area; Placing the support structure on a test table of a wafer testing device, acquiring an image of each wafer fragment, and acquiring offset data of each wafer fragment based on the image of each wafer fragment and a reference mark on the image of each wafer fragment, wherein the reference mark is used to calibrate a position offset between the wafer fragment and the testing device; Position compensation is performed on the wafer fragments when wafer testing is performed based on the offset data.
2. The method for testing wafer fragments according to claim 1, wherein: The supporting structure includes a film adhered to the wafer fragments and a frame surrounding the splicing area, and the frame is used to tighten the film.
3. The method for testing wafer fragments according to claim 1, wherein: The angular deviation between the cutting path of each wafer fragment and the preset direction is less than or equal to a set value.
4. The method for testing wafer fragments according to claim 1, wherein: The step of respectively acquiring the offset data of each wafer fragment according to the image of each wafer fragment and the reference mark on the image of each wafer fragment comprises: Acquire a first image in which a characteristic pattern on the wafer fragment is offset from the reference mark and a second image in which the characteristic pattern is aligned with the reference mark; The offset data of the wafer fragments is obtained by the position offset between the characteristic pattern on the first image and the characteristic pattern on the second image, and the offset data includes plane offset data and angle offset data.
5. The method for testing wafer fragments according to claim 4, wherein: The step of obtaining the offset data of each wafer fragment according to the image of each wafer fragment and the reference mark on the image of each wafer fragment further includes: Scan the wafer fragments in the splicing area to obtain boundary information of each wafer fragment, and mark each wafer fragment in sequence as the first wafer fragment to the Nth wafer fragment, where N is an integer greater than or equal to 2, and obtain offset data from the first wafer fragment to the Nth wafer fragment respectively.
6. The method for testing wafer fragments according to claim 4, wherein: The characteristic pattern includes scribe lines on the wafer fragments.
7. The method for testing wafer fragments according to any one of claims 1 to 6, characterized in that: The reference mark is a crosshair located in the center of the image of each wafer fragment.
8. The method for testing wafer fragments according to any one of claims 1 to 6, characterized in that: The performing position compensation when performing wafer testing on the wafer fragments according to the offset data further includes: The needle insertion position of each wafer fragment is determined, a test map including test information of a plurality of wafer fragments is obtained according to the needle insertion position, the offset data and the image of the wafer fragment, and the wafer fragment is tested according to the test map.
9. The method for testing wafer fragments according to claim 4, wherein: Testing the wafer fragments according to the test map includes: Each of the wafer fragments is tested in sequence, and the movement of the wafer testing platform is controlled according to the offset data so that the probe card is aligned with the needle insertion position on each of the wafer fragments.
10. A wafer testing device for performing wafer testing on wafer fragments, characterized in that: include: A test table, used to support a support structure, wherein a plurality of wafer fragments are tiled and spliced in a splicing area of the support structure along a preset direction according to their cutting paths; An image acquisition device, disposed above the test table, for acquiring images of each wafer fragment in the splicing area; a position calculation module, configured to obtain offset data of each wafer fragment based on an image of each wafer fragment and a reference mark on the image of each wafer fragment to calibrate a position offset between the wafer fragment and the testing device; The test execution module is used to perform position compensation when performing wafer testing on each of the wafer fragments according to the offset data of each of the wafer fragments.