Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and the method comprises the steps: sequentially forming a bottom dielectric layer, a graphical etching delay layer and an interconnection layer which comprises an interconnection dielectric layer and an interconnection metal layer on the upper surface of a substrate, and sequentially etching the substrate, the bottom dielectric layer and the etching delay layer from the lower surface of the substrate through employing a deep hole etching technology, the substrate is etched, the lower surface of the bottom interconnection metal layer is exposed to form a first through hole, the substrate, the bottom dielectric layer and the interconnection dielectric layer located between the bottom dielectric layer and the top interconnection metal layer are etched at the same time, the lower surface of the top interconnection metal layer is exposed to form a second through hole, and the etching speed of the etching delay layer is lower than that of the interconnection dielectric layer. The etching rate of the bottom interconnection metal layer is actively regulated and controlled, it is ensured that the etching depths of the multiple layers of through holes synchronously reach the standard, and the risks that the bottom interconnection metal layer is thinned due to over-etching, the resistance is increased and the electrical performance is degraded are remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] Against the backdrop of the rapid development of semiconductor technology today, 3D stacking technology has emerged. It greatly improves the integration density and performance of integrated circuits by integrating multi-layer chip structures in the vertical direction, thereby meeting the growing demand for high-performance chips.

[0003] As a key process for achieving 3D stacking, through-silicon via (TSV) technology plays a vital role. In particular, in the TSV-Last manufacturing process, it is necessary to accurately etch through-silicon vias from the bottom surface of the wafer to achieve reliable connection with the interconnect metal layer, thereby building a conductive path between layers in the three-dimensional structure. However, in the actual etching process, if it is necessary to etch the interconnect metal layers at different levels at the same time, the interconnect metal layers at the higher level (close to the bottom surface of the wafer) will often be over-etched due to being exposed to the etching environment for a relatively long time. This over-etching problem will cause the thickness of the higher-level interconnect metal layer to be thinned, thereby causing an increase in resistance and a significant degradation of electrical performance, which seriously restricts the further development and application of high-precision 3D stacking technology. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor structure and a preparation method thereof, which are used to solve the problem of over-etching of higher-level interconnect metal layers in the existing through-silicon via (TLSV) process due to prolonged exposure to the etching environment.

[0005] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a semiconductor structure, the method comprising:

[0006] Providing a substrate, wherein the substrate has an upper surface and a lower surface opposite to each other, and a bottom dielectric layer is formed on the upper surface of the substrate;

[0007] forming a patterned etching delay layer on the underlying dielectric layer;

[0008] forming an interconnection layer on the resulting structure, the interconnection layer comprising an interconnection dielectric layer and an interconnection metal layer, the interconnection metal layer being embedded in the interconnection dielectric layer, the interconnection metal layer comprising a bottom interconnection metal layer close to the substrate and a top interconnection metal layer away from the substrate, the upper surface of the etch delay layer being in contact with the lower surface of the bottom interconnection metal layer at a predetermined position, and the etching rate of the etch delay layer being lower than the etching rate of the interconnection dielectric layer;

[0009] A deep hole etching process is used to sequentially etch the substrate, the bottom dielectric layer, and the etching delay layer from the bottom surface of the substrate, and expose the bottom surface of the bottom interconnect metal layer to form a first through hole. At the same time, the substrate, the bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer are sequentially etched from the bottom surface of the substrate, and the bottom surface of the top interconnect metal layer is exposed to form a second through hole.

[0010] Optionally, the material of the interconnect dielectric layer includes SiO 2 , and the material of the etch delay layer includes SiN.

[0011] Optionally, a ratio η of an etching rate of the etch delay layer to an etching rate of the interconnect dielectric layer is ≤ 1 / 5.

[0012] Optionally, the thickness of the etch delay layer is T, and T is defined as ΔL*η, where η is the ratio of the etching rate of the etch delay layer to the etching rate of the interconnect dielectric layer, and ΔL is the distance between the lower surface of the top interconnect metal layer and the lower surface of the bottom interconnect metal layer.

[0013] Optionally, the thickness of the etch delay layer is T, and T is defined as ΔL*η / (1-η), where η is the ratio of the etching rate of the etch delay layer to the etching rate of the interconnect dielectric layer, and ΔL is the distance between the lower surface of the top interconnect metal layer and the lower surface of the bottom interconnect metal layer.

[0014] Optionally, the thickness of the etch delay layer is 0.1 μm to 0.5 μm.

[0015] Optionally, a horizontal projection of the etch delay layer is located within the bottom interconnect metal layer.

[0016] Optionally, a projection of the etch delay layer in a horizontal direction covers the bottom interconnect metal layer.

[0017] Optionally, before forming the first through hole and the second through hole by using the deep hole etching process, the method further includes turning over the substrate so that the lower surface of the substrate faces upward and thinning the lower surface of the substrate.

[0018] The present invention also provides a semiconductor structure, which is prepared using any one of the above methods for preparing a semiconductor structure.

[0019] As described above, the semiconductor structure and fabrication method of the present invention have the following beneficial effects: a bottom dielectric layer, a patterned etch delay layer, and an interconnection layer comprising an interconnect dielectric layer and an interconnect metal layer are sequentially formed on the upper surface of a substrate, and the substrate, bottom dielectric layer, and etch delay layer are sequentially etched from the lower surface of the substrate using a deep hole etching process, exposing the lower surface of the bottom interconnect metal layer to form a first through-hole. Simultaneously, the substrate, bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer are etched, exposing the lower surface of the top interconnect metal layer to form a second through-hole. By introducing an etch delay layer having a lower etching rate than that of the interconnect dielectric layer, the etching rate of the bottom interconnect metal layer is actively controlled, ensuring that the etching depth of the multiple through-holes is simultaneously met, significantly reducing the risk of thinning, resistance increase, and electrical performance degradation of the bottom interconnect metal layer due to over-etching. Furthermore, this method is highly compatible with existing processes, eliminating the need for additional complex steps. Furthermore, the dimensional design of the etch delay layer is flexible and adaptable to various design scenarios, thereby providing a more efficient and reliable solution for the fabrication of semiconductor structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic flow chart of the method for preparing the semiconductor structure of the present invention.

[0021] Figures 2 to 7 Shown are schematic cross-sectional structures of various steps in the method for preparing a semiconductor structure of the present invention.

[0022] Component number description

[0023] 10 substrate

[0024] 101 upper surface

[0025] 102 lower surface

[0026] 11 Bottom dielectric layer

[0027] 12 Etch delay layer

[0028] 13 Photoresist layer

[0029] 14 Interconnect dielectric layer

[0030] 15 Bottom Interconnect Metal Layer

[0031] 16 Top interconnect metal layer

[0032] 17 First through hole

[0033] 18 Second through hole

[0034] 20 Interconnect Metal Layers

[0035] 21 Interconnection Layer DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] See also Figures 1 to 7 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0038] like Figure 1 As shown, this embodiment provides a method for preparing a semiconductor structure, the method comprising:

[0039] S1, providing a substrate, wherein the substrate has an upper surface and a lower surface opposite to each other, and a bottom dielectric layer is formed on the upper surface of the substrate;

[0040] S2, forming a patterned etching delay layer on the underlying dielectric layer;

[0041] S3, forming an interconnection layer on the obtained structure, wherein the interconnection layer includes an interconnection dielectric layer and an interconnection metal layer, the interconnection metal layer is embedded in the interconnection dielectric layer, the interconnection metal layer includes a bottom interconnection metal layer close to the substrate and a top interconnection metal layer away from the substrate, the upper surface of the etch delay layer contacts the lower surface of the bottom interconnection metal layer at a predetermined position, and the etching rate of the etch delay layer is lower than the etching rate of the interconnection dielectric layer;

[0042] S4, using a deep hole etching process to sequentially etch the substrate, the underlying dielectric layer and the etching delay layer from the lower surface of the substrate, and expose the lower surface of the underlying interconnect metal layer to form a first through hole, and at the same time, sequentially etch the substrate, the underlying dielectric layer and the interconnect dielectric layer located between the underlying dielectric layer and the top interconnect metal layer from the lower surface of the substrate, and expose the lower surface of the top interconnect metal layer to form a second through hole.

[0043] The method for fabricating a semiconductor structure of this embodiment sequentially forms a bottom dielectric layer, a patterned etch delay layer, and an interconnect layer comprising an interconnect dielectric layer and an interconnect metal layer on the top surface of a substrate. A deep hole etching process is then used to sequentially etch the substrate, bottom dielectric layer, and etch delay layer from the bottom surface of the substrate, exposing the bottom surface of the bottom interconnect metal layer to form a first through-hole. Simultaneously, the substrate, bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer are etched, exposing the bottom surface of the top interconnect metal layer to form a second through-hole. By introducing an etch delay layer having a lower etching rate than the interconnect dielectric layer, the etching rate of the bottom interconnect metal layer is actively controlled, ensuring that the etching depth of multiple through-holes is simultaneously met. This significantly reduces the risk of over-etching leading to thinning of the bottom interconnect metal layer, increased resistance, and degraded electrical performance. Furthermore, this method is highly compatible with existing processes, eliminating the need for additional complex steps. The etch delay layer's flexible design dimensions can accommodate a variety of design scenarios, providing a more efficient and reliable solution for fabricating semiconductor structures.

[0044] The following combination Figures 2 to 7 The method for preparing the semiconductor structure of this embodiment is described in detail.

[0045] like Figure 2 As shown, step S1 is first performed to provide a substrate 10 . The substrate 10 has an upper surface 101 and a lower surface 102 opposite to each other. A bottom dielectric layer 11 is formed on the upper surface 101 of the substrate 10 .

[0046] As an example, the material of the substrate 10 includes but is not limited to silicon, germanium, gallium arsenide, indium phosphide and silicon carbide. The size of the substrate 10 is not limited here, and is preferably wafer-level.

[0047] like Figure 5 As shown, step S2 is then performed to form a patterned etching delay layer 12 on the underlying dielectric layer 11 .

[0048] As a specific example, Figures 3 to 5 As shown, the method for forming the patterned etching delay layer 12 on the underlying dielectric layer 11 includes:

[0049] S21, such as Figure 3 As shown, an etching delay layer 12 is deposited on the bottom dielectric layer 11 .

[0050] S22, such as Figure 4 As shown, a photoresist layer 13 is formed on the etch delay layer 12 and patterned.

[0051] S23, such as Figure 5As shown, a patterned etching delay layer 12 is formed based on the patterned photoresist layer 13, and the patterned photoresist layer 13 is removed.

[0052] like Figure 6 As shown, then proceed to step S3, as shown in Figure 5 An interconnection layer 21 is formed on the resulting structure shown. The interconnection layer 21 includes an interconnection dielectric layer 14 and an interconnection metal layer 20. The interconnection metal layer 20 is embedded in the interconnection dielectric layer 14. The interconnection metal layer 20 includes a bottom interconnection metal layer 15 close to the substrate 10 and a top interconnection metal layer 16 away from the substrate 10. The upper surface of the etch delay layer 12 contacts the lower surface of the bottom interconnection metal layer 15 at a predetermined position, and the etching rate of the etch delay layer 12 is lower than the etching rate of the interconnection dielectric layer 14.

[0053] It should be noted here that those skilled in the art should understand that the interconnection metal layer 20 formed may also include interconnection metal layers of other levels in addition to the bottom interconnection metal layer 15 and the top interconnection metal layer 16 to meet different electrical connection requirements, and in order to meet different electrical connection requirements, the bottom interconnection metal layer 15 and the top interconnection metal layer 16 will not completely overlap in their horizontal projections.

[0054] As an example, the material of the interconnect dielectric layer 14 includes silicon dioxide (SiO2), and the material of the etch delay layer 12 includes silicon nitride (SiN). The higher etching selectivity between silicon nitride and silicon dioxide, as well as the dual effects of chemical inertness and physical barrier of silicon nitride are utilized to delay the etching process, and the etching rates of the bottom interconnect metal layer 15 and the top interconnect metal layer 16 are precisely regulated to ensure that the subsequent multi-layer through-hole etching depths meet the standards simultaneously, while avoiding over-etching damage to the bottom interconnect metal layer 15. In addition, the material of the etch delay layer 12 also includes other materials with higher density and significant etching selectivity than the material of the interconnect dielectric layer 14. As long as they can play a role in delaying the etching process, no excessive restrictions are imposed here.

[0055] As an example, the ratio η of the etching rate of the etching delay layer 12 to the etching rate of the interconnect dielectric layer 14 is ≤ 1 / 5, and the etching rates of the bottom interconnect metal layer 15 and the top interconnect metal layer 16 are further precisely controlled to ensure that the subsequent multi-layer through-hole etching depths meet the standards synchronously.

[0056] As an example, the thickness of the etching delay layer 12 is T, and T is defined as ΔL*η, where η is the ratio of the etching rate of the etching delay layer 12 to the etching rate of the interconnect dielectric layer 14, and ΔL is the distance between the lower surface of the top interconnect metal layer 16 and the lower surface of the bottom interconnect metal layer 15 (e.g., Figure 6 As shown in FIG, when a rough estimate of the thickness of the etch delay layer 12 is required, or when the distance (ΔL) between the lower surface of the top interconnect metal layer 16 and the lower surface of the bottom interconnect metal layer 15 reaches more than 10 times the thickness of the etch delay layer 12 and can be ignored, the formula T = ΔL*η can be used to estimate the thickness of the etch delay layer 12.

[0057] As another example, the thickness of the etching delay layer 12 is T, and T is defined as ΔL*η / (1-η), where η is the ratio of the etching rate of the etching delay layer 12 to the etching rate of the interconnect dielectric layer 14, and ΔL is the distance between the lower surface of the top interconnect metal layer 16 and the lower surface of the bottom interconnect metal layer 15 (e.g., Figure 6 As shown), when the distance (ΔL) between the lower surface of the top interconnect metal layer 16 and the lower surface of the bottom interconnect metal layer 15 is less than 10 times the thickness of the etching delay layer 12 and cannot be ignored, the formula T = ΔL*η / (1-η) is used to determine the thickness of the etching delay layer 12 to ensure the accuracy of the etching effect.

[0058] As a further example, the thickness of the etching delay layer 12 is 0.1 μm to 0.5 μm, which further accurately controls the etching rates of the bottom interconnect metal layer 15 and the top interconnect metal layer 16 to ensure that the subsequent multi-layer through-hole etching depths meet the standards synchronously.

[0059] like Figure 7 As shown, step S4 is then performed, in which the substrate 10, the underlying dielectric layer 11 and the etching delay layer 12 are sequentially etched from the lower surface of the substrate 10 using a deep hole etching process, and the lower surface of the underlying interconnection metal layer 15 is exposed to form a first through hole 17. At the same time, the substrate 10, the underlying dielectric layer 11 and the interconnection dielectric layer 14 located between the underlying dielectric layer 11 and the top interconnection metal layer 16 are sequentially etched from the lower surface of the substrate 10, and the lower surface of the top interconnection metal layer 16 is exposed to form a second through hole 18.

[0060] As an example, Figure 7 As shown, before performing step S4, that is, before using the deep hole etching process to form the first through hole 17 and the second through hole 18, it also includes the steps of flipping the substrate 10 so that the lower surface of the substrate 10 faces upward and thinning the lower surface of the substrate 10, so that the deep hole etching process can proceed smoothly.

[0061] To adapt to different design scenarios, as an example, the horizontal projection of the etch delay layer 12 is located within the underlying interconnect metal layer 15, that is, in step S2, the etch delay layer 12 is formed only in the area where the first through hole 17 is formed in the subsequent step S4, or in step S2, the etch delay layer 12 is formed in an area larger than the planar size of the first through hole 17 area, rather than forming the etch delay layer 12 in the entire area of ​​the underlying interconnect metal layer 15. By limiting the formation area of ​​the etch delay layer 12 to a range slightly larger than the area where the first through hole 17 is subsequently formed, it is easier to achieve precise alignment of the etch delay layer 12 with the area of ​​the first through hole 17 to be formed subsequently, reducing process complexity and error probability, while ensuring that key metal areas are fully protected in the subsequent etching process, avoiding metal layer thinning and performance degradation caused by over-etching.

[0062] As another example, the horizontal projection of the etch delay layer 12 covers the underlying interconnect metal layer 15. The formation area of ​​the etch delay layer 12 covers the entire area where the underlying interconnect metal layer 15 is subsequently formed, ensuring that all areas that may be affected by etching can be effectively protected during the etching process, further avoiding the problem of over-etching of the underlying interconnect metal layer 15.

[0063] This embodiment also provides a semiconductor structure, which is prepared using the preparation method of the semiconductor structure in the above embodiment. The beneficial effects that can be achieved can be found in the specific description of the preparation method, which will not be repeated here.

[0064] In summary, the semiconductor structure and fabrication method of the present invention sequentially form a bottom dielectric layer, a patterned etch delay layer, and an interconnection layer comprising an interconnect dielectric layer and an interconnect metal layer on the upper surface of a substrate. The substrate, bottom dielectric layer, and etch delay layer are sequentially etched from the lower surface of the substrate using a deep hole etching process, exposing the lower surface of the bottom interconnect metal layer to form a first through-hole. Simultaneously, the substrate, bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer are etched, exposing the lower surface of the top interconnect metal layer to form a second through-hole. By introducing an etch delay layer having a lower etching rate than that of the interconnect dielectric layer, the etching rate of the bottom interconnect metal layer is actively regulated, ensuring that the etching depth of the multi-layer through-holes is simultaneously met, significantly reducing the risk of thinning, increased resistance, and electrical performance degradation of the bottom interconnect metal layer due to over-etching. Furthermore, the method is highly compatible with existing processes, eliminating the need for additional complex steps. Furthermore, the dimensional design of the etch delay layer is flexible and adaptable to various design scenarios, thereby providing a more efficient and reliable solution for the fabrication of semiconductor structures. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0065] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: Providing a substrate, wherein the substrate has an upper surface and a lower surface opposite to each other, and a bottom dielectric layer is formed on the upper surface of the substrate; forming a patterned etching delay layer on the underlying dielectric layer; forming an interconnection layer on the resulting structure, the interconnection layer comprising an interconnection dielectric layer and an interconnection metal layer, the interconnection metal layer being embedded in the interconnection dielectric layer, the interconnection metal layer comprising a bottom interconnection metal layer close to the substrate and a top interconnection metal layer away from the substrate, the upper surface of the etch delay layer being in contact with the lower surface of the bottom interconnection metal layer at a predetermined position, and the etching rate of the etch delay layer being lower than the etching rate of the interconnection dielectric layer; A deep hole etching process is used to sequentially etch the substrate, the bottom dielectric layer, and the etching delay layer from the bottom surface of the substrate, and expose the bottom surface of the bottom interconnect metal layer to form a first through hole. At the same time, the substrate, the bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer are sequentially etched from the bottom surface of the substrate, and the bottom surface of the top interconnect metal layer is exposed to form a second through hole.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The material of the interconnect dielectric layer includes SiO2, and the material of the etch delay layer includes SiN.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The ratio η of the etching rate of the etching delay layer to the etching rate of the interconnect dielectric layer is ≤ 1 / 5.

4. The method for preparing a semiconductor structure according to claim 1, wherein: The thickness of the etch delay layer is T, and T is defined as ΔL*η, where η is the ratio of the etching rate of the etch delay layer to the etching rate of the interconnect dielectric layer, and ΔL is the distance between the lower surface of the top interconnect metal layer and the lower surface of the bottom interconnect metal layer.

5. The method for preparing a semiconductor structure according to claim 1, wherein: The thickness of the etch delay layer is T, and T is defined as ΔL*η / (1-η), where η is the ratio of the etching rate of the etch delay layer to the etching rate of the interconnect dielectric layer, and ΔL is the distance between the lower surface of the top interconnect metal layer and the lower surface of the bottom interconnect metal layer.

6. The method for preparing a semiconductor structure according to claim 1, wherein: The thickness of the etching delay layer is 0.1 μm to 0.5 μm.

7. The method for preparing a semiconductor structure according to claim 1, wherein: The projection of the etch delay layer in the horizontal direction is located within the bottom interconnect metal layer.

8. The method for preparing a semiconductor structure according to claim 1, wherein: The projection of the etch delay layer in the horizontal direction covers the bottom interconnect metal layer.

9. The method for preparing a semiconductor structure according to claim 1, wherein: Before forming the first through hole and the second through hole by adopting the deep hole etching process, the method further includes the steps of turning over the substrate so that the lower surface of the substrate faces upward and thinning the lower surface of the substrate.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 9.

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