Novel stacked packaging structure
The combined structure of FOW film and leads solves the chip stacking line collapse problem, achieves stable connection, reduces package size and cost, improves integration, and adapts to the design requirements of portable electronic devices.
Patent Information
- Application Number
- CN202510929655.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-07
- Publication Date
- 2025-09-05
AI Technical Summary
Existing chip stacking wire bonding technology is prone to wire collapse when the chip areas vary greatly, leading to electrical connection failures. Traditional solutions also increase package size and cost, limiting the design and functional expansion of portable electronic devices.
By adopting a combined structure of FOW film and leads, and precisely controlling the film thickness and lead arc height, stable connections between chips are achieved, avoiding the risk of lead collapse, and reducing materials and process steps.
Significantly reduce package size, improve product stability and reliability, reduce defect rate, reduce production costs, enhance chip integration, and adapt to miniaturization needs.
Smart Images
Figure CN120600720A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip stacking packaging, and in particular to a novel stacking packaging structure. Background Art
[0002] In existing chip stacking designs, wire bonding packaging technology is often used when the chips have significantly different areas. It primarily leverages the area difference between the chips to achieve electrical connections between the chips and the lead frame or substrate. Traditional chip stacking wire bonding solutions typically stack the chips first, then perform wire bonding between the individual chips. However, this approach has numerous drawbacks. Due to the height difference created by the stacked chips, wires can easily collapse during the bonding process due to factors such as gravity and external interference, leading to electrical connection failures and seriously impacting product stability and reliability. Furthermore, traditional chip stacking wire bonding solutions are not suitable for wire bonding processes with comparable chip areas. When the chips have similar areas, wire bonding often requires the use of larger packages or the addition of spacers to create sufficient space. This significantly increases the overall package size and stacking volume, resulting in a product disadvantage in terms of space utilization, and can also significantly increase production costs, reducing product competitiveness in the market. Moreover, the larger package size and stacking volume will limit product design and functional expansion in some application scenarios with extremely high space requirements, such as portable electronic devices and wearable devices. Summary of the Invention
[0003] The purpose of the present invention is to solve the shortcomings of the prior art and to propose a new stacking package structure.
[0004] In order to achieve the above objectives, the present invention adopts the following technical solution: a new stacked packaging structure, characterized in that it includes a substrate, the upper surface of which includes a first FOW film, a first chip die, a first lead, a second FOW film and a second chip die.
[0005] As a further description of the above technical solution:
[0006] The stacked package structure includes a second lead, a third FOW film and a third chip bare die.
[0007] As a further description of the above technical solution:
[0008] The stacked package structure includes a third lead, a fourth FOW film and a fourth chip bare die.
[0009] As a further description of the above technical solution:
[0010] A first lead is connected between the substrate and the first chip die, or a second lead is connected between the substrate and the second chip die.
[0011] As a further description of the above technical solution:
[0012] A third lead is connected between the substrate and the third chip die.
[0013] As a further description of the above technical solution:
[0014] The second FOW film covers the first lead and the first chip die.
[0015] As a further description of the above technical solution:
[0016] The third FOW film covers the second lead and the second chip die.
[0017] As a further description of the above technical solution:
[0018] The fourth FOW film covers the third lead and the third chip die.
[0019] As a further description of the above technical solution:
[0020] Solder balls are arranged on the bottom of the substrate.
[0021] As a further description of the above technical solution:
[0022] The thickness of the first FOW film, the second FOW film, the third FOW film and the fourth FOW film is 60-100 μm.
[0023] As a further description of the above technical solution:
[0024] The arc heights of the first lead, the second lead, the third lead, and the fourth lead are ≤55 μm.
[0025] The present invention has the following beneficial effects:
[0026] The present invention does not require additional spacer chips or a stepped stacking method to successfully complete the chip stacking work. It can significantly tighten the package size and reduce the package volume. Since the risk of line collapse caused by the height difference of chip stacking is avoided, the stability and reliability of the product are greatly improved, the electrical connection failure caused by line collapse is reduced, and the product defective rate is reduced. By reducing unnecessary materials and process steps, the production cost is reduced and the cost performance of the product is improved. This new structure can also improve the integration of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1This is a schematic structural diagram of a novel stacked package structure proposed by the present invention.
[0028] Legend:
[0029] 1. Substrate; 2. First FOW film; 3. First chip die; 4. Second FOW film; 5. Second chip die; 6. Third FOW film; 7. Third chip die; 8. Fourth FOW film; 9. Fourth chip die; 10. Fourth lead; 11. Third lead; 12. Second lead; 13. First lead; 14. Solder ball. DETAILED DESCRIPTION
[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0031] Reference Figure 1 , the present invention provides a typical embodiment: a new type of stacked packaging structure, the basic structure of which is developed around the substrate 1. On the upper surface of the substrate 1, the first FOW film 2 is laid in sequence. The laying of the first FOW film 2 provides a stable foundation and a good electrical isolation environment for the installation of subsequent components. Next, the first chip die 3 is precisely placed on the first FOW film 2, and then the electrical connection between the substrate 1 and the first chip die 3 is achieved through the first lead 13. After completing this step, the second FOW film 4 is covered above the first lead 13 and the first chip die 3. The covering of the second FOW film 4 not only plays a physical protection role for the components below, but also further enhances the electrical isolation effect. On top of the second FOW film 4, the second chip die 5 is placed. If necessary, the electrical connection between the substrate 1 and the second chip die 5 can be established through the second lead 12.
[0032] As the number of packaging levels increases, the stacked packaging structure is further expanded. A third FOW film 6 and a third chip die 7 are sequentially laid on top of the second chip die 5. Electrical connection is achieved between the substrate 1 and the third chip die 7 via a third lead 11. The third FOW film 6 covers the second lead 12 and the second chip die 5, providing protection and isolation. Similarly, a fourth FOW film 8 and a fourth chip die 9 can be added on top of the third chip die 7. Electrical connection is achieved via a fourth lead 10. The fourth FOW film 8 covers the third lead 11 and the third chip die 7.
[0033] Solder balls 14 are evenly distributed on the bottom of the substrate 1. In actual applications, these solder balls 14 will be soldered to corresponding pads on an external circuit board to achieve electrical connection and mechanical fixation between the package structure and the external circuit.
[0034] In the actual production process, it is crucial to strictly control the dimensional parameters of each component. The thickness of the first FOW film 2, the second FOW film 4, the third FOW film 6 and the fourth FOW film 8 needs to be precisely controlled between 60-100μm. For example, in a specific production batch, the thickness of each layer of FOW film is controlled at about 80μm by high-precision film coating equipment, ensuring the consistency and stability of the film performance. At the same time, the arc height of the first lead 13, the second lead 12, the third lead 11 and the fourth lead 10 needs to be strictly limited to ≤55μm. With the help of advanced wire bonding equipment, the wire bonding parameters are precisely adjusted so that the arc height of each lead is maintained at about 50μm, effectively avoiding the risk of line collapse.
[0035] Thanks to the scientific and rational structural design of this invention, the connections between the various components are tight and stable, fundamentally avoiding the problem of wire collapse caused by chip stack height differences. This provides a solid guarantee for the reliability of the electrical connection, significantly improving the stability and reliability of the product and significantly reducing the product defect rate. Moreover, this innovative structure does not require the addition of additional spacer chips, reducing material usage and process steps. While reducing production costs, it also significantly increases chip integration, meeting the urgent demand for miniaturization, high performance, and low cost in modern electronic products.
[0036] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A novel stacked package structure, characterized by: The invention comprises a substrate (1), wherein the upper surface of the substrate (1) comprises a first FOW film (2), a first chip bare die (3), a first lead (13), a second FOW film (4) and a second chip bare die (5).
2. The novel package-on-package structure according to claim 1, wherein: It includes a second lead (12), a third FOW film (6) and a third chip bare die (7).
3. The novel package-on-package structure according to claim 2, wherein: It includes a third lead (11), a fourth FOW film (8) and a fourth chip bare die (9).
4. The novel package-on-package structure according to claim 1, wherein: A first lead (13) is connected between the substrate (1) and the first chip die (3), or a second lead (12) is connected between the substrate (1) and the second chip die (5).
5. The novel package-on-package structure according to claim 1, wherein: A third lead (11) is connected between the substrate (1) and the third chip bare die (7).
6. The novel package-on-package structure according to claim 1, wherein: The second FOW film (4) covers the first lead (13) and the first chip bare die (3).
7. The novel package-on-package structure according to claim 1, wherein: The third FOW film (6) covers the second lead (12) and the second chip bare die (5).
8. The novel package-on-package structure according to claim 1, wherein: The fourth FOW film (8) covers the third lead (11) and the third chip bare die (7).
9. The novel package-on-package structure according to claim 3, wherein: A solder ball (14) is provided at the bottom of the substrate (1).
10. The novel package-on-package structure according to claim 4, characterized in that: The thickness of the first FOW film (2), the second FOW film (4), the third FOW film (6) and the fourth FOW film (8) is 60-100 μm.
11. The novel package-on-package structure according to claim 5, wherein: The arc heights of the first lead (13), the second lead (12), the third lead (11) and the fourth lead (10) are ≤55 μm.