Memory device and preparation method thereof

Abstract

The invention discloses a memory device and a preparation method thereof, relates to the related technical field of memories, and is used for solving the problems of large voltage loss and high power supply difficulty of an existing memory device. The memory device comprises a substrate layer, the substrate layer is provided with a first surface and a second surface which are opposite, and a memory array structure is located on one side of the first surface; the first interconnection structure penetrates through the first surface and the second surface; and the second interconnection structure is located on the second surface, is electrically connected with the storage array structure through the first interconnection structure, and is used for supplying power to the storage array structure through the first interconnection structure. The electron transmission path is directly and electrically connected with the storage array structure from the second interconnection structure through the first interconnection structure, the number of layers penetrated in the electron transmission process is reduced, and therefore the loss of voltage in the transmission process is reduced. And meanwhile, the second interconnection structure and the storage array structure are respectively positioned on different sides of the substrate layer, so that the power supply difficulty is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of memory-related technologies, and in particular to a memory device and a method for manufacturing the same. Background Art

[0002] In existing memory devices, when the chip's device structure is powered on, voltage is transmitted layer by layer from top to bottom, resulting in voltage loss with each layer. The greater the number of layers, the greater the voltage loss. Furthermore, the contact structure between the conductive layer and the interconnect structure must pass through the memory array structure. As the storage density of the memory array structure increases, the contact structure must be placed away from the memory array structure. Consequently, the contact structure can only be placed around the memory array structure, resulting in a gradually decreasing contact arrangement area, which increases the difficulty of power supply.

[0003] Therefore, there is an urgent need to provide a storage device to solve the above technical problems. Summary of the Invention

[0004] The present application provides a memory device and a method for manufacturing the same, which can solve the problems of large voltage loss and high power supply difficulty in existing memory devices.

[0005] To achieve the above objectives, in a first aspect, the present application provides a storage device comprising:

[0006] a substrate layer having opposing first and second surfaces;

[0007] A storage array structure is located on one side of the first surface;

[0008] a first interconnect structure extending through the first surface and the second surface;

[0009] The second interconnect structure is located on the second surface and is electrically connected to the storage array structure through the first interconnect structure, and is used to supply power to the storage array structure through the first interconnect structure.

[0010] In some embodiments of the present application, the storage device further includes:

[0011] a device structure located between the memory array structure and the substrate layer and electrically connected to the second interconnect structure via the first interconnect structure;

[0012] a third interconnect structure, disposed on the first surface and located between the memory array structure and the device structure, and electrically connecting the memory array structure and the device structure;

[0013] The second interconnect structure is used to supply power to the storage array structure through the first interconnect structure, the device structure, and the third interconnect structure.

[0014] In some embodiments of the present application, the second interconnect structure includes a first conductive layer, a second conductive layer, and a first conductive column connecting the first conductive layer and the second conductive layer; the distance from the first conductive layer to the substrate layer is smaller than the distance from the second conductive layer to the substrate layer, and the first conductive layer is electrically connected to the device structure through the first interconnect structure.

[0015] In some embodiments of the present application, the thickness of the second conductive layer is 5 to 20 times the thickness of the first conductive layer.

[0016] In some embodiments of the present application, the third interconnect structure includes at least two electrically connected metal layers, and the thickness of the metal layer closest to the substrate layer is equal to the thickness of the first conductive layer.

[0017] In some embodiments of the present application, the storage device further includes:

[0018] An array region and a peripheral region, wherein the storage array structure is located in the array region;

[0019] The first power terminal is located in the peripheral area and on a side of the second conductive layer away from the substrate layer, and is electrically connected to the device structure through the second interconnection structure and the first interconnection structure.

[0020] In some embodiments of the present application, the storage device further includes:

[0021] a device structure disposed on the second surface, electrically connected to the second interconnect structure, and electrically connected to the memory array structure through the first interconnect structure;

[0022] The second interconnect structure is used to supply power to the storage array structure through the device structure and the first interconnect structure.

[0023] In some embodiments of the present application, the storage device further includes:

[0024] a fourth interconnect structure, disposed between the substrate layer and the memory array structure, and electrically connecting the first interconnect structure and the memory array structure;

[0025] An array region and a peripheral region, wherein the storage array structure is located in the array region;

[0026] The second power terminal is located in the peripheral area, is provided on one side of the first surface, and is electrically connected to the device structure through the fourth interconnection structure and the first interconnection structure.

[0027] In some embodiments of the present application, the second interconnect structure includes a metal interconnect layer, a third conductive layer, and a second conductive pillar connecting the metal interconnect layer and the third conductive layer, wherein the metal interconnect layer is located between the substrate layer and the third conductive layer;

[0028] The thickness of the second power terminal is equal to the thickness of the third conductive layer.

[0029] In a second aspect, the present application further provides a method for preparing a memory device, comprising:

[0030] providing a substrate layer;

[0031] forming a memory array structure on one side of the first surface of the substrate layer;

[0032] forming a first interconnect structure penetrating the first surface and the second surface of the substrate layer;

[0033] A second interconnect structure is formed on the second surface of the substrate layer, and the second interconnect structure is electrically connected to the memory array structure through the first interconnect structure.

[0034] The above technical solution of this application has at least the following beneficial effects:

[0035] In this technical solution, the first interconnect structure runs from the first surface of the substrate layer to the second surface, so that the electron transmission path can be directly connected to the storage array structure through the first interconnect structure from the second interconnect structure, shortening the electron transmission path and reducing the number of layers passed through during electron transmission, thereby significantly reducing the voltage loss during transmission. At the same time, the second interconnect structure and the storage array structure are located on different sides of the substrate layer, so that the second interconnect structure does not need to pass through the storage array structure to establish an electrical connection, avoiding the squeezing of the arrangement area of ​​the second interconnect structure due to the increased storage density of the storage array structure. The second surface of the substrate layer has a larger area for arranging the second interconnect structure, thereby reducing the difficulty of power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is a top view of an embodiment of a memory device;

[0038] Figure 2 yes Figure 1 A cross-sectional view of the cross section of the middle A region;

[0039] Figure 3 is a schematic diagram of a cross section of a memory device in an embodiment of the present application;

[0040] Figure 4 yes Figure 3 Schematic cross-sections of some specific implementations of the illustrated embodiment;

[0041] Figure 5 is a schematic diagram of a cross section of another memory device in an embodiment of the present application;

[0042] Figure 6 yes Figure 5 Schematic cross-sections of some specific implementations of the illustrated embodiment;

[0043] Figures 7 to 10 It is a schematic cross-sectional structural diagram of the storage device formation process according to an embodiment of the present application.

[0044] Description of reference numerals:

[0045] 1-substrate layer; 11-first surface; 12-second surface; 2-storage array structure; 3-first interconnection structure; 4-second interconnection structure; 41-first conductive layer; 42-second conductive layer; 43-first conductive pillar; 44-metal interconnection layer; 45-third conductive layer; 46-second conductive pillar; 5-device structure; 6-third interconnection structure; 61-metal layer; 7-first power terminal; 8-first passivation layer; 9-fourth interconnection structure; 91-fourth conductive layer; 92-fifth conductive layer; 10-second power terminal; 1a-array area; 1b-peripheral area; 100-carrier; 200-contact structure; 300-conductive layer. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0047] In the description of this application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0048] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0049] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0050] As described in the background, in existing memory devices, voltage is transmitted layer by layer from top to bottom, resulting in voltage loss with each layer. The greater the number of layers, the greater the voltage loss. As the storage density of memory array structures increases, the contact structure needs to be positioned away from the memory array structure. Consequently, the contact structure can only be placed around the memory array structure, resulting in a gradually decreasing contact arrangement area and increasing the difficulty of power supply.

[0051] In one embodiment, if Figure 1 and Figure 2 As shown, the conductive layer 300 and the memory array structure 2 of the memory device are both located on the same side of the substrate layer 1 , and the conductive layer 300 is located on the side of the memory array structure 2 facing away from the substrate layer 1 .

[0052] In this embodiment, when the device structure is powered on, electrons must pass through the conductive layer 300, then through the storage array structure 2, and then gradually through the interconnect structure 400 to the transistor. The voltage is transmitted layer by layer from top to bottom, and voltage loss occurs in each layer. The more layers there are, the greater the voltage loss.

[0053] In addition, the contact structure 200 between the conductive layer 300 and the interconnection structure 400 needs to pass through the storage array structure 2. As the storage density of the storage array structure 2 gradually increases, the contact structure 200 needs to avoid the storage array structure 2. The contact structure 200 can only be set around the storage array structure 2, resulting in the arrangement area of ​​the contact structure 200 gradually decreasing, thereby increasing the difficulty of power supply.

[0054] To address the above-mentioned issues, the technical solution of this application provides a memory device and a method for manufacturing the same, which are described in detail below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments of this application. Furthermore, in the following embodiments, the description of each embodiment has its own focus. For any portion not described in detail in one embodiment, please refer to the relevant description of other embodiments.

[0055] Please refer to Figure 3 and Figure 4The memory device includes a substrate layer 1, a memory array structure 2, a first interconnect structure 3, and a second interconnect structure 4. The substrate layer 1 has a first surface 11 and a second surface 12 opposite to each other. The memory array structure 2 is located on one side of the first surface 11, and the first interconnect structure 3 penetrates the first surface 11 and the second surface 12. The second interconnect structure 4 is located on the second surface 12 and is used to supply power to the memory array structure 2 through the first interconnect structure 3.

[0056] In this technical solution, the first interconnect structure 3 runs from the first surface 11 of the substrate layer 1 to the second surface 12, so that the electron transmission path can be directly connected to the storage array structure 2 through the first interconnect structure 3 from the second interconnect structure 4, shortening the electron transmission path and reducing the number of layers passed through during electron transmission, thereby significantly reducing the voltage loss during transmission. At the same time, the second interconnect structure 4 and the storage array structure 2 are located on different sides of the substrate layer 1, so that the second interconnect structure 4 does not need to pass through the storage array structure 2 to establish an electrical connection, avoiding the squeezing of the arrangement area of ​​the second interconnect structure 4 due to the increased storage density of the storage array structure 2. There is a larger area on the second surface 12 of the substrate layer 1 to arrange the second interconnect structure 4, thereby reducing the difficulty of power supply.

[0057] like Figure 3 and Figure 4 As shown, in some embodiments of the present application, the storage device further includes a device structure 5, which is located between the storage array structure 2 and the substrate layer 1, and is electrically connected to the second interconnection structure 4 through the first interconnection structure 3. As a result, the transmission path (i.e., the power supply distance) of the signal from the second interconnection structure 4 to the device structure 5 is shortened, the signal transmission delay is reduced, and it helps to improve the overall read and write speed and data processing efficiency of the storage device, and solves the problem of insufficient power supply. At the same time, the shorter transmission path reduces the attenuation and interference of the signal during transmission, ensuring the integrity and accuracy of the signal. In addition, even if the second interconnection structure 4 is revised, it will not be affected by the storage array structure 2, saving costs.

[0058] It should be noted that the device structure 5 is arranged on the first surface 11, and the second interconnect structure 4 is located on the second surface 12. One end of the above-mentioned first interconnect structure 3 is electrically connected to the device structure 5, and the other end passes through the second surface 12 and at least partially extends out of the second surface 12. There is no need to additionally make complex wiring layers or through-holes on the second surface 12. The extended part of the first interconnect structure 3 is directly used to achieve its electrical connection with the second interconnect structure 4, thereby simplifying the packaging process and reducing the intermediate interconnection layers.

[0059] The second interconnect structure 4 includes a first conductive layer 41 and a second conductive layer 42. The distance between the first conductive layer 41 and the substrate layer 1 is smaller than the distance between the second conductive layer 42 and the substrate layer 1. The first conductive layer 41 is located on one side of the second surface 12 and is electrically connected to the device structure 5 through the first interconnect structure 3. The second conductive layer 42 is located on one side of the second surface 12 and is electrically connected to the first conductive layer 41. The layered design of the first conductive layer 41 and the second conductive layer 42 allows signals with different functions to be transmitted independently in their respective conductive layers. Isolating different signals can avoid crosstalk and interference between signals, ensure stable and reliable operation of the memory device, and help improve the integrity and accuracy of signal transmission.

[0060] In addition, the distance from the first conductive layer 41 to the substrate layer 1 is smaller than the distance from the second conductive layer 42 to the substrate layer 1. This layered layout in the vertical direction provides more flexibility for wiring. On the side of the second surface 12, the first conductive layer 41 and the second conductive layer 42 can be independently wired. Layered wiring can make signal lines more orderly, reduce wiring conflicts and intersections, and improve the integration of the chip. For example, the first conductive layer 41 can use the area close to the substrate layer 1 for more dense wiring, which is used to connect the device structure 5 and some signal lines that need to be controlled at close range. The second conductive layer 42 can be wired in an area relatively far away from the substrate layer 1 to connect more external interfaces or transmit high-speed signals, making full use of the space resources on the chip surface.

[0061] Based on the above embodiment, the second interconnect structure 4 further includes a first conductive pillar 43, which is located between the first conductive layer 41 and the second conductive layer 42 and electrically connects the first conductive layer 41 and the second conductive layer 42. The first conductive pillar 43 serves as a direct connection channel between the first conductive layer 41 and the second conductive layer 42, providing a shorter transmission path for the current. Compared with a wiring detour connection, the conductive pillar can reduce the resistance during the current transmission process, thereby reducing power consumption and the Joule heat generated during the current transmission process. At the same time, it can ensure that the current is transmitted more quickly between the first conductive layer 41 and the second conductive layer 42 through the first conductive pillar 43, reducing signal transmission delay and improving the read and write speed of the storage device.

[0062] In some embodiments of the present application, the thickness of the second conductive layer 42 is 5 to 20 times the thickness of the first conductive layer 41. Due to the relatively thick thickness of the second conductive layer 42, its resistance will be significantly reduced when other conditions such as material and cross-sectional area are similar. Smaller resistance means that when current passes through the second conductive layer 42 for global power supply, the voltage drop generated will be reduced, and the stable power supply voltage can ensure the normal operation of the storage device and accurate reading and writing of data. In addition, when the thickness of the second conductive layer 42 is larger, it is ensured that it can withstand higher current density without electromigration failure, thereby improving the reliability and service life of the storage device. For example, the thickness of the first conductive layer 41 is 2000 angstroms and the thickness of the second conductive layer 42 is 10,000 angstroms. Alternatively, the thickness of the first conductive layer 41 is 1000 angstroms and the thickness of the second conductive layer 42 is 10,000 angstroms.

[0063] At the same time, due to the greater thickness and lower resistance of second conductive layer 42, the power supply voltage can be effectively and evenly distributed across all memory cells. Even if different locations in the memory array have varying current demands, the thicker second conductive layer 42 ensures a substantially consistent power supply voltage across all locations. This ensures that each memory cell receives a stable power supply voltage, preventing data errors or memory cell damage caused by localized power shortages or oversupply, thereby improving the overall performance and data reliability of the memory.

[0064] For example, the thickness of the second conductive layer 42 is 5 times the thickness of the first conductive layer 41; the thickness of the second conductive layer 42 is 8 times the thickness of the first conductive layer 41, the thickness of the second conductive layer 42 is 10 times the thickness of the first conductive layer 41, the thickness of the second conductive layer 42 is 12 times the thickness of the first conductive layer 41, the thickness of the second conductive layer 42 is 15 times the thickness of the first conductive layer 41, the thickness of the second conductive layer 42 is 17 times the thickness of the first conductive layer 41, or the thickness of the second conductive layer 42 is 20 times the thickness of the first conductive layer 41.

[0065] It should be noted that the first conductive layer 41 may be a single conductive layer or a stack of at least two conductive layers. In the case where the first conductive layer 41 is a stack of at least two conductive layers, the thickness of the second conductive layer 42 is 5 to 20 times the thickness of the first conductive layer 41 closest to the substrate layer 1 among the multiple first conductive layers 41.

[0066] Please continue to refer to Figure 3 and Figure 4In some embodiments of the present application, the memory device further includes a third interconnect structure 6, which is disposed on the first surface 11 and is located between the memory array structure 2 and the device structure 5. The third interconnect structure 6 electrically connects the memory array structure 2 and the device structure 5, effectively establishing an electrical connection between the memory array structure 2 and the device structure 5, and directly interacting the signal and power requirements of the memory array structure 2 with the device structure 5. The third interconnect structure 6 can provide a direct connection channel to enable communication between the memory cells in the memory array structure 2 and the control logic of the device structure 5, thereby avoiding signal attenuation and interference during long-distance transmission.

[0067] Furthermore, the third interconnect structure 6 includes at least two electrically connected metal layers 61. The thickness of the metal layer 61 closest to the substrate layer 1 is equal to that of the first conductive layer 41. Therefore, during current transmission, the resistance of the metal layer 61 matches that of the first conductive layer 41, facilitating impedance matching. When signals are transmitted between these two layers, reflections are reduced, enabling more complete signal transmission and preventing data loss and bit errors.

[0068] In some embodiments, the memory device includes an array region 1a and a peripheral region 1b, with a memory array structure 2 located within the array region 1a. The memory device also includes a first power terminal 7 located within the peripheral region 1b and on the side of the second conductive layer 42 away from the substrate layer 1. The first power terminal 7 is electrically connected to the device structure 5 via the second interconnect structure 4 and the first interconnect structure 3, respectively, thereby achieving rational utilization of space resources. The first interconnect structure 3 and the second interconnect structure 4 of the array region 1a and the peripheral region 1b can be fabricated in the same process.

[0069] In addition, the memory device further includes a first passivation layer 8 disposed on a side of the second conductive layer 42 away from the first conductive layer 41. The first passivation layer 8 may have one or more openings for encapsulating and forming a first power terminal 7. At least one first power terminal 7 is in contact with the second conductive layer 42. The second conductive layer 42 may be formed of a conductive material such as W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. In some embodiments, other conductive materials may also be used.

[0070] Among them, the above-mentioned first power terminal 7 is made of material Al, and the second conductive layer 42 is also made of material Al. The part of the second conductive layer 42 exposed to the above-mentioned opening is used to constitute the first power terminal 7 and can also serve as a wiring layer, thereby saving the production cost of the device structure 5.

[0071] Please refer to Figure 5 and Figure 6In some other embodiments of the present application, the storage device further includes a device structure 5. The device structure 5 is located on the second surface 12, is electrically connected to the second interconnect structure 4, and is electrically connected to the storage array structure 2 through the first interconnect structure 3. The second interconnect structure 4 is used to supply power to the storage array structure 2 through the device structure 5 and the first interconnect structure 3. Since the second interconnect structure 4 and the storage array structure 2 are respectively located on different sides of the substrate layer 1, the substrate layer 1 can separate the second interconnect structure 4 from the storage array structure 2, so that the second interconnect structure 4 and the storage array structure 2 can be completed independently in different process steps. The storage array structure 2 is connected to the second interconnect structure 4 on the second surface 12 through the first interconnect structure 3 to avoid mutual constraints between the two at the same process stage. At the same time, it is ensured that the power supply of the second interconnect structure 4 is no longer affected by the layout of the storage array structure 2.

[0072] The second interconnect structure 4 includes a metal interconnect layer 44 and a third conductive layer 45. The metal interconnect layer 44 is disposed on the second surface 12 and located between the substrate layer 1 and the third conductive layer 45. The metal interconnect layer 44 is electrically connected to the third conductive layer 45 and is electrically connected to the storage array structure 2 through the first interconnect structure 3. The metal interconnect layer 44 is located on the second surface 12 and between the substrate layer 1 and the third conductive layer 45. This layered design makes the transmission path of signals and power clearer. Signals with different functions can be transmitted independently in different layers, reducing mutual interference between signals. Increasing the thickness of the third conductive layer 45 or using a material with high conductivity can enable it to withstand large currents without overheating or burning.

[0073] Among them, the second interconnect structure 4 also includes a second conductive column 46, which is located between the metal interconnect layer 44 and the third conductive layer 45, and is electrically connected to the metal interconnect layer 44 and the third conductive layer 45. It has the same technical effect as the first conductive column 43 in the above technical solution, and this application will not repeat it here.

[0074] In some embodiments of the present application, the memory device further includes a fourth interconnect structure 9, which is disposed between the substrate layer 1 and the memory array structure 2 and electrically connects the first interconnect structure 3 to the memory array structure 2. The fourth interconnect structure 9 provides an additional electrical connection channel, enhancing the reliability of the electrical connection between the first interconnect structure 3 and the memory array structure 2. Through reasonable layout and design, the fourth interconnect structure 9 can optimize the signal transmission environment and improve the overall performance of the memory. For example, the fourth interconnect structure 9 includes a fourth conductive layer 91 and a fifth conductive layer 92. The distance between the fourth conductive layer 91 and the substrate layer 1 is less than the distance between the fifth conductive layer 92 and the substrate layer 1. The fourth conductive layer 91 and the fifth conductive layer 92 are used to connect the contact terminals of the bitline selector and the wordline driver, ensuring signal integrity during transmission and reducing signal attenuation and interference. Through the contact terminal connection, the circuit connections of the bitline selector and the wordline driver can be integrated and optimized, reducing the number and complexity of external wiring. At the same time, it can also accelerate the signal exchange speed between the bitline selector and the wordline driver, thereby improving the response speed of the memory and meeting the requirements of high-speed data processing.

[0075] It should be noted that the device structure 5 is arranged on the second surface 12, and the fourth interconnect structure 9 is located on the first surface 11. One end of the above-mentioned first interconnect structure 3 is electrically connected to the device structure 5, and the other end passes through the second surface 12 and at least partially extends out of the first surface 11. Therefore, there is no need to additionally make complex wiring layers or through-holes on the first surface 11. The extended part of the first interconnect structure 3 is directly used to realize its electrical connection with the fourth interconnect structure 9, thereby simplifying the packaging process and reducing the intermediate interconnection layers.

[0076] In some embodiments of the present application, the memory device includes an array area 1a and a peripheral area 1b, and the memory array structure 2 is located in the array area 1a. The memory device also includes a second power terminal 10. The second power terminal 10 is located in the peripheral area 1b and is arranged on one side of the first surface 11. The second power terminal 10 is electrically connected to the device structure 5 through the fourth interconnection structure 9 and the first interconnection structure 3. The present application arranges the second power terminal 10 in the peripheral area 1b to facilitate connection to an external power supply during packaging and system-level integration. The second power terminal 10 in the peripheral area 1b is more easily connected to an external circuit such as a printed circuit board through pins or pads, reducing the complexity of the power connection. Among them, the fourth interconnection structure 9, the first interconnection structure 3 and the second interconnection structure 4 in the array area 1a and the peripheral area 1b can all be prepared in the same process.

[0077] In some embodiments of the present application, the thickness of the second power terminal 10 is equal to the thickness of the third conductive layer 45, allowing the second power terminal 10 and the third conductive layer 45 to be processed using similar process parameters. For example, when depositing a metal layer of the same thickness, the same deposition rate, time, and process conditions can be used. This consistency simplifies the manufacturing process and improves process repeatability and stability. It also reduces the need for process adjustments due to thickness differences, lowering production costs and manufacturing difficulty.

[0078] In some embodiments of the present application, the memory device further includes multiple dielectric structures, each of which is disposed around the periphery of the second interconnect structure 4, the third interconnect structure 6, and the fourth interconnect structure 9. The dielectric structures provide electrical insulation to isolate the different conductive layers within each interconnect structure, thereby preventing direct contact between the different conductive layers and causing a short circuit. Each dielectric structure can also fill the space surrounding the corresponding interconnect structure to prevent loosening or displacement of the structure, thereby enhancing the stability of the entire memory device.

[0079] In some embodiments of the present application, the present application provides a method for preparing a memory device, which includes: providing a substrate layer 1; forming a memory array structure 2 on one side of a first surface 11 of the substrate layer 1; forming a first interconnect structure 3 that penetrates the first surface 11 and reaches the second surface 12 of the substrate layer 1; forming a second interconnect structure 4 on the second surface 12 of the substrate layer 1, the second interconnect structure 4 being electrically connected to the memory array structure 2 through the first interconnect structure 3.

[0080] In this technical solution, the storage device obtained by the above-mentioned preparation method has a first interconnect structure 3 that extends from the first surface 11 of the substrate layer 1 to the second surface 12, so that the electron transmission path can be directly electrically connected to the storage array structure 2 through the first interconnect structure 3 from the second interconnect structure 4, shortening the electron transmission path and reducing the number of layers passed through during electron transmission, thereby significantly reducing the voltage loss during transmission. At the same time, the second interconnect structure 4 and the storage array structure 2 are respectively located on different sides of the substrate layer 1, so that the second interconnect structure 4 does not need to pass through the storage array structure 2 to establish an electrical connection, avoiding the squeezing of the arrangement area of ​​the second interconnect structure 4 due to the increased storage density of the storage array structure 2. The second surface 12 of the substrate layer 1 has a larger area for arranging the second interconnect structure 4, thereby reducing the difficulty of power supply.

[0081] Accordingly, the present invention also provides a method for forming a memory device, specifically Figures 7 to 9 shown.

[0082] Please refer to Figure 7, providing a substrate layer 1, the substrate layer 1 having a first surface 11 and a second surface 12 arranged opposite to each other; forming a third interconnect structure 6 on one side of the first surface 11 of the substrate layer 1, and forming a storage array structure 2 on the side of the third interconnect structure 6 facing away from the substrate layer 1.

[0083] Please refer to Figure 8 After forming the memory array structure 2 and before forming the first interconnect structure 3 extending from the first surface 11 to the second surface 12, the method for manufacturing the memory device further includes bonding a carrier wafer 100 to the side of the memory array structure 2 facing away from the substrate layer 1, and flipping the substrate layer 1. With the above design, flipping the substrate layer 1 after bonding the carrier wafer 100 allows the memory array structure 2, originally located above, to be flipped to the bottom of the substrate layer 1, exposing the other side surface (second surface 12) of the substrate layer 1 to the top, facilitating subsequent processing.

[0084] In some embodiments, as Figure 9 As shown, the first interconnect structure 3 formed from the first surface 11 to the second surface 12 directly connects the circuits of the first surface 11 and the second surface 12, avoiding long-distance winding transmission of signals, thereby significantly reducing signal transmission delay, which is particularly important for high-speed signal transmission systems, such as data transmission between high-speed computer processors and memory.

[0085] Please refer to Figure 10 A second interconnect structure 4 is formed on the second surface 12 of the substrate layer 1. The second interconnect structure 4 is electrically connected to the memory array structure 2 or the device structure 5 through the first interconnect structure 3. For example, a first conductive layer 41, a first conductive pillar 43, and a second conductive layer 42 are sequentially formed on the second surface 12 of the substrate layer 1.

[0086] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0087] The above are only specific implementation methods of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims. In addition, the specification uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. The content of this specification should not be understood as limiting the present application.

Claims

1. A memory device, characterized in that: include: a substrate layer having opposing first and second surfaces; a storage array structure, located on one side of the first surface; a first interconnection structure extending through the first surface and the second surface; A second interconnect structure is located on the second surface and is electrically connected to the storage array structure through the first interconnect structure, and is used to supply power to the storage array structure through the first interconnect structure.

2. The memory device according to claim 1, wherein: The storage device further includes: a device structure, located between the memory array structure and the substrate layer, and electrically connected to the second interconnect structure through the first interconnect structure; a third interconnect structure, disposed on the first surface and located between the memory array structure and the device structure, and electrically connecting the memory array structure and the device structure; The second interconnect structure is used to supply power to the storage array structure through the first interconnect structure, the device structure, and the third interconnect structure.

3. The memory device according to claim 2, wherein: The second interconnect structure includes a first conductive layer, a second conductive layer, and a first conductive column connecting the first conductive layer and the second conductive layer; the distance from the first conductive layer to the substrate layer is smaller than the distance from the second conductive layer to the substrate layer, and the first conductive layer is electrically connected to the device structure through the first interconnect structure.

4. The memory device according to claim 3, wherein: The thickness of the second conductive layer is 5 to 20 times the thickness of the first conductive layer.

5. The memory device according to claim 3, wherein: The third interconnect structure includes at least two electrically connected metal layers, and the thickness of the metal layer closest to the substrate layer is equal to the thickness of the first conductive layer.

6. The memory device according to claim 3, wherein: The storage device further includes: an array region and a peripheral region, wherein the storage array structure is located in the array region; The first power terminal is located in the peripheral area and on a side of the second conductive layer away from the substrate layer, and is electrically connected to the device structure through the second interconnect structure and the first interconnect structure.

7. The memory device according to claim 1, wherein: The storage device further includes: a device structure, located on the second surface, electrically connected to the second interconnect structure, and electrically connected to the memory array structure through the first interconnect structure; The second interconnect structure is used to supply power to the storage array structure through the device structure and the first interconnect structure.

8. The memory device according to claim 7, wherein: The storage device further includes: a fourth interconnect structure, disposed between the substrate layer and the memory array structure, and electrically connecting the first interconnect structure and the memory array structure; An array region and a peripheral region, wherein the memory array structure is located in the array region; the memory device further comprises: A second power terminal is located in the peripheral area, is provided on one side of the first surface, and is electrically connected to the device structure through the fourth interconnection structure and the first interconnection structure.

9. The memory device according to claim 8, wherein: The second interconnect structure includes a metal interconnect layer, a third conductive layer, and a second conductive pillar connecting the metal interconnect layer and the third conductive layer, wherein the metal interconnect layer is located between the substrate layer and the third conductive layer; The thickness of the second power terminal is equal to the thickness of the third conductive layer.

10. A method for preparing a memory device, characterized in that: include: providing a substrate layer; forming a storage array structure on one side of the first surface of the substrate layer; forming a first interconnect structure penetrating the first surface and the second surface of the substrate layer; A second interconnect structure is formed on the second surface of the substrate layer, and the second interconnect structure is electrically connected to the memory array structure through the first interconnect structure.

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