Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, the semiconductor structure comprises a first combination structure, the first combination structure comprises a substrate, a plurality of first chips and a second conductive interconnection structure, the substrate comprises a plurality of first areas and a second area, the plurality of first chips are respectively arranged on one side, facing a first direction, of the substrate and are respectively in bonding connection with the substrate in the first region, each first chip further comprises a first conductive interconnection structure, the first conductive interconnection structure extends from the first region to the second region, and the second conductive interconnection structure extends from the first region to the second region. The second conductive interconnection structure is arranged on the side, facing the first direction, of the substrate and located in the second area, and the second conductive interconnection structure is in bonding connection with the first conductive interconnection structures. According to the semiconductor structure, three-dimensional integration can be achieved, meanwhile, the packaging thickness is reduced, the use amount of TSVs is reduced, and the cost is reduced. And the device performance of the three-dimensional semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Three-dimensional integration technology has been widely used in cloud computing, artificial intelligence (AI), high-performance computing (HPC) and other fields. The bonding methods of three-dimensional integration technology include wafer-to-wafer, chip-to-chip and wafer-to-chip.

[0003] Chip thickness can't be reduced indefinitely. For example, when the thickness of a dynamic random access memory (DRAM) chip is reduced to a certain level, data retention issues may occur. Therefore, chips have certain thickness requirements. However, as chip performance improves, the number of layers in three-dimensional integration also increases accordingly. When chips with many layers are stacked vertically, the overall thickness increases, significantly increasing packaging costs.

[0004] In addition, multi-layer chip stacking technology requires the use of a large number of through-silicon vias (TSVs), and the stress of TSVs can adversely affect three-dimensional semiconductor devices and reduce their performance. Summary of the Invention

[0005] The present application provides a semiconductor structure that can effectively reduce the package thickness, reduce the use of TSVs, and improve the device performance of three-dimensional semiconductor devices while achieving three-dimensional integration.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor structure, which includes a first combination structure, wherein the first combination structure includes: a substrate, including multiple first regions and one second region; multiple first chips, respectively arranged on a side of the substrate facing a first direction, and respectively bonded to the substrate in the first region, each of the first chips also including a first conductive interconnect structure, the first conductive interconnect structure extending from the first region to the second region; a second conductive interconnect structure, arranged on a side of the substrate facing the first direction and located in the second region, the second conductive interconnect structure being bonded to each of the first conductive interconnect structures.

[0007] Optionally, the first chip includes a first bonding layer, the substrate includes a second bonding layer, the first bonding layer and the second bonding layer are bonded to each other, and the bonding method of the first bonding layer and the second bonding layer includes fusion bonding or adhesive bonding.

[0008] Optionally, the first conductive interconnect structure includes a first metal layer, the second conductive interconnect structure includes a second metal layer, the first metal layer and the second metal layer are bonded to each other, and the bonding method between the first metal layer and the second metal layer includes metal bonding.

[0009] Optionally, the first bonding layer and the second bonding layer are bonded to each other at a side of the first bonding layer facing the substrate, and the first metal layer and the second metal layer are bonded to each other at a side of the first metal layer facing the substrate.

[0010] Optionally, the first metal layer includes a first portion disposed in the second area, and an orthographic projection of the second metal layer on the substrate covers an orthographic projection of the first portion on the substrate.

[0011] Optionally, the first metal layer further includes a second portion disposed in the first region, the second portion is connected to the first portion, and a width of the second portion is smaller than that of the first portion.

[0012] Optionally, the first portion includes a plurality of first sub-portions, and the first metal layer further includes a second portion disposed in the first region, and the second portion is electrically connected to the plurality of first sub-portions.

[0013] Optionally, the semiconductor structure further includes: a filling dielectric layer, which is arranged on the side of the first combination structure facing the first direction and is located in the first region and / or the second region, and the filling dielectric layer is used to fill the surface of the first combination structure facing the first direction in the first region and the second region, and / or, in the difference between the two first regions.

[0014] Optionally, the semiconductor structure further includes: a passivation layer, which is arranged on the side of the first combined structure facing the first direction, wherein the passivation layer includes a plurality of first openings and one second opening, the first openings exposing at least a portion of the first conductive interconnect structure, and the second openings exposing at least a portion of the second conductive interconnect structure.

[0015] Optionally, the first combined structure includes: a first wafer, the first wafer including the substrate and the second conductive interconnect structure.

[0016] Optionally, the first combined structure includes: a first wafer, the first wafer including the substrate; a second chip, arranged on a side of the substrate facing the first direction and bonded to the substrate in a second region, wherein the second chip includes the second conductive interconnect structure.

[0017] Optionally, the semiconductor structure further includes: a third bonding layer, the third bonding layer being disposed on a side of the first combined structure facing the first direction, the third bonding layer including a plurality of connecting portions, the connecting portions being electrically connected to the first conductive interconnect structure and / or the second conductive interconnect structure;

[0018] The second wafer is arranged on a side of the third bonding layer away from the substrate, and the second wafer is electrically connected to the first conductive interconnect structure and / or the second conductive interconnect structure through the connecting portion.

[0019] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising the following steps:

[0020] Providing a substrate, forming a second conductive interconnect structure on a side of the substrate facing a first direction, the substrate comprising a plurality of first regions and a second region, and the second conductive interconnect structure is located in the second region;

[0021] A plurality of first chips are formed on a side of the substrate facing the first direction, each of the first chips is correspondingly arranged on a plurality of the first regions and bonded to the substrate, wherein the first chip also includes a first conductive interconnect structure, the first conductive interconnect structure extends from the first region to the second region and is bonded to the second conductive interconnect structure.

[0022] The present application provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure includes a first combination structure, the first combination structure includes a substrate, multiple first chips and a second conductive interconnection structure, wherein the substrate includes multiple first regions and a second region, the multiple first chips are respectively arranged on a side of the substrate facing a first direction, and are respectively bonded to the substrate in the first region, each first chip also includes a first conductive interconnection structure, the first conductive interconnection structure extends from the first region to the second region, the second conductive interconnection structure is arranged on a side of the substrate facing the first direction and is located in the second region, and the second conductive interconnection structure is bonded to each of the first conductive interconnection structures. The semiconductor structure provided by the present application can reduce the packaging thickness, reduce the use of TSV, and improve the device performance of three-dimensional semiconductor devices while achieving three-dimensional integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1a It is a planar schematic diagram of a substrate in a semiconductor structure provided in some embodiments of the present application.

[0024] Figure 1b This is a schematic plan view of two first chips in a semiconductor structure provided in some embodiments of the present application.

[0025] Figure 1c This is a planar schematic diagram of a substrate and two first chips in a semiconductor structure provided by some embodiments of the present application.

[0026] Figure 1d Some embodiments of this application provide Figure 1c Schematic diagram of the cross section of the semiconductor structure taken along line AA' in FIG.

[0027] Figure 2 It is a cross-sectional schematic diagram of the first wafer provided in some embodiments of the present application.

[0028] Figure 3 This is a cross-sectional schematic diagram of one of the first chips provided in some embodiments of the present application.

[0029] Figure 4a This is a partial planar schematic diagram of a first metal layer and a second metal layer provided in some embodiments of the present application.

[0030] Figure 4b This is a partial plan view of another first metal layer and a second metal layer provided in some embodiments of the present application.

[0031] Figure 4c This is a partial plan view of another first metal layer and a second metal layer provided in some embodiments of the present application.

[0032] Figure 5 Some embodiments of this application provide Figure 1c A schematic cross-sectional view of another semiconductor structure taken along line AA' in FIG.

[0033] Figure 6 Some embodiments of this application provide Figure 1c A schematic cross-sectional view of another semiconductor structure taken along line AA' in FIG.

[0034] Figure 7 It is a flow chart of a method for preparing a semiconductor structure provided in some embodiments of the present application.

[0035] Figure 8 3 is a schematic cross-sectional view of a first wafer that has not been etched, provided in some embodiments of the present application.

[0036] Figure 93 is a schematic cross-sectional view of a first chip that has not been etched, provided in some embodiments of the present application.

[0037] Figure 10 This is a cross-sectional schematic diagram of another first chip that has not been etched, provided in some embodiments of the present application.

[0038] Figure 11 It is a cross-sectional schematic diagram of the first wafer provided in some embodiments of the present application.

[0039] Figure 12 It is a cross-sectional schematic diagram of the second chip provided in some embodiments of the present application.

[0040] Figure 13 Some embodiments of this application provide Figure 1c Schematic diagram of the cross section of the semiconductor structure taken along line AA' in FIG.

[0041] Figure 14 Some embodiments of this application provide Figure 1c A schematic cross-sectional view of another semiconductor structure taken along line AA' in FIG.

[0042] Description of reference numerals:

[0043] Substrate 10; substrate 10'; first region 11; second region 12; second bonding layer 13; second bonding layer 13'; conductive portion 131'; first chip 20; first conductive interconnect structure 21; first bonding layer 22; second conductive interconnect structure 30; filling dielectric layer 40; passivation layer 50; second chip 60; third bonding layer 70; connecting portion 71; first metal layer M1; first portion M11; first sub-portion M111; second portion M12; second metal layer M2; first opening H1; second opening H2; first wafer A1; first wafer A1'; second wafer A2; first direction Y; DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0045] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, examples of various specific processes and materials are provided in the present application, but a person of ordinary skill in the art will recognize the application of other processes and / or the use of other materials. Each of the following is described in detail. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0046] Example 1

[0047] Figure 1a is a schematic plan view of a substrate in a semiconductor structure provided by some embodiments of the present application; Figure 1b is a schematic plan view of two first chips in a semiconductor structure provided by some embodiments of the present application; Figure 1c is a schematic plan view of a substrate and two first chips in a semiconductor structure provided by some embodiments of the present application; Figure 1d Some embodiments of this application provide Figure 1c Schematic diagram of the cross section of the semiconductor structure cut along line AA' in FIG. Figure 1a 、 Figure 1b 、 Figure 1c and Figure 1d As shown, an embodiment of the present application provides a semiconductor structure, comprising a first composite structure, the first composite structure comprising a substrate 10, a plurality of first chips 20, and a second conductive interconnect structure 30. The substrate 10 comprises a plurality of first regions 11 and a second region 12; the plurality of first chips 20 are respectively disposed on a side of the substrate 10 facing a first direction Y and are respectively bonded to the substrate 10 in the first regions 11; each first chip 20 further comprises a first conductive interconnect structure 21, the first conductive interconnect structure 21 extending from the first region 11 to the second region 12; the second conductive interconnect structure 30 is disposed on a side of the substrate 10 facing the first direction Y and located in the second region 12, and is bonded to each of the first conductive interconnect structures 21.

[0048] In the semiconductor structure provided in the embodiment of the present application, the first combined structure includes a substrate 10, a plurality of first chips 20, and a second conductive interconnect structure 30, wherein the plurality of first chips 20 arranged on the same side of the substrate 10 (i.e., the side of the substrate 10 facing the first direction Y) are bonded to the substrate 10 in the plurality of first regions 11, thereby achieving a horizontal arrangement of the plurality of first chips 20 and reducing the overall thickness of the first combined structure. In addition, since each of the first chips 20 also includes a first conductive interconnect structure 21, and the first conductive interconnect structure 21 extends from the first region 11 to the second region 12, electrical connection between the plurality of first chips 20 can be achieved by bonding each of the first conductive interconnect structures 21 to the second conductive interconnect structure 30 arranged in the second region 12. This can greatly reduce the use of TSVs while achieving high-density three-dimensional integration, thereby avoiding the problem of device performance degradation caused by the adverse effects of TSV stress on three-dimensional semiconductor devices, thereby improving the device performance of the semiconductor structure.

[0049] Figure 2 is a schematic cross-sectional view of a first wafer provided in some embodiments of the present application; Figure 3 FIG. 1 is a cross-sectional diagram of one of the first chips provided in some embodiments of the present application. Figure 2 and Figure 3 As shown, in some embodiments of the present application, the first combined structure includes a first wafer A1 and a plurality of the first chips 20 , and the first wafer A1 includes the substrate 10 and the second conductive interconnect structure 30 .

[0050] In the semiconductor structure provided in the embodiment of the present application, the first wafer A1 includes the substrate 10 and the second conductive interconnect structure 30, that is, the substrate 10 and the second conductive interconnect structure 30 are an integrated structure, thereby reducing the number of components of the semiconductor structure and improving integration efficiency.

[0051] In some embodiments of the present application, the first wafer A1 includes a non-device wafer, the first wafer A1 has an SOI structure or a non-SOI structure, and the first wafer A1 may include a TSV that does not completely penetrate the substrate 10. The internal filling material of the TSV may be a metal material such as Cu, Al, W, or a non-metallic material such as polysilicon or graphene. The material of the substrate 10 may be a silicon-based material, gallium arsenide, indium phosphide, diamond, or other materials. The first metal interconnect structure and the second metal interconnect structure may have multiple metal layers, and the materials of the metal layers include metals or metal alloys such as Cu, Al, W, Ag, and Au. A metal interlayer dielectric layer is filled between the metal layers, and the material of the metal interlayer dielectric layer may be a low-dielectric common sense material such as silicon dioxide, silicon nitride, silicon carbide, and nitride silicon carbide.

[0052] In some embodiments of the present application, the structures of the plurality of first chips 20 may be the same or different. The first chip 20 may include a circuit layer, which may include one or more combinations of CMOS, DRAM, RF, NAND FLASH, NOR FLASH, photodiodes, avalanche diodes, and other devices.

[0053] In some embodiments of the present application, the first chip 20 includes a logic chip, and the metal wiring of the first chip 20 is located at the periphery of the first chip 20. The metal wiring can serve as the first conductive interconnect structure 21. The metal wiring can be led out from the logic computing unit or input-output unit in the first chip 20, or directly led out from the input-output unit.

[0054] In some embodiments of the present application, the first chip 20 includes a memory chip. The first chip 20 includes a control circuit portion of a memory unit. The control circuit portion can serve as the first conductive interconnect structure 21 .

[0055] In some embodiments of the present application, the substrate 10 may include a second region 12 and two first regions 11 , where the two first regions 11 are respectively disposed on both sides of the second region 12 .

[0056] In some embodiments of the present application, the substrate 10 may include one second region 12 and four first regions 11 , where two first regions 11 are respectively disposed on four sides of the second region 12 .

[0057] Continue to refer to 1d, Figure 2 and Figure 3In some embodiments of the present application, the first chip 20 includes a first bonding layer 22, the substrate 10 includes a second bonding layer 13, the first bonding layer 22 is bonded to the second bonding layer 13, and the bonding connection method between the first bonding layer 22 and the second bonding layer 13 includes melt bonding or adhesive bonding.

[0058] In the semiconductor structure provided in the embodiment of the present application, the first bonding layer 22 in each first chip 20 and the second bonding layer 13 in the substrate 10 are bonded in the corresponding first region 11 by fusion bonding or adhesive bonding. Fusion bonding and adhesive bonding include bonding connection methods between the first chip 20 and the substrate 10 that do not involve an electrical connection relationship, which can effectively reduce the bonding difficulty of multiple first chips 20 and the substrate 10 and improve the bonding efficiency of multiple first chips 20 and the substrate 10.

[0059] In some embodiments of the present application, the bonding connection method between the first bonding layer 22 and the second bonding layer 13 is melt bonding. Through melt bonding, a stable covalent bond structure can be formed between the first chip 20 and the substrate 10 in the first wafer A1. Exemplarily, the first bonding layer 22 includes one or more of silicon dioxide, silicon nitride, silicon carbonitride, and silicon oxynitride. The first bonding layer 22 can be formed by processes such as thermal oxidation, chemical vapor deposition, and atomic layer deposition; the second bonding layer 13 includes the film layer in the substrate 10 that is closest to the first bonding layer 22, such as an oxide layer. It should be noted that the bonding connection may eliminate the interface between the two film layers, as shown in FIG. Figure 1d As shown, there is no interface between the first bonding layer 22 and the second bonding layer 13 .

[0060] In some embodiments of the present application, the bonding connection between the first bonding layer 22 and the second bonding layer 13 is adhesive bonding. Through adhesive bonding, a stable covalent bond structure can also be formed between the first chip 20 and the substrate 10 in the first wafer A1. Exemplarily, the first bonding layer 22 includes a polymer material, and the polymer material includes epoxy resin, divinylsiloxane diphenylpropylcyclobutene. The second bonding layer 13 includes a film layer in the substrate 10 that is closest to the first bonding layer 22, and its material is not limited.

[0061] Continue to refer to Figure 1d 、 Figure 2 and Figure 3In some embodiments of the present application, the first conductive interconnect structure 21 includes a first metal layer M1, the second conductive interconnect structure 30 includes a second metal layer M2, the first metal layer M1 and the second metal layer M2 are bonded to each other, and the bonding connection method between the first metal layer M1 and the second metal layer M2 includes metal bonding.

[0062] In the semiconductor structure provided in the embodiment of the present application, the bonding connection method between the first metal layer M1 and the second metal layer M2 includes metal bonding, and the first conductive interconnection structure 21 and the second conductive interconnection structure 30 are electrically connected through the metal bonding between the first metal layer M1 and the second metal layer M2, thereby achieving electrical connection between multiple first chips 20, so that the semiconductor structure forms a high-density three-dimensional integrated structure with a lighter packaging thickness through lateral hybrid bonding including two bonding methods (such as metal bonding and adhesive bonding, or metal bonding and melt bonding).

[0063] In some embodiments of the present application, metal bonding methods include Cu-Cu bonding, Al-Al bonding, Cu-Al bonding, Cu-Sn-Al bonding, and Cu-Sn / CuSn bonding.

[0064] In some embodiments of the present application, the first bonding layer 22 and the second bonding layer 13 are bonded to each other on the side of the first bonding layer 22 facing the substrate 10 , and the first metal layer M1 and the second metal layer M2 are bonded to each other on the side of the first metal layer M1 facing the substrate 10 .

[0065] In the semiconductor structure provided in the embodiment of the present application, the first bonding layer 22 and the second bonding layer 13 are bonded to each other on the side of the first bonding layer 22 facing the substrate 10, and the first metal layer M1 and the second metal layer M2 are bonded to each other on the side of the first metal layer M1 facing the substrate 10, that is, the bonding surface of the first bonding layer 22 and the bonding surface of the first metal layer M1 are oriented in the same direction, so that the bonding connection between the first bonding layer 22 and the second bonding layer 13 can be carried out simultaneously with the bonding connection between the first metal layer M1 and the second metal layer M2, thereby improving the bonding efficiency.

[0066] Figure 4a is a partial plan view of a first metal layer and a second metal layer provided in some embodiments of the present application; Figure 4b is a partial plan view of another first metal layer and a second metal layer provided in some embodiments of the present application; Figure 4c This is a partial plan view of another first metal layer and a second metal layer provided in some embodiments of the present application. Figure 4a 、 Figure 4b and Figure 4c As shown, in some embodiments of the present application, the first metal layer M1 includes a first portion M11 disposed in the second region 12 , and the orthographic projection of the second metal layer M2 on the substrate 10 covers the orthographic projection of the first portion M11 on the substrate 10 .

[0067] In the semiconductor structure provided in the embodiment of the present application, the first part M11 in the first metal layer M1 is arranged in the second area 12, that is, the first part M11 is the part that is metal-bonded to the second metal layer M2. Since the orthographic projection of the second metal layer M2 on the substrate 10 covers the orthographic projection of the first part M11 on the substrate 10, the difficulty of aligning the first part M11 with the second metal layer M2 can be reduced, and the stability of the metal bonding between the first metal layer M1 and the second metal layer M2 can be improved.

[0068] Continue to refer to Figure 4a In some embodiments of the present application, the first metal layer M1 further includes a second portion M12 disposed in the first region 11 , the second portion M12 is connected to the first portion M11 , and the width of the second portion M12 is smaller than that of the first portion M11 .

[0069] In the semiconductor structure provided in the embodiment of the present application, since the width of the second part M12 located in the first area 11 in the first metal layer M1 is smaller than the width of the first part M11 located in the second area 12, that is, the first metal layer M1 widens the width of the first part M11 in the second area 12, so as to increase the metal bonding area between the first metal layer M1 and the second metal layer M2 as much as possible, improve the metal bonding strength, ensure the metal bonding quality, and thereby improve the electrical connection stability between the first conductive interconnect structure 21 and the second conductive interconnect structure 30, extend the life of the semiconductor structure, and improve the performance of the semiconductor structure.

[0070] Continue to refer to Figure 4c In some embodiments of the present application, the first portion M11 includes a plurality of first sub-portions M111 , and the first metal layer M1 further includes a second portion M12 disposed in the first region 11 , and the second portion M12 is electrically connected to the plurality of first sub-portions M111 .

[0071] In the semiconductor structure provided in the embodiment of the present application, since in the first metal layer M1, the first part M11 located in the second area 12 includes multiple first sub-parts M111, and the multiple first sub-parts M111 are electrically connected to the second part M12 set in the first area 11, therefore, the conduction path between the first part M11 and the second part M12 in the first metal layer M1 can be increased, and the problem of poor contact and inability to electrically connect between the first conductive interconnect structure 21 and the second conductive interconnect structure 30 due to a broken circuit in a certain conduction path can be improved, the electrical connection stability between the first conductive interconnect structure 21 and the second conductive interconnect structure 30 is improved, the life of the semiconductor structure is extended, and the performance of the semiconductor structure is improved.

[0072] Continue to refer to Figure 1d In some embodiments of the present application, the semiconductor structure further includes: a filling dielectric layer 40, the filling dielectric layer 40 being arranged on the side of the first combination structure facing the first direction Y and located in the second region 12, the filling dielectric layer 40 being used to fill the surface difference of the first combination structure facing the first direction Y in the first region 11 and the second region 12.

[0073] In the semiconductor structure provided in the embodiment of the present application, the filling dielectric layer 40 can effectively eliminate the step difference between the first region 11 and the second region 12 on the surface of the first combined structure facing the first direction Y, so as to facilitate the subsequent integration of other components.

[0074] Of course, the present application does not limit the setting area of ​​the filling dielectric layer 40. In other embodiments of the present application, the filling dielectric layer 40 can be set on the side of the first combined structure facing the first direction Y, and located in the first area 11 and the second area 12, or only in the first area 11. Its function is to fill the discontinuity of the surface of the first combined structure facing the first direction Y in the first area 11 and the second area 12, or to fill the discontinuity of the surface of the first combined structure facing the first direction Y in the two first areas 11.

[0075] In some embodiments of the present application, the material of the filling dielectric layer 40 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other low dielectric constant materials and combinations thereof, or thermosetting polymers such as epoxy resins, or thermoplastic polymers such as polydimethylsiloxane, or polymer composite materials such as polymer fibers.

[0076] Figure 5 Some embodiments of this application provide Figure 1cAnother cross-sectional schematic diagram of a semiconductor structure cut along line AA' in FIG. Figure 5 As shown, in some embodiments of the present application, the semiconductor structure further includes: a passivation layer 50, the passivation layer 50 is arranged on the side of the first combined structure facing the first direction Y, wherein the passivation layer 50 includes a plurality of first openings H1 and one second opening H2, the first opening H1 exposes at least a portion of the first conductive interconnect structure 21, and the second opening H2 exposes at least a portion of the second conductive interconnect structure 30.

[0077] In the semiconductor structure provided in the embodiment of the present application, the passivation layer 50 is used to cover and protect the circuit structure in the first combination structure, and by generating the first opening H1 and the second opening H2, a free connection between the first conductive interconnection structure 21, the second conductive interconnection structure 30 and other components is achieved, which facilitates the subsequent design of a packaging solution with higher degrees of freedom, such as using it as an independent packaging body, or realizing multi-layer packaging integration through a vertical hybrid bonding process.

[0078] Figure 6 Some embodiments of this application provide Figure 1c A schematic cross-sectional view of another semiconductor structure cut along line AA' in FIG. Figure 6 As shown, in some embodiments of the present application, the semiconductor structure further includes: a third bonding layer 70, the third bonding layer 70 is arranged on the side of the first combination structure facing the first direction Y, the third bonding layer 70 includes a plurality of connecting parts 71, and the connecting parts 71 are electrically connected to the first conductive interconnect structure 21 and / or the second conductive interconnect structure; a second wafer A2 is arranged on the side of the third bonding layer 70 away from the substrate 10, and the second wafer A2 is electrically connected to the first conductive interconnect structure 21 and / or the second conductive interconnect structure through the connecting parts 71.

[0079] In the semiconductor structure provided in the embodiment of the present application, the provision of the third bonding layer 70 enables further integration of the second wafer A2 in the vertical direction, thereby further enriching the three-dimensional integrated structure of the semiconductor structure.

[0080] In some embodiments of the present application, the second wafer A2 is a logic wafer, which includes a plurality of logic chips. The logic chips include one or more of logic circuits, control circuits, input / output circuits, and digital-to-analog conversion circuits. The circuit structure may include the following device structures, such as MOSFET transistors, FINFET transistors, GAAFET transistors, diodes, etc. The second wafer A2 may also include metal interconnect layers and bonding metal structures, etc.

[0081] In some embodiments of the present application, the plurality of first chips 20 include SRAM chips, flash chips, MRAM chips, and RRAM chips, and the second wafer A2 is a logic wafer. The semiconductor structure can be used as a microcontroller, which can effectively improve the problem of incompatibility between the flash process and the logic process, difficulty in improving the yield, and very limited capacity of flash and SRAM, and improve the performance of the microcontroller.

[0082] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor structure. Figure 7 Schematic diagram of the process of preparing a semiconductor structure provided by some embodiments of the present application. Figure 7 As shown, the method for preparing the semiconductor structure includes the following steps:

[0083] Step S01 : providing a substrate 10 , forming a second conductive interconnect structure 30 on a side of the substrate 10 facing a first direction Y, wherein the substrate 10 includes a plurality of first regions 11 and a second region 12 , and the second conductive interconnect structure 30 is located in the second region 12 .

[0084] Step S02: A plurality of first chips 20 are formed on the side of the substrate 10 facing the first direction Y, each of the first chips 20 is correspondingly arranged on a plurality of the first regions 11 and bonded to the substrate 10, wherein the first chip 20 also includes a first conductive interconnect structure 21, the first conductive interconnect structure 21 extends from the first region 11 to the second region 12, and is bonded to the second conductive interconnect structure 30.

[0085] Continue to refer to Figure 2 In some embodiments of the present application, in step S01 , the substrate 10 and the second conductive interconnect structure 30 are both integrated on a first wafer A1 .

[0086] Figure 8 1 is a cross-sectional view of a first wafer that has not been etched, as provided in some embodiments of the present application. Figure 8 and Figure 2 As shown, in some embodiments of the present application, step S01 includes: etching the first wafer A1 so that the first wafer A1 is Figure 8 The corresponding structure is transformed into Figure 2 The etching process includes dry etching, and the oxide layer in the substrate 10 can be used as an etching barrier layer in the etching process. For example, the etching depth is 2um-50um.

[0087] Figure 9: is a cross-sectional schematic diagram of a first chip that has not been etched provided in some embodiments of the present application. Figure 9 and Figure 3 As shown, in some embodiments of the present application, step S02 includes: etching a local area (such as a peripheral area) of the first chip 20 to remove the substrate layer, device layer, part of the intermetallic dielectric layer, and part of the metal layer in the first conductive interconnect structure 21 in the local area of ​​the first chip 20. The etching process includes dry etching, wet etching, or a combination of the two. The top metal layer or other metal layer in the first conductive interconnect structure 21 can be used as an etch stop layer. Exemplarily, the etching width is 0.5um-100um. In some embodiments of the present application, the local area is the area where the first chip 20 overlaps with the second area 12.

[0088] In some embodiments of the present application, step S02 includes: performing surface pretreatment on the substrate 10 of the first region 11 and the second conductive interconnect structure 30 of the second region 12. The surface pretreatment method may be wet surface treatment or dry surface treatment. Afterwards, a bonding process is performed to melt-bond or adhesive-bond the first bonding layer 22 in the first chip 20 and the second bonding layer 13 in the substrate 10, and to metal-bond the first metal layer M1 in the first conductive interconnect structure 21 and the second metal layer M2 in the second conductive interconnect structure 30. Melt bonding and metal bonding are performed simultaneously, or adhesive bonding and metal bonding are performed simultaneously. Afterwards, an annealing process is performed. The annealing temperature may be 150°C-350°C. After the annealing process is completed, the metals in the first metal layer M1 and the second metal layer M2 form a stable electrical connection structure through diffusion. At the same time, the first bonding layer 22 forms a stable covalent bond with the second bonding layer 13. structure, thereby forming a first combined structure, which includes: a substrate 10, including multiple first regions 11 and a second region 12; multiple first chips 20, respectively arranged on the side of the substrate 10 facing the first direction Y, and respectively bonded to the substrate 10 in the first region 11, each of the first chips 20 also includes a first conductive interconnect structure 21, the first conductive interconnect structure 21 extends from the first region 11 to the second region 12; a second conductive interconnect structure 30, arranged on the side of the substrate 10 facing the first direction Y and located in the second region 12, the second conductive interconnect structure 30 is bonded to each of the first conductive interconnect structures 21.

[0089] Continue to refer to Figure 9In some embodiments of the present application, before the step of etching a local area of ​​the first chip 20, the first bonding layer 22 in the first chip 20 is arranged in a full-surface manner. This arrangement can reduce the difficulty of making the first bonding layer 22, but will increase the etching cost in the step of etching a local area of ​​the first chip 20. Figure 10 is a cross-sectional schematic diagram of another first chip provided in some embodiments of the present application without etching, referring to Figure 10 As shown, in other embodiments of the present application, before the step of etching a local area of ​​the first chip 20, the first bonding layer 22 in the first chip 20 can be set only on an area other than the local area of ​​the first chip 20 (that is, an area other than the etching area that needs to be etched later) to reduce the etching cost of the step of etching the local area of ​​the first chip 20.

[0090] Continue to refer to Figure 9 In some embodiments of the present application, the first bonding layer 22 in the first chip 20 is already formed before etching the local area of ​​the first chip 20. However, in other embodiments of the present application, the first bonding layer 22 can be formed after etching the local area of ​​the first chip 20, so as to avoid the problem of increased etching cost caused by etching the first bonding layer 22 during the etching step of the local area of ​​the first chip 20.

[0091] In some embodiments of the present application, the method for preparing the semiconductor structure further includes step S03: forming a filling dielectric layer 40 on the side of the first composite structure facing the first direction Y, and performing a planarization process to eliminate a step difference between the first region 11 and the second region 12, and / or between the two first regions 11, on the surface of the first composite structure facing the first direction Y. The planarization process may be performed by chemical mechanical polishing, wet etching, dry etching, or the like.

[0092] In some embodiments of the present application, the method for preparing the semiconductor structure also includes step S04: forming a passivation layer 50 on the entire side of the first combined structure facing the first direction Y, and etching the passivation layer 50 to form a plurality of first openings H1 and one second opening H2, wherein the first opening H1 exposes at least a portion of the first conductive interconnect structure 21, and the second opening H2 exposes at least a portion of the second conductive interconnect structure 30.

[0093] In some embodiments of the present application, the method for preparing the semiconductor structure further includes steps S05 and S06, wherein when performing step S05, step S04 can be omitted. Step S05 includes: depositing one or more of silicon nitride, silicon dioxide, silicon carbide, and silicon oxynitride above the first conductive interconnect structure 21 in the first chip 20 to form a dielectric layer in the third bonding layer 70, and then forming a connecting portion 71 in the third bonding layer 70 by a damascene process. The material of the connecting portion 71 can be Cu, Al, W, Ag, Au, etc., and the connecting portion 71 is electrically connected to the first conductive interconnect structure 21. Step S06 includes: forming a second wafer A2 on the third bonding layer 70, and the second wafer A2 is electrically connected to the first conductive interconnect structure 21 and / or the second conductive interconnect structure through the connecting portion 71.

[0094] Example 2

[0095] Figure 11 is a schematic cross-sectional view of a first wafer provided in some embodiments of the present application; Figure 12 is a cross-sectional schematic diagram of a second chip provided in some embodiments of the present application; Figure 13 Some embodiments of this application provide Figure 1c Schematic diagram of the cross section of the semiconductor structure cut along line AA' in FIG. Figure 11-13 As shown, in a first aspect, an embodiment of the present application provides a semiconductor structure, comprising a first composite structure, the first composite structure comprising a substrate 10', a plurality of first chips 20, and a second conductive interconnect structure 30. The substrate 10' comprises a plurality of first regions 11 and a second region 12; the plurality of first chips 20 are respectively disposed on a side of the substrate 10' facing a first direction Y and are respectively bonded to the substrate 10' in the first regions 11; each first chip 20 further comprises a first conductive interconnect structure 21, the first conductive interconnect structure 21 extending from the first region 11 to the second region 12; the second conductive interconnect structure 30 is disposed on a side of the substrate 10' facing the first direction Y and located in the second region 12, and the second conductive interconnect structure 30 is bonded to each of the first conductive interconnect structures 21.

[0096] It should be noted that the semiconductor structure provided in the second embodiment of the present application is similar to the semiconductor structure provided in the first embodiment. Only the different parts are described below, and the same parts will not be repeated in the second embodiment of the present application.

[0097] In some embodiments of the present application, the first combined structure includes a first wafer A1' and a second chip 60, wherein the first wafer A1' includes the substrate 10', the second chip 60 is arranged on the side of the substrate 10' facing the first direction Y, and is bonded to the substrate 10' in the second area 12, and the second chip 60 includes the second conductive interconnect structure 30.

[0098] In the semiconductor structure provided in the embodiment of the present application, the second conductive interconnect structure 30 is part of the second chip 60. Unlike the first embodiment, the first wafer A1' does not include the second conductive interconnect structure 30. The substrate 10' in the first wafer A1' and the second chip 60 are independent of each other. Therefore, it is necessary to bond the second chip 60 to the substrate 10' in the second region 12 by means of a bonding connection. This structure enables the design of the second conductive interconnect structure 30 to no longer be restricted by the first wafer A1', and can further improve the design freedom of the semiconductor structure. The bonding connection method between the second chip 60 and the substrate 10' includes vertical hybrid bonding with the back to face connection.

[0099] In some embodiments of the present application, the first bonding layer 22 of the first chip 20 is bonded to the second bonding layer 13' of the substrate 10' in the first region 11, and the bonding method includes fusion bonding or adhesive bonding. The first wafer A1' is a device wafer, and the second bonding layer 13' further includes a conductive portion 131'. The first wafer A1' is electrically connected to the second conductive interconnect structure 30 of the second chip 60 via the conductive portion 131'.

[0100] In some embodiments of the present application, the second chip 60 may be a chip containing certain complete functions, such as a logic chip, a flash chip, a PMU chip, a CIS chip, etc. The second chip 60 may include non-through-structure TSVs, as well as device structure layers and metal interconnect structures. The first chip 20 and the second chip 60 may also be core chips, which may, for example, include an ALU, a cache, an input / output unit, an ESD, a RAM, a ROM, etc.

[0101] Figure 14 Some embodiments of this application provide Figure 1c A schematic cross-sectional view of another semiconductor structure cut along line AA' in FIG. Figure 14In some embodiments of the present application, the semiconductor structure further includes: a third bonding layer 70, the third bonding layer 70 being arranged on the side of the first combination structure facing the first direction Y, the third bonding layer 70 including a plurality of connecting portions 71, the connecting portions 71 being electrically connected to the first conductive interconnect structure 21 and / or the second conductive interconnect structure; a second wafer A2 being arranged on the side of the third bonding layer 70 facing away from the substrate 10`, the second wafer A2 being electrically connected to the first conductive interconnect structure 21 and / or the second conductive interconnect structure through the connecting portions 71.

[0102] In some embodiments of the present application, multiple first chips 20 can all be flash chips, the second chip 60 includes an SRAM chip, the first wafer A1' is a logic wafer, and the second wafer A2 is a power management chip. The semiconductor structure can be used as a microcontroller, which can effectively improve the problem of incompatibility between the flash process and the logic process, the difficulty in improving the yield, and the very limited capacity of flash and SRAM, and improve the performance of the microcontroller.

[0103] In the second aspect, the present invention provides another method for preparing a semiconductor structure. Figure 8 , the method for preparing the semiconductor structure comprises the following steps:

[0104] Step S01 : providing a substrate 10 ′, forming a second conductive interconnect structure 30 on a side of the substrate 10 ′ facing the first direction Y, the substrate 10 ′ including a plurality of first regions 11 and a second region 12 , and the second conductive interconnect structure 30 is located in the second region 12 .

[0105] Step S02: A plurality of first chips 20 are formed on the side of the substrate 10' facing the first direction Y, each of the first chips 20 is correspondingly arranged on a plurality of the first regions 11 and bonded to the substrate 10', wherein the first chip 20 also includes a first conductive interconnect structure 21, the first conductive interconnect structure 21 extends from the first region 11 to the second region 12, and is bonded to the second conductive interconnect structure 30.

[0106] In which, step S01 includes: providing a substrate 10', forming a second chip 60 on the side of the substrate 10' facing the first direction Y, the second chip 60 is bonded to the substrate 10', the second chip 60 includes a second conductive interconnect structure 30, the substrate 10' includes multiple first regions 11 and a second region 12, and the second conductive interconnect structure 30 is located in the second region 12.

[0107] In the preparation method of the semiconductor structure provided in the present application, the second chip 60 is bonded to the substrate 10' in the second region 12, and the second chip 60 includes a second conductive interconnect structure 30, so that the design of the second conductive interconnect structure 30 is no longer restricted by the substrate 10', which can further improve the design freedom of the semiconductor structure.

[0108] In summary, the present application provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure includes a first combination structure, the first combination structure includes a substrate, a plurality of first chips and a second conductive interconnection structure, wherein the substrate includes a plurality of first regions and a second region, the plurality of first chips are respectively arranged on the side of the substrate facing the first direction, and are respectively bonded to the substrate in the first region, each first chip also includes a first conductive interconnection structure, the first conductive interconnection structure extends from the first region to the second region, the second conductive interconnection structure is arranged on the side of the substrate facing the first direction and is located in the second region, the second conductive interconnection structure is bonded to each of the first conductive interconnection structures, the semiconductor structure provided by the present application can reduce the packaging thickness, reduce the use of TSV, and improve the device performance of three-dimensional semiconductor devices while achieving three-dimensional integration.

[0109] The semiconductor structure and preparation method thereof provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A semiconductor structure, characterized in that The semiconductor structure includes a first combined structure, wherein the first combined structure includes: a substrate comprising a plurality of first regions and a second region; a plurality of first chips, each disposed on a side of the substrate facing the first direction and bonded to the substrate in the first region; each first chip further comprising a first conductive interconnect structure extending from the first region to the second region; The second conductive interconnect structure is arranged on a side of the substrate facing the first direction and located in the second area. The second conductive interconnect structure is bonded to each of the first conductive interconnect structures.

2. The semiconductor structure according to claim 1, wherein: The first chip includes a first bonding layer, the substrate includes a second bonding layer, the first bonding layer and the second bonding layer are bonded to each other, and the bonding method of the first bonding layer and the second bonding layer includes fusion bonding or adhesive bonding.

3. The semiconductor structure according to claim 2, wherein: The first conductive interconnect structure includes a first metal layer, the second conductive interconnect structure includes a second metal layer, the first metal layer and the second metal layer are bonded to each other, and the bonding method of the first metal layer and the second metal layer includes metal bonding.

4. The semiconductor structure according to claim 3, wherein: The first bonding layer and the second bonding layer are bonded to each other at a side of the first bonding layer facing the substrate, and the first metal layer and the second metal layer are bonded to each other at a side of the first metal layer facing the substrate.

5. The semiconductor structure according to claim 3, wherein: The first metal layer includes a first portion disposed in the second region, and an orthographic projection of the second metal layer on the substrate covers an orthographic projection of the first portion on the substrate.

6. The semiconductor structure according to claim 5, wherein: The first metal layer further includes a second portion disposed in the first region, the second portion is connected to the first portion, and a width of the second portion is smaller than that of the first portion.

7. The semiconductor structure according to claim 5, wherein: The first portion includes a plurality of first sub-portions, and the first metal layer further includes a second portion disposed in the first region, wherein the second portion is electrically connected to the plurality of first sub-portions.

8. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: A filling dielectric layer is provided on a side of the first combined structure facing the first direction and is located in the first region and / or the second region. The filling dielectric layer is used to fill the surface of the first combined structure facing the first direction in the first region and the second region, and / or in the two first regions.

9. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: A passivation layer is provided on a side of the first combined structure facing the first direction, wherein the passivation layer includes a plurality of first openings and a second opening, the first openings exposing at least a portion of the first conductive interconnect structure, and the second openings exposing at least a portion of the second conductive interconnect structure.

10. The semiconductor structure according to claim 1, wherein: The first combined structure includes: a first wafer, wherein the first wafer includes the substrate and the second conductive interconnect structure.

11. The semiconductor structure according to claim 1, wherein: The first combined structure includes: a first wafer, wherein the first wafer includes the substrate; A second chip is disposed on a side of the substrate facing the first direction and bonded to the substrate in the second region, wherein the second chip includes the second conductive interconnect structure.

12. The semiconductor structure according to claim 10 or 11, characterized in that: The semiconductor structure further comprises: a third bonding layer, the third bonding layer being disposed on a side of the first combined structure facing the first direction, the third bonding layer comprising a plurality of connecting portions, the connecting portions being electrically connected to the first conductive interconnect structure and / or the second conductive interconnect structure; The second wafer is arranged on a side of the third bonding layer away from the substrate, and the second wafer is electrically connected to the first conductive interconnect structure and / or the second conductive interconnect structure through the connecting portion.

13. A method for preparing a semiconductor structure, characterized in that: The following steps are involved: Providing a substrate, forming a second conductive interconnect structure on a side of the substrate facing a first direction, the substrate comprising a plurality of first regions and a second region, and the second conductive interconnect structure is located in the second region; A plurality of first chips are formed on a side of the substrate facing the first direction, each of the first chips is correspondingly arranged on a plurality of the first regions and bonded to the substrate, wherein the first chip also includes a first conductive interconnect structure, the first conductive interconnect structure extends from the first region to the second region and is bonded to the second conductive interconnect structure.

Images