Semiconductor test structure and preparation method thereof

Abstract

The invention provides a semiconductor test structure and a preparation method thereof, relates to the technical field of semiconductors, and aims to solve the problem that a connecting line interferes with a test signal. The semiconductor test structure provided by the invention comprises a packaging substrate, an adapter plate, a plurality of test chips and a signal line. Wherein the plurality of test chips are stacked on one side of the packaging substrate. The plurality of test chips comprise a target test chip. The packaging substrate is connected with the target test chip through a signal line. The adapter plate comprises a connecting contact, the signal line comprises a first wire and a second wire, the first wire and the second wire are connected to the connecting contact, the other end of the first wire is connected with the packaging substrate, and the other end of the second wire is connected with the target test chip. Through the above arrangement, the adapter plate can obtain the test signal transmitted to the target test chip, and the test signal does not need to be transmitted to the adapter plate through a connecting line, thereby reducing the interference of the connecting line on the test signal, and facilitating the improvement of the accuracy of a test result.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor test structure and a preparation method thereof. Background Art

[0002] Semiconductor testing is an important step in the semiconductor design, production, packaging, and testing process. It is the process of using specific equipment to detect DUT (Device Under Test) to identify device defects and verify whether the device meets the design goals. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor test structure and a method for manufacturing the same.

[0004] The embodiments of the present disclosure adopt the following technical solutions:

[0005] In one aspect, a semiconductor test structure is provided, comprising: a packaging substrate, an adapter board, and a plurality of test chips and signal lines. The plurality of test chips are stacked on one side of the packaging substrate, and the plurality of test chips are located between the packaging substrate and the adapter board; the plurality of test chips include a target test chip. The packaging substrate and the target test chip are connected via the signal lines; the adapter board includes connection contacts, and the signal lines include a first wire and a second wire, the first wire and the second wire being connected to the connection contacts, the other end of the first wire being connected to the packaging substrate, and the other end of the second wire being connected to the target test chip.

[0006] In some embodiments, when the target test chip is the test chip closest to the packaging substrate among the multiple test chips: the other end of the first wire is directly connected to the packaging substrate; the semiconductor test structure also includes a first connecting line; among the multiple test chips, any two adjacent test chips are connected through the first connecting line.

[0007] In some embodiments, when the target test chip is between the test chip closest to the package substrate and the test chip farthest from the package substrate among the multiple test chips, the other end of the first conductive wire is connected to the test chip located on the side of the target test chip closest to the package substrate. The semiconductor test structure also includes a second connecting wire; the second connecting wire is connected to the package substrate, the second connecting wire connects the test chip between the target test chip and the package substrate, and the second connecting wire is connected to the first conductive wire to electrically connect the first conductive wire to the package substrate. The semiconductor test structure also includes a third connecting wire; the third connecting wire connects the test chip between the target test chip and the adapter board.

[0008] In some embodiments, when the target test chip is the test chip closest to the transfer board among the multiple test chips, the other end of the first conductive wire is connected to the test chip located on the side of the target test chip closest to the package substrate. The semiconductor test structure further includes a fourth connecting wire connected to the package substrate, the fourth connecting wire connecting the test chip between the target test chip and the package substrate, and the fourth connecting wire connected to the first conductive wire to electrically connect the first conductive wire to the package substrate.

[0009] In some embodiments, the semiconductor test structure further comprises: a package housing, the package housing covering the plurality of test chips and the adapter board and connected to the package substrate; the adapter board further comprising test contacts; and the package housing further comprising a test opening exposing the test contacts.

[0010] In some embodiments, the packaging shell is in contact with the packaging substrate, the test chip, and the transfer board.

[0011] In some embodiments, a plurality of test chips and an adapter board are sequentially formed on a packaging substrate, wherein the plurality of test chips include a target test chip; a first wire and a second wire are connected to connection contacts on the adapter board; the other end of the first wire is connected to the packaging substrate; and the other end of the second wire is connected to the target test chip.

[0012] In some embodiments, when the target test chip is the test chip closest to the packaging substrate among the multiple test chips, after connecting the other end of the second wire to the target test chip, it also includes: connecting any two adjacent test chips through a first connecting line.

[0013] In some embodiments, when the target test chip is a test chip between the test chip closest to the packaging substrate and the test chip farthest from the packaging substrate among the multiple test chips, connecting the other end of the first wire to the packaging substrate includes: connecting the other end of the first wire to the test chip located on the side of the target test chip close to the packaging substrate and closest to the target test chip; and connecting the packaging substrate, the test chip between the target test chip and the packaging substrate, and the first wire through the second connecting line.

[0014] In some embodiments, after connecting the other end of the second wire to the target test chip, the method further includes connecting the target test chip to the test chip between the adapter board through a third connection line.

[0015] In some embodiments, when the target test chip is the test chip closest to the adapter board among the multiple test chips, connecting the other end of the first wire to the packaging substrate includes: connecting the other end of the first wire to the test chip located on the side of the target test chip close to the packaging substrate and closest to the target test chip; and connecting the packaging substrate, the test chip between the target test chip and the packaging substrate, and the first wire through a fourth connecting line.

[0016] In some embodiments, after connecting the other end of the second wire to the target test chip, the method further includes: forming a sacrificial layer on the test contact of the adapter board; forming a packaging shell on the packaging substrate; grinding the packaging shell to expose the sacrificial layer; and removing the sacrificial layer to expose the test contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0018] Figure 1 is a schematic structural diagram of a semiconductor test structure in which a target test chip is a test chip closest to a package substrate according to some embodiments;

[0019] Figure 2is a schematic structural diagram of a semiconductor test structure in which a target test chip is a test chip between a test chip closest to a package substrate and a test chip farthest from the package substrate according to some embodiments;

[0020] Figure 3 is a schematic structural diagram of a semiconductor test structure in which a target test chip is the test chip farthest from a package substrate according to some embodiments;

[0021] Figure 4 is a flow chart of a method for preparing a semiconductor test structure according to some embodiments;

[0022] Figure 5 is a structural schematic diagram of a semiconductor test structure after a plurality of test chips and an adapter board are sequentially formed on a packaging substrate according to some embodiments;

[0023] Figure 6 is a structural diagram of a semiconductor test structure after any two adjacent test chips are connected via a first connecting line according to some embodiments;

[0024] Figure 7 is a structural schematic diagram of a semiconductor test structure after a target test chip and a test chip between an adapter board and each other are connected via a third connection line according to some embodiments;

[0025] Figure 8 is a structural diagram of a semiconductor test structure after the package substrate, the target test chip, the test chip between the package substrate, and the first wire are all connected via a fourth connecting wire according to some embodiments;

[0026] Figure 9 A flowchart of a method for preparing a semiconductor test structure in which a target test chip is a test chip between a test chip closest to a package substrate and a test chip farthest from the package substrate according to some embodiments;

[0027] Figure 10 A flowchart of a method for preparing a semiconductor test structure in which a target test chip is the test chip farthest from a package substrate according to some embodiments;

[0028] Figure 11 is a schematic structural diagram of a semiconductor test structure after a sacrificial layer is formed on a test contact of an interposer according to some embodiments;

[0029] Figure 12 is a structural schematic diagram of a semiconductor test structure after a packaging shell is formed on a packaging substrate according to some embodiments;

[0030] Figure 13 This is a schematic structural diagram of a semiconductor test structure after the package shell is polished to expose the sacrificial layer according to some embodiments;

[0031] Figure 14 FIG. 1 is a schematic structural diagram of a semiconductor test structure after removing a sacrificial layer to expose test contacts according to some embodiments.

[0032] Figure numerals: 1. semiconductor test structure; 10. packaging substrate; 20. adapter board; 21. connection contact; 22. test contact; 30. test chip; 31. target test chip; 40. signal line; 41. first wire; 42. second wire; 51. first connection line; 52. second connection line; 53. third connection line; 54. fourth connection line; 60. packaging shell; 61. test opening; 70. solder ball; 80. sacrificial layer. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0034] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0035] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0036] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the embodiments disclosed herein.

[0037] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0038] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0039] Before a chip can be finally made into a terminal product, it generally needs to go through the following links: chip design, wafer manufacturing, packaging, semiconductor testing, board-level packaging, etc. Semiconductor testing, as an important step, is a process of using specific instruments to test the DUT (Device Under Test) to verify whether the device under test meets the design goals and separate good products from bad products. For example, the device under test may include a packaged chip product. According to the "ten-fold rule" in electronic system fault detection: if semiconductor testing fails to find fault problems related to chip design and manufacturing, then the cost of finding the fault at the circuit board level will rise to ten times that of the chip level. By analogy, the cost of finding a fault increases exponentially. Therefore, semiconductor testing plays an important role in reducing cost waste. Semiconductor testing provides engineers with real and effective test results. Engineers can improve the design and manufacturing plans of the chip based on these test results, thereby reducing cost waste.

[0040] The basic working mechanism of semiconductor testing is: program the tester so that it can generate any type of signal. Multiple signals together constitute a test signal. The tester applies a test signal to the DUT, transmits the output signal generated by the DUT to the instrument of the tester to measure its parameters, and compares the test result with the test signal stored in the tester. If the difference between the measurement result and the test signal is within the acceptable tolerance range, then the DUT will be considered to be good, otherwise it is a bad product.

[0041] According to some embodiments, the present disclosure provides a semiconductor test structure as a device under test for performing semiconductor testing. Figure 1 Schematic diagram of a semiconductor test structure in which the target test chip is the test chip closest to the package substrate in some embodiments. Some embodiments of the present disclosure provide a semiconductor test structure, such as Figure 1As shown, a semiconductor test structure 1 includes a package substrate 10, at least one test chip 30, an interposer 20, and signal lines 40. Multiple test chips 30 are stacked on one side of the package substrate 10, and the multiple test chips 30 are located between the package substrate 10 and the interposer 20. The multiple test chips 30 include a target test chip 31. The interposer 20 includes connection pads 21.

[0042] The packaging substrate 10 is connected to the target test chip 31 via a signal line 40. The signal line 40 includes a first wire 41 and a second wire 42. The first wire 41 and the second wire 42 are connected to the connection pad 21. The other end of the first wire 41 is connected to the packaging substrate 10, and the other end of the second wire 42 is connected to the target test chip 31. The signal line 40 is used to transmit a test signal to the target test chip 31. For example, when the target test chip 31 is the test chip 30 closest to the packaging substrate 10 among the multiple test chips 30, the other end of the first wire 41 can be directly connected to the packaging substrate 10, and the other end of the second wire 42 can be directly connected to the target test chip 31. The first wire 41 and the second wire 42 are connected to the connection pad 21. The test signal is transmitted to the target test chip 31 via the packaging substrate 10, the first wire 41, and the second wire 42.

[0043] In this embodiment, the packaging substrate 10 can be connected to the tester to receive the test signal sent by the tester. The test signal can be transmitted to the target test chip 31 via the packaging substrate 10, the first wire 41 and the second wire 42. The first wire 41 and the second wire 42 are connected to the connection contact 21 on the adapter board 20, that is, the connection contact 21 on the adapter board 20 is connected in series to the circuit that transmits the test signal to the target test chip 31. Then the test signal can be transmitted to the adapter board 20 via the packaging substrate 10 and the first wire 41. The adapter board 20 can be connected to the tester so that the tester can obtain the test signal transmitted to the target test chip 31 to achieve the purpose of detection.

[0044] Moreover, in some other embodiments, the test chip 30 closest to the package substrate 10 is connected to the package substrate 10, adjacent test chips 30 are connected to each other, and the test chip 30 closest to the adapter board 20 is connected to the adapter board 20. The test chip 30 includes a target test chip 31. For example, when the target test chip 31 is located between other test chips 30, the test signal sent by the tester to the target test chip 31 can be transmitted to the target test chip 31 in sequence via the package substrate 10, the connection line connecting the package substrate 10 and the test chip 30, and the connection line connecting the test chip 30 and the target test. This test signal also needs to be transmitted to the adapter board 20 via the connection line connecting the target test chip 31 and the test chip 30, and the connection line connecting the test chip 30 and the connection pad 21 on the adapter board 20. Subsequently, the adapter board 20 can be connected to the tester so that the tester can obtain the test signal and achieve the purpose of detection.

[0045] In the above embodiment, the test signal transmitted to the target test chip 31 needs to be transmitted to the adapter board 20 via multiple connecting wires. Even if the target test chip 31 is the test chip 30 closest to the adapter board 20, it is still necessary to connect the target test chip 31 to the connection pads 21 on the adapter board 20 via connecting wires. Therefore, the test signal transmitted to the target test chip 31 needs to pass through at least one connecting wire before it can be transmitted to the adapter board 20. When performing high-speed test signal transmission, the connecting wires may interfere with the test signal, resulting in distorted test results.

[0046] When the semiconductor test structure 1 provided in some embodiments of the present disclosure is tested, the adapter board 20 can obtain the test signal transmitted to the target test chip 31. The test signal transmitted to the target test chip 31 no longer needs to be transmitted to the adapter board 20 through the connecting line, which reduces the interference of the connecting line on the test signal and is conducive to improving the accuracy of the test results.

[0047] Figure 2 FIG. 1 is a schematic structural diagram of a semiconductor test structure in which a target test chip is a test chip between a test chip closest to a package substrate and a test chip farthest from the package substrate in some embodiments. Figure 3 FIG. 1 is a schematic diagram of a semiconductor test structure in which the target test chip is the test chip farthest from the package substrate in some embodiments. Figure 1 、 Figure 2 and Figure 3 , the connection relationship of the signal line 40 when the target test chip 31 is at different positions of the multiple test chips 30 is explained.

[0048] In some embodiments, as Figure 1As shown, when the target test chip 31 is the test chip 30 closest to the package substrate 10 among the multiple test chips 30, the first wire 41 and the second wire 42 are connected to the connection pad 21 on the adapter board 20, the other end of the first wire 41 is directly connected to the package substrate 10, and the other end of the second wire 42 is connected to the target test chip 31. The semiconductor test structure 1 also includes a first connecting wire 51. Among the multiple test chips 30, any two adjacent test chips 30 are connected by the first connecting wire 51. Exemplarily, the semiconductor test structure 1 may include one first connecting wire 51, and the first connecting wire 51 sequentially connects the multiple test chips 30; or, the semiconductor test structure 1 may include multiple first connecting wires 51, and one first connecting wire 51 connects two adjacent test chips 30.

[0049] Through the above-mentioned setting, multiple test chips 30 are connected to each other to simulate the chip usage scenario, which is conducive to making the test results obtained by semiconductor testing more referenceable. In addition, the first wire 41 and the second wire 42 are connected to the connection contact 21 on the adapter board 20, and the other end of the first wire 41 is directly connected to the package substrate 10, so the test signal can be transmitted to the adapter board 20 via the package substrate 10 and the first wire 41. The other end of the second wire 42 is connected to the target test chip 31, and the test signal can be transmitted to the target test chip 31 via the package substrate 10, the first wire 41 and the second wire 42. The tester is connected to the adapter board 20. Since the first wire 41 and the second wire 42 are connected to the adapter board 20, the tester can detect the test signal input to the target test chip 31. Compared with the test signal being transmitted to the target test chip 31 and then transmitted to the adapter board 20 through the connecting wire, the interference of the connecting wire on the test signal is reduced, which is conducive to improving the accuracy of the test results.

[0050] In some embodiments, as Figure 2 As shown, when the target test chip 31 is the test chip 30 between the test chip 30 closest to the package substrate 10 and the test chip 30 farthest from the package substrate 10 among the multiple test chips 30, the first wire 41 and the second wire 42 are connected to the connection pad 21 on the interposer 20. The other end of the first wire 41 is connected to the test chip 30 located on the side of the target test chip 31 close to the package substrate 10 and closest to the target test chip 31, and the other end of the second wire 42 is connected to the target test chip 31. The semiconductor test structure 1 also includes a second connection wire 52 and a third connection wire 53. The second connection wire 52 is connected to the package substrate 10, and the second connection wire 52 connects the test chip 30 between the target test chip 31 and the package substrate 10. The second connection wire 52 is connected to the first wire 41 to electrically connect the first wire 41 to the package substrate 10. The third connection wire 53 connects the test chip 30 between the target test chip 31 and the interposer 20.

[0051] For example, the semiconductor test structure 1 may include a second connection line 52, one end of which is connected to the package substrate 10, and the other end of which is connected to the test chip 30 between the package substrate 10 and the target test chip 31 and is connected to the first conductive line 41. Alternatively, the semiconductor test structure 1 may include multiple second connection lines 52, each of which may connect the package substrate 10 and the test chip 30 closest to the package substrate 10, and two adjacent test chips 30 between the package substrate 10 and the target test chip 31. Furthermore, the second connection line 52 and the first conductive line 41 are connected to the test chip 30 located on the side of the target test chip 31 close to the package substrate 10 and closest to the target test chip 31.

[0052] For example, the semiconductor test structure 1 may include one third connection line 53, which sequentially connects the test chips 30 between the target test chip 31 and the interposer 20. Alternatively, the semiconductor test structure 1 may include multiple third connection lines 53, which connect any two adjacent test chips 30 between the target test chip 31 and the interposer 20.

[0053] Through the above arrangement, the test signal is transmitted to the target test chip 31 via the package substrate 10, the second connecting wire 52, the first wire 41, and the second wire 42. Furthermore, the test signal is transmitted to the adapter board 20 via the package substrate 10, the second connecting wire 52, and the first wire 41. The tester is connected to the adapter board 20 to obtain the test signal transmitted to the target test chip 31. Compared to transmitting the test signal to the target test chip 31 and then transmitting it to the adapter board 20 via connecting wires, this reduces interference with the test signal caused by the connecting wires, thereby improving the accuracy of the test results.

[0054] In addition, the second connection lines 52 and the third connection lines 53 connect the plurality of test chips 30 to each other to simulate chip usage scenarios, which is beneficial for making the test results obtained from the semiconductor test more referenceable.

[0055] In some embodiments, as Figure 3As shown, when the target test chip 31 is the test chip 30 closest to the interposer 20 among the multiple test chips 30, the first wire 41 and the second wire 42 are connected to the connection pad 21 on the interposer 20. The other end of the first wire 41 is connected to the test chip 30 located on the side of the target test chip 31 close to the package substrate 10 and closest to the target test chip 31, and the other end of the second wire 42 is connected to the target test chip 31. The semiconductor test structure 1 also includes a fourth connection wire 54. The fourth connection wire 54 is connected to the package substrate 10. The fourth connection wire 54 connects the test chip 30 between the target test chip 31 and the package substrate 10, and the fourth connection wire 54 is connected to the first wire 41 to electrically connect the first wire 41 to the package substrate 10.

[0056] Illustratively, the semiconductor test structure 1 may include a fourth connection line 54, which sequentially connects the package substrate 10 and the test chip 30 between the package substrate 10 and the target test chip 31. Alternatively, the semiconductor test structure 1 may include multiple fourth connection lines 54, which connect the package substrate 10 and the test chip 30 closest to the package substrate 10, as well as any two adjacent test chips 30 between the package substrate 10 and the target test chip 31. Furthermore, the fourth connection line 54 is connected to the first conductive line 41 at the test chip 30 located on the side of the target test chip 31 close to the package substrate 10 and closest to the target test chip 31, thereby electrically connecting the first conductive line 41 to the package substrate 10.

[0057] Through the above arrangement, the test signal is transmitted to the target test chip 31 via the package substrate 10, the fourth connecting wire 54, the first wire 41, and the second wire 42. Furthermore, the test signal is transmitted to the adapter board 20 via the package substrate 10, the fourth connecting wire 54, and the first wire 41. The tester is connected to the adapter board 20 to obtain the test signal transmitted to the target test chip 31. Compared to transmitting the test signal to the target test chip 31 and then transmitting it to the adapter board 20 via connecting wires, this reduces interference with the test signal caused by the connecting wires, thereby improving the accuracy of the test results.

[0058] In addition, the fourth connection lines 54 connect the plurality of test chips 30 to each other to simulate chip usage scenarios, which is beneficial for making the test results obtained from the semiconductor test more referenceable.

[0059] In the following, combined Figure 1 , the positional relationship among the package shell 60 , the test chip 30 , the transfer board 20 and the package substrate 10 in the semiconductor test structure 1 is explained.

[0060] In some embodiments, as Figure 1As shown, the semiconductor test structure 1 also includes a packaging shell 60. The packaging shell 60 covers multiple test chips 30 and the adapter board 20, and is connected to the packaging substrate 10. The packaging shell 60 can protect the adapter board 20 and the test chip 30 from the influence of the external environment (water vapor, temperature, pollution, etc.) to improve the accuracy of the test results. The adapter board 20 also includes a test contact 22. Exemplarily, the test contact 22 can be located on the side of the adapter board 20 away from the packaging substrate 10. The packaging shell 60 also includes a test opening 61, which exposes the test contact 22 to facilitate the connection of the probe of the test machine with the test contact 22 on the adapter board 20, which is beneficial for the adapter board 20 to transmit the test signal to the test machine. In addition, the semiconductor test structure 1 needs to be placed on the test machine during testing. The test machine clamps the semiconductor test structure 1, and the adapter shell structure can realize composite functions such as moisture resistance, pressure resistance and support for the semiconductor test structure 1.

[0061] In some embodiments, as Figure 1 As shown, the packaging shell 60 is in contact with the packaging substrate 10, the test chip 30 and the adapter plate 20. Exemplarily, the packaging shell 60 may include EMC (Epoxy Molding Compound). Before filling the mold cavity of the semiconductor test structure 1 with EMC, it is necessary to cover the test contacts 22 of the adapter plate 20 with a sacrificial material. Exemplarily, the sacrificial material may include high-temperature tape or a hydrosol. After the sacrificial material is formed above the test contacts 22, the EMC is squeezed into the mold cavity of the semiconductor test structure 1 and the test chip 30 and the adapter plate 20 are embedded. After being cured and formed in the mold cavity, it becomes a structure with a certain hardness. After the EMC is cured and formed, special equipment is required to grind the EMC and reduce the mold thickness to expose the sacrificial material, and then the sacrificial material is removed to expose the test contacts 22, and finally the semiconductor test structure 1 is formed. Through the above arrangement, the packaging shell 60 is in contact with the packaging substrate 10, the test chip 30 and the adapter plate 20, which is beneficial for the packaging shell 60 to protect the adapter plate 20 and the test chip 30 from the influence of the external environment (water vapor, temperature, pollution, etc.), thereby improving the accuracy of the test results.

[0062] In the following, combined Figure 1 , the solder balls 70 in the semiconductor test structure 1 are introduced.

[0063] In some embodiments, reference Figure 1 The semiconductor test structure 1 further includes solder balls 70, which are located on the side of the package substrate 10 facing away from the test chip 30. During semiconductor testing, the solder balls 70 are electrically connected to the tester to obtain test signals output by the tester and transmit the obtained test signals to the package substrate 10. This arrangement facilitates the semiconductor test structure 1 to obtain test signals output by the tester.

[0064] In the following, combined Figures 4 to 14 , a preparation method of the semiconductor test structure 1 is introduced in detail.

[0065] In some embodiments, as Figure 4 As shown, a method for preparing a semiconductor test structure 1 is also provided, comprising:

[0066] S1. Forming a plurality of test chips and a transfer board in sequence on a packaging substrate, wherein the plurality of test chips includes a target test chip.

[0067] In this step, refer to Figure 5 、 Figure 6 、 Figure 7 and Figure 8 A plurality of test chips 30 and an adapter plate 20 are sequentially formed on the packaging substrate 10. For example, the plurality of test chips 30 are stacked in a direction perpendicular to the packaging substrate 10, and the plurality of test chips 30 can be sequentially staggered by a distance in a direction parallel to the packaging substrate 10 (for example, in the figure, the plurality of test chips 30 are sequentially horizontally staggered by a distance to the right from bottom to top, but not completely staggered), exposing the connection portion of each test chip 30 to facilitate interconnection of the plurality of test chips 30 in subsequent steps. The plurality of test chips 30 includes a target test chip 31. The target test chip 31 can be the test chip 30 closest to the packaging substrate 10, or the target test chip 31 can be a test chip 30 between the test chip 30 closest to the packaging substrate 10 and the test chip 30 farthest from the packaging substrate 10, or the target test chip 31 can be the test chip 30 farthest from the packaging substrate 10 (i.e., the test chip 30 closest to the adapter plate 20). The adapter board 20 may include connection contacts 21 and test contacts 22, and the connection contacts 21 and test contacts 22 may be located on a side of the adapter board 20 facing away from the package substrate 10 (e.g., the upper surface of the adapter board 20 in the figure). The connection contacts 21 are used to connect to the test chip 30 or the package substrate 10 to enable the test chip 30 to transmit a test signal to the adapter board 20, or to enable the package substrate 10 to transmit a test signal to the adapter board 20. The test contacts 22 are used to connect to a test machine to enable the adapter board 20 to transmit a test signal to the test machine.

[0068] S2. Connect the first wire and the second wire to the connection contacts on the adapter board.

[0069] In this step, if Figure 6 、 Figure 7 and Figure 8As shown, the first wire 41 and the second wire 42 are connected to the connection contact 21 on the adapter board 20, that is, the first wire 41 and the second wire 42 are short-circuited at the connection contact 21. In subsequent steps, the test signal can be transmitted to the adapter board 20 and the second wire 42 via the first wire 41.

[0070] S3. Connect the other end of the first wire to the packaging substrate.

[0071] In this step, if Figure 6 、 Figure 7 and Figure 8 As shown, the other end of the first wire 41 is electrically connected to the package substrate 10. Figure 6 As shown, when the target test chip 31 is the test chip 30 closest to the packaging substrate 10 among multiple test chips 30, the other end of the first wire 41 can be connected to the packaging substrate 10 after the first wire 41 and the second wire 42 are connected to the connection contact 21 on the adapter board 20.

[0072] S4. Connect the other end of the second wire to the target test chip.

[0073] In this step, if Figure 6 、 Figure 7 and Figure 8 As shown, after the first wire 41 and the second wire 42 are connected to the connection contact 21 on the adapter board 20, the other end of the second wire 42 is connected to the target test chip 31. The first wire 41 and the second wire 42 together constitute a signal line 40 to transmit the test signal to the target test chip 31.

[0074] In the semiconductor test structure 1 prepared through the above steps, test signals can be transmitted to the target test chip 31 via the package substrate 10, the first wire 41, and the second wire 42. Furthermore, the test signals can be transmitted to the adapter board 20 via the package substrate 10 and the first wire 41. In this way, the adapter board 20 can obtain the test signals input to the target test chip 31. Compared to transmitting the test signals to the target test chip 31 and then transmitting them to the adapter board 20 via connecting wires, this reduces interference with the test signals caused by the connecting wires, thereby improving the accuracy of the test results.

[0075] In some embodiments, when the target test chip 31 is the test chip 30 closest to the package substrate 10 among the multiple test chips 30 , after S4 , connecting the other end of the second wire 42 to the target test chip 31 , the method further includes: S5 .

[0076] S5. Connect any two adjacent test chips via a first connecting line.

[0077] In this step, if Figure 5 and Figure 6As shown, when the target test chip 31 is the test chip 30 closest to the packaging substrate 10 among multiple test chips 30, multiple test chips 30 are stacked on the target test chip 31, so that any two adjacent test chips 30 are connected through the first connecting line 51, which is conducive to simulating the chip usage scenario and making the test results obtained from the semiconductor test more referenceable.

[0078] In some embodiments, as Figure 9 As shown, when the target test chip 31 is the test chip 30 between the test chip 30 closest to the packaging substrate 10 and the test chip 30 farthest from the packaging substrate 10 among the multiple test chips 30, S3, connects the other end of the first wire 41 to the packaging substrate 10, including: S31~S32.

[0079] S31 , connecting the other end of the first wire to a test chip that is located on a side of the target test chip close to the packaging substrate and closest to the target test chip.

[0080] In this step, if Figure 5 and Figure 7 As shown, since the target test chip 31 is the test chip 30 between the test chip 30 closest to the packaging substrate 10 and the test chip 30 farthest from the packaging substrate 10 among the multiple test chips 30, in order to simulate the chip usage scenario and connect the test chips 30 to each other, the other end of the first wire 41 can be connected to the test chip 30 located on the side of the target test chip 31 close to the packaging substrate 10 and closest to the target test chip 31. In a subsequent step, the first wire 41 is electrically connected to the packaging substrate 10 to enable the packaging substrate 10 to transmit the test signal to the target test chip 31.

[0081] S32, connecting the packaging substrate, the target test chip, the test chip between the packaging substrate, and the first wire through a second connecting wire.

[0082] In this step, if Figure 5 and Figure 7 As shown, the package substrate 10 is connected to the test chip 30 closest to the package substrate 10 via the second connection wire 52, and any two adjacent test chips 30 between the package substrate 10 and the target test chip 31 are connected via the second connection wire 52. Furthermore, the second connection wire 52 connecting the test chip 30 located on the side of the target test chip 31 close to the package substrate 10 and closest to the target test chip 31 is connected to the first wire 41, thereby electrically connecting the first wire 41 to the package substrate 10.

[0083] In the semiconductor test structure prepared through the above steps, the test signal can be transmitted to the target test chip 31 via the package substrate 10, the second connecting wire 52, the first conductive wire 41, and the second conductive wire 42. Furthermore, the test signal can be transmitted to the adapter board 20 via the package substrate 10, the second connecting wire 52, and the first conductive wire 41. The adapter board 20 can transmit the test signal transmitted to the target test chip 31 to the tester. Compared to transmitting the test signal to the target test chip 31 and then transmitting it to the adapter board 20 via the connecting wire, this reduces interference caused by the connecting wire on the test signal, which helps improve the accuracy of the test results.

[0084] In some embodiments, when the target test chip 31 is a test chip 30 between the test chip 30 closest to the packaging substrate 10 and the test chip 30 farthest from the packaging substrate 10 among multiple test chips 30, after connecting the other end of the second wire 42 to the target test chip 31, it also includes: S33.

[0085] S33, connecting the target test chip and the test chip on the adapter board via a third connection line.

[0086] In this step, if Figure 5 and Figure 7 As shown, since the target test chip 31 is the test chip 30 between the test chip 30 closest to the package substrate 10 and the test chip 30 farthest from the package substrate 10 among the multiple test chips 30, in order to simulate the usage scenario of the chips and connect the chips to each other, the target test chip 31 and any two adjacent test chips 30 between the adapter board 20 can be connected via a third connection line 53. Exemplarily, the test chips 30 between the target test chip 31 and the adapter board 20 can be connected sequentially via a third connection line 53, or any two adjacent test chips 30 between the target test chip 31 and the adapter board 20 can be connected via a third connection line 53. After the above steps, any two adjacent test chips 30 among the multiple test chips 30 are connected, which is conducive to simulating the usage scenario of the chips and making the test results obtained from the semiconductor test more referenceable.

[0087] In some embodiments, as Figure 10 As shown, when the target test chip 31 is the test chip 30 closest to the transfer board 20 among the multiple test chips 30 , S3 , connecting the other end of the first wire 41 to the package substrate 10 , including: S34 - S35 .

[0088] S34 , connecting the other end of the first wire to a test chip that is located on a side of the target test chip close to the packaging substrate and closest to the target test chip.

[0089] In this step, if Figure 5 and Figure 8As shown, the target test chip 31 is the test chip 30 closest to the adapter board 20 among the multiple test chips 30. In order to simulate the usage scenario of the chip and connect the chips to each other, the other end of the first wire 41 can be connected to the test chip 30 located on the side of the target test chip 31 close to the packaging substrate 10 and closest to the target test chip 31. In the subsequent steps, the first wire 41 is electrically connected to the packaging substrate 10 to enable the packaging substrate 10 to transmit the test signal to the target test chip 31.

[0090] S35 , connecting the packaging substrate, the target test chip, the test chip between the packaging substrate, and the first wire through a fourth connecting wire.

[0091] In this step, if Figure 5 and Figure 8 As shown, the package substrate 10 can be connected to the test chip 30 closest to the package substrate 10 via a fourth connecting wire 54, and any two adjacent test chips 30 between the package substrate 10 and the target test chip 31 can be connected via the fourth connecting wire 54. Furthermore, the fourth connecting wire 54 connecting the test chip 30 located on the side of the target test chip 31 closest to the package substrate 10 and closest to the target test chip 31 is connected to the first conductive wire 41, thereby electrically connecting the package substrate 10 to the first conductive wire 41. After the above steps, the test signal can be transmitted to the target test chip 31 via the package substrate 10, the fourth connecting wire 54, the first conductive wire 41, and the second conductive wire 42. Furthermore, the test signal can be transmitted to the adapter board 20 via the package substrate 10, the fourth connecting wire 54, and the first conductive wire 41. The adapter board 20 can transmit the test signal transmitted to the target test chip 31 to the tester. Compared to transmitting the test signal to the target test chip 31 and then transmitting it to the adapter board 20 via the connecting wire, this reduces interference caused by the connecting wire on the test signal, thereby improving the accuracy of the test results.

[0092] In some embodiments, after S4 , connecting the other end of the second wire to the target test chip, the method further includes: S6 to S9 .

[0093] S6. Form a sacrificial layer on the test contacts of the transfer board.

[0094] In this step, if Figure 11 As shown, a sacrificial layer 80 is formed on the test contacts 22 of the interposer 20. The sacrificial layer 80 can protect the test contacts 22 on the interposer 20 from being damaged when packaging the semiconductor test structure 1. For example, the sacrificial layer 80 can include high-temperature tape or aqueous glue to facilitate removal of the sacrificial layer 80 in subsequent steps.

[0095] S7. Form a packaging shell on the packaging substrate.

[0096] In this step, if Figure 12As shown, a packaging shell 60 is formed on the packaging substrate 10. For example, a mold can be formed on the packaging substrate 10, and EMC (Epoxy Molding Compound) is squeezed into the mold cavity and the EMC is embedded in the test chip 30 and the adapter board 20. The EMC is cured in the mold cavity by high temperature to form a packaging shell 60 with a certain hardness.

[0097] S8. Grind the package shell to expose the sacrificial layer.

[0098] In this step, refer to Figure 12 and Figure 13 , grinding the package shell 60 to reduce the mold thickness until the sacrificial layer 80 is exposed, so as to facilitate the removal of the sacrificial layer 80 in the subsequent step to expose the test contacts 22.

[0099] S9. Remove the sacrificial layer to expose the test contacts.

[0100] In this step, refer to Figure 13 and Figure 14 The sacrificial layer 80 can be removed by high temperature or other methods to expose the test contacts 22. This facilitates connection between the test contacts 22 and the tester's probes, allowing the adapter board 20 to transmit test signals to the tester, thereby achieving the test purpose. After removing the sacrificial layer 80, solder balls 70 can be formed on the side of the package substrate 10 facing away from the test chip 30 to facilitate electrical connection between the package substrate 10 and the tester.

[0101] The semiconductor test structure 1 prepared by the above-described preparation method can be used for semiconductor testing. The package shell 60 can protect the test chip 30 and the adapter board 20 from the external environment (water vapor, temperature, pollution, etc.) and realize the composite functions of moisture resistance, pressure resistance, and support.

[0102] The above are only specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A semiconductor test structure, characterized in that: include: Package substrate; an adapter board and a plurality of test chips, wherein the plurality of test chips are stacked on one side of the package substrate and located between the package substrate and the adapter board; the plurality of test chips include a target test chip; A signal line, the packaging substrate and the target test chip are connected through the signal line; the adapter board includes a connection contact, the signal line includes a first wire and a second wire, the first wire and the second wire are connected to the connection contact, the other end of the first wire is connected to the packaging substrate, and the other end of the second wire is connected to the target test chip.

2. The semiconductor test structure according to claim 1, wherein: When the target test chip is the test chip closest to the package substrate among the multiple test chips: the other end of the first wire is directly connected to the package substrate; The semiconductor test structure further includes a first connecting line; any two adjacent test chips among the plurality of test chips are connected via the first connecting line.

3. The semiconductor test structure according to claim 1, wherein: When the target test chip is a test chip between the test chip closest to the package substrate and the test chip farthest from the package substrate among the multiple test chips, the other end of the first wire is connected to the test chip that is located on a side of the target test chip close to the package substrate and closest to the target test chip; The semiconductor test structure further includes a second connecting line connected to the package substrate, the second connecting line connecting the test chip between the target test chip and the package substrate, and the second connecting line connected to the first wire to electrically connect the first wire to the package substrate; The semiconductor test structure further includes a third connecting line; the third connecting line connects the target test chip and the test chip between the adapter board.

4. The semiconductor test structure according to claim 1, wherein: When the target test chip is the test chip closest to the transfer board among the multiple test chips: the other end of the first wire is connected to the test chip that is located on a side of the target test chip close to the packaging substrate and is closest to the target test chip; The semiconductor test structure also includes a fourth connecting line; the fourth connecting line is connected to the packaging substrate, the fourth connecting line connects the test chip between the target test chip and the packaging substrate, and the fourth connecting line is connected to the first wire to electrically connect the first wire to the packaging substrate.

5. The semiconductor test structure according to any one of claims 1 to 4, characterized in that: Also includes: a packaging shell, the packaging shell covering the plurality of test chips and the adapter board and connected to the packaging substrate; The transfer board further includes a test contact; the package housing further includes a test opening, and the test opening exposes the test contact.

6. The semiconductor test structure according to claim 5, wherein: The packaging shell is in contact with the packaging substrate, the test chip and the adapter board.

7. A method for preparing a semiconductor test structure, characterized in that: include: forming a plurality of test chips and an adapter plate in sequence on a packaging substrate, wherein the plurality of test chips include a target test chip; Connecting the first wire and the second wire to the connection contacts on the adapter board; connecting the other end of the first wire to the packaging substrate; The other end of the second wire is connected to the target test chip.

8. The method for preparing a semiconductor test structure according to claim 7, wherein: When the target test chip is the test chip closest to the package substrate among the plurality of test chips, after connecting the other end of the second wire to the target test chip, the method further includes: Any two adjacent test chips are connected via a first connecting line.

9. The method for preparing a semiconductor test structure according to claim 7, wherein: When the target test chip is a test chip between a test chip closest to the package substrate and a test chip farthest from the package substrate among the plurality of test chips, connecting the other end of the first wire to the package substrate includes: connecting the other end of the first wire to a test chip that is located on a side of the target test chip close to the packaging substrate and closest to the target test chip; The packaging substrate, the target test chip, the test chip between the packaging substrate, and the first wire are all connected through the second connection line.

10. The method for preparing a semiconductor test structure according to claim 9, wherein: After connecting the other end of the second wire to the target test chip, the method further includes: The target test chip and the test chip between the adapter board are connected via a third connection line.

11. The method for preparing a semiconductor test structure according to claim 7, wherein: When the target test chip is the test chip closest to the adapter board among the multiple test chips, connecting the other end of the first wire to the package substrate includes: connecting the other end of the first wire to a test chip that is located on a side of the target test chip close to the packaging substrate and closest to the target test chip; The packaging substrate, the target test chip, the test chip between the packaging substrate, and the first wire are all connected via a fourth connecting wire.

12. The method for preparing a semiconductor test structure according to any one of claims 7 to 11, characterized in that: After connecting the other end of the second wire to the target test chip, the method further includes: forming a sacrificial layer on the test contacts of the adapter board; forming a packaging shell on the packaging substrate; Grinding the packaging shell to expose the sacrificial layer; The sacrificial layer is removed to expose the test contacts.

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