Semiconductor structure and forming method of semiconductor structure

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the steps of providing a substrate and a liner layer located on the substrate; a composite structure layer and first grooves located in the composite structure layer are formed on the liner layer, the first grooves are exposed out of the surface of the liner layer, the composite structure layer comprises a plurality of first layers and a plurality of second layers, and the second layers are located between the adjacent first layers; removing a part of the second layer exposed by the first grooves, forming second grooves between adjacent first layers, and communicating the second grooves with the first grooves; dielectric layers are formed on the side wall surface and the bottom surface of the first groove and the side wall surface and the bottom surface of the second groove; forming a first electrode layer in the first groove and the second groove; the composite structure layer is removed, a second electrode layer located on the liner layer is formed, the first electrode layer and the second electrode layer are located on the two sides of the dielectric layer respectively, and the first electrode layer and the second electrode layer are electrically isolated through the dielectric layer. The capacitance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] The semiconductor industry is continually reducing the size of components within integrated circuits.

[0003] For capacitors, reducing the footprint while maintaining the same or higher capacitance is a considerable challenge. Fabricating capacitors with high capacitance / high area ratios is a technical problem that needs to be continuously addressed. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to prepare a capacitor with a high capacitance / high area ratio.

[0005] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate and a liner layer located on the substrate; forming a composite structure layer and a first groove located in the composite structure layer on the liner layer, the first groove exposing the surface of the liner layer, the composite structure layer including several first layers and several second layers, the second layer being located between adjacent first layers, and the first layer and the second layer being made of different materials; removing the portion of the second layer exposed by the first groove, forming a second groove between adjacent first layers, the second groove being connected to the first groove; forming a dielectric layer on the sidewall surface and bottom surface of the first groove, and on the sidewall surface and bottom surface of the second groove; forming a first electrode layer located in the first groove and the second groove; removing the composite structure layer to form a second electrode layer located on the liner layer, the first electrode layer and the second electrode layer being located on both sides of the dielectric layer, respectively, and the first electrode layer and the second electrode layer being electrically isolated by the dielectric layer.

[0006] Optionally, the method for forming the dielectric layer, the first electrode layer and the second electrode layer includes: forming a dielectric material layer on the side wall surface and bottom surface of the first groove, the side wall surface and bottom surface of the second groove and the top surface of the composite structure layer; forming a filling material layer on the dielectric material layer; flattening the filling material layer and the dielectric material layer until the surface of the composite structure layer is exposed, forming a dielectric layer on the side wall surface and bottom surface of the first groove, and the side wall surface and bottom surface of the second groove, and forming a filling layer located on the surface of the dielectric layer in the first groove and the second groove; removing the composite structure layer until the surface of the liner layer and the side wall surface of the dielectric layer are exposed; forming an electrode material layer on the liner layer and the surface of the filling layer; flattening the electrode material layer until the top surface of the filling layer and the top surface of the dielectric layer are exposed, and forming a second electrode layer on the liner layer.

[0007] Optionally, the material of the filling layer is the same as that of the first electrode layer, and the filling layer serves as the first electrode layer.

[0008] Optionally, after forming the second electrode layer, the filling layer is removed; after removing the filling layer, an electrode material layer is formed in the first groove, in the second groove and on the top surface of the second electrode layer; the electrode material layer is flattened until the top surface of the second electrode layer and the top surface of the dielectric layer are exposed to form a first electrode layer located on the surface of the dielectric layer, the first electrode layer and the second electrode layer are respectively located on both sides of the dielectric layer, and the first electrode layer and the second electrode layer are electrically isolated by the dielectric layer.

[0009] Optionally, the material of the filling layer is different from the material of the dielectric layer.

[0010] Optionally, the material of the filling layer includes an organic material, and the organic material includes amorphous carbon or amorphous silicon.

[0011] Optionally, the material of the dielectric layer is different from the material of the composite structure layer.

[0012] Optionally, the material of the dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the material of the dielectric layer includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0013] Optionally, the material of the first electrode layer is different from the material of the second electrode layer.

[0014] Optionally, there are multiple first electrode layers and dielectric layers; and the method further includes: forming a connection layer at the bottom or top of the multiple first electrode layers, and the multiple first electrode layers are electrically connected through the connection layer.

[0015] Optionally, the substrate includes a first region and a second region, and the first electrode layer, the second electrode layer and the dielectric layer are located on the first region; it also includes: a device structure formed on the second region and several conductive layers located on the device structure, the device structure and the conductive layer are located in the pad layer, the conductive layer is electrically connected to the device structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure; the first electrode layer or the second electrode layer is formed simultaneously with one of the target conductive layers, and the connecting layer is formed simultaneously with the upper conductive layer or the lower conductive layer of the target conductive layer.

[0016] Optionally, the material of the first layer includes a dielectric material, which includes silicon nitride, silicon oxycarbide, silicon oxynitride or silicon oxide; the material of the second layer includes a dielectric material, which includes silicon nitride, silicon oxycarbide, silicon oxynitride or silicon oxide.

[0017] Optionally, the projection shape of the first groove on the substrate includes a circle, an ellipse or a square.

[0018] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate and a liner layer located on the substrate; a second electrode layer located on the liner layer; a first groove and a second groove located in the second electrode layer, the second groove is connected to the first groove, and the bottom of the second groove extends into the second electrode layer of the side wall of the first groove; a dielectric layer located on the side wall surface and bottom surface of the first groove, and the side wall surface and bottom surface of the second groove; a first electrode layer located in the first groove and the second groove, the first electrode layer and the second electrode layer are respectively located on both sides of the dielectric layer, and the first electrode layer and the second electrode layer are electrically isolated by the dielectric layer.

[0019] Optionally, the material of the dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the material of the dielectric layer includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0020] Optionally, the material of the first electrode layer is different from the material of the second electrode layer.

[0021] Optionally, the material of the first electrode layer includes: one or more of metals and metal nitrides, and the material of the second electrode layer includes: one or more of metals and metal nitrides; the metal includes titanium, copper, aluminum, tungsten, cobalt, nickel or tantalum, and the metal nitride includes titanium nitride or tantalum nitride.

[0022] Optionally, there are multiple first electrode layers and dielectric layers; and further comprising: a connection layer located at the bottom or top of the multiple first electrode layers, and the multiple first electrode layers are electrically connected through the connection layer.

[0023] Optionally, the substrate includes a first region and a second region, and the first electrode layer, the second electrode layer and the dielectric layer are located on the first region; it also includes: a device structure located on the second region, and several conductive layers located on the device structure, the device structure and part of the conductive layer are located in the pad layer, the conductive layer is electrically connected to the device structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure; the first electrode layer or the second electrode layer is formed simultaneously with a target conductive layer on the pad layer, and the connecting layer is formed simultaneously with the upper conductive layer or the lower conductive layer of the target conductive layer.

[0024] Optionally, the material of the liner layer includes a dielectric material, and the dielectric material includes silicon oxide, silicon nitride or silicon oxycarbide.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] In the semiconductor structure of the present invention, the first electrode layer and the second electrode layer are respectively located on both sides of the dielectric layer in a direction parallel to the substrate surface, and the dielectric layer is located on the sidewall surface and bottom surface of the first groove and the sidewall surface and bottom surface of the second groove. Without increasing the opening size of the first groove and the size of the first region, the dielectric layer is located on the sidewall surface and bottom surface of the second groove, which can increase the area of ​​the dielectric layer, thereby increasing the capacitance of the capacitor formed by the first electrode layer, the second electrode layer and the dielectric layer.

[0027] Furthermore, the dielectric constant of the dielectric layer material is greater than 3.9. The dielectric constant of the dielectric layer material is relatively large, so that the capacitance of the capacitor formed by the first electrode layer, the second electrode layer and the dielectric layer is increased.

[0028] In the method for forming a semiconductor structure of the present invention, the process of forming a capacitor in the first region of the substrate can be integrated with the process of forming a semiconductor structure in the second region, thereby simplifying the process flow, improving production efficiency, and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 11 is a schematic diagram of a semiconductor structure forming process according to an embodiment of the present invention;

[0030] Figure 12 and Figure 13 FIG. 4 is a schematic diagram of a semiconductor structure forming process according to another embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 1 to 11FIG. 1 is a schematic diagram of a semiconductor structure forming process according to an embodiment of the present invention.

[0033] Please refer to Figure 1 , providing a substrate 200 and a lining layer 201 located on the substrate 200; forming a composite structure layer on the lining layer 201, the composite structure layer includes several first layers 202 and several second layers 203, the second layers 203 are located between adjacent first layers 202, and the materials of the first layers 202 and the second layers 203 are different.

[0034] The substrate 200 includes a first region and a second region, and the composite structure layer is located on the first region. Figure 1 Shown is the structure of the first zone. Figure 1 Three first layers 202 and two second layers 203 are schematically shown.

[0035] The material of the first layer 202 includes a dielectric material, which includes silicon nitride, silicon oxycarbide, silicon oxynitride, or silicon oxide; the material of the second layer 203 includes a dielectric material, which includes silicon nitride, silicon oxycarbide, silicon oxynitride, or silicon oxide.

[0036] In this embodiment, the material of the first layer 202 includes silicon oxide; the material of the second layer 203 includes silicon nitride.

[0037] The first layer 202 and the second layer 203 are made of different materials, so that the second layer 203 can be selectively removed later.

[0038] The material of the liner layer 201 includes a dielectric material including silicon oxide, silicon nitride or silicon oxycarbide. The material of the liner layer 201 is different from that of the composite structure layer so that the subsequent etching process of the composite structure layer can stop on the surface of the liner layer 201.

[0039] Please refer to Figure 2 , forming a first groove 204 located in the composite structure layer, wherein the first groove 204 exposes the surface of the liner layer 201 .

[0040] The projection shape of the first groove 204 on the substrate 200 includes a circle, an ellipse or a square.

[0041] The method for forming the first groove 204 includes: forming a patterned mask layer (not shown) on the composite structure layer; using the patterned mask layer as a mask, etching the composite structure layer using an anisotropic dry etching process until the surface of the liner layer 201 is exposed, thereby forming a first groove 204 in the composite structure layer.

[0042] Please refer to Figure 3, removing the portion of the second layer 203 exposed by the first groove 204 , forming a second groove 205 between adjacent first layers 202 , and the second groove 205 is connected to the first groove 204 .

[0043] The process of removing the portion of the second layer 203 exposed by the first groove 204 includes an isotropic etching process. The etching rate of the isotropic etching process on the second layer 203 is greater than the etching rate on the first layer 202 .

[0044] In this embodiment, the isotropic etching process includes a wet etching process, and the etching solution of the wet etching process includes phosphoric acid.

[0045] Next, a dielectric layer is formed on the sidewall surface and bottom surface of the first groove 204 and the sidewall surface and bottom surface of the second groove 205; a first electrode layer is formed in the first groove 204 and the second groove 205; the composite structure layer is removed to form a second electrode layer on the liner layer, the first electrode layer and the second electrode layer are respectively located on both sides of the dielectric layer, and the first electrode layer and the second electrode layer are electrically isolated by the dielectric layer. The formation process of the dielectric layer, the first electrode layer and the second electrode layer can be referred to Figures 4 to 9 .

[0046] Please refer to Figure 4 A dielectric material layer 206 is formed on the sidewall surface and bottom surface of the first groove 204, the sidewall surface and bottom surface of the second groove 205, and the top surface of the composite structure layer.

[0047] The material of the dielectric material layer 206 is different from that of the composite structure layer, so that when the composite structure layer is subsequently removed, the process of removing the composite structure layer causes less damage to the dielectric material layer 206 .

[0048] The material of the dielectric material layer 206 includes a high dielectric constant material, the dielectric constant of which is greater than 3.9. The material of the dielectric material layer 206 includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0049] Please refer to Figure 5 , forming a filling material layer 207 on the dielectric material layer 206 .

[0050] In this embodiment, the material of the filling material layer 207 includes one or more of metal and metal nitride, the metal includes titanium, copper, aluminum, tungsten, cobalt, nickel or tantalum, and the metal nitride includes titanium nitride or tantalum nitride.

[0051] Please refer to Figure 6, planarize the filling material layer 207 and the dielectric material layer 206 until the surface of the composite structure layer is exposed, form a dielectric layer 208 on the side wall surface and bottom surface of the first groove 204, and the side wall surface and bottom surface of the second groove 205, and form a filling layer located on the surface of the dielectric layer in the first groove 204 and the second groove 205.

[0052] In this embodiment, the material of the filling layer is the same as that of the first electrode layer, and the filling layer is the first electrode layer 209 .

[0053] Please refer to Figure 7 , removing the composite structure layer until the surface of the liner layer 201 and the sidewall surface of the dielectric layer 208 are exposed.

[0054] The process of removing the composite structure layer includes an isotropic wet etching process. The dielectric layer 208 and the composite structure layer are made of different materials. Therefore, the isotropic wet etching process causes less damage to the dielectric layer 208 .

[0055] Please refer to Figure 8 and Figure 9 , Figure 9 for Figure 8 A top view of Figure 8 for Figure 9 Schematic diagram of the structure along the section line AA1, an electrode material layer (not shown) is formed on the pad layer 201 and the surface of the first electrode layer 209; the electrode material layer is flattened until the top surface of the first electrode layer 209 and the top surface of the dielectric layer 208 are exposed, and a second electrode layer 210 is formed on the pad layer 201, and the first electrode layer 209 and the second electrode layer 210 are respectively located on both sides of the dielectric layer 208, and the first electrode layer 209 and the second electrode layer 210 are electrically isolated by the dielectric layer 208.

[0056] In this embodiment, the material of the first electrode layer 209 is different from the material of the second electrode layer 210 , so that the process of planarizing the electrode material layer to form the second electrode layer 210 can stop on the first electrode layer 209 .

[0057] The material of the first electrode layer 209 includes one or more of metals and metal nitrides, the metal including titanium, copper, aluminum, tungsten, cobalt, nickel or tantalum, and the metal nitride including titanium nitride or tantalum nitride; the material of the second electrode layer 210 includes one or more of metals and metal nitrides, the metal including titanium, copper, aluminum, tungsten, cobalt, nickel or tantalum, and the metal nitride including titanium nitride or tantalum nitride.

[0058] In another embodiment, the material of the first electrode layer is the same as the material of the second electrode layer.

[0059] In this embodiment, the first electrode layer 209 and the second electrode layer 210 are respectively located on both sides of the dielectric layer 208 along a direction parallel to the surface of the substrate 200. The dielectric layer 208 is located on the side wall surface and bottom surface of the first groove 204 and the side wall surface and bottom surface of the second groove 205. Without increasing the opening size of the first groove 204 and the size of the first region, the dielectric layer 208 is located on the side wall surface and bottom surface of the second groove 205, which can increase the area of ​​the dielectric layer 208, thereby increasing the capacitance of the capacitor formed by the first electrode layer 209, the second electrode layer 210 and the dielectric layer 208.

[0060] In addition, the dielectric constant of the material of the dielectric layer 208 is greater than 3.9. The dielectric constant of the material of the dielectric layer 208 is large, so that the capacitance of the capacitor formed by the first electrode layer 209, the second electrode layer 210 and the dielectric layer 208 is increased.

[0061] In this embodiment, there are multiple first electrode layers 209 and multiple dielectric layers 208. The multiple first electrode layers 209 are electrically connected to each other.

[0062] Please refer to Figure 10 A connection layer 212 is formed on top of the plurality of first electrode layers 209 , and the plurality of first electrode layers 209 are electrically connected through the connection layer 212 .

[0063] In this embodiment, the connection layer 212 is electrically connected to each of the first electrode layers 209 through the first plugs 211 .

[0064] The plurality of first electrode layers 209 are electrically connected to each other, that is, a plurality of capacitors are connected in parallel, thereby further increasing the capacitance without increasing the size of the first region.

[0065] In another embodiment, before forming the composite structure layer on the liner layer, the method further includes: forming a connection layer on the liner layer, wherein the plurality of first electrode layers are located on the connection layer, and the plurality of first electrode layers are electrically connected via the connection layer.

[0066] Please refer to Figure 11 , Figure 11 This is a schematic diagram of the structure of the second area of ​​the substrate 200, which also includes: a device structure 301 formed on the second area, and several conductive layers 304 located on the device structure 301, the device structure and part of the conductive layer 304 are located in the liner layer 201, and part of the conductive layer 304 is located in the dielectric structure 302 on the liner layer 201, and the conductive layer 304 is electrically connected to the device structure 301.

[0067] In this embodiment, the process further includes forming second plugs 303 between adjacent conductive layers 304 and between the conductive layer 304 and the device structure 301 .

[0068] The device structure 301 includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure. In this embodiment, the device structure 301 includes a transistor.

[0069] In this embodiment, the first electrode layer 209 or the second electrode layer 210 is formed simultaneously with one of the target conductive layers 304 on the liner layer 201 .

[0070] In this embodiment, the connection layer is formed simultaneously with the upper conductive layer of the target conductive layer 304. The first plug 211 is formed simultaneously with the second plug 303 on the target conductive layer 304.

[0071] In another embodiment, a plurality of first electrode layers are located on the connection layer, and the connection layer is formed simultaneously with a lower conductive layer of the target conductive layer.

[0072] The process of forming the capacitor in the first region of the substrate can be integrated with the process of forming the semiconductor structure in the second region, which can save process flow, improve production efficiency and save costs.

[0073] Accordingly, a semiconductor structure is also provided in the embodiment of the present invention, please continue to refer to Figure 10 and Figure 11 ,include:

[0074] A substrate 200 and a liner layer 201 located on the substrate 200;

[0075] a second electrode layer 210 located on the liner layer 201;

[0076] A first groove and a second groove are located in the second electrode layer 210, wherein the second groove is connected to the first groove, and the bottom of the second groove extends into the second electrode layer 210 on the sidewall of the first groove;

[0077] a dielectric layer 208 located on the sidewall surface and the bottom surface of the first groove and the sidewall surface and the bottom surface of the second groove;

[0078] The first electrode layer 209 is located in the first groove and the second groove. The first electrode layer 209 and the second electrode layer 210 are respectively located on both sides of the dielectric layer 208. The first electrode layer 209 and the second electrode layer 210 are electrically isolated by the dielectric layer 208.

[0079] In this embodiment, the material of the dielectric layer 208 includes a high dielectric constant material, the dielectric constant of which is greater than 3.9, and the material of the dielectric layer 208 includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0080] In this embodiment, the material of the first electrode layer is different from the material of the second electrode layer.

[0081] In this embodiment, the material of the first electrode layer 209 includes: one or more of metals and metal nitrides, and the material of the second electrode layer 210 includes: one or more of metals and metal nitrides; the metal includes titanium, copper, aluminum, tungsten, cobalt, nickel or tantalum, and the metal nitride includes titanium nitride or tantalum nitride.

[0082] In this embodiment, there are multiple first electrode layers 209 and dielectric layers 208 . The embodiment further includes a connection layer 212 located on top of the multiple first electrode layers 209 , and the multiple first electrode layers 209 are electrically connected via the connection layer 212 .

[0083] In this embodiment, the substrate 200 includes a first region and a second region, and the first electrode layer 209 , the second electrode layer 210 and the dielectric layer 208 are located on the first region.

[0084] In this embodiment, please continue to refer to Figure 11 , also includes: a device structure 301 located on the second area, and several layers of conductive layers 304 located on the device structure 301, the device structure 301 and the conductive layer 304 are located in the liner layer 201, the conductive layer 304 is electrically connected to the device structure 301, and the device structure 301 includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0085] In this embodiment, the first electrode layer 209 or the second electrode layer 210 is formed simultaneously with one of the target conductive layers 304 , and the connecting layer 212 is formed simultaneously with the upper conductive layer or the lower conductive layer of the target conductive layer 304 .

[0086] In this embodiment, the material of the liner layer 201 includes a dielectric material, and the dielectric material includes silicon oxide, silicon nitride, or silicon oxycarbide.

[0087] Figure 12 and Figure 13 FIG. 4 is a schematic diagram of a semiconductor structure forming process according to another embodiment of the present invention.

[0088] Please refer to Figure 12 , Figure 12 For Figure 8Based on the schematic diagram, after the second electrode layer 210 is formed, the filling layer is removed; after removing the filling layer, an electrode material layer 307 is formed in the first groove 204, in the second groove 205 and on the top surface of the second electrode layer 210.

[0089] In this embodiment, the material of the filling layer is different from that of the dielectric layer 208. Therefore, during the process of removing the filling layer, the etching rate of the dielectric layer 208 during the process of removing the filling layer is greater than the etching rate of the filling layer, so that the dielectric layer 208 is less damaged.

[0090] The filling layer is made of an organic material, and the organic material includes amorphous carbon or amorphous silicon.

[0091] In this embodiment, the process of removing the filling layer includes a dry etching process or a wet etching process, and the etching solution of the wet etching process includes ammonium hydroxide.

[0092] Please refer to Figure 13 , flattening the electrode material layer 307 until the top surface of the second electrode layer 210 and the top surface of the dielectric layer 208 are exposed, forming a first electrode layer 309 located on the surface of the dielectric layer 208, wherein the first electrode layer 309 and the second electrode layer 210 are respectively located on both sides of the dielectric layer 208, and the first electrode layer 309 and the second electrode layer 210 are electrically isolated by the dielectric layer 208.

[0093] The material of the first electrode layer 309 includes one or more of metal and metal nitride. The metal includes titanium, copper, aluminum, tungsten, cobalt, nickel or tantalum. The metal nitride includes titanium nitride or tantalum nitride.

[0094] In this embodiment, the material of the first electrode layer 309 is different from the material of the second electrode layer 210 .

[0095] In another embodiment, the material of the first electrode layer is the same as the material of the second electrode layer.

[0096] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate and a liner layer located on the substrate; forming a composite structural layer and a first groove in the composite structural layer on the liner layer, wherein the first groove exposes the surface of the liner layer, the composite structural layer includes a plurality of first layers and a plurality of second layers, wherein the second layers are located between adjacent first layers, and the first and second layers are made of different materials; removing a portion of the second layer exposed by the first groove, forming a second groove between adjacent first layers, wherein the second groove is connected to the first groove; forming a dielectric layer on the sidewall surface and the bottom surface of the first groove and the sidewall surface and the bottom surface of the second groove; forming a first electrode layer located in the first groove and the second groove; The composite structure layer is removed to form a second electrode layer on the liner layer, the first electrode layer and the second electrode layer are respectively located on both sides of the dielectric layer, and the first electrode layer and the second electrode layer are electrically isolated by the dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the dielectric layer, the first electrode layer and the second electrode layer includes: forming a dielectric material layer on the side wall surface and bottom surface of the first groove, the side wall surface and bottom surface of the second groove and the top surface of the composite structure layer; forming a filling material layer on the dielectric material layer; planarizing the filling material layer and the dielectric material layer until the surface of the composite structure layer is exposed, forming a dielectric layer on the side wall surface and bottom surface of the first groove, and the side wall surface and bottom surface of the second groove, and forming a filling layer located on the surface of the dielectric layer in the first groove and the second groove; removing the composite structure layer until the surface of the liner layer and the side wall surface of the dielectric layer are exposed; forming an electrode material layer on the liner layer and the surface of the filling layer; planarizing the electrode material layer until the top surface of the filling layer and the top surface of the dielectric layer are exposed, and forming a second electrode layer on the liner layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the filling layer is the same as that of the first electrode layer, and the filling layer serves as the first electrode layer.

4. The method for forming a semiconductor structure according to claim 2, wherein: After forming the second electrode layer, the filling layer is removed; after removing the filling layer, an electrode material layer is formed in the first groove, in the second groove and on the top surface of the second electrode layer; the electrode material layer is flattened until the top surface of the second electrode layer and the top surface of the dielectric layer are exposed, forming a first electrode layer located on the surface of the dielectric layer, the first electrode layer and the second electrode layer are respectively located on both sides of the dielectric layer, and the first electrode layer and the second electrode layer are electrically isolated by the dielectric layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The material of the filling layer is different from that of the dielectric layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: The filling layer is made of an organic material, and the organic material includes amorphous carbon or amorphous silicon.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the dielectric layer is different from the material of the composite structure layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The material of the dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the material of the dielectric layer includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first electrode layer is different from that of the second electrode layer.

10. The method for forming a semiconductor structure according to claim 1, wherein: There are multiple first electrode layers and dielectric layers; and the method further includes: forming a connection layer at the bottom or top of the multiple first electrode layers, and the multiple first electrode layers are electrically connected through the connection layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The substrate includes a first region and a second region, and the first electrode layer, the second electrode layer and the dielectric layer are located on the first region; it also includes: a device structure formed on the second region and several conductive layers located on the device structure, the device structure and the conductive layer are located in the liner layer, the conductive layer is electrically connected to the device structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure; the first electrode layer or the second electrode layer is formed simultaneously with one of the target conductive layers, and the connecting layer is formed simultaneously with the upper conductive layer or the lower conductive layer of the target conductive layer.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first layer includes a dielectric material, which includes silicon nitride, silicon oxycarbide, silicon oxynitride, or silicon oxide; the material of the second layer includes a dielectric material, which includes silicon nitride, silicon oxycarbide, silicon oxynitride, or silicon oxide.

13. The method for forming a semiconductor structure according to claim 1, wherein: The projection shape of the first groove on the substrate includes a circle, an ellipse or a square.

14. A semiconductor structure, characterized in that include: a substrate and a liner layer located on the substrate; a second electrode layer located on the liner layer; a first groove and a second groove located in the second electrode layer, wherein the second groove is connected to the first groove, and the bottom of the second groove extends into the second electrode layer on the sidewall of the first groove; and a dielectric layer located on the sidewall surface and bottom surface of the first groove and the sidewall surface and bottom surface of the second groove; The first electrode layer is located in the first groove and the second groove. The first electrode layer and the second electrode layer are respectively located on both sides of the dielectric layer. The first electrode layer and the second electrode layer are electrically isolated by the dielectric layer.

15. The semiconductor structure according to claim 14, wherein: The material of the dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the material of the dielectric layer includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

16. The semiconductor structure according to claim 14, wherein: The material of the first electrode layer is different from that of the second electrode layer.

17. The semiconductor structure according to claim 16, wherein: The material of the first electrode layer includes: one or more of metals and metal nitrides, and the material of the second electrode layer includes: one or more of metals and metal nitrides; the metal includes titanium, copper, aluminum, tungsten, cobalt, nickel or tantalum, and the metal nitride includes titanium nitride or tantalum nitride.

18. The semiconductor structure according to claim 14, wherein: There are multiple first electrode layers and dielectric layers; and further comprising: a connection layer located at the bottom or top of the multiple first electrode layers, and the multiple first electrode layers are electrically connected through the connection layer.

19. The semiconductor structure according to claim 18, wherein: The substrate includes a first region and a second region, and the first electrode layer, the second electrode layer and the dielectric layer are located on the first region; it also includes: a device structure located on the second region, and several conductive layers located on the device structure, the device structure and part of the conductive layer are located in the pad layer, the conductive layer is electrically connected to the device structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure; the first electrode layer or the second electrode layer is formed simultaneously with a target conductive layer on the pad layer, and the connecting layer is formed simultaneously with the upper conductive layer or the lower conductive layer of the target conductive layer.

20. The method for forming a semiconductor structure according to claim 14, wherein: The material of the liner layer includes a dielectric material, and the dielectric material includes silicon oxide, silicon nitride or silicon oxycarbide.

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