A method and circuit for eliminating output voltage fluctuations during startup in a switching power supply chip

Abstract

The present invention provides a method and circuit for eliminating output voltage fluctuations during startup in a switching power supply chip. During the soft-start phase of the switching power supply, a three-stage mode switching is designed. A fixed-frequency discontinuous current mode is additionally added as an intermediate mode between a variable-frequency discontinuous current mode and a fixed-frequency forced continuous current mode. This solves the problem of excessive output voltage fluctuations caused by two-stage mode switching at the end of soft-start in conventional switching power supply chips, thereby greatly improving chip reliability and system performance. Furthermore, the present invention does not require the addition of additional digital and analog interfaces, nor does it require external compensation components, thereby reducing costs and ensuring versatility and reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and more particularly to a method and circuit for eliminating output voltage fluctuations during startup. Background Art

[0002] In existing industrial electronic applications with high performance requirements, such as server arrays, storage, telecommunications base stations, and embedded computing, there is a huge demand for switching power supply chips with high switching frequency, high voltage, and high load current. The requirements for output voltage stability of switching power supply chips are increasing day by day. However, existing switching power supply chips will experience voltage fluctuations at the output voltage due to mode switching during startup.

[0003] Therefore, there is an urgent need for a low-cost, high-reliability elimination circuit that can eliminate output voltage fluctuations when a switching power supply chip is started.

[0004] According to the existing switching power supply chip startup circuit Figure 1 As shown, it includes an error amplifier, a soft-start comparator, a current comparator, a wake-up comparator, a current detection module, a clock module, a current detection module, a current zero-crossing detection module, a PWM controller, a power upper tube Q1, a power lower tube Q2, an inductor L, an output capacitor Co, etc.

[0005] During the soft start phase after the chip is powered on, the system operates in the variable frequency discontinuous current mode; when the soft start ends, the system directly switches from the variable frequency discontinuous current mode to the fixed frequency forced continuous current mode.

[0006] like Figure 2 As shown in the waveform timing diagram, at the end of soft-start, Tstart_end, the system switches directly from variable-frequency discontinuous current mode to fixed-frequency forced continuous current mode. This direct switch can cause significant fluctuations in Vc and the output voltage Vo, affecting chip efficiency and potentially causing system instability, impacting chip reliability, and creating a significant risk of downtime and damage to downstream circuits.

[0007] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the Invention

[0008] The purpose of the present invention is to solve the problem of excessive output voltage fluctuation caused by mode switching at the end of soft start in traditional switching power supply chips. A method and circuit for eliminating output voltage fluctuation during startup in a switching power supply chip are proposed. The present invention designs a three-stage mode switching to reduce fluctuations in Vc and output voltage Vo, greatly improving chip reliability and system performance.

[0009] The technical solution of the present invention is:

[0010] The present invention provides a method for eliminating output voltage fluctuations during startup in a switching power supply chip, comprising:

[0011] Obtain the output voltage and generate a feedback voltage through a feedback resistor, compare it with the reference level and amplify it to generate an error level;

[0012] Generating a sampling voltage by sampling the inductor current, and comparing the sampling voltage with the error level to generate a comparison signal to control the switching states of the power upper tube and the power lower tube;

[0013] The switches of the power upper tube and the power lower tube are controlled by three-stage mode switching, including a variable frequency discontinuous current mode, a fixed frequency discontinuous current mode and a fixed frequency forced continuous current mode, wherein the fixed frequency discontinuous current mode is arranged as an intermediate mode between the variable frequency discontinuous current mode and the fixed frequency forced continuous current mode to reduce output voltage fluctuations.

[0014] Furthermore, the method comprises the following steps:

[0015] S1. Obtain the output voltage and generate a feedback voltage through a feedback resistor, input the feedback voltage and a reference level into an error amplifier to obtain an error level; sample the inductor current to generate a sampling voltage, input the sampling voltage and the error level into a current comparator to generate a comparison signal Vcmp;

[0016] S2. When the switching power supply chip is in the soft start phase after power-on, the circuit enters a variable frequency discontinuous current mode, and the current source charges the capacitor to generate the reference level;

[0017] If the inductor current crosses zero, the current zero-crossing detection module is triggered to output a shutdown signal, turning off both the upper and lower power tubes to avoid negative inductor current.

[0018] S3. When the soft start is completed, the circuit switches from the variable frequency discontinuous current mode to the fixed frequency discontinuous current mode; the clock signal and the output signal of the wake-up comparator jointly trigger the opening of the power upper tube and the shutdown of the power lower tube;

[0019] If the inductor current crosses zero, the current zero-crossing detection module is triggered to output a shutdown signal, turning off both the upper and lower power tubes to avoid negative inductor current.

[0020] S4: In the fixed-frequency discontinuous current mode, the clock signal is counted. When the accumulated count reaches a preset threshold, the circuit switches from the fixed-frequency discontinuous current mode to the fixed-frequency forced continuous current mode. The rising edge of the clock signal triggers the turning on of the upper power tube and the turning off of the lower power tube.

[0021] Negative inductor current is allowed, and the frequency of the duty cycle signal output by the trigger is consistent with the frequency of the clock signal.

[0022] Furthermore, S1 includes:

[0023] Feedback resistors R1 and R2 are used to divide the output voltage Vo to obtain the feedback voltage Vfb. The feedback voltage Vfb is input into the error amplifier for comparison and amplification with the reference level vref1 to generate the error level Vc.

[0024] The inductor current I L Sampling is performed to obtain a sampled voltage Vsns; the sampled voltage Vsns is compared with the error level Vc input current comparator to generate a comparison signal Vcmp;

[0025] The switching states of the power upper tube Q1 and the power lower tube Q2 are controlled according to the comparison signal Vcmp; if the comparison signal Vcmp jumps from a low level to a high level, Q1 is turned off and Q2 is turned on.

[0026] Furthermore, S2 includes:

[0027] During the soft start phase, the circuit operates in variable frequency discontinuous current mode. At this time, the wake-up comparator outputs the Vwake signal to turn on the upper power tube Q1 and turn off the lower power tube Q2.

[0028] When the inductor current passes through zero, the current zero-crossing detection module outputs a high level Vzc that takes precedence over other control signals, and synchronously turns off the upper power tube Q1 and the lower power tube Q2.

[0029] Furthermore, S3 includes:

[0030] When the soft start is completed, the inverting input terminal Vref1 of the soft start comparator is connected to the non-inverting input terminal Vref, and the soft start comparator output Vsoft is low. The trigger counter starts to receive the CLK signal output by the clock module and counts. During the counting period, the counter output voltage Vsoft_delay is maintained at a high level.

[0031] The clock module outputs the CLK signal and the wake-up comparator outputs the Vwake signal, and a logic AND operation is performed. When the CLK and Vwake signals are both high, the power upper tube Q1 is triggered to turn on and the power lower tube Q2 is turned off.

[0032] When the inductor current passes through zero, the current zero-crossing detection module outputs a high level Vzc that takes precedence over other control signals, and synchronously turns off the upper power tube Q1 and the lower power tube Q2.

[0033] In the constant-frequency discontinuous current mode, the counter output voltage Vsoft_delay is triggered to be low after the counter completes the preset number of counts.

[0034] Furthermore, in S4, in the fixed-frequency forced continuous current mode, the soft-start comparator output voltage Vsoft and the counter output voltage Vsoft_delay become low levels at the same time. At this time, the rising edge of the CLK signal output by the clock module controls the power upper tube Q1 to turn on and the power lower tube Q2 to turn off.

[0035] A startup voltage fluctuation elimination circuit in a switching power supply chip includes: an error amplifier, a current source I1, a capacitor C1, a soft-start comparator, a current comparator, a wake-up comparator, a current detection module, a clock module, a current zero-crossing detection module, a trigger, a PWM controller, and a power upper tube Q1 and a power lower tube Q2;

[0036] The output voltage is fed back through the error amplifier to generate a feedback voltage, which is compared with a reference level and output as an error level. The inductor current is sampled through the current detection module to generate a sampled voltage. The current comparator compares the sampled voltage with the error level to generate a comparison signal Vcmp, which is output to the trigger to control the switching states of the power upper tube Q1 and the power lower tube Q2.

[0037] When the switching power supply chip is in the soft start phase after power-on, the circuit enters the variable frequency discontinuous current mode, the current source I1 charges the capacitor C1 to generate the reference level, and the soft start comparator outputs a control signal Vsoft, which is combined with the output signal Vwake of the wake-up comparator to control the power upper tube Q1 to turn on and the power lower tube Q2 to turn off;

[0038] When the soft start is over, the circuit switches from the variable frequency discontinuous current mode to the fixed frequency discontinuous current mode; the clock signal and the output signal of the wake-up comparator jointly trigger the opening of the power upper tube and the shutdown of the power lower tube;

[0039] In the fixed-frequency discontinuous current mode, the clock signal is counted. When the accumulated count reaches the preset threshold, the circuit switches from the fixed-frequency discontinuous current mode to the fixed-frequency forced continuous current mode; the rising edge of the clock signal triggers the turning on of the power upper tube and the turning off of the power lower tube.

[0040] Furthermore, the circuit includes an inductor L, a capacitor Co, a current source I1, a capacitor C1, feedback resistors R1 and R2, an error amplifier, a soft-start comparator, a current comparator, a wake-up comparator, a current detection module, a clock module, a counter, a current zero-crossing detection module, a trigger, a PWM controller, and a power upper tube Q1 and a power lower tube Q2;

[0041] The inductor L is connected in series between the power upper tube Q1 and the output voltage Vo, one end of the capacitor Co is connected to the output voltage Vo, and the other end is grounded;

[0042] The output voltage Vo is connected in series with feedback resistors R1 and R2 and then grounded. The connection point of the feedback resistors R1 and R2 generates a feedback voltage Vfb which is connected to the inverting input of the error amplifier. The non-inverting input of the error amplifier is connected to the reference level vref1. The output of the error amplifier outputs the error level Vc to the non-inverting input of the current comparator. The inverting input of the current comparator is connected to the output of the current detection module and the input of the current zero-crossing detection module. The current detection module is connected to the inductor L for sampling. The output of the current zero-crossing detection module is connected to the input of the PWM controller. The two output ends of the PWM controller are respectively connected to the power upper tube Q1 and the power lower tube Q2. The switch of the power upper tube Q1 is connected in series between the input voltage Vin and the inductor L. One end of the power lower tube Q2 is connected to the connection point between the current detection module and the inductor L, and the other end is grounded.

[0043] The output terminal of the current comparator is connected to the trigger R terminal, the trigger Q terminal is connected to the duty cycle signal input terminal of the PWM controller, the trigger S terminal is connected to the output terminal of the first AND gate through the switch K1, connected to the output terminal Vwake of the wake-up comparator through the switch K2, and connected to the output terminal of the clock module through the switch K3, one input terminal of the first AND gate is connected to the clock module, and the other input terminal is connected to the output terminal Vwake of the wake-up comparator, the non-inverting input terminal of the wake-up comparator is connected to the non-inverting input terminal of the current comparator, and the inverting input terminal of the wake-up comparator is connected to the non-inverting input terminal Vref of the soft start comparator;

[0044] The control signal of the switch K1 is output by a second AND gate, one input of which is connected to the output terminal Vsoft_delay of the counter, and the other input of which is connected to the output terminal Vsoft of the soft-start comparator via a NOT gate. The control signal of the switch K2 is connected to the output terminal Vsoft of the soft-start comparator. The control signal of the switch K3 is connected to the output terminal Vsoft_delay of the counter via a NOT gate.

[0045] One input terminal of the counter is connected to the clock module, and the other input terminal is connected to the output terminal Vsoft of the start comparator. The inverting input terminal of the soft start comparator serves as a reference level vref1 and is connected to the connection point of the current source I1 and the capacitor C1 through a switch K4. The current source I1 is connected in series with the capacitor C1 and then grounded. A switch K5 is connected in series between the inverting input terminal Vref1 and the non-inverting input terminal Vref of the soft start comparator. The control signal of the switch K4 is connected to the output terminal Vsoft of the soft start comparator. The control signal of the switch K5 is connected to the output terminal Vsoft of the soft start comparator through a NOT gate.

[0046] Beneficial effects of the present invention:

[0047] The method of the present invention designs a three-stage mode switching in the soft start phase of the switching power supply. Between the traditional variable frequency discontinuous current mode and the fixed frequency forced continuous current mode, the fixed frequency discontinuous current mode is additionally added as an intermediate mode. This solves the problem of excessive output voltage fluctuation caused by the two-stage mode switching of the traditional switching power supply chip at the end of soft start, greatly improving the chip reliability and system performance. At the same time, the present invention does not need to add additional digital interfaces and analog interfaces, nor does it need to connect additional external compensation components, thereby reducing costs and ensuring versatility and reliability.

[0048] The present invention discloses a control method for a switching power supply chip. The method generates an error level by comparing a feedback voltage with a reference level, and controls the switching state of a power tube by comparing the error level with the inductor current sampling voltage. In the soft start stage, a variable frequency discontinuous current mode is adopted, a reference level is generated by charging a current source, and current zero-crossing detection is used to avoid negative inductor current. After the soft start is completed, the method switches to a fixed frequency discontinuous current mode, and controls the power tube through a logical operation of a clock signal and a wake-up comparator output. When the accumulated count reaches a threshold, the method switches to a fixed frequency forced continuous current mode, allowing negative inductor current and keeping it consistent with the clock signal frequency. The circuit and method optimize the entire process of the switching power supply chip from soft start to stable operation by switching and controlling the three working modes, thereby improving power supply efficiency and stability.

[0049] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0051] Figure 1 The figure shows a schematic diagram of a startup circuit of a switching power supply chip in the background art.

[0052] Figure 2 The waveform timing diagram of the switching power supply chip startup circuit in the background art is shown.

[0053] Figure 3 A circuit diagram for eliminating output voltage fluctuations during startup in a switching power supply chip according to an embodiment of the present invention is shown.

[0054] Figure 4 The waveform timing diagram of the output voltage fluctuation elimination circuit at startup in a switching power supply chip according to one embodiment of the present invention is shown. DETAILED DESCRIPTION

[0055] The preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0056] Example 1

[0057] The present invention provides a method for eliminating output voltage fluctuations during startup in a switching power supply chip, comprising:

[0058] Obtain the output voltage and generate a feedback voltage through a feedback resistor, compare it with the reference level and amplify it to generate an error level;

[0059] Generating a sampling voltage by sampling the inductor current, and comparing the sampling voltage with the error level to generate a comparison signal to control the switching states of the power upper tube and the power lower tube;

[0060] The switches of the power upper tube and the power lower tube are controlled by three-stage mode switching, including a variable frequency discontinuous current mode, a fixed frequency discontinuous current mode and a fixed frequency forced continuous current mode, wherein the fixed frequency discontinuous current mode is arranged as an intermediate mode between the variable frequency discontinuous current mode and the fixed frequency forced continuous current mode to reduce output voltage fluctuations.

[0061] Figure 3 FIG1 shows a circuit diagram for eliminating output voltage fluctuations during startup in a switching power supply chip according to an embodiment of the present invention. Figure 3 The circuit structure is described using a 6-bit counter as an example. The actual circuit is not limited to this structure. For different analog circuits, different targeted counters or other timing modules can be designed to implement the discontinuous current mode as an intermediate mode in addition to the fixed-frequency mode.

[0062] In this example, the following steps are included:

[0063] S1. Obtain the output voltage and generate a feedback voltage through a feedback resistor, input the feedback voltage and a reference level into an error amplifier to obtain an error level; sample the inductor current to generate a sampling voltage, input the sampling voltage and the error level into a current comparator to generate a comparison signal Vcmp;

[0064] Specifically, the output voltage Vo is divided by the feedback resistors R1 and R2 to obtain the feedback voltage Vfb; the feedback voltage Vfb is input into the error amplifier for comparison and amplification with the reference level vref1 to generate the error level Vc;

[0065] The inductor current I LSampling is performed to obtain a sampled voltage Vsns; the sampled voltage Vsns is compared with the error level Vc input current comparator to generate a comparison signal Vcmp;

[0066] The switching states of the power upper tube Q1 and the power lower tube Q2 are controlled according to the comparison signal Vcmp; if the comparison signal Vcmp jumps from a low level to a high level, Q1 is turned off and Q2 is turned on.

[0067] S2. When the switching power supply chip is in the soft start phase after power-on, the circuit enters a variable frequency discontinuous current mode, and the current source charges the capacitor to generate the reference level;

[0068] If the inductor current crosses zero, the current zero-crossing detection module is triggered to output a shutdown signal, turning off both the upper and lower power tubes to avoid negative inductor current.

[0069] Specifically, during the soft-start phase, the circuit operates in variable-frequency discontinuous current mode. The inverting input terminal Vref1 of the soft-start comparator is connected to the charging terminal of the capacitor C1, and the current source I1 charges the capacitor C1. The output voltage Vsoft of the soft-start comparator and the output voltage Vsoft_delay of the counter are high. At this time, the output signal Vwake of the wake-up comparator determines the control signal Vs, which in turn controls the power upper tube Q1 to turn on and the power lower tube Q2 to turn off.

[0070] The current zero-crossing detection module is used to detect the zero-crossing point of the inductor current and generate a current zero-crossing signal Vzc. When Vzc is high, the power upper tube Q1 and the power lower tube Q2 are synchronously turned off to avoid negative inductor current.

[0071] S3. When the soft start is completed, the circuit switches from the variable frequency discontinuous current mode to the fixed frequency discontinuous current mode; the clock signal and the output signal of the wake-up comparator jointly trigger the opening of the power upper tube and the shutdown of the power lower tube;

[0072] Specifically, when the soft start is completed, the inverting input terminal Vref1 of the soft start comparator is connected to the non-inverting input terminal Vref, and the soft start comparator output Vsoft is low; the trigger counter starts to receive the CLK signal output by the clock module and counts, and maintains the counter output voltage Vsoft_delay at a high level during the counting period;

[0073] The clock module outputs the CLK signal and the wake-up comparator outputs the Vwake signal, and a logic AND operation is performed. When the CLK and Vwake signals are both high, the power upper tube Q1 is triggered to turn on and the power lower tube Q2 is turned off.

[0074] When the inductor current passes through zero, the current zero-crossing detection module outputs a high level Vzc that takes precedence over other control signals, and synchronously turns off the upper power tube Q1 and the lower power tube Q2.

[0075] In the constant-frequency discontinuous current mode, the counter output voltage Vsoft_delay is triggered to be low after the counter completes the preset number of counts.

[0076] S4. In the fixed-frequency discontinuous current mode, the clock signal is counted. When the cumulative count reaches the preset threshold, the circuit switches from the fixed-frequency discontinuous current mode to the fixed-frequency forced continuous current mode. The rising edge of the clock signal triggers the turning on of the upper power tube and the turning off of the lower power tube. Negative inductor current is allowed, and the frequency of the duty cycle signal output by the trigger is consistent with the frequency of the clock signal.

[0077] Specifically, in the constant-frequency discontinuous current mode, the system's switching frequency is synchronized to an integer multiple of the CLK frequency, reducing fluctuations in Vc and the output voltage Vo. This mode lasts for as long as the 6-bit counter counts six CLK signal beats.

[0078] When the 6-bit counter counts to six, the system switches from constant-frequency discontinuous current mode to constant-frequency forced continuous current mode. Vsoft and Vsoft_delay both become low. At this point, only the rising edge of the CLK clock determines whether Q1 turns on or Q2 turns off. Negative inductor current is allowed, and the switching frequency remains fixed with the CLK clock frequency.

[0079] Example 2

[0080] The present invention provides a circuit for eliminating output voltage fluctuations during startup in a switching power supply chip, comprising: an error amplifier, a soft-start comparator, a current comparator, a wake-up comparator, a current detection module, a clock module, a current zero-crossing detection module, a trigger, a PWM controller, and a power upper tube Q1 and a power lower tube Q2;

[0081] The output voltage is fed back through the error amplifier to generate a feedback voltage, which is compared with a reference level and outputs an error level; the inductor current is sampled through the current detection module to generate a sampled voltage; the sampled voltage is compared with the error level through the current comparator to generate a comparison signal Vcmp, which is output to the trigger to control the switching states of the power upper tube Q1 and the power lower tube Q2;

[0082] When the switching power supply chip is in the soft start phase after power-on, the circuit enters the variable frequency discontinuous current mode, the current source I1 charges the capacitor C1 to generate the reference level, and the soft start comparator outputs a control signal Vsoft, which is combined with the output signal Vwake of the wake-up comparator to control the power upper tube Q1 to turn on and the power lower tube Q2 to turn off;

[0083] When the soft start is over, the circuit switches from the variable frequency discontinuous current mode to the fixed frequency discontinuous current mode; the clock signal and the output signal of the wake-up comparator jointly trigger the opening of the power upper tube and the shutdown of the power lower tube;

[0084] In the fixed-frequency discontinuous current mode, the clock signal is counted. When the accumulated count reaches the preset threshold, the circuit switches from the fixed-frequency discontinuous current mode to the fixed-frequency forced continuous current mode; the rising edge of the clock signal triggers the turning on of the power upper tube and the turning off of the power lower tube.

[0085] In one example, the circuit includes: an inductor L, a capacitor Co, a current source I1, a capacitor C1, feedback resistors R1 and R2, an error amplifier, a soft-start comparator, a current comparator, a wake-up comparator, a current detection module, a clock module, a counter, a current zero-crossing detection module, a trigger, a PWM controller, and a power upper tube Q1 and a power lower tube Q2;

[0086] The inductor L is connected in series between the power upper tube Q1 and the output voltage Vo, one end of the capacitor Co is connected to the output voltage Vo, and the other end is grounded;

[0087] The output voltage Vo is connected in series with feedback resistors R1 and R2 and then grounded. The connection point of the feedback resistors R1 and R2 generates a feedback voltage Vfb which is connected to the inverting input of the error amplifier. The non-inverting input of the error amplifier is connected to the reference level vref1. The output of the error amplifier outputs the error level Vc to the non-inverting input of the current comparator. The inverting input of the current comparator is connected to the output of the current detection module and the input of the current zero-crossing detection module. The current detection module is connected to the inductor L for sampling. The output of the current zero-crossing detection module is connected to the input of the PWM controller. The two output ends of the PWM controller are respectively connected to the power upper tube Q1 and the power lower tube Q2. The switch of the power upper tube Q1 is connected in series between the input voltage Vin and the inductor L. One end of the power lower tube Q2 is connected to the connection point between the current detection module and the inductor L, and the other end is grounded.

[0088] The output terminal of the current comparator is connected to the trigger R terminal, the trigger Q terminal is connected to the duty cycle signal input terminal of the PWM controller, the trigger S terminal is connected to the output terminal of the first AND gate through the switch K1, connected to the output terminal Vwake of the wake-up comparator through the switch K2, and connected to the output terminal of the clock module through the switch K3, one input terminal of the first AND gate is connected to the clock module, and the other input terminal is connected to the output terminal Vwake of the wake-up comparator, the non-inverting input terminal of the wake-up comparator is connected to the non-inverting input terminal of the current comparator, and the inverting input terminal of the wake-up comparator is connected to the non-inverting input terminal Vref of the soft start comparator;

[0089] The control signal of the switch K1 is output by a second AND gate, one input of which is connected to the output terminal Vsoft_delay of the counter, and the other input of which is connected to the output terminal Vsoft of the soft-start comparator via a NOT gate. The control signal of the switch K2 is connected to the output terminal Vsoft of the soft-start comparator. The control signal of the switch K3 is connected to the output terminal Vsoft_delay of the counter via a NOT gate.

[0090] One input terminal of the counter is connected to the clock module, and the other input terminal is connected to the output terminal Vsoft of the start comparator. The inverting input terminal of the soft start comparator serves as a reference level vref1 and is connected to the connection point of the current source I1 and the capacitor C1 through a switch K4. The current source I1 is connected in series with the capacitor C1 and then grounded. A switch K5 is connected in series between the inverting input terminal Vref1 and the non-inverting input terminal Vref of the soft start comparator. The control signal of the switch K4 is connected to the output terminal Vsoft of the soft start comparator. The control signal of the switch K5 is connected to the output terminal Vsoft of the soft start comparator through a NOT gate.

[0091] While various embodiments of the present invention have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for eliminating output voltage fluctuations during startup in a switching power supply chip, characterized in that: include: Obtain the output voltage and generate a feedback voltage through a feedback resistor, compare it with the reference level and amplify it to generate an error level; Generating a sampling voltage by sampling the inductor current, and comparing the sampling voltage with the error level to generate a comparison signal to control the switching states of the power upper tube and the power lower tube; The switching of the power upper tube and the power lower tube is controlled by three-stage mode switching, including a variable frequency discontinuous current mode, a fixed frequency discontinuous current mode, and a fixed frequency forced continuous current mode, wherein the fixed frequency discontinuous current mode is provided as an intermediate mode between the variable frequency discontinuous current mode and the fixed frequency forced continuous current mode to reduce output voltage fluctuation; The method comprises the following steps: S1. Obtain the output voltage and generate a feedback voltage through a feedback resistor, input the feedback voltage and a reference level into an error amplifier to obtain an error level; sample the inductor current to generate a sampling voltage, input the sampling voltage and the error level into a current comparator to generate a comparison signal Vcmp; S2. When the switching power supply chip is in the soft start phase after power-on, the circuit enters a variable frequency discontinuous current mode, where the current source charges the capacitor to generate the reference voltage level. If the inductor current crosses zero, the current zero-crossing detection module is triggered to output a shutdown signal, simultaneously shutting down the upper power tube and the lower power tube to prevent negative inductor current. S3. After the soft start is completed, the circuit switches from the variable-frequency discontinuous current mode to the fixed-frequency discontinuous current mode. The clock signal and the output signal of the wake-up comparator jointly trigger the opening of the power upper tube and the shutdown of the power lower tube. If the inductor current crosses zero, the current zero-crossing detection module is triggered to output a shutdown signal, turning off both the power upper tube and the power lower tube at the same time to avoid negative inductor current. S4. In the fixed-frequency discontinuous current mode, the clock signal is counted. When the cumulative count reaches the preset threshold, the circuit switches from the fixed-frequency discontinuous current mode to the fixed-frequency forced continuous current mode; the rising edge of the clock signal triggers the turning on of the power upper tube and the turning off of the power lower tube; negative inductor current is allowed, and the frequency of the duty cycle signal output by the trigger is consistent with the frequency of the clock signal.

2. The method for eliminating output voltage fluctuation during startup in a switching power supply chip according to claim 1, characterized in that S1 includes: using feedback resistors R1 and R2 to divide the output voltage Vo to obtain a feedback voltage Vfb; inputting the feedback voltage Vfb and the reference level vref1 into the error amplifier for comparison and amplification to generate an error level Vc; The inductor current I L Sampling is performed to obtain a sampled voltage Vsns; the sampled voltage Vsns is compared with the error level Vc input into the current comparator to generate a comparison signal Vcmp; The switching states of the power upper tube Q1 and the power lower tube Q2 are controlled according to the comparison signal Vcmp; if the comparison signal Vcmp jumps from a low level to a high level, Q1 is turned off and Q2 is turned on.

3. The method for eliminating output voltage fluctuation during startup in a switching power supply chip according to claim 1, wherein S2 include: During the soft start phase, the circuit operates in variable frequency discontinuous current mode. At this time, the wake-up comparator outputs the Vwake signal to control the power upper tube Q1 to turn on and the power lower tube Q2 to turn off. When the inductor current passes through zero, the current zero-crossing detection module outputs a high level Vzc that takes precedence over other control signals, and synchronously turns off the upper power tube Q1 and the lower power tube Q2.

4. The method for eliminating output voltage fluctuation during startup in a switching power supply chip according to claim 1, wherein S3 includes: when the soft start is completed, the inverting input terminal Vref1 of the soft start comparator is connected to the non-inverting input terminal Vref, and the soft start comparator output Vsoft is low level; triggering the counter to start receiving the CLK signal output by the clock module and counting, and maintaining the counter output voltage Vsoft_delay at a high level during the counting period; The clock module outputs the CLK signal and the wake-up comparator outputs the Vwake signal, and performs a logic AND operation. When the CLK and Vwake signals are both high, the power upper tube Q1 is triggered to turn on and the power lower tube Q2 is turned off. When the inductor current passes through zero, the current zero-crossing detection module outputs a high level Vzc, which takes precedence over other control signals and synchronously turns off the power upper tube Q1 and the power lower tube Q2; In the constant-frequency discontinuous current mode, the counter output voltage Vsoft_delay is triggered to be low after the counter completes the preset number of counts.

5. The method for eliminating output voltage fluctuation during startup in a switching power supply chip according to claim 1, characterized in that In S4, in the fixed-frequency forced continuous current mode, the soft-start comparator output voltage Vsoft and the counter output voltage Vsoft_delay become low at the same time. At this time, the rising edge of the clock module output CLK signal controls the power upper tube Q1 to turn on and the power lower tube Q2 to turn off.

6. A circuit for eliminating output voltage fluctuations during startup in a switching power supply chip, characterized in that include: Error amplifier, current source I1, capacitor C1, soft-start comparator, current comparator, wake-up comparator, current detection module, clock module, current zero-crossing detection module, trigger, PWM controller, and power upper tube Q1 and power lower tube Q2; The output voltage is fed back through the error amplifier to generate a feedback voltage, which is compared with the reference level and outputs the error level; The inductor current is sampled through the current detection module to generate a sampling voltage; The current comparator compares the sampled voltage with the error level, generates a comparison signal Vcmp and outputs it to the trigger to control the switching state of the power upper tube Q1 and the power lower tube Q2; When the switching power supply chip is in the soft start phase after power-on, the circuit enters the variable frequency discontinuous current mode, and the current source I1 charges the capacitor C1 to generate the reference level. The soft start comparator outputs a control signal Vsoft, which, combined with the output signal Vwake of the wake-up comparator, controls the power upper tube Q1 to turn on and the power lower tube Q2 to turn off. When the soft start is over, the circuit switches from the variable frequency discontinuous current mode to the fixed frequency discontinuous current mode; the clock signal and the output signal of the wake-up comparator jointly trigger the opening of the power upper tube and the shutdown of the power lower tube; In the fixed-frequency discontinuous current mode, the clock signal is counted. When the accumulated count reaches the preset threshold, the circuit switches from the fixed-frequency discontinuous current mode to the fixed-frequency forced continuous current mode; the rising edge of the clock signal triggers the turning on of the power upper tube and the turning off of the power lower tube.

7. The circuit for eliminating output voltage fluctuations during startup in a switching power supply chip according to claim 6, characterized in that The circuit includes: an inductor L, a capacitor Co, a current source I1, a capacitor C1, feedback resistors R1 and R2, an error amplifier, a soft-start comparator, a current comparator, a wake-up comparator, a current detection module, a clock module, a counter, a current zero-crossing detection module, a trigger, a PWM controller, and a power upper tube Q1 and a power lower tube Q2; The inductor L is connected in series between the power upper tube Q1 and the output voltage Vo, one end of the capacitor Co is connected to the output voltage Vo, and the other end is grounded; The output voltage Vo is connected in series with feedback resistors R1 and R2 and then grounded. The connection point of the feedback resistors R1 and R2 generates a feedback voltage Vfb which is connected to the inverting input of the error amplifier. The non-inverting input of the error amplifier is connected to the reference voltage vref1. The output of the error amplifier outputs the error level Vc to the non-inverting input of the current comparator. The inverting input of the current comparator is connected to the output of the current detection module and the input of the current zero-crossing detection module. The current detection module is connected to the inductor L for sampling. The output of the current zero-crossing detection module is connected to the input of the PWM controller. The two output ends of the PWM controller are respectively connected to the power upper tube Q1 and the power lower tube Q2. The switch of the power upper tube Q1 is connected in series between the input voltage Vin and the inductor L. One end of the power lower tube Q2 is connected to the connection point between the current detection module and the inductor L, and the other end is grounded. The output terminal of the current comparator is connected to the trigger R terminal, the trigger Q terminal is connected to the duty cycle signal input terminal of the PWM controller, the trigger S terminal is connected to the output terminal of the first AND gate through the switch K1, connected to the output terminal Vwake of the wake-up comparator through the switch K2, and connected to the output terminal of the clock module through the switch K3, one input terminal of the first AND gate is connected to the clock module, and the other input terminal is connected to the output terminal Vwake of the wake-up comparator, the non-inverting input terminal of the wake-up comparator is connected to the non-inverting input terminal of the current comparator, and the inverting input terminal of the wake-up comparator is connected to the non-inverting input terminal Vref of the soft start comparator; The control signal of the switch K1 is output by a second AND gate, one input of which is connected to the output terminal Vsoft_delay of the counter, and the other input of which is connected to the output terminal Vsoft of the soft-start comparator via a NOT gate. The control signal of the switch K2 is connected to the output terminal Vsoft of the soft-start comparator. The control signal of the switch K3 is connected to the output terminal Vsoft_delay of the counter via a NOT gate. One input terminal of the counter is connected to the clock module, and the other input terminal is connected to the output terminal Vsoft of the start comparator. The inverting input terminal of the soft start comparator serves as the reference level vref1 and is connected to the connection point of the current source I1 and the capacitor C1 through the switch K4. The current source I1 is connected in series with the capacitor C1 and then grounded. A switch K5 is connected in series between the inverting input terminal Vref1 and the non-inverting input terminal Vref of the soft start comparator. The control signal of the switch K4 is connected to the output terminal Vsoft of the soft start comparator. The control signal of the switch K5 is connected to the output terminal Vsoft of the soft start comparator through the NOT gate.

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