Wake-up device circuit and electronic equipment

Abstract

The invention relates to a wake-up device circuit, which is characterized in that the wake-up device circuit comprises a first super-cut-off stack structure comprising a first transistor and a second transistor which are connected in series, the drain electrode of the first transistor is electrically connected to a power supply, the source electrode of the first transistor is electrically connected with the source electrode of the second transistor, and the gate electrode of the first transistor serves as a first signal input end; the gate electrode of the second transistor serves as a second signal input end, the first transistor is an N-type transistor, and the second transistor is a P-type transistor; the first end of the first resistor or the first current source is electrically connected with the drain electrode of the second transistor, and the second end is grounded; the input end of the first Schmitt trigger is electrically connected to the drain electrode of the second transistor and a first node electrically connected with the first end of the first resistor; the input end of the first phase inverter is electrically connected to the output end of the first Schmitt trigger, and the output end of the first phase inverter serves as the output end of the wake-up device circuit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a wake-up circuit and electronic equipment. Background Art

[0002] With the rapid development of emerging applications such as the Internet of Things (IoT), wearable electronics, and electric vehicles, the demand for efficient energy management solutions in battery-powered systems has become more urgent than ever. As a core component for extending device battery life and optimizing energy efficiency, the design of a low-power battery management system requires a balance between key performance indicators such as static power consumption, dynamic response speed, and system reliability. In this technological context, the system's wake-up reception mechanism plays a crucial role, as its performance directly determines the energy efficiency and response time of the device's transition from deep sleep mode to active operation.

[0003] As a typical representative of ultra-low-power pure analog signal acquisition subsystems, wake-up receivers play an irreplaceable role in micro-energy IoT systems. By continuously monitoring low-frequency trigger signals in the environment, these devices provide intelligent wake-up functionality for high-performance microbattery-based power supply systems, enabling the main system to maintain near-zero power consumption at nanowatt levels during standby. Therefore, optimizing the power consumption of key functional modules such as the receiver front-end and comparator becomes a core challenge in system design. Existing technologies use a clock signal to wake up the wake-up receiver, but this approach increases power consumption in deep sleep mode.

[0004] However, traditional circuit architectures often find it difficult to simultaneously achieve performance indicators under strict power consumption constraints (e.g., sub-microwatt level) and low supply voltage (e.g., subthreshold region) conditions. Summary of the Invention

[0005] In response to the technical problems existing in the prior art, the present application proposes an awakener circuit, comprising a first super-cutoff stack structure, comprising a first transistor and a second transistor connected in series with each other, wherein the drain electrode of the first transistor is electrically connected to a power supply, the source electrode is electrically connected to the source electrode of the second transistor, the gate electrode of the first transistor serves as a first signal input terminal, the gate electrode of the second transistor serves as a second signal input terminal, the first transistor is an N-type transistor, and the second transistor is a P-type transistor; a first resistor or a first current source, a first end of which is electrically connected to the drain electrode of the second transistor, and a second end is grounded; a first Schmitt trigger, an input end of which is electrically connected to a first node where the drain electrode of the second transistor and the first end of the first resistor are electrically connected, and the output end of the Schmitt trigger serves as the awakener output end; or the awakener circuit further includes a first inverter, an input end of which is electrically connected to the output end of the first Schmitt trigger, and an output end of which serves as the output end of the awakener circuit.

[0006] In particular, the awakener circuit is characterized in that the first Schmitt trigger includes a third transistor, a fourth transistor, and a fifth transistor whose gates are electrically connected together as the input end of the first Schmitt trigger, wherein the source electrode of the third transistor is electrically connected to the power supply, the source electrode of the fifth transistor is grounded, the drain electrode of the third transistor is electrically connected to the source electrode of the fourth transistor, the drain electrode of the fourth transistor is electrically connected to the drain electrode of the fifth transistor, the drain electrode of the sixth transistor is grounded, and its source electrode is electrically connected to the drain electrode of the third transistor, the gate electrode of the sixth transistor is electrically connected to the drain electrode of the fourth transistor and the drain electrode of the fifth transistor, and serves as the output end of the first Schmitt trigger; wherein the fifth transistor is complementary to the types of the third, fourth and sixth transistors, and the width-to-length ratio of the fifth transistor is greater than the width-to-length ratios of other transistors in the first Schmitt trigger.

[0007] The present application also proposes an awakener circuit, characterized in that it includes a second super-cutoff stack structure, including a seventh transistor and an eighth transistor connected in series with each other, wherein the source electrode of the seventh transistor is electrically connected to the source electrode of the eighth transistor, the gate electrode of the seventh transistor serves as a first signal input terminal, and the gate electrode of the eighth transistor serves as a second signal input terminal, the seventh transistor is an N-type transistor, and the eighth transistor is a P-type transistor; a second resistor or a second current source, a first end of which is electrically connected to the drain electrode of the seventh transistor, and a second end of which is electrically connected to a power supply; a second Schmitt trigger, an input end of which is electrically connected to a second node where the drain electrode of the seventh transistor and the first end of the second resistor are electrically connected, and the output end of the Schmitt trigger serves as the awakener output end; or the awakener circuit further includes a second inverter, an input end of which is electrically connected to the output end of the second Schmitt trigger, and an output end of which serves as the output end of the awakener circuit.

[0008] In particular, the awakener circuit is characterized in that the second Schmitt trigger includes a ninth transistor, a tenth transistor, and an eleventh transistor whose gates are electrically connected together as the input end of the second Schmitt trigger, wherein the source electrode of the ninth transistor is electrically connected to the power supply, the source electrode of the eleventh transistor is grounded, the drain electrode of the eleventh transistor is electrically connected to the source electrode of the tenth transistor, the drain electrode of the ninth transistor is electrically connected to the drain electrode of the tenth transistor, the drain electrode of the twelfth transistor is connected to the power supply, and its source electrode is electrically connected to the source electrode of the tenth transistor, the gate electrode of the twelfth transistor is electrically connected to the drain electrode of the ninth transistor and the drain electrode of the tenth transistor, and serves as the output end of the second Schmitt trigger; wherein the type of the ninth transistor is complementary to that of the tenth transistor, the eleventh transistor and the twelfth transistor, and the width-to-length ratio of the ninth transistor is greater than the width-to-length ratios of other transistors in the second Schmitt trigger.

[0009] The present application also proposes an awakener circuit, characterized in that it includes a third super-cutoff stacking structure, including a thirteenth transistor and a fourteenth transistor connected in series with each other, wherein the drain electrode of the thirteenth transistor is electrically connected to the power supply, the source electrode is electrically connected to the source electrode of the fourteenth transistor, the gate electrode of the thirteenth transistor serves as a first signal input terminal, the gate electrode of the fourteenth transistor serves as a second signal input terminal, the thirteenth transistor is an N-type transistor, and the fourteenth transistor is a P-type transistor; a fourth super-cutoff stacking structure includes a fifteenth transistor and a sixteenth transistor connected in series with each other, wherein the source electrode of the fifteenth transistor is electrically connected to the source electrode of the sixteenth transistor, the gate electrode of the fifteenth transistor serves as the first signal input terminal, the gate electrode of the sixteenth transistor serves as the second signal input terminal, and the fifteenth transistor is an N-type transistor. transistor, the sixteenth transistor is a P-type transistor; a third resistor or a third current source, a first end of which is electrically connected to the drain electrode of the fourteenth transistor, and a second end is grounded; a fourth resistor or a fourth current source, a first end of which is electrically connected to the drain electrode of the fifteenth transistor, and a second end is connected to the power supply; a third Schmitt trigger, an input end of which is electrically connected to a third node where the drain electrode of the fourteenth transistor and the first end of the third resistor are electrically connected; a fourth Schmitt trigger, an input end of which is electrically connected to a fourth node where the drain electrode of the fifteenth transistor and the first end of the fourth resistor are electrically connected; a third inverter, an input end of which is electrically connected to the output end of the fourth Schmitt trigger; a first NAND gate, two input ends of which are respectively electrically connected to the output end of the third inverter and the output end of the third Schmitt trigger, and the output end of the first NAND gate serves as the output end of the wake-up circuit.

[0010] In particular, the wake-up circuit is characterized in that the third Schmitt trigger includes a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor whose gates are electrically connected together as the input terminal of the third Schmitt trigger, wherein the source electrode of the seventeenth transistor is electrically connected to the power supply, the source electrode of the nineteenth transistor is grounded, the drain electrode of the seventeenth transistor is electrically connected to the source electrode of the eighteenth transistor, the drain electrode of the eighteenth transistor is electrically connected to the drain electrode of the nineteenth transistor, the drain electrode of the twentieth transistor is grounded, and its source electrode is electrically connected to the drain electrode of the seventeenth transistor, the gate electrode of the twentieth transistor is electrically connected to the drain electrode of the eighteenth transistor and the drain electrode of the nineteenth transistor, and serves as the output terminal of the third Schmitt trigger, wherein the type of the nineteenth transistor is complementary to the seventeenth transistor, the eighteenth transistor and the twentieth transistor, and the width-to-length ratio of the nineteenth transistor is greater than the width-to-length ratios of the other transistors of the third Schmitt trigger; and / or The fourth Schmitt trigger includes a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor whose gates are electrically connected together as the input terminal of the fourth Schmitt trigger, wherein the source electrode of the twenty-first transistor is electrically connected to the power supply, the source electrode of the twenty-third transistor is grounded, the drain electrode of the twenty-third transistor is electrically connected to the source electrode of the twenty-second transistor, the drain electrode of the twenty-first transistor is electrically connected to the drain electrode of the twenty-second transistor, the drain electrode of the twenty-fourth transistor is connected to the power supply, and its source electrode is electrically connected to the source electrode of the twenty-second transistor, the gate electrode of the twenty-fourth transistor is electrically connected to the drain electrode of the twenty-first transistor and the drain electrode of the twenty-second transistor, and serves as the output terminal of the fourth Schmitt trigger, wherein the type of the twenty-first transistor is complementary to the twenty-second transistor, the twenty-third transistor and the twenty-fourth transistor, and the width-to-length ratio of the twenty-first transistor is greater than the width-to-length ratio of other transistors in the fourth Schmitt trigger.

[0011] The present application also includes a wake-up circuit, characterized in that it includes a fifth super-cutoff stack structure, including a twenty-fifth transistor and a twenty-sixth transistor connected in series with each other, wherein the drain electrode of the twenty-fifth transistor is electrically connected to the power supply, the source electrode is electrically connected to the source electrode of the twenty-sixth transistor, the gate electrode of the twenty-fifth transistor serves as a first signal input terminal, the gate electrode of the twenty-sixth transistor serves as a second signal input terminal, the twenty-fifth transistor is an N-type transistor, and the twenty-sixth transistor is a P-type transistor; a sixth super-cutoff stack structure, including a twenty-seventh transistor and a twenty-eighth transistor connected in series with each other, wherein the source electrode of the twenty-seventh transistor is electrically connected to the source electrode of the twenty-eighth transistor, the gate electrode of the twenty-seventh transistor serves as the first signal input terminal, the gate electrode of the twenty-eighth transistor serves as the second signal input terminal, and the twenty-seventh transistor is an N-type transistor. The transistor is an N-type transistor, and the twenty-eighth transistor is a P-type transistor; the fifth resistor or the fifth current source, the first end of which is electrically connected to the drain electrode of the twenty-sixth transistor, and the second end is grounded; the sixth resistor or the sixth current source, the first end of which is electrically connected to the drain electrode of the twenty-seventh transistor, and the second end is connected to the power supply; the fifth Schmitt trigger, the input end of which is electrically connected to the fifth node where the drain electrode of the twenty-sixth transistor and the first end of the fifth resistor are electrically connected; the sixth Schmitt trigger, the input end of which is electrically connected to the sixth node where the drain electrode of the twenty-seventh transistor and the first end of the sixth resistor are electrically connected; the fourth inverter, the input end of which is electrically connected to the output end of the fifth Schmitt trigger; the first OR gate, the two input ends of which are respectively electrically connected to the output end of the fourth inverter and the output end of the sixth Schmitt trigger, and the output end of the first OR gate serves as the output end of the wake-up circuit.

[0012] In particular, the wake-up circuit is characterized in that the fifth Schmitt trigger includes a twenty-ninth transistor, a thirtieth transistor, and a thirty-first transistor whose gates are electrically connected together as the input terminal of the fifth Schmitt trigger, wherein the source electrode of the twenty-ninth transistor is electrically connected to the power supply, the source electrode of the thirty-first transistor is grounded, the drain electrode of the twenty-ninth transistor is electrically connected to the source electrode of the thirtieth transistor, the drain electrode of the thirtieth transistor is electrically connected to the drain electrode of the thirty-first transistor, the drain electrode of the thirty-second transistor is grounded, and its source electrode is electrically connected to the drain electrode of the twenty-ninth transistor, the gate electrode of the thirty-second transistor is electrically connected to the drain electrode of the thirtieth transistor and the drain electrode of the thirty-first transistor, and serves as the output terminal of the fifth Schmitt trigger, wherein the type of the thirty-first transistor is complementary to that of the twenty-ninth transistor, the thirtieth transistor, and the thirty-second transistor, and the width-to-length ratio of the thirty-first transistor is greater than that of the other transistors of the fifth Schmitt trigger. aspect ratio; and / or the sixth Schmitt trigger includes a thirty-third transistor, a thirty-fourth transistor, and a thirty-fifth transistor whose gates are electrically connected together as the input terminal of the sixth Schmitt trigger, wherein the source electrode of the thirty-third transistor is electrically connected to the power supply, the source electrode of the thirty-fifth transistor is grounded, the drain electrode of the thirty-fifth transistor is electrically connected to the source electrode of the thirty-fourth transistor, the drain electrode of the thirty-third transistor is electrically connected to the drain electrode of the thirty-fourth transistor, the drain electrode of the thirty-sixth transistor is connected to the power supply, and its source electrode is electrically connected to the source electrode of the thirty-fourth transistor, the gate electrode of the thirty-sixth transistor is electrically connected to the drain electrode of the thirty-third transistor and the drain electrode of the thirty-fourth transistor, and serves as the output terminal of the sixth Schmitt trigger, wherein the type of the thirty-third transistor is complementary to the thirty-fourth transistor, the thirty-fifth transistor and the thirty-sixth transistor, and the aspect ratio of the thirty-third transistor is greater than the aspect ratios of the other transistors of the sixth Schmitt trigger.

[0013] The present application also proposes a wake-up circuit, characterized in that it includes a first wake-up unit, including a first wake-up sub-unit, including a seventh super-cutoff stack structure electrically connected to a power supply at one end and a seventh resistor or a seventh current source connected in series with the seventh resistor at one end and the other end is grounded; and / or a second wake-up sub-unit, including an eighth super-cutoff stack structure connected in series with the eighth resistor at one end and the other end is electrically connected to the power supply at the eighth resistor or the eighth current source; a first feedback circuit electrically connected to the output end of the first wake-up sub-unit and the output end of the second wake-up sub-unit is electrically connected to a first output unit of the first feedback circuit; a second wake-up unit, including a third wake-up sub-unit, including a ninth super-cutoff stack structure electrically connected to the power supply at one end and a ninth resistor or a ninth current source connected in series with the ninth resistor at one end and the other end is grounded; and / or a fourth wake-up sub-unit, including a tenth super-cutoff stack structure connected in series with the eighth resistor or the tenth current source at one end and the other end is electrically connected to the power supply; a second feedback circuit electrically connected to the output end of the third wake-up sub-unit and the output end of the fourth wake-up sub-unit is electrically connected to a second output unit of the second feedback circuit; the first feedback circuit is configured to receive the output of the second wake-up unit, and the second feedback circuit is configured to receive the output of the first wake-up unit.

[0014] In particular, the awakening circuit is characterized in that, when the first awakening unit includes a first awakening sub-unit and a second awakening sub-unit, the first output unit includes a seventh Schmitt trigger, whose input end is electrically connected to the output end of the first awakening sub-unit; an eighth Schmitt trigger, whose input end is electrically connected to the output end of the second awakening sub-unit; a fifth inverter and a second NAND gate, wherein the fifth inverter input end is electrically connected to the eighth Schmitt trigger output end, and the output end of the fifth inverter and the output end of the seventh Schmitt trigger are electrically connected to the input end of the second NAND gate; the output end of the second NAND gate serves as the output end of the first output unit; or a sixth inverter and a second OR gate, wherein the sixth inverter input end is electrically connected to the seventh Schmitt trigger The output end of the sixth inverter and the output end of the eighth Schmitt trigger are electrically connected to the input end of the second OR gate; the output end of the second OR gate serves as the output end of the first output unit; or when the first wake-up unit includes a first wake-up sub-unit, the first output unit includes a seventh Schmitt trigger and a sixth inverter, wherein the input end of the sixth inverter is electrically connected to the output end of the seventh Schmitt trigger, and the output end of the sixth inverter serves as the output end of the first output unit; or when the first wake-up unit includes a second wake-up sub-unit, the first output unit includes an eighth Schmitt trigger and a fifth inverter, wherein the input end of the fifth inverter is electrically connected to the output end of the eighth Schmitt trigger, and the output end of the fifth inverter serves as the output end of the first output unit.

[0015] In particular, the awakening circuit is characterized in that, when the second awakening unit includes a third awakening subunit and a fourth awakening subunit, the second output unit includes a ninth Schmitt trigger, whose input terminal is electrically connected to the output terminal of the third awakening subunit; a tenth Schmitt trigger, whose input terminal is electrically connected to the output terminal of the fourth awakening subunit; a seventh inverter and a third NAND gate, wherein the seventh inverter input terminal is electrically connected to the tenth Schmitt trigger output terminal, and the output terminal of the seventh inverter and the ninth Schmitt trigger output terminal are electrically connected to the input terminal of the third NAND gate; or an eighth inverter and a third OR gate, wherein the eighth inverter input terminal is electrically connected to the ninth Schmitt trigger output terminal. The output terminal of the eighth inverter and the output terminal of the tenth Schmitt trigger are electrically connected to the input terminal of the third OR gate; or when the second wake-up unit includes the third wake-up sub-unit, the second output unit includes a ninth Schmitt trigger and an eighth inverter, wherein the input terminal of the eighth inverter is electrically connected to the output terminal of the ninth Schmitt trigger, and the output terminal of the eighth inverter serves as the output terminal of the second output unit; or when the second wake-up unit includes the fourth wake-up sub-unit, the second output unit includes a tenth Schmitt trigger and a seventh inverter, wherein the input terminal of the seventh inverter is electrically connected to the output terminal of the tenth Schmitt trigger, and the output terminal of the seventh inverter serves as the output terminal of the second output unit.

[0016] In particular, the awakening circuit is characterized in that, when the first awakening unit includes a first awakening sub-unit and a second awakening sub-unit, the first feedback circuit includes a thirty-seventh transistor, a drain electrode of which is electrically connected to the eighth Schmitt trigger input terminal, and a source electrode of which is electrically connected to the power supply; an eleventh resistor, one end of which is electrically connected to the power supply, and the other end of which is electrically connected to the gate of the thirty-seventh transistor; a first capacitor, a first plate of which is electrically connected to the gate of the thirty-seventh transistor; a ninth inverter, an input terminal of which is electrically connected to the output terminal of the second awakening unit, and an output terminal of which is electrically connected to the second plate of the first capacitor; a thirty-eighth transistor, a drain electrode of which is electrically connected to the seventh Schmitt trigger input terminal, a source electrode of which is electrically connected to the first end of the twelfth resistor and receives the ground potential, a gate electrode of which is electrically connected to the second end of the twelfth resistor and the first plate of the second capacitor, and the second plate of the second capacitor is electrically connected to the ninth inverter input terminal and the output terminal of the second awakening unit; or when the When the first wake-up unit includes a first wake-up sub-unit, the first feedback circuit includes a twelfth resistor, a first end of which receives a ground potential; a thirty-eighth transistor, a drain electrode of which is electrically connected to the seventh Schmitt trigger input terminal, a source electrode of which is electrically connected to the first end of the twelfth resistor, and a gate electrode of which is electrically connected to the second end of the twelfth resistor and the first plate of the second capacitor; a second capacitor, a second plate of which is electrically connected to the output terminal of the second wake-up unit; or when the first wake-up unit includes a second wake-up sub-unit, the first feedback circuit includes a thirty-seventh transistor, a drain electrode of which is electrically connected to the eighth Schmitt trigger input terminal, and a source electrode of which is electrically connected to a power supply; an eleventh resistor, one end of which is electrically connected to the power supply and the other end of which is electrically connected to the gate of the thirty-seventh transistor; a first capacitor, a first plate of which is electrically connected to the gate of the thirty-seventh transistor; a ninth inverter, an input end of which is electrically connected to the output terminal of the second wake-up unit, and an output end of which is electrically connected to the second plate of the first capacitor.

[0017] In particular, the awakening circuit is characterized in that, when the second awakening unit includes a third awakening sub-unit and a fourth awakening sub-unit, the second feedback circuit includes a thirty-ninth transistor, a drain electrode of which is electrically connected to the tenth Schmitt trigger input terminal, and a source electrode of which is electrically connected to the power supply, a thirteenth resistor, one end of which is electrically connected to the power supply, and the other end of which is electrically connected to the gate of the thirty-ninth transistor; a third capacitor, a first plate of which is electrically connected to the gate of the thirty-ninth transistor; a tenth inverter, an input terminal of which is electrically connected to the output terminal of the first awakening unit, and an output terminal of which is electrically connected to the second plate of the third capacitor; a fortieth transistor, a drain electrode of which is electrically connected to the ninth Schmitt trigger input terminal, a source electrode of which is electrically connected to the first end of the fourteenth resistor and receives the ground potential, a gate electrode of which is electrically connected to the second end of the fourteenth resistor and the first plate of the fourth capacitor, and the second plate of the fourth capacitor is electrically connected to the tenth inverter input terminal and the output terminal of the first awakening unit; or when the When the second wake-up unit includes the third wake-up sub-unit, the second feedback circuit includes a fourteenth resistor, a first end of which receives the ground potential; a fortieth transistor, a drain electrode of which is electrically connected to the ninth Schmitt trigger input terminal, a source electrode of which is electrically connected to the first end of the fourteenth resistor, and a gate electrode of which is electrically connected to the second end of the fourteenth resistor and the first plate of the fourth capacitor; a fourth capacitor, a second plate of which is electrically connected to the output terminal of the first wake-up unit; or when the second wake-up unit includes the fourth wake-up sub-unit, the second feedback circuit includes a thirty-ninth transistor, a drain electrode of which is electrically connected to the tenth Schmitt trigger input terminal, and a source electrode of which is electrically connected to the power supply; a thirteenth resistor, one end of which is electrically connected to the power supply and the other end of which is electrically connected to the gate of the thirty-ninth transistor; a third capacitor, a first plate of which is electrically connected to the gate of the thirty-ninth transistor; a tenth inverter, an input end of which is electrically connected to the output terminal of the first wake-up unit, and an output end of which is electrically connected to the second plate of the third capacitor.

[0018] In particular, the awakener circuit is characterized in that the seventh super-cutoff stacking structure includes a forty-first transistor and a forty-second transistor connected in series with each other, wherein the drain electrode of the forty-second transistor is electrically connected to the first end of the seventh resistor, and its source electrode is electrically connected to the source electrode of the forty-first transistor, the forty-first transistor is an N-type transistor, and the forty-second transistor is a P-type transistor; and / or the eighth super-cutoff stacking structure includes a forty-third transistor and a forty-fourth transistor connected in series with each other, wherein the drain electrode of the forty-third transistor is electrically connected to the first end of the eighth resistor, and its source electrode is electrically connected to the source electrode of the forty-fourth transistor, the forty-third transistor is an N-type transistor, and the forty-fourth transistor is a P-type transistor; and / or the ninth super-cutoff stacking structure includes a forty-fifth transistor and a forty-sixth transistor connected in series with each other, wherein the The drain electrode of the forty-sixth transistor is electrically connected to the first end of the ninth resistor, and its source electrode is electrically connected to the source electrode of the forty-fifth transistor, the forty-fifth transistor is an N-type transistor, and the forty-sixth transistor is a P-type transistor; and / or the tenth super-cutoff stack structure includes a forty-seventh transistor and a forty-eighth transistor connected in series with each other, wherein the drain electrode of the forty-seventh transistor is electrically connected to the first end of the tenth resistor, and its source electrode is electrically connected to the source electrode of the forty-eighth transistor, the forty-seventh transistor is an N-type transistor, and the forty-eighth transistor is a P-type transistor; wherein the gate electrodes of the forty-first transistor, the forty-third transistor, the forty-sixth transistor and the forty-eighth transistor serve as the first signal input terminal; and the gate electrodes of the forty-second transistor, the forty-fourth transistor, the forty-fifth transistor and the forty-seventh transistor serve as the second signal input terminal.

[0019] In particular, the awakener circuit is characterized in that the seventh Schmitt trigger includes a forty-ninth transistor, a fiftieth transistor, and a fifty-first transistor whose gates are electrically connected together as the input terminal of the seventh Schmitt trigger, wherein the source electrode of the forty-ninth transistor is electrically connected to the power supply, the source electrode of the fifty-first transistor is grounded, the drain electrode of the forty-ninth transistor is electrically connected to the source electrode of the fiftieth transistor, the drain electrode of the fiftieth transistor is electrically connected to the drain electrode of the fifty-first transistor, the drain electrode of the fifty-second transistor is grounded, and its source electrode is electrically connected to the drain electrode of the forty-ninth transistor, the gate electrode of the fifty-second transistor is electrically connected to the drain electrode of the fiftieth transistor and the drain electrode of the fifty-first transistor, and serves as the output terminal of the seventh Schmitt trigger, wherein the type of the fifty-first transistor is complementary to that of the forty-ninth transistor, the fiftieth transistor, and the fifty-second transistor, and the width-to-length ratio of the fifty-first transistor is greater than that of the other transistors of the seventh Schmitt trigger. aspect ratio; and / or the eighth Schmitt trigger includes a fifty-third transistor, a fifty-fourth transistor, and a fifty-fifth transistor whose gates are electrically connected together as the input terminal of the eighth Schmitt trigger, wherein the source electrode of the fifty-third transistor is electrically connected to the power supply, the source electrode of the fifty-fifth transistor is grounded, the drain electrode of the fifty-fifth transistor is electrically connected to the source electrode of the fifty-fourth transistor, the drain electrode of the fifty-third transistor is electrically connected to the drain electrode of the fifty-fourth transistor, the drain electrode of the fifty-sixth transistor is connected to the power supply, and its source electrode is electrically connected to the source electrode of the fifty-fourth transistor, the gate electrode of the fifty-sixth transistor is electrically connected to the drain electrode of the fifty-third transistor and the drain electrode of the fifty-fourth transistor, and serves as the output terminal of the eighth Schmitt trigger, wherein the type of the fifty-third transistor is complementary to the fifty-fourth transistor, the fifty-fifth transistor and the fifty-sixth transistor, and the aspect ratio of the fifty-third transistor is greater than the aspect ratios of other transistors of the eighth Schmitt trigger.

[0020] In particular, the awakener circuit is characterized in that the ninth Schmitt trigger includes a fifty-seventh transistor, a fifty-eighth transistor, and a fifty-ninth transistor whose gates are electrically connected together as the input terminal of the ninth Schmitt trigger, wherein the source electrode of the fifty-seventh transistor is electrically connected to the power supply, the source electrode of the fifty-ninth transistor is grounded, the drain electrode of the fifty-seventh transistor is electrically connected to the source electrode of the fifty-eighth transistor, the drain electrode of the fifty-eighth transistor is electrically connected to the drain electrode of the fifty-ninth transistor, the drain electrode of the sixtieth transistor is grounded, and its source electrode is electrically connected to the drain electrode of the fifty-seventh transistor, the gate electrode of the sixtieth transistor is electrically connected to the drain electrode of the fifty-eighth transistor and the drain electrode of the fifty-ninth transistor, and serves as the output terminal of the ninth Schmitt trigger; wherein the fifty-ninth transistor is complementary to the types of the fifty-seventh transistor, the fifty-eighth transistor, and the sixtieth transistor, and the width-to-length ratio of the fifty-ninth transistor is greater than that of the other transistors of the ninth Schmitt trigger. The width-to-length ratio of the tube; and / or the tenth Schmitt trigger includes a sixty-first transistor, a sixty-second transistor, and a sixty-third transistor, whose gates are electrically connected together as the input terminal of the tenth Schmitt trigger, wherein the source electrode of the sixty-first transistor is electrically connected to the power supply, the source electrode of the sixty-third transistor is grounded, the drain electrode of the sixty-third transistor is electrically connected to the source electrode of the sixty-second transistor, the drain electrode of the sixty-first transistor is electrically connected to the drain electrode of the sixty-second transistor, the drain electrode of the sixty-fourth transistor is connected to the power supply, and its source electrode is electrically connected to the source electrode of the sixty-second transistor, the gate electrode of the sixty-fourth transistor is electrically connected to the drain electrode of the sixty-first transistor and the drain electrode of the sixty-second transistor, and serves as the output terminal of the tenth Schmitt trigger; wherein the type of the sixty-first transistor is complementary to the sixty-second transistor, the sixty-third transistor and the sixty-fourth transistor, and the width-to-length ratio of the sixty-first transistor is greater than the width-to-length ratios of the other transistors of the tenth Schmitt trigger.

[0021] The present application also proposes an electronic device comprising any of the above-mentioned wake-up circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein: Figure 1 FIG2 is a schematic diagram of a wake-up circuit according to an embodiment of the present application; Figure 2 FIG2 is a schematic diagram of a wake-up circuit according to another embodiment of the present application; Figure 3 and Figure 4 Shown is a Schmitt trigger circuit diagram according to one embodiment of the present application; Figure 5 FIG2 is a schematic diagram of a wake-up circuit according to another embodiment of the present application; Figure 6 FIG2 is a schematic diagram of a wake-up circuit according to another embodiment of the present application; Figure 7-10 Shown is a schematic diagram of a wake-up circuit according to other embodiments of the present application; Figure 11 FIG. 1 is a timing diagram of the operation of the wake-up circuit according to one embodiment of the present application. DETAILED DESCRIPTION

[0023] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0025] Figure 1 FIG. 1 is a schematic diagram of a wake-up circuit according to an embodiment of the present application.

[0026] like Figure 1 As shown, according to one embodiment, the circuit includes a super cutoff stack structure 100 and a resistor R100 connected in series.

[0027] According to one embodiment, the super-cutoff stack structure 100 includes an NMOS transistor MN100 and a PMOS transistor MP100, which are electrically connected in series, wherein the drain electrode of the NMOS transistor MN100 receives a voltage source VDD, the source electrode is electrically connected to the source electrode of the PMOS transistor MP100, the gate electrode of the transistor MN100 serves as a signal VGN input terminal, and the gate electrode of the transistor MP100 serves as a signal VGP input terminal.

[0028] According to one embodiment, the total threshold voltage of the super-cutoff stack structure can be adjusted by using MOS transistor devices with different threshold voltages. In the following, Vthn is the threshold voltage of the NMOS transistor, and Vthp is the threshold voltage of the PMOS transistor.

[0029] According to one embodiment, the wake-up circuit may further include a Schmitt trigger ST100 whose input terminal is electrically connected to the drain electrode of the PMOS transistor MP100 in the super-cutoff stack structure 100 and the first end of the resistor R100. The second end of the resistor R100 receives a ground potential. According to one embodiment, the wake-up circuit also includes an inverter INV100 whose input terminal is electrically connected to the output end of the Schmitt trigger ST100. According to one embodiment, the resistor R100 can be flexibly configured as a passive resistor or an active current source, which has high circuit compatibility. In the resistor solution, since a bias circuit is not required, power consumption is further reduced.

[0030] According to one embodiment, the wake-up circuit using the resistor R100 in the above solution can operate under low power supply voltage conditions. In traditional circuits, a bias circuit is required to operate normally, and the bias circuit consumes a certain amount of power.

[0031] The transistor MP100 and the transistor MN100 in the super-cutoff stack structure 100 have equal current characteristics in the sub-threshold operating region, as shown in the following formula (1):

[0032] Where I0 is a constant related to the process (such as the transistor width-to-length ratio W / L), V th represents the transistor threshold voltage, n is the subthreshold slope factor (assuming that n is equal for each transistor), and kT / q is the thermal voltage. 0,n = I 0,p = I0, and considering Vthn ≈ |Vthp| ≈ V th When the voltage V x will be equal to (VGN + VGP) / 2, and the resulting current I is given by the following formula (2):

[0033] From formula (2), it can be obtained that the super-cutoff stack structure 100 is equivalent to a gate-source voltage of V GS = (VGN-VGP) / 2, where VGN is the gate input voltage of transistor MN100 and VGP is the gate input voltage of transistor MP100.

[0034] According to the above formula (2), the super cutoff stack structure 100 is equivalent to a threshold voltage of V th transistors.

[0035] According to one embodiment, when the two signals at the input end of the super cutoff stack structure 100 are common mode signals, V GS =(VGN-VGP) / 2 is equal to 0 and must be less than V th , the super-cutoff stack structure 100 is in a super-cutoff state, that is, the voltage of the SEN_N100 node is 0.

[0036] According to one embodiment, when the two signals at the input end of the super cutoff stack structure 100 are differential signals, and the input differential voltage of the two signals at the input end is less than Vthn+|Vthp| (equivalent to V GS Less than V th ), the super cutoff stack structure 100 is still in the cutoff state.

[0037] According to one embodiment, when the two signals at the input end of the super cutoff stack structure 100 are differential signals and the input differential voltage is greater than or equal to Vthn+|Vthp| (equivalent to V GS Greater than or equal to V th ), the super-cutoff stack structure is turned on, and as the differential voltage continues to increase, the voltage of the node SEN_N100 rises from the ground potential.

[0038] In the present application, since the transistor exhibits a strictly matched exponential current-voltage transfer characteristic in the subthreshold operating region, the super-cutoff stack structure 100 operates in a super-cutoff state. Without any bias voltage conditions exceeding the power supply rail (voltage source), a super-cutoff state leakage current far lower than the leakage current level of a conventional transistor can be achieved, thereby reducing the power consumption of the circuit when operating in a static state.

[0039] According to one embodiment, the value of resistor R100 is related to the frequency of the differential signal input to the two input terminals of the super-cutoff stack structure 100. The lower the frequency, the larger the value of resistor R100, and the corresponding source-drain current is also smaller, thereby reducing the dynamic power consumption of the above-mentioned sensor circuit. For example, when the input differential signal frequency is 2 MHz, the value of resistor R100 can be 600 kΩ to 1.2 MΩ.

[0040] If the voltage at node SEN_N100 is directly input to the inverter, the voltage will slowly rise or fall, which will result in high power consumption when the inverter flips. Therefore, according to one embodiment, the voltage at node SEN_N100 can be provided to the Schmitt trigger ST100, and then output through the series inverter INV100, further reducing the dynamic power consumption of the wake-up circuit.

[0041] According to one embodiment, the solution of the present application adopts a new type of Schmitt trigger, which can further save power consumption compared with the traditional Schmitt trigger.

[0042] Figure 2 FIG. 1 is a schematic diagram of a wake-up circuit according to another embodiment of the present application.

[0043] like Figure 2 As shown, according to one embodiment, the circuit includes a super cutoff stack structure 200 and a resistor R200 connected in series.

[0044] According to one embodiment, the super-cutoff stack structure 200 includes an NMOS transistor MN200 and a PMOS transistor MP200, which are electrically connected in series, wherein the drain electrode of the NMOS transistor MN200 is electrically connected to the first end of the resistor R200, and the source electrode is electrically connected to the source electrode of the PMOS transistor MP200, the gate electrode of the transistor MN200 serves as the input terminal of the signal VGN, and the gate electrode of the transistor MP200 serves as the input terminal of the signal VGP.

[0045] According to one embodiment, the wake-up circuit may further include a Schmitt trigger ST200 having an input end electrically connected to the drain electrode of the NMOS transistor MN200 in the super-cutoff stack structure 200 and a first end of the resistor R200. The second end of the resistor R200 receives a power supply voltage VDD. According to one embodiment, the wake-up circuit also includes an inverter INV200 having an input end electrically connected to the output end of the Schmitt trigger ST200. According to one embodiment, the resistor R200 can be flexibly configured as a passive resistor or an active current source, which has high circuit compatibility. In the resistor solution, since a bias circuit is not required, power consumption is further reduced.

[0046] According to one embodiment, the wake-up circuit using resistor R200 in the above solution can operate under low power supply voltage conditions. In traditional circuits, a bias circuit needs to be set to work properly, and the bias circuit consumes a certain amount of power. From the above formulas (1) and (2), it can also be obtained that the super-cutoff stack structure 200 is equivalent to a threshold voltage of V th transistors.

[0047] According to one embodiment, when the two signals at the input end of the super cutoff stack structure 200 are common mode signals, V GS =(VGN-VGP) / 2 is equal to 0 and must be less than V th , the super cutoff stack structure 200 is in a super cutoff state, that is, the voltage of the SEN_P200 node is VDD.

[0048] According to one embodiment, when the two signals at the input end of the super cutoff stack structure 200 are differential signals, and the input differential voltage of the two signals at the input end is less than Vthn+|Vthp| (equivalent to V GS Less than V th ), the super cutoff stack structure 200 is still in the cutoff state.

[0049] According to one embodiment, when the two signals at the input end of the super cutoff stack structure 200 are differential signals and the input differential voltage is greater than or equal to Vthn+|Vthp| (equivalent to V GS Greater than or equal to V th ), the super-cutoff stack structure is turned on, and as the differential voltage continues to increase, the voltage of the node SEN_P200 drops from the power supply voltage VDD.

[0050] In the present application, since the transistor exhibits a strictly matched exponential current-voltage transfer characteristic in the subthreshold operating region, the super-cutoff stack structure 200 operates in a super-cutoff state. Without any bias voltage conditions exceeding the power supply rail (voltage source), a super-cutoff state leakage current far lower than the leakage current level of a conventional transistor can be achieved, thereby reducing the power consumption of the circuit when operating in a static state.

[0051] According to one embodiment, the value of resistor R200 is related to the frequency of the differential signal input to the two input terminals of the super-cutoff stack structure 200. The lower the frequency, the larger the value of resistor R200, and the corresponding source-drain current is also smaller, thereby reducing the dynamic power consumption of the above-mentioned sensor circuit. For example, when the input differential signal frequency is 2 MHz, the value of resistor R200 can be 600 kΩ to 1.2 MΩ.

[0052] If the voltage at node SEN_P200 is directly input to the inverter, the voltage will slowly rise or fall, resulting in high power consumption when the inverter flips. Therefore, according to one embodiment, the voltage at node SEN_P200 can be provided to a Schmitt trigger ST200, which is then output through the series-connected inverter INV200, further reducing the dynamic power consumption of the wake-up circuit.

[0053] According to one embodiment, the solution of the present application adopts a new type of Schmitt trigger, which can further save power consumption compared with the traditional Schmitt trigger.

[0054] Use Figure 1 and Figure 2 The wake-up circuit of the super-cutoff stack structure shown does not require the clock requirement of the traditional wake-up circuit, which not only reduces power consumption but also makes the wake-up function simple to implement. It only needs to meet the requirement that the input differential mode signal is greater than the turn-on threshold of the super-cutoff stack structure.

[0055] Figure 3 and Figure 4 Shown is a Schmitt trigger circuit diagram according to one embodiment of the present application.

[0056] like Figure 3 As shown, according to one embodiment, the gate electrodes of transistors P11, P12, and N11 are electrically connected and receive an input signal IN1, the source electrode of transistor P11 receives a power supply voltage VDD, the source electrode of transistor N11 receives a ground potential, the drain electrode of transistor P11 is electrically connected to the source electrode of transistor P12, the drain electrode of transistor P12 is electrically connected to the drain electrode of transistor N11, the drain electrode of transistor P13 receives a ground potential, and its source electrode is electrically connected to the drain electrode of transistor P11, the gate electrode of transistor P13 is electrically connected to a node NV11 between the drain electrode of transistor P12 and the drain electrode of transistor N11, and outputs a signal OUT3 as an output terminal.

[0057] According to one embodiment, the width-to-length ratio W / L of transistor P11 can be 1 μm for width and 16 μm for length. According to one embodiment, the width of transistors P12 and P13 can be 2 μm for width and 4 μm-6 μm for length. According to one embodiment, the width-to-length ratio W / L of transistor N11 can be 8 μm for width and 0.6 μm for length. In other words, the width-to-length ratio of transistor N11 is much larger than the width-to-length ratios of other transistors in the Schmitt trigger of this embodiment.

[0058] According to one embodiment, when the input signal IN1 of the Schmitt trigger rises, the potential of the node NV11 and the output signal OUT3 are pulled down to the ground potential due to the large width-to-length ratio W / L of the transistor N11 and the fast turn-on speed; at this time, the transistor P13 is turned on, and the potential of the node NV12 between the transistor P11 and the transistor P12 is also pulled down to the ground potential; the source and drain potentials of the transistor P12 are both at the ground potential, so no current flows through the transistor P12, and the output signal OUT3 is controlled only by branch 1.

[0059] According to one embodiment, to prevent false triggering due to glitches or jitter during the rising phase of input signal IN1, which could affect the output of OUT3, branch 2 provides a hysteresis window, directing the current generated by the false trigger signal to ground through transistors P11 and P13. Transistor P11 has a small aspect ratio, resulting in a smaller current flowing through branch 2, thereby reducing power consumption. Compared to a traditional Schmitt trigger, the input signal does not need to meet a high threshold to reverse the voltage through branch 1. This is because transistor N11 in this embodiment of the Schmitt trigger has a large aspect ratio, low on-resistance, and a low on-threshold, thereby reducing dynamic power consumption.

[0060] like Figure 4As shown, according to one embodiment, the gate electrodes of transistor P21, transistor N21 and transistor N22 are electrically connected and receive the input signal IN2, the source electrode of transistor P21 receives the power supply voltage VDD, the source electrode of transistor N22 receives the ground potential, the drain electrode of transistor P21 is electrically connected to the drain electrode of transistor N21, the source electrode of transistor N21 is electrically connected to the drain electrode of transistor N22, the drain electrode of transistor N23 receives the power supply voltage VDD, the source electrode of transistor N23 is electrically connected to the drain electrode of transistor N22, the gate electrode of transistor N23 is electrically connected to the node NV22 between the drain electrode of transistor P21 and the drain electrode of transistor N21, and outputs the signal OUT4 as the output terminal.

[0061] According to one embodiment, the width-to-length ratio W / L of transistor N22 can be 1 μm for width and 16 μm for length. According to one embodiment, the width of transistor N21 and transistor N23 can be 2 μm for width and 4 μm-6 μm for length. According to one embodiment, the width-to-length ratio W / L of transistor P21 can be 8 μm for width and 0.6 μm for length. In other words, the width-to-length ratio of transistor P21 is much larger than the width-to-length ratios of other transistors in the Schmitt trigger of this embodiment.

[0062] According to one embodiment, when the input signal IN2 of the Schmitt trigger drops, since the transistor P21 has a large width-to-length ratio W / L and opens quickly, the potential of the node NV22 and the output signal OUT4 are pulled to a high potential; at this time, the transistor N23 is turned on, and the potential of the node NV21 between the transistor N21 and the transistor N22 is also pulled to a high potential; the source and drain potentials of the transistor N21 are both high potentials, so no current flows through the transistor N21, and the output signal OUT4 is only controlled by branch 4.

[0063] According to one embodiment, to prevent false triggering due to glitches or jitter during the falling edge of input signal IN2, which could affect the output of OUT4, branch 3 provides a hysteresis window, directing the current generated by the false trigger signal to ground through transistors N22 and N23. Transistor N22 has a small aspect ratio, resulting in a smaller current flowing through branch 3, thereby reducing power consumption. Compared to a traditional Schmitt trigger, the input signal does not need to meet a lower threshold to invert the voltage through branch 4. This is because transistor P21 in this embodiment of the Schmitt trigger has a large aspect ratio, low on-resistance, and a low on-threshold, thereby reducing dynamic power consumption.

[0064] Figure 5 FIG. 4 is a schematic diagram of a wake-up circuit according to another embodiment of the present application.

[0065] Since the signals at the two input ends of the super-cutoff stack structure start from common-mode signals, such as Figure 1 and Figure 2As shown, the common mode signal affects the potential V of the electrical connection point X in the two wake-up circuits. X .

[0066] According to one embodiment, turning on the Schmitt trigger ST100 requires that the voltage at the node SEN_N100 rise to a sufficiently high level. When the received common-mode signal is relatively low, the super-cutoff stack structure does not have enough differential voltage to fully turn on, resulting in the voltage at the node SEN_N100 being too low to trigger the Schmitt trigger ST100. For example, when the common-mode signal is lower than (Vthn + |Vthp|) / 2, at a power supply voltage of 1.2V, the input differential voltage cannot fully turn on the super-cutoff stack structure, and the voltage at the node SEN_N100 cannot effectively rise. Figure 1 When the wake-up circuit shown is working, the super-cutoff stack structure requires a higher common-mode voltage, for example, higher than (Vthn+|Vthp|) / 2. According to one embodiment, turning on the Schmitt trigger ST200 requires the voltage at the node SEN_P200 to drop sufficiently low. When the common-mode signal is relatively high, for example, the common-mode signal is higher than VDD-(Vthn+|Vthp|) / 2, the super-cutoff stack structure does not have enough differential voltage to fully open, resulting in the voltage at the node SEN_P200 not being able to effectively drop. Figure 2 When the wake-up device shown in the figure works, a lower common-mode voltage is required to be input to the signal input terminal.

[0067] In order to ensure that the wake-up circuit can still work normally when the input signals of the two input ends of the super-cutoff stack structure are low common mode or high common mode, the present application provides the following Figure 5 The wake-up circuit shown will Figure 1 and Figure 2 The wake-up circuit shown in the figure can make the input common-mode signal range unlimited, that is, realize the rail-to-rail input signal.

[0068] like Figure 5 As shown, according to one embodiment, the drain electrode of the PMOS transistor MP1 in the super cutoff stack structure 501 is electrically connected to the first end of the resistor R1 and the input end of the Schmitt trigger ST1, the intersection voltage is the voltage of the node SEN_N1, and the drain electrode of the NMOS transistor MN1 receives the voltage source VDD. According to one embodiment, the Schmitt trigger ST1 can be as follows Figure 3 The Schmitt trigger shown.

[0069] According to one embodiment, the drain electrode of the NMOS transistor MN2 in the super cutoff stack structure 502 is electrically connected to the first end of the resistor R2 and the input end of the Schmitt trigger ST2, the intersection voltage is the voltage of the node SEN_P1, and the drain electrode of the PMOS transistor MP2 receives the ground potential. According to one embodiment, the Schmitt trigger ST2 can be as follows Figure 4 The Schmitt trigger shown.

[0070] According to one embodiment, the gates of the two super-cutoff stacked NMOS transistors MN1 and MN2 are electrically connected to receive the signal VGN, and the gates of the PMOS transistors MP1 and MP2 are electrically connected to receive the signal VGP.

[0071] According to one embodiment, the second terminal of resistor R1 receives ground potential, and the second terminal of resistor R2 receives voltage source VDD. According to one embodiment, resistors R1 and R2 have equal resistance values. According to one embodiment, resistors R1 and R2 can be flexibly configured as passive resistors or active current sources.

[0072] According to one embodiment, the output end of the Schmitt trigger ST2 can be electrically connected to the input end of the inverter INV1. The output end of the inverter INV1 and the output end of the Schmitt trigger ST1 are two input ends of the NAND gate NAND1. The output of the NAND gate NAND1 is the signal OUT5 output end of the entire circuit.

[0073] According to one embodiment, when the differential input signal satisfies Vthn+|Vthp|, Figure 5 The wake-up circuit shown can achieve rail-to-rail input, wherein the two branches of the NAND gate input signal can reinforce each other, one for low common mode and the other for high common mode.

[0074] According to one embodiment, when the power supply voltage is 1.2V, the power consumption when the input differential voltage value is zero is only 132pW. Even when the input differential voltage is the power supply voltage of 1.2V, the power consumption is only 410nW. At a communication frequency of 2MHz, the energy efficiency is 0.103pJ / Hz.

[0075] Figure 6 FIG. 4 is a schematic diagram of a wake-up circuit according to another embodiment of the present application.

[0076] According to one embodiment, the drain electrode of the PMOS transistor MP3 in the super cutoff stack structure 601 is electrically connected to the first end of the resistor R3 and the input end of the Schmitt trigger ST3, the intersection voltage is the voltage of the node SEN_N2, and the drain electrode of the NMOS transistor MN3 receives the voltage source VDD. According to one embodiment, the Schmitt trigger ST3 can be as follows Figure 3 The Schmitt trigger shown.

[0077] According to one embodiment, the drain electrode of the NMOS transistor MN4 in the super cutoff stack structure 602 is electrically connected to the first end of the resistor R4 and the input end of the Schmitt trigger ST4, the intersection voltage is the voltage of the node SEN_P2, and the drain electrode of the PMOS transistor MP4 receives the ground potential. According to one embodiment, the Schmitt trigger ST4 can be as follows Figure 4 The Schmitt trigger shown.

[0078] According to one embodiment, the gates of the two super-cutoff stacked NMOS transistors MN3 and MN4 are electrically connected to receive the signal VGN, and the gates of the PMOS transistors MP3 and MP4 are electrically connected to receive the signal VGP.

[0079] According to one embodiment, a second terminal of resistor R3 receives ground potential, and a second terminal of resistor R4 receives voltage source VDD. According to one embodiment, resistors R3 and R4 have equal resistance values. According to one embodiment, resistors R3 and R4 can be flexibly configured as passive resistors or active current sources.

[0080] According to one embodiment, the output of the Schmitt trigger ST3 can be electrically connected to the input of the inverter INV2. The output of the inverter INV2 and the output of the Schmitt trigger ST4 are two inputs of the OR gate OR1. The output of the OR gate OR1 is the signal OUT6 output of the entire circuit.

[0081] According to one embodiment, when the differential input signal satisfies Vthn+|Vthp|, Figure 6 The wake-up circuit shown can achieve rail-to-rail input, wherein the two branches of the OR gate input signal can reinforce each other, one for low common mode and the other for high common mode.

[0082] According to one embodiment, when the power supply voltage is 1.2V, the power consumption when the input differential voltage value is zero is only 132pW. Even when the input differential voltage is the power supply voltage of 1.2V, the power consumption is only 410nW. At a communication frequency of 2MHz, the energy efficiency is 0.103pJ / Hz.

[0083] Use Figure 5 and Figure 6 The double-sided rail-to-rail wake-up circuit shown does not need to consider the level of the common-mode signal in the input signal. As long as the differential-mode signal meets the conduction threshold condition of the super-cutoff stack structure, the wake-up function of the subsequent circuit can be realized.

[0084] However, when waking up the subsequent circuit, due to the interference in the environment, the following Figure 5 or Figure 6 The wake-up circuit shown may result in inaccurate output signals, so two Figure 5 and / or Figure 6The wake-up circuit shown determines whether to wake up the subsequent circuit by the synchronization status of the outputs of the two wake-up circuits.

[0085] Figure 7-10 FIG. 2 is a schematic diagram of a wake-up circuit according to another embodiment of the present application.

[0086] like Figure 7 The wake-up circuit shown adopts two wake-up units, and the input signals of the two wake-up units are opposite. According to one embodiment, the gates of the transistors MN11 and MN12 in the wake-up unit A1 and the gates of the transistors MP21 and MP22 in the wake-up unit A2 are electrically connected as the differential signal VGN input terminal, and the gates of the transistors MP11 and MP12 in the wake-up unit A1 and the gates of the transistors MN21 and MN22 in the wake-up unit A2 are electrically connected as the differential signal VGP input terminal. The wake-up unit has a fast rising response under the action of the voltage source VDD, but in the falling response, it cannot respond quickly due to the limitation of the resistance value. The long falling delay time limits its application in receiving fast signals, so that when the two wake-up units are communicating at high speed at the same time, the output signals OUT71 and OUT72 may be erroneously output as high levels. In order to achieve a fast and symmetrical response of the input signal in a high-frequency state and solve the problem of asymmetric rise and fall times, as shown in FIG. Figure 7 As shown, the fast rising edge of the output signal OUT71 of the wake-up unit A1 and the output signal OUT72 of the wake-up unit A2 is used to feed back the other circuit of the two circuits to achieve the above-mentioned effect.

[0087] According to one embodiment, the wake-up circuit can operate at an input signal frequency greater than 500KHZ.

[0088] According to one embodiment, the awakening unit A1 includes a first awakening subunit including a super-cutoff stack structure 701 and a resistor R11, a second awakening subunit including a super-cutoff stack structure 702 and a resistor R12; and a feedback circuit B1 and an output unit C1 electrically connected thereto in sequence, wherein the feedback circuit B1 includes a transistor MP13, a resistor R14, a capacitor C11, an inverter INV11, a capacitor C12, a resistor R13 and a transistor MN13, and the output unit C1 includes a Schmitt trigger ST11, a Schmitt trigger ST12, an inverter INV712 and a NAND gate NAND2.

[0089] According to one embodiment, the drain electrode of the PMOS transistor MP11 in the super-cutoff stack structure 701 in the wake-up unit A1, the first end of the resistor R11, and the input end of the Schmitt trigger ST11 are all electrically connected to the node SEN_N1, the drain electrode of the NMOS transistor MN11 receives the power supply voltage VDD, the source electrode of the NMOS transistor MN11 is electrically connected to the source electrode of the transistor MP11, and the node SEN_N1 is the output end of the above-mentioned super-cutoff stack structure 701.

[0090] According to one embodiment, the drain electrode of the NMOS transistor MN12 in the super-cutoff stack structure 702 is electrically connected to the node SEN_N2 along with the first end of the resistor R12 and the input end of the Schmitt trigger ST12. The drain electrode of the PMOS transistor MP12 receives the ground potential, and the source electrode of the PMOS transistor MP12 is electrically connected to the source electrode of the transistor MN12. The node SEN_N2 is the output end of the super-cutoff stack structure 702.

[0091] According to one embodiment, the output terminal of the Schmitt trigger ST12 is electrically connected to the input terminal of the inverter INV712, the output terminal of the inverter INV712 and the output terminal of the Schmitt trigger ST11 are electrically connected to the input terminal of the NAND gate NAND2, and the output terminal of the NAND gate NAND2 serves as the output terminal OUT71 of the wake-up unit A1. According to one embodiment, ST11 can be as follows Figure 3 According to one embodiment, ST12 can be as follows Figure 4 The Schmitt trigger shown.

[0092] According to one embodiment, the drain electrode of the transistor MP13 is electrically connected to the input terminal of the Schmitt trigger ST12, the source electrode of the transistor MP13 is electrically connected to the first terminal of the resistor R14, and is configured to receive the power supply voltage VDD, the gate electrode of the transistor MP13 is electrically connected to the second terminal of the resistor R14 and the first plate of the capacitor C11, the second plate of the capacitor C11 is electrically connected to the output terminal of the inverter INV11, the drain electrode of the transistor MN13 is electrically connected to the input terminal of the Schmitt trigger ST11, the source electrode of the transistor MN13 is electrically connected to the first terminal of the resistor R13, and is configured to receive the ground potential, the gate electrode of the transistor MN13 is electrically connected to the second terminal of the resistor R13 and the first plate of the capacitor C12, the second plate of the capacitor C12 is electrically connected to the input terminal of the inverter INV11 and the output terminal of the output signal OUT72 of the wake-up unit A2.

[0093] According to one embodiment, the drain electrode of the PMOS transistor MP21 in the super-cutoff stack structure 703 in the wake-up unit A2 is electrically connected to the voltage of the node SEN_N3, the first end of the resistor R21, and the input end of the Schmitt trigger ST21, the drain electrode of the NMOS transistor MN21 is configured to receive the power supply voltage VDD, and the node SEN_N3 is the output end of the above-mentioned super-cutoff stack structure 703.

[0094] According to one embodiment, the drain electrode of the NMOS transistor MN22 in the super-cutoff stack structure 704 is electrically connected to the node SEN_N4 along with the first end of the resistor R22 and the input end of the Schmitt trigger ST22. The drain electrode of the PMOS transistor MP22 receives the ground potential. The source electrode of the NMOS transistor MN22 is electrically connected to the source electrode of the transistor MP22. The node SEN_N4 is the output end of the super-cutoff stack structure 704.

[0095] According to one embodiment, the output of the Schmitt trigger ST22 is electrically connected to the input of the inverter INV722, the output of the inverter INV722 and the output of the Schmitt trigger ST21 are electrically connected to the input of the NAND gate NAND3, and the output of the NAND gate NAND3 serves as the output OUT72 of the wake-up unit A2. According to one embodiment, ST21 can be as follows Figure 3 According to one embodiment, ST22 can be as follows Figure 4 The Schmitt trigger shown.

[0096] According to one embodiment, the drain electrode of the transistor MP23 is electrically connected to the input terminal of the Schmitt trigger ST22, the source electrode of the transistor MP23 is electrically connected to the first terminal of the resistor R24, and is configured to receive the power supply voltage VDD, the gate electrode of the transistor MP23 is electrically connected to the second terminal of the resistor R24 ​​and the first plate of the capacitor C21, the second plate of the capacitor C21 is electrically connected to the output terminal of the inverter INV21, the drain electrode of the transistor MN23 is electrically connected to the input terminal of the Schmitt trigger ST21, the source electrode of the transistor MN23 is electrically connected to the first terminal of the resistor R23, and is configured to receive the ground potential, the gate electrode of the transistor MN23 is electrically connected to the second terminal of the resistor R23 and the first plate of the capacitor C22, the second plate of the capacitor C22 is electrically connected to the input terminal of the inverter INV21 and the output terminal of the wake-up unit A1 signal OUT71.

[0097] According to one embodiment, the awakening unit A2 includes a third awakening sub-unit including a super-cutoff stack structure 703 and a resistor R21, a fourth awakening sub-unit including a super-cutoff stack structure 704 and a resistor R22; and a feedback circuit B2 and an output unit C2 electrically connected thereto in sequence, wherein the feedback circuit B2 includes a transistor MP23, a resistor R24, a capacitor C21, an inverter INV21, a capacitor C22, a resistor R23 and a transistor MN23, and the output unit C2 includes a Schmitt trigger ST21, a Schmitt trigger ST22, an inverter INV722 and a NAND gate NAND3.

[0098] According to one embodiment, wake-up unit A1 may only include a super-cutoff stack structure 701, a resistor R11, a Schmitt trigger ST11, an inverter (not shown), a transistor MN13, a resistor R13, and a capacitor C12. According to one embodiment, the output of the Schmitt trigger ST11 is electrically connected to the input of the inverter, and the output of the inverter serves as the signal output of wake-up unit A1.

[0099] According to one embodiment, the awakening unit A1 may only include the super-cutoff stack structure 702, the resistor R12, the Schmitt trigger ST12, the inverter INV712, the inverter INV11, the capacitor C11, the resistor R14, and the transistor MP13, and the output end of the inverter INV712 serves as the output end of the awakening unit A1.

[0100] According to one embodiment, the awakening unit A2 may only include a super-cutoff stack structure 703, a resistor R21, a Schmitt trigger ST21, an inverter (not shown in the figure), a transistor MN23, a resistor R23, and a capacitor C22. The output end of the Schmitt trigger ST21 is electrically connected to the input end of the inverter, and the output end of the inverter serves as the output end of the awakening unit A2.

[0101] According to one embodiment, the awakening unit A2 may only include a super-cutoff stack structure 704, a resistor R22, a Schmitt trigger ST22, an inverter INV722, an inverter INV21, a capacitor C21, a resistor R24, and a transistor MP23, the output end of the Schmitt trigger ST22 is electrically connected to the input end of the inverter INV722, and the output end of the inverter INV722 serves as the output end of the awakening unit A2.

[0102] According to one embodiment, the resistors R11 , R12 , R21 , and R22 can be flexibly configured as passive resistors or active current sources.

[0103] like Figure 8 As shown, Figure 7Similar parts will not be repeated here. According to one embodiment, the output unit C1 may include a Schmitt trigger ST11, a Schmitt trigger ST12, an inverter INV812, and an OR gate OR2. The output of the Schmitt trigger ST11 is electrically connected to the input of the inverter INV812, the output of the inverter INV812 and the output of the Schmitt trigger ST12 are electrically connected to the input of the OR gate OR2, and the output of the Schmitt trigger ST12 serves as the output of the wake-up unit A1 signal OUT81. According to one embodiment, the output unit C2 may include a Schmitt trigger ST21, a Schmitt trigger ST22, an inverter INV722, and a NAND gate NAND3. The output of the Schmitt trigger ST22 is electrically connected to the input of the inverter INV722, the output of the inverter INV722 and the output of the Schmitt trigger ST21 are electrically connected to the input of the NAND gate NAND3, and the output of the Schmitt trigger ST21 serves as the output of the wake-up unit A2 signal OUT82.

[0104] like Figure 9 As shown, according to one embodiment, the output unit C1 may include a Schmitt trigger ST11, a Schmitt trigger ST12, an inverter INV712, and a NAND gate NAND2, wherein the output of the Schmitt trigger ST12 is electrically connected to the input of the inverter INV712, the output of the inverter INV712 and the output of the Schmitt trigger ST11 are electrically connected to the input of the NAND gate NAND2, and the output of the Schmitt trigger ST11 serves as the output of the wake-up unit A1 signal OUT91. According to one embodiment, the output unit C2 may include a Schmitt trigger ST21, a Schmitt trigger ST22, an inverter INV922, and an OR gate OR3, wherein the output of the Schmitt trigger ST21 is electrically connected to the input of the inverter INV922, the output of the inverter INV922 and the output of the Schmitt trigger ST22 are electrically connected to the input of the OR gate OR3, and the output of the OR gate OR3 serves as the output of the wake-up unit A2 signal OUT92.

[0105] like Figure 10As shown, according to one embodiment, the output unit C1 may include a Schmitt trigger ST11, a Schmitt trigger ST12, an inverter INV812, and an OR gate OR2, wherein the output of the Schmitt trigger ST11 is electrically connected to the input of the inverter INV812, the output of the inverter INV812 and the output of the Schmitt trigger ST12 are electrically connected to the input of the OR gate OR2, and the output of the Schmitt trigger ST12 serves as the output of the wake-up unit A1 signal OUT101. According to one embodiment, the output unit C2 may include a Schmitt trigger ST21, a Schmitt trigger ST22, an inverter INV922, and an OR gate OR3, wherein the output of the Schmitt trigger ST21 is electrically connected to the input of the inverter INV922, the output of the inverter INV922 and the output of the Schmitt trigger ST22 are electrically connected to the input of the OR gate OR3, and the output of the OR gate OR3 serves as the output of the wake-up unit A2 signal OUT102.

[0106] Figure 11 An example of an embodiment of the present application is shown. Figure 7 The working sequence diagram of the wake-up circuit in FIG. Figure 11 As shown, according to one embodiment, during the t0-t1 phase, the input signals VGN and VGP are initially in common mode. As the differential mode signal gradually increases to a threshold voltage satisfying VGN-VGP greater than or equal to Vthn+|Vthp|, the super-cutoff stack structures 701 and 702 in the wake-up unit A1 are turned on, the voltage of the node SEN_N1 gradually increases, and after passing through the Schmitt trigger ST11, a low potential signal is output; the voltage of the node SEN_N2 gradually decreases, and after passing through the Schmitt trigger ST12 and the inverter INV712, a low potential signal is output. The output signals of the Schmitt trigger ST11 and the inverter INV712 pass through the NAND gate NAND2, and the output signal OUT71 rises from a low potential to a high potential. The node FPP in the wake-up unit A2 transmits a short rising pulse voltage through the capacitor.

[0107] According to one embodiment, during the t1-t2 phase, as the differential mode voltage VGN-VGP of the input signals VGN and VGP decreases, the differential mode voltage VGP-VGN increases, the voltage of the node SEN_N1 gradually decreases, and the voltage of the node SEN_N2 gradually increases. However, since the resistors R11 and R12 are large resistance devices, the voltage of the node SEN_N1 decreases very slowly, and the voltage of the node SEN_N2 increases very slowly. When the differential mode of the input signals VGN and VGP decreases to satisfy VGP-VGN greater than or equal to Vthn+|Vthp|, the super cutoff stacks 703 and 704 in the wake-up unit A2 are turned on, the voltage of the node SEN_N3 gradually increases, and a low potential signal is output after passing through the Schmitt trigger ST21; the voltage of the node SEN_N4 gradually decreases, and a low potential signal is output after passing through the Schmitt trigger ST22 and the inverter INV722. The output signal of the Schmitt trigger ST21 and the inverter INV722 passes through the NAND Gate NAND3, the output signal OUT72 changes from a low potential to a high potential. Due to the AC-passing and DC-blocking characteristics of capacitor C12, and resistor R13, the AC signal transmitted by the capacitor can be briefly maintained, that is, a short rising pulse voltage of node FNP. Transistor MN13 is instantly turned on, causing the voltage at node SEN_N1 to be quickly reduced to a low potential. After passing through the Schmitt trigger ST11, a high potential signal is output. At the same time, under the combined action of inverter INV11, capacitor C11 and resistor R14, transistor MP13 is quickly turned on, and the voltage at node SEN_N2 is quickly pulled up to a high potential. After passing through the Schmitt trigger ST12 and inverter INV712, a high potential signal is output. After the output signals of Schmitt trigger ST11 and inverter INV712 pass through the NAND gate NAND2, the output signal OUT71 quickly changes to a low potential.

[0108] According to one embodiment, during the t2-t3 phase, the differential-mode signal VGP-VGN of the input signals VGN and VGP gradually decreases, the voltage at node SEN_N3 gradually decreases, and the voltage at node SEN_N4 gradually increases. However, because resistors R21 and R22 are large-resistance devices, the voltage at node SEN_N3 decreases very slowly, and the voltage at node SEN_N4 increases very slowly. When the differential-mode signal VGN-VGP is greater than or equal to the threshold voltage Vthn+|Vthp|, the super-cutoff stack structures 701 and 702 in the wake-up unit A1 are turned on, the voltage at node SEN_N1 gradually increases, and after passing through the Schmitt trigger ST11, a low-level signal is output; the voltage at node SEN_N2 gradually decreases, and after passing through the Schmitt trigger ST12 and inverter INV712, a low-level signal is output. The output signals of the Schmitt trigger ST11 and inverter INV712 pass through the NAND gate NAND2, and the output signal OUT71 changes from a low level to a high level. At this time, node FPP transmits a short circuit through the capacitor. Due to the short-term rising pulse voltage, the transistor MN23 is turned on instantaneously, so that the voltage of the node SEN_N3 is quickly reduced to a low potential, and a high potential signal is output through the Schmitt trigger ST21. At the same time, under the joint action of the inverter INV21, the capacitor C21 and the resistor R24, the transistor MP23 is turned on quickly, and the voltage of the node SEN_N4 is quickly pulled up to a high potential, and a high potential signal is output through the Schmitt trigger ST22 and the inverter INV722. After the output signals of the Schmitt trigger ST21 and the inverter INV722 pass through the NAND gate NAND3, the output signal OUT72 quickly changes to a low potential.

[0109] Figure 7-10 As shown, the fast rising / falling edge of the output of one wake-up branch is used to reset the slow falling / rising edge of another wake-up branch, so that symmetrical hysteresis and fast response can be achieved.

[0110] The present application also proposes an electronic device comprising the above-mentioned wake-up circuit.

[0111] The wake-up circuit of the present application is a super-cutoff stacking structure constructed by connecting PMOS transistors and NMOS transistors in series. When the system is in sleep mode, that is, static, the super-cutoff stacking structure works in the super-cutoff state. Since the wake-up circuit of the present application is threshold triggered instead of periodic detection, there is no need to use a clock signal, which greatly reduces the static power consumption of the wake-up circuit; by improving the traditional Schmitt trigger and utilizing different forms of combinations of super-cutoff stacking structures and resistors in the circuit, two forms of wake-up sub-units are constructed, and the wake-up sub-units are combined, and their output ends are respectively realized through output units to output rail-to-rail wake-up circuits, and by combining the outputs of the above two rail-to-rail wake-up circuits in a circuit with mutual feedback, on the one hand, the working efficiency of the wake-up circuit is improved, and on the other hand, the dynamic power consumption of the wake-up circuit is reduced.

[0112] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A wake-up circuit, characterized in that: include, A first super-cutoff stack structure includes a first transistor and a second transistor connected in series, wherein the drain electrode of the first transistor is electrically connected to a power supply, the source electrode is electrically connected to the source electrode of the second transistor, the gate electrode of the first transistor serves as a first signal input terminal, the gate electrode of the second transistor serves as a second signal input terminal, the first transistor is an N-type transistor, and the second transistor is a P-type transistor; a first resistor or a first current source, a first end of which is electrically connected to the drain electrode of the second transistor and a second end of which is grounded; a first Schmitt trigger, whose input terminal is electrically connected to a first node where the drain electrode of the second transistor and the first end of the first resistor are electrically connected, and whose output terminal serves as the wake-up device output terminal; or The awakening circuit further includes a first inverter, an input end of which is electrically connected to the output end of the first Schmitt trigger, and an output end of which serves as the output end of the awakening circuit.

2. The wake-up circuit according to claim 1, characterized in that: The first Schmitt trigger includes a third transistor, a fourth transistor, and a fifth transistor whose gates are electrically connected together as an input terminal of the first Schmitt trigger, wherein a source electrode of the third transistor is electrically connected to a power supply, a source electrode of the fifth transistor is grounded, a drain electrode of the third transistor is electrically connected to the source electrode of the fourth transistor, a drain electrode of the fourth transistor is electrically connected to the drain electrode of the fifth transistor, a drain electrode of the sixth transistor is grounded, and a source electrode thereof is electrically connected to the drain electrode of the third transistor, a gate electrode of the sixth transistor is electrically connected to the drain electrode of the fourth transistor and the drain electrode of the fifth transistor, and serves as an output terminal of the first Schmitt trigger; The fifth transistor is complementary to the third transistor, the fourth transistor, and the sixth transistor in type, and the width-to-length ratio of the fifth transistor is greater than the width-to-length ratios of other transistors in the first Schmitt trigger.

3. A wake-up circuit, characterized in that: include, a second super-cutoff stack structure, comprising a seventh transistor and an eighth transistor connected in series, wherein a source electrode of the seventh transistor is electrically connected to a source electrode of the eighth transistor, a gate electrode of the seventh transistor serves as a first signal input terminal, and a gate electrode of the eighth transistor serves as a second signal input terminal, the seventh transistor is an N-type transistor, and the eighth transistor is a P-type transistor; a second resistor or a second current source, a first end of which is electrically connected to the drain electrode of the seventh transistor, and a second end of which is electrically connected to a power supply; A second Schmitt trigger, whose input end is electrically connected to a second node where the drain electrode of the seventh transistor and the first end of the second resistor are electrically connected, and whose output end serves as the output end of the wake-up device; or The awakening circuit further includes a second inverter, an input end of which is electrically connected to the output end of the second Schmitt trigger, and an output end of which serves as the output end of the awakening circuit.

4. The wake-up circuit according to claim 3, characterized in that: The second Schmitt trigger includes, a ninth transistor, a tenth transistor, and an eleventh transistor whose gates are electrically connected together as input terminals of the second Schmitt trigger, wherein a source electrode of the ninth transistor is electrically connected to a power supply, a source electrode of the eleventh transistor is grounded, a drain electrode of the eleventh transistor is electrically connected to the source electrode of the tenth transistor, a drain electrode of the ninth transistor is electrically connected to the drain electrode of the tenth transistor, a drain electrode of the twelfth transistor is connected to a power supply, and a source electrode thereof is electrically connected to the source electrode of the tenth transistor, a gate electrode of the twelfth transistor is electrically connected to the drain electrode of the ninth transistor and the drain electrode of the tenth transistor, and serves as an output terminal of the second Schmitt trigger; The type of the ninth transistor is complementary to that of the tenth transistor, the eleventh transistor and the twelfth transistor, and the width-to-length ratio of the ninth transistor is greater than the width-to-length ratios of other transistors in the second Schmitt trigger.

5. A wake-up circuit, characterized in that: include, a third super-cutoff stack structure, comprising a thirteenth transistor and a fourteenth transistor connected in series, wherein the drain electrode of the thirteenth transistor is electrically connected to a power supply, the source electrode of the thirteenth transistor is electrically connected to the source electrode of the fourteenth transistor, the gate electrode of the thirteenth transistor serves as a first signal input terminal, the gate electrode of the fourteenth transistor serves as a second signal input terminal, the thirteenth transistor is an N-type transistor, and the fourteenth transistor is a P-type transistor; a fourth super-cutoff stack structure, comprising a fifteenth transistor and a sixteenth transistor connected in series, wherein a source electrode of the fifteenth transistor is electrically connected to a source electrode of the sixteenth transistor, a gate electrode of the fifteenth transistor serves as a first signal input terminal, and a gate electrode of the sixteenth transistor serves as a second signal input terminal, the fifteenth transistor is an N-type transistor, and the sixteenth transistor is a P-type transistor; a third resistor or a third current source, a first end of which is electrically connected to the drain electrode of the fourteenth transistor and a second end of which is grounded; a fourth resistor or a fourth current source, a first end of which is electrically connected to the drain electrode of the fifteenth transistor and a second end of which is connected to a power supply; a third Schmitt trigger, an input terminal of which is electrically connected to a third node where the drain electrode of the fourteenth transistor and the first terminal of the third resistor are electrically connected; a fourth Schmitt trigger, an input end of which is electrically connected to a fourth node where the drain electrode of the fifteenth transistor and the first end of the fourth resistor are electrically connected; a third inverter, an input terminal of which is electrically connected to the output terminal of the fourth Schmitt trigger; The first NAND gate has two input terminals electrically connected to the output terminal of the third inverter and the output terminal of the third Schmitt trigger respectively, and the output terminal of the first NAND gate serves as the output terminal of the wake-up circuit.

6. The wake-up circuit according to claim 5, characterized in that: The third Schmitt trigger includes a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor whose gates are electrically connected together as the input terminal of the third Schmitt trigger, wherein the source electrode of the seventeenth transistor is electrically connected to a power supply, the source electrode of the nineteenth transistor is grounded, the drain electrode of the seventeenth transistor is electrically connected to the source electrode of the eighteenth transistor, the drain electrode of the eighteenth transistor is electrically connected to the drain electrode of the nineteenth transistor, the drain electrode of the twentieth transistor is grounded, and its source electrode is electrically connected to the drain electrode of the seventeenth transistor, the gate electrode of the twentieth transistor is electrically connected to the drain electrode of the eighteenth transistor and the drain electrode of the nineteenth transistor, and serves as the output terminal of the third Schmitt trigger, wherein the type of the nineteenth transistor is complementary to the seventeenth transistor, the eighteenth transistor and the twentieth transistor, and the width-to-length ratio of the nineteenth transistor is greater than the width-to-length ratios of the other transistors of the third Schmitt trigger; and / or, The fourth Schmitt trigger includes a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor whose gates are electrically connected together as the input terminal of the fourth Schmitt trigger, wherein the source electrode of the twenty-first transistor is electrically connected to the power supply, the source electrode of the twenty-third transistor is grounded, the drain electrode of the twenty-third transistor is electrically connected to the source electrode of the twenty-second transistor, the drain electrode of the twenty-first transistor is electrically connected to the drain electrode of the twenty-second transistor, the drain electrode of the twenty-fourth transistor is connected to the power supply, and its source electrode is electrically connected to the source electrode of the twenty-second transistor, the gate electrode of the twenty-fourth transistor is electrically connected to the drain electrode of the twenty-first transistor and the drain electrode of the twenty-second transistor, and serves as the output terminal of the fourth Schmitt trigger, wherein the type of the twenty-first transistor is complementary to the twenty-second transistor, the twenty-third transistor and the twenty-fourth transistor, and the width-to-length ratio of the twenty-first transistor is greater than the width-to-length ratio of other transistors in the fourth Schmitt trigger.

7. A wake-up circuit, characterized in that: include, a fifth super-cutoff stack structure, comprising a twenty-fifth transistor and a second sixth transistor connected in series, wherein the drain electrode of the twenty-fifth transistor is electrically connected to a power supply, the source electrode of the twenty-sixth transistor is electrically connected to the source electrode of the twenty-sixth transistor, the gate electrode of the twenty-fifth transistor serves as a first signal input terminal, the gate electrode of the twenty-sixth transistor serves as a second signal input terminal, the twenty-fifth transistor is an N-type transistor, and the twenty-sixth transistor is a P-type transistor; a sixth super-cutoff stack structure, comprising a twenty-seventh transistor and a twenty-eighth transistor connected in series, wherein a source electrode of the twenty-seventh transistor is electrically connected to a source electrode of the twenty-eighth transistor, a gate electrode of the twenty-seventh transistor serves as a first signal input terminal, and a gate electrode of the twenty-eighth transistor serves as a second signal input terminal, the twenty-seventh transistor is an N-type transistor, and the twenty-eighth transistor is a P-type transistor; a fifth resistor or a fifth current source, a first end of which is electrically connected to the drain electrode of the twenty-sixth transistor and a second end of which is grounded; a sixth resistor or a sixth current source, a first end of which is electrically connected to the drain electrode of the twenty-seventh transistor and a second end of which is connected to a power supply; a fifth Schmitt trigger, an input terminal of which is electrically connected to a fifth node where the drain electrode of the twenty-sixth transistor and the first terminal of the fifth resistor are electrically connected; a sixth Schmitt trigger, an input terminal of which is electrically connected to a sixth node where the drain electrode of the twenty-seventh transistor and the first terminal of the sixth resistor are electrically connected; a fourth inverter, an input terminal of which is electrically connected to the output terminal of the fifth Schmitt trigger; The first OR gate has two input terminals electrically connected to the output terminal of the fourth inverter and the output terminal of the sixth Schmitt trigger respectively, and the output terminal of the first OR gate serves as the output terminal of the wake-up circuit.

8. The wake-up circuit according to claim 7, characterized in that: The fifth Schmitt trigger includes a twenty-ninth transistor, a thirtieth transistor, and a thirty-first transistor whose gates are electrically connected together as the input terminal of the fifth Schmitt trigger, wherein the source electrode of the twenty-ninth transistor is electrically connected to a power supply, the source electrode of the thirty-first transistor is grounded, the drain electrode of the twenty-ninth transistor is electrically connected to the source electrode of the thirtieth transistor, the drain electrode of the thirtieth transistor is electrically connected to the drain electrode of the thirty-first transistor, the drain electrode of the thirty-second transistor is grounded, and its source electrode is electrically connected to the drain electrode of the twenty-ninth transistor, the gate electrode of the thirty-second transistor is electrically connected to the drain electrode of the thirtieth transistor and the drain electrode of the thirty-first transistor, and serves as the output terminal of the fifth Schmitt trigger, wherein the type of the thirty-first transistor is complementary to that of the twenty-ninth transistor, the thirtieth transistor, and the thirty-second transistor, and the width-to-length ratio of the thirty-first transistor is greater than the width-to-length ratios of the other transistors of the fifth Schmitt trigger; and / or, The sixth Schmitt trigger includes a thirty-third transistor, a thirty-fourth transistor, and a thirty-fifth transistor whose gates are electrically connected together as the input terminal of the sixth Schmitt trigger, wherein the source electrode of the thirty-third transistor is electrically connected to the power supply, the source electrode of the thirty-fifth transistor is grounded, the drain electrode of the thirty-fifth transistor is electrically connected to the source electrode of the thirty-fourth transistor, the drain electrode of the thirty-third transistor is electrically connected to the drain electrode of the thirty-fourth transistor, the drain electrode of the thirty-sixth transistor is connected to the power supply, and its source electrode is electrically connected to the source electrode of the thirty-fourth transistor, the gate electrode of the thirty-sixth transistor is electrically connected to the drain electrode of the thirty-third transistor and the drain electrode of the thirty-fourth transistor, and serves as the output terminal of the sixth Schmitt trigger, wherein the type of the thirty-third transistor is complementary to the thirty-fourth transistor, the thirty-fifth transistor and the thirty-sixth transistor, and the width-to-length ratio of the thirty-third transistor is greater than the width-to-length ratios of the other transistors of the sixth Schmitt trigger.

9. A wake-up circuit, characterized in that: include, The first wake-up unit includes: The first awakening subunit includes a seventh super-cutoff stack structure having one end electrically connected to the power supply and a seventh resistor or a seventh current source having one end connected in series with the power supply and the other end grounded; and / or, The second awakening subunit includes an eighth super-cutoff stack structure with one end grounded and an eighth resistor or an eighth current source connected in series with the eighth resistor at one end and electrically connected to a power supply at the other end; a first feedback circuit electrically connected to the output terminal of the first wake-up subunit and the output terminal of the second wake-up subunit; a first output unit electrically connected to the first feedback circuit; The second wake-up unit includes: The third awakening subunit includes a ninth super-cutoff stack structure having one end electrically connected to the power supply and a ninth resistor or a ninth current source having one end connected in series with the power supply and the other end grounded; and / or, A fourth awakening subunit includes a tenth super cutoff stack structure with one end grounded and a tenth resistor or a tenth current source with one end connected in series with the tenth super cutoff stack structure and the other end electrically connected to a power supply; a second feedback circuit electrically connected to the output terminal of the third awakening subunit and the output terminal of the fourth awakening subunit; a second output unit electrically connected to the second feedback circuit; The first feedback circuit is configured to receive an output of the second wake-up unit, and the second feedback circuit is configured to receive an output of the first wake-up unit.

10. The wake-up circuit according to claim 9, characterized in that: When the first awakening unit includes a first awakening subunit and a second awakening subunit, The first output unit includes: a seventh Schmitt trigger, an input end of which is electrically connected to the output end of the first wake-up sub-unit; an eighth Schmitt trigger, an input end of which is electrically connected to the output end of the second wake-up sub-unit; a fifth inverter and a second NAND gate, wherein the input terminal of the fifth inverter is electrically connected to the output terminal of the eighth Schmitt trigger, the output terminal of the fifth inverter and the output terminal of the seventh Schmitt trigger are electrically connected to the input terminal of the second NAND gate, and the output terminal of the second NAND gate serves as the output terminal of the first output unit; or a sixth inverter and a second OR gate, wherein the input terminal of the sixth inverter is electrically connected to the output terminal of the seventh Schmitt trigger, the output terminal of the sixth inverter and the output terminal of the eighth Schmitt trigger are electrically connected to the input terminal of the second OR gate, and the output terminal of the second OR gate serves as the output terminal of the first output unit; or When the first awakening unit includes a first awakening subunit, The first output unit includes: a seventh Schmitt trigger and a sixth inverter, wherein the input terminal of the sixth inverter is electrically connected to the output terminal of the seventh Schmitt trigger, and the output terminal of the sixth inverter serves as the output terminal of the first output unit; or When the first awakening unit includes a second awakening subunit, The first output unit includes: An eighth Schmitt trigger and a fifth inverter, wherein the input terminal of the fifth inverter is electrically connected to the output terminal of the eighth Schmitt trigger, and the output terminal of the fifth inverter serves as the output terminal of the first output unit.

11. The wake-up circuit according to claim 9, characterized in that: When the second awakening unit includes a third awakening subunit and a fourth awakening subunit, The second output unit includes: a ninth Schmitt trigger, an input end of which is electrically connected to the output end of the third wake-up sub-unit; a tenth Schmitt trigger, an input end of which is electrically connected to the output end of the fourth wake-up sub-unit; a seventh inverter and a third NAND gate, wherein the input terminal of the seventh inverter is electrically connected to the output terminal of the tenth Schmitt trigger, the output terminal of the seventh inverter and the output terminal of the ninth Schmitt trigger are electrically connected to the input terminal of the third NAND gate, and the output terminal of the third NAND gate serves as the output terminal of the second output unit; or an eighth inverter and a third OR gate, wherein the input terminal of the eighth inverter is electrically connected to the output terminal of the ninth Schmitt trigger, the output terminal of the eighth inverter and the output terminal of the tenth Schmitt trigger are electrically connected to the input terminal of the third OR gate, and the output terminal of the third OR gate serves as the output terminal of the second output unit; or When the second awakening unit includes a third awakening subunit, The second output unit includes: a ninth Schmitt trigger and an eighth inverter, wherein the input terminal of the eighth inverter is electrically connected to the output terminal of the ninth Schmitt trigger, and the output terminal of the eighth inverter serves as the output terminal of the second output unit; or When the second awakening unit includes a fourth awakening subunit, The second output unit includes: A tenth Schmitt trigger and a seventh inverter, wherein the input terminal of the seventh inverter is electrically connected to the output terminal of the tenth Schmitt trigger, and the output terminal of the seventh inverter serves as the output terminal of the second output unit.

12. The wake-up circuit according to claim 10, wherein: When the first awakening unit includes a first awakening subunit and a second awakening subunit, The first feedback circuit includes: a thirty-seventh transistor, a drain electrode of which is electrically connected to the eighth Schmitt trigger input terminal, and a source electrode of which is electrically connected to a power supply; an eleventh resistor, one end of which is electrically connected to a power supply, and the other end of which is electrically connected to the gate of the thirty-seventh transistor; a first capacitor, a first plate of which is electrically connected to the gate of the thirty-seventh transistor; a ninth inverter, an input end of which is electrically connected to the output end of the second wake-up unit, and an output end of which is electrically connected to the second plate of the first capacitor; a thirty-eighth transistor, whose drain electrode is electrically connected to the seventh Schmitt trigger input terminal, whose source electrode is electrically connected to the first terminal of the twelfth resistor and receives the ground potential, whose gate electrode is electrically connected to the second terminal of the twelfth resistor and the first plate of the second capacitor, and whose second plate is electrically connected to the ninth inverter input terminal and the second wake-up unit output terminal; or When the first awakening unit includes a first awakening subunit, The first feedback circuit includes: a twelfth resistor, a first end of which receives a ground potential; a thirty-eighth transistor, a drain electrode of which is electrically connected to the input terminal of the seventh Schmitt trigger, a source electrode of which is electrically connected to the first terminal of the twelfth resistor, and a gate electrode of which is electrically connected to the second terminal of the twelfth resistor and the first plate of the second capacitor; A second capacitor, a second plate of which is electrically connected to the output terminal of the second wake-up unit; or When the first awakening unit includes a second awakening subunit, The first feedback circuit includes: a thirty-seventh transistor, a drain electrode of which is electrically connected to the eighth Schmitt trigger input terminal, and a source electrode of which is electrically connected to a power supply; an eleventh resistor, one end of which is electrically connected to a power supply, and the other end of which is electrically connected to the gate of the thirty-seventh transistor; a first capacitor, a first plate of which is electrically connected to the gate of the thirty-seventh transistor; A ninth inverter has an input end electrically connected to the output end of the second wake-up unit, and an output end electrically connected to the second plate of the first capacitor.

13. The wake-up circuit according to claim 11, characterized in that: When the second awakening unit includes a third awakening subunit and a fourth awakening subunit, The second feedback circuit includes, a thirty-ninth transistor, a drain electrode of which is electrically connected to the tenth Schmitt trigger input terminal, and a source electrode of which is electrically connected to a power supply; a thirteenth resistor, one end of which is electrically connected to a power supply, and the other end of which is electrically connected to the gate of the thirty-ninth transistor; a third capacitor, a first plate of which is electrically connected to the gate of the thirty-ninth transistor; a tenth inverter, an input end of which is electrically connected to the output end of the first wake-up unit, and an output end of which is electrically connected to the second plate of the third capacitor; a fortieth transistor, having a drain electrode electrically connected to the ninth Schmitt trigger input terminal, a source electrode electrically connected to the first terminal of the fourteenth resistor and receiving a ground potential, a gate electrode electrically connected to the second terminal of the fourteenth resistor and the first plate of the fourth capacitor, and the second plate of the fourth capacitor electrically connected to the tenth inverter input terminal and the first wake-up unit output terminal; or When the second awakening unit includes a third awakening subunit, The second feedback circuit includes, a fourteenth resistor, a first end of which receives a ground potential; a fortieth transistor, having a drain electrode electrically connected to the ninth Schmitt trigger input terminal, a source electrode electrically connected to the first terminal of the fourteenth resistor, and a gate electrode electrically connected to the second terminal of the fourteenth resistor and the first plate of the fourth capacitor; a fourth capacitor, the second plate of which is electrically connected to the output terminal of the first wake-up unit; or When the second awakening unit includes a fourth awakening subunit, The second feedback circuit includes, a thirty-ninth transistor, a drain electrode of which is electrically connected to the tenth Schmitt trigger input terminal, and a source electrode of which is electrically connected to a power supply; a thirteenth resistor, one end of which is electrically connected to a power supply, and the other end of which is electrically connected to the gate of the thirty-ninth transistor; a third capacitor, a first plate of which is electrically connected to the gate of the thirty-ninth transistor; A tenth inverter has an input end electrically connected to the output end of the first wake-up unit, and an output end electrically connected to the second plate of the third capacitor.

14. The wake-up circuit according to claim 9, wherein: The seventh super cutoff stack structure, include, a forty-first transistor and a forty-second transistor connected in series, wherein a drain electrode of the forty-second transistor is electrically connected to the first end of the seventh resistor, and a source electrode thereof is electrically connected to the source electrode of the forty-first transistor, the forty-first transistor is an N-type transistor, and the forty-second transistor is a P-type transistor; and / or, The eighth super cutoff stack structure, include, a forty-third transistor and a forty-fourth transistor connected in series, wherein a drain electrode of the forty-third transistor is electrically connected to the first end of the eighth resistor, and a source electrode of the forty-third transistor is electrically connected to the source electrode of the forty-fourth transistor, the forty-third transistor is an N-type transistor, and the forty-fourth transistor is a P-type transistor; and / or, The ninth super cutoff stacking structure, include, a forty-fifth transistor and a forty-sixth transistor connected in series, wherein a drain electrode of the forty-sixth transistor is electrically connected to the first end of the ninth resistor, and a source electrode thereof is electrically connected to the source electrode of the forty-fifth transistor, the forty-fifth transistor is an N-type transistor, and the forty-sixth transistor is a P-type transistor; and / or, The tenth super cutoff stack structure, include, a forty-seventh transistor and a forty-eighth transistor connected in series, wherein a drain electrode of the forty-seventh transistor is electrically connected to the first end of the tenth resistor, and a source electrode thereof is electrically connected to the source electrode of the forty-eighth transistor, the forty-seventh transistor is an N-type transistor, and the forty-eighth transistor is a P-type transistor; Among them, the gate electrodes of the forty-first transistor, the forty-third transistor, the forty-sixth transistor and the forty-eighth transistor serve as the first signal input terminal; the gate electrodes of the forty-second transistor, the forty-fourth transistor, the forty-fifth transistor and the forty-seventh transistor serve as the second signal input terminal.

15. The wake-up circuit according to claim 10, wherein: The seventh Schmitt trigger includes: a forty-ninth transistor, a fiftieth transistor, and a fifty-first transistor whose gates are electrically connected together as an input terminal of the seventh Schmitt trigger, wherein the source electrode of the forty-ninth transistor is electrically connected to a power supply, the source electrode of the fifty-first transistor is grounded, the drain electrode of the forty-ninth transistor is electrically connected to the source electrode of the fiftieth transistor, the drain electrode of the fiftieth transistor is electrically connected to the drain electrode of the fifty-first transistor, the drain electrode of the fifty-second transistor is grounded, and its source electrode is electrically connected to the drain electrode of the forty-ninth transistor, the gate electrode of the fifty-second transistor is electrically connected to the drain electrode of the fiftieth transistor and the drain electrode of the fifty-first transistor, and serves as an output terminal of the seventh Schmitt trigger, wherein the type of the fifty-first transistor is complementary to that of the forty-ninth transistor, the fiftieth transistor, and the fifty-second transistor, and the width-to-length ratio of the fifty-first transistor is greater than the width-to-length ratios of the other transistors of the seventh Schmitt trigger; and / or, The eighth Schmitt trigger includes a fifty-third transistor, a fifty-fourth transistor, and a fifty-fifth transistor whose gates are electrically connected together as the input terminal of the eighth Schmitt trigger, wherein the source electrode of the fifty-third transistor is electrically connected to the power supply, the source electrode of the fifty-fifth transistor is grounded, the drain electrode of the fifty-fifth transistor is electrically connected to the source electrode of the fifty-fourth transistor, the drain electrode of the fifty-third transistor is electrically connected to the drain electrode of the fifty-fourth transistor, the drain electrode of the fifty-sixth transistor is connected to the power supply, and its source electrode is electrically connected to the source electrode of the fifty-fourth transistor, the gate electrode of the fifty-sixth transistor is electrically connected to the drain electrode of the fifty-third transistor and the drain electrode of the fifty-fourth transistor, and serves as the output terminal of the eighth Schmitt trigger, wherein the type of the fifty-third transistor is complementary to the fifty-fourth transistor, the fifty-fifth transistor and the fifty-sixth transistor, and the width-to-length ratio of the fifty-third transistor is greater than the width-to-length ratio of other transistors in the eighth Schmitt trigger.

16. The wake-up circuit according to claim 11, wherein: The ninth Schmitt trigger includes a fifty-seventh transistor, a fifty-eighth transistor, and a fifty-ninth transistor whose gates are electrically connected together as the input terminal of the ninth Schmitt trigger, wherein the source electrode of the fifty-seventh transistor is electrically connected to a power supply, the source electrode of the fifty-ninth transistor is grounded, the drain electrode of the fifty-seventh transistor is electrically connected to the source electrode of the fifty-eighth transistor, the drain electrode of the fifty-eighth transistor is electrically connected to the drain electrode of the fifty-ninth transistor, the drain electrode of the sixtieth transistor is grounded, and its source electrode is electrically connected to the drain electrode of the fifty-seventh transistor, the gate electrode of the sixtieth transistor is electrically connected to the drain electrode of the fifty-eighth transistor and the drain electrode of the fifty-ninth transistor, and serves as the output terminal of the ninth Schmitt trigger; wherein the fifty-ninth transistor is complementary to the types of the fifty-seventh, fifty-eighth, and sixtieth transistors, and the width-to-length ratio of the fifty-ninth transistor is greater than the width-to-length ratios of the other transistors of the ninth Schmitt trigger; and / or, The tenth Schmitt trigger includes a sixty-first transistor, a sixty-second transistor, and a sixty-third transistor, whose gates are electrically connected together as the input terminal of the tenth Schmitt trigger, wherein the source electrode of the sixty-first transistor is electrically connected to the power supply, the source electrode of the sixty-third transistor is grounded, the drain electrode of the sixty-third transistor is electrically connected to the source electrode of the sixty-second transistor, the drain electrode of the sixty-first transistor is electrically connected to the drain electrode of the sixty-second transistor, the drain electrode of the sixty-fourth transistor is connected to the power supply, and its source electrode is electrically connected to the source electrode of the sixty-second transistor, the gate electrode of the sixty-fourth transistor is electrically connected to the drain electrode of the sixty-first transistor and the drain electrode of the sixty-second transistor, and serves as the output terminal of the tenth Schmitt trigger; wherein the type of the sixty-first transistor is complementary to the sixty-second transistor, the sixty-third transistor and the sixty-fourth transistor, and the width-to-length ratio of the sixty-first transistor is greater than the width-to-length ratios of the other transistors of the tenth Schmitt trigger.

17. An electronic device comprising the wake-up circuit according to any one of claims 1 to 16.

Images