Composite analog signal generation system and method based on direct digital synthesis

Abstract

The invention discloses a composite analog signal generation system and method based on direct digital synthesis, and the system comprises an upper computer which is used for presetting and transmitting calculation parameters and waveform characteristic functions; the phase accumulator module is used for generating a continuous waveform phase sequence through a nonlinear phase accumulation algorithm according to the calculation parameters transmitted by the upper computer; the waveform amplitude calculation module is used for receiving the phase sequence output by the phase accumulator module, calculating the amplitude of each sampling point in combination with a preset waveform characteristic function, and generating waveform data; the waveform modulation module is used for carrying out modulation optimization on the waveform data output by the waveform amplitude calculation module based on the current waveform modulation parameter, and carrying out seamless splicing and superposition on the modulated waveform data to generate a digital waveform signal; and the DAC digital-to-analog conversion module is used for converting the digital waveform signal output by the waveform modulation module into a composite analog signal. According to the invention, high-time-sequence-resolution composite analog signal synthesis and dynamic modulation functions are realized.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a composite analog signal generation system and method based on direct digital synthesis. Background Art

[0002] With the increasing variety of applications in electronic testing, communication systems, and power equipment, waveform signal generation technology plays a vital role in high-precision signal generation, debugging, and analysis. Direct digital synthesis (DDS) technology, as one of the core methods for waveform generation, is widely used in test instruments and communication signal generators. Traditional DDS technology uses a phase accumulator to accumulate a frequency adjustment word (FTW) with each rising edge of the sampling clock. Several most significant bits of the phase accumulator's output are used to address a waveform memory to output waveform samples. After the waveform phase and amplitude conversion is complete, the sample is converted into an analog waveform signal via a digital-to-analog converter (DAC). However, because waveform samples are stored in a read-only waveform memory (ROM) to synthesize the waveform, and ROM capacity is limited, the waveform storage capacity is insufficient when generating high-precision waveforms. Furthermore, due to the read-only nature of ROM, timing parameters are difficult to change continuously, limiting the frequency range of arbitrary waveform output and the requirements for signal generation.

[0003] Currently, in order to change the limitations of ROM, researchers have proposed a method based on real-time calculation of waveform amplitude. This method is no longer limited by storage capacity, and can adjust waveform parameters at the same time, and can synthesize characteristic waveforms with high resolution without waveform memory. However, its phase accumulator makes periodic waveforms prone to harmonic distortion and phase overflow when the period changes. At the same time, waveform synthesis based on real-time calculation requires a waveform modulation process, but the modulation parameters need to rely on manual setting. It has a single function and requires rich expert knowledge to achieve good synthesis performance, and lacks parameter optimization capabilities.

[0004] In summary, the above-mentioned traditional technologies have some common problems. First, the waveform signal output is not flexible enough and relies on pre-stored data or fixed formulas, making it impossible to generate customizable waveform functions in real time; second, the adjustment of the modulation waveform parameters relies on prior knowledge and cannot be adaptively optimized; third, the computing resources are not high, and the timing of the signal may be inconsistent, resulting in a contradiction between high-precision waveforms and computing resources or storage capacity. Summary of the Invention

[0005] To address the deficiencies in the prior art, the present invention provides a composite analog signal generation system and method based on direct digital synthesis, which overcomes the problems of storage capacity limitations, insufficient waveform flexibility, manual reliance on parameter adjustment, and low multi-channel synchronization accuracy in the prior art, and realizes waveform synthesis and dynamic modulation functions with high timing resolution.

[0006] The present invention adopts the following technical solutions.

[0007] In a first aspect, the present invention provides a composite analog signal generation system based on direct digital synthesis, the system comprising:

[0008] The host computer is used to preset and transmit calculation parameters and waveform characteristic functions;

[0009] The phase accumulator module is used to generate a continuous waveform phase sequence through a nonlinear phase accumulation algorithm based on the calculation parameters transmitted by the host computer;

[0010] The waveform amplitude calculation module is used to receive the phase sequence output by the phase accumulator module and calculate the amplitude of each sampling point in combination with a preset waveform characteristic function to generate waveform data;

[0011] The waveform modulation module is used to modulate and optimize the waveform data output by the waveform amplitude calculation module based on the current waveform modulation parameters, and seamlessly splice and superimpose the modulated waveform data to generate a digital waveform signal;

[0012] The DAC digital-to-analog conversion module is used to convert the digital waveform signal output by the waveform modulation module into a composite analog signal.

[0013] Optionally, the system further includes:

[0014] The modulation parameter optimization module is used to optimize the waveform modulation parameters using the Q-learning algorithm of reinforcement learning to compensate for the nonlinear error generated by the waveform, and feed the optimized waveform modulation parameters back to the waveform modulation module.

[0015] Optionally, the calculation parameter includes a sampling clock frequency, and the system further includes:

[0016] The clock adaptation module is used to dynamically adjust the sampling clock frequency by judging the phase overflow error.

[0017] Optionally, the calculation parameters include: an initial phase value P0, a bit width N, a frequency adjustment word K and a target waveform frequency f0.

[0018] Optionally, the expression for generating a continuous waveform phase sequence by the nonlinear phase accumulation algorithm is as follows:

[0019] P=(P1,P2,…,P n )

[0020] P t =P t-1 +K t +αsin(2πP t-1 ), t=1,2…n

[0021] Where P represents the waveform phase sequence, P t Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t, K t is the frequency adjustment word updated at the current time t, α is the first compensation coefficient set, sin(2πP t-1 ) is the introduced nonlinear mapping function, the phase value P0 at the initial moment is the preset value, and n represents the total number of time steps.

[0022] Optional, frequency adjustment word K t The update formula is as follows:

[0023]

[0024] Where K t-Δt is the frequency adjustment word at Δt time intervals before the current time t, β is the set second compensation coefficient; Δ f It represents the deviation value after dynamic frequency modulation or the deviation value between the actual output frequency f and the target waveform frequency f0; Δt is the time interval from the occurrence of frequency deviation to the current moment; the updated K t Send it to the phase accumulator module to replace the original frequency adjustment word K t-Δt ; Among them, the frequency adjustment word K0 at the initial moment is calculated by the following formula:

[0025]

[0026] Where N is the bit width, f s is the sampling clock frequency, and f0 is the target waveform frequency.

[0027] Optionally, the state space s, action space a, and reward function r when optimizing waveform modulation parameters using the reinforcement learning Q-learning algorithm are defined as follows:

[0028] The state space s is the waveform output state characteristics measured in real time in each cycle, including the distortion value THD and amplitude deviation of the current harmonic;

[0029] Action space a is for adjusting the modulation parameters, including changing the increments of pulse width, frequency and amplitude modulation parameters;

[0030] The reward function r is:

[0031] r=-((∑(V target -V out ) 2 )+λ·THD)

[0032] Where V targetIndicates the amplitude of the target waveform signal, V out It represents the actual output waveform signal amplitude under the current modulation parameters, λ is the weighting factor, and THD represents the current harmonic distortion value.

[0033] Optionally, the calculation formula for dynamically adjusting the sampling clock frequency is as follows:

[0034] f s，t+1 =f s,t ·(1+ρ·ΔP t )

[0035]

[0036] ε=αsin(2πP t )-αsin(2πP t-1 )

[0037] f s，t+1 =f s,t ·(1+ρ·ΔP t )

[0038] Where ΔP t The frequency adjustment word K at the current time t t The theoretical phase change under s，t is the current sampling clock frequency; ε is the nonlinear compensation error, P t Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t; f s，t+1 is the adjusted sampling clock frequency, and ρ is the clock adjustment coefficient.

[0039] Optionally, the DAC digital-to-analog conversion module receives the digital waveform signal output by the waveform modulation module through multiple JESD204B interfaces; each JESD204B interface is sequentially connected to a time synchronization unit and a DAC channel unit;

[0040] Each of the time synchronization units is used to compensate for the data transmission delay of the channel in which it is located by adding a timestamp and a forward feedback mechanism;

[0041] Each of the DAC channel units is used to convert a digital waveform signal received by the channel where it is located into a composite analog signal.

[0042] Optionally, compensating for the data transmission delay of the channel by adding a timestamp and a forward feedback mechanism includes:

[0043] Calculate the time compensation delay value Δt of each channel separately comp , and based on the Δt of each channel compAdjust the timestamp of the waveform data in each corresponding channel respectively so that the data of each channel can be aligned, thereby achieving synchronous output of multi-channel signals; among them, the time compensation delay value Δt comp The calculation formula is as follows:

[0044] Δt comp =Δt+k p ·e -t / τ

[0045] Where Δt represents the transmission time difference of the data packet from the sender to the receiver of each channel, k p is the proportional coefficient, and τ is the time constant.

[0046] Optional,

[0047] The phase accumulator module, waveform amplitude calculation module, waveform modulation module and clock adaptive adjustment module are integrated into the FPGA platform, and the modulation parameter optimization module is integrated into the CPU platform;

[0048] The FPGA platform is responsible for data processing of phase accumulation, waveform amplitude calculation, pulse width modulation, frequency modulation, amplitude modulation and updating sampling clock frequency; the CPU platform is responsible for data processing of optimizing waveform modulation parameters based on Q-learning algorithm of reinforcement learning.

[0049] In a second aspect, the present invention provides a method for generating a composite analog signal based on direct digital synthesis, using the composite analog signal generation system based on direct digital synthesis as described in any one of the first aspects of the present invention, the method comprising:

[0050] The calculation parameters and waveform characteristic functions are preset and transmitted by the host computer.

[0051] The phase accumulator module generates a continuous waveform phase sequence through a nonlinear phase accumulation algorithm according to the calculation parameters transmitted by the host computer;

[0052] The waveform amplitude calculation module receives the phase sequence output by the phase accumulator module, and calculates the amplitude of each sampling point in combination with the preset waveform characteristic function to generate waveform data;

[0053] The waveform modulation module is used to modulate and optimize the waveform data output by the waveform amplitude calculation module based on the current waveform modulation parameters, including pulse width modulation, frequency modulation and amplitude modulation, and the modulated waveform data are seamlessly spliced ​​and superimposed to generate a digital waveform signal;

[0054] The digital waveform signal output by the waveform modulation module is converted into a composite analog signal through the DAC digital-to-analog conversion module.

[0055] Optionally, the method further includes:

[0056] The waveform modulation parameters are optimized by the modulation parameter optimization module using the Q-learning algorithm of reinforcement learning to compensate for the nonlinear error generated by the waveform, and the optimized waveform modulation parameters are fed back to the waveform modulation module.

[0057] Optionally, the calculation parameter includes a sampling clock frequency, and the method further includes:

[0058] The clock adaptive module is used to dynamically adjust the sampling clock frequency by judging the phase overflow error. Optionally, the calculation parameters also include: initial phase value P0, bit width N, frequency adjustment word K and target waveform frequency f0.

[0059] Optionally, the expression for generating a continuous waveform phase sequence by the nonlinear phase accumulation algorithm is as follows:

[0060] P=(P1,P2,…,P n )

[0061] P t =P t-1 +K t +αsin(2πP t-1 ), t=1,2…n

[0062] Where P represents the waveform phase sequence, P t Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t, K t is the frequency adjustment word updated at the current time t, α is the first compensation coefficient set, sin(2πP t-1 ) is the introduced nonlinear mapping function, the phase value P0 at the initial moment is the preset value, and n represents the total number of time steps.

[0063] Optional, frequency adjustment word K t The update formula is as follows:

[0064]

[0065] Where K t-Δt is the frequency adjustment word at Δt time intervals before the current time t, β is the set second compensation coefficient; Δ f It represents the deviation value after dynamic frequency modulation or the deviation value between the actual output frequency f and the target waveform frequency f0; Δt is the time interval from the occurrence of frequency deviation to the current moment; the updated K t Send it to the phase accumulator module to replace the original frequency adjustment word K t-Δt ; Among them, the frequency adjustment word K0 at the initial moment is calculated by the following formula:

[0066]

[0067] Where N is the bit width, f s is the sampling clock frequency, and f0 is the target waveform frequency.

[0068] Optionally, the state space s, action space a, and reward function r when optimizing waveform modulation parameters using the reinforcement learning Q-learning algorithm are defined as follows:

[0069] The state space s is the waveform output state characteristics measured in real time in each cycle, including the distortion value THD and amplitude deviation of the current harmonic;

[0070] Action space a is for adjusting the modulation parameters, including changing the increments of pulse width, frequency and amplitude modulation parameters;

[0071] The reward function r is:

[0072] r=-((∑(V target -V out ) 2 )+λ·THD)

[0073] Where V target Indicates the amplitude of the target waveform signal, V out It represents the actual output waveform signal amplitude under the current modulation parameters, λ is the weighting factor, and THD represents the current harmonic distortion value.

[0074] Optionally, the calculation formula for dynamically adjusting the sampling clock frequency is as follows:

[0075] f s,t+1 =f s,t ·(1+ρ·ΔP t )

[0076]

[0077] ε=αsin(2πP t )-αsin(2πP t-1 )

[0078] Where ΔP t The frequency adjustment word K at the current time t t The theoretical phase change under s，t is the current sampling clock frequency; ε is the nonlinear compensation error, P t Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t; f s，t+1is the adjusted sampling clock frequency, and ρ is the clock adjustment coefficient.

[0079] Optionally, the DAC digital-to-analog conversion module receives the digital waveform signal output by the waveform modulation module through multiple JESD204B interfaces; each JESD204B interface is sequentially connected to a time synchronization unit and a DAC channel unit;

[0080] Each of the time synchronization units is used to compensate for the data transmission delay of the channel in which it is located by adding a timestamp and a forward feedback mechanism;

[0081] Each of the DAC channel units is used to convert a digital waveform signal received by the channel where it is located into a composite analog signal.

[0082] Optionally, compensating for the data transmission delay of the channel by adding a timestamp and a forward feedback mechanism includes:

[0083] Calculate the time compensation delay value Δt of each channel separately comp , and based on the Δt of each channel comp Adjust the timestamp of the waveform data in each corresponding channel respectively so that the data of each channel can be aligned, thereby achieving synchronous output of multi-channel signals; among them, the time compensation delay value Δt comp The calculation formula is as follows:

[0084] Δt comp =Δt+k p ·e -t / τ

[0085] Where Δt represents the transmission time difference of the data packet from the sender to the receiver of each channel, k p is the proportional coefficient, and τ is the time constant.

[0086] Optionally, the phase accumulator module, waveform amplitude calculation module, waveform modulation module and clock adaptive adjustment module are integrated into the FPGA platform, and the modulation parameter optimization module is integrated into the CPU platform;

[0087] The FPGA platform is responsible for data processing of phase accumulation, waveform amplitude calculation, pulse width modulation, frequency modulation, amplitude modulation and updating sampling clock frequency; the CPU platform is responsible for data processing of optimizing waveform modulation parameters based on Q-learning algorithm of reinforcement learning.

[0088] The beneficial effects of the present invention are as follows:

[0089] 1. The phase accumulator module provided by the present invention generates a continuous and smooth phase sequence through a nonlinear phase accumulation algorithm. Combined with dynamic frequency adjustment word compensation, it effectively avoids the problems of phase overflow and harmonic distortion that are easily generated by traditional linear phase accumulators when the frequency changes greatly or the system nonlinearity is strong.

[0090] 2. The modulation parameter optimization module provided by the present invention optimizes waveform modulation parameters by adopting the Q-learning algorithm of reinforcement learning to compensate for the nonlinear errors generated by the waveform. This reduces the threshold of prior knowledge and does not rely on pre-stored data or fixed formula assignments based on artificial prior knowledge. It can achieve adaptive optimization and adjustment of modulation parameters, further improving the accuracy of the modulation waveform and the flexibility of the waveform signal.

[0091] 3. The clock adaptation module provided by the present invention dynamically adjusts the sampling clock frequency by judging the phase overflow error, effectively reducing the phase accumulation error and phase overflow risk under high frequency and large bandwidth conditions, avoiding signal distortion and waveform inconsistency, and improving the timing consistency of signal output.

[0092] 4. The present invention takes into account both real-time performance and computing efficiency by establishing an FPGA and CPU collaborative computing architecture, and utilizes the time synchronization unit in the DAC digital-to-analog conversion module to compensate for the data transmission delay of the channel and ensure the timing and stability of multi-channel signal output.

[0093] In summary, the technologies introduced in the present invention, such as nonlinear phase accumulation, dynamic frequency adjustment word compensation, waveform amplitude calculation and corresponding waveform modulation, waveform modulation parameter optimization control, clock frequency adaptive adjustment and multi-channel time synchronization, effectively solve the storage limitations, phase overflow, clock sampling deviation and multi-channel output time synchronization problems existing in traditional DDS systems, provide an efficient, intelligent and high-fidelity waveform generation path, and realize composite analog signal synthesis and dynamic modulation functions with high timing resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] Figure 1 Schematic diagram of the structure of a composite analog signal generation system based on direct digital synthesis in an embodiment of the present invention;

[0095] Figure 2 Schematic diagram of the relationship between the phase and amplitude of the trapezoidal wave in an embodiment of the present invention;

[0096] Figure 3 Schematic diagram of the structure of the high-speed serial data channel between the FPGA and CPU collaborative computing architecture and the DAC in an embodiment of the present invention. DETAILED DESCRIPTION

[0097] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. The embodiments described in the present invention are only part of the embodiments of the present invention, not all of the embodiments. Based on the spirit of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0098] Reference Figure 1 The embodiment of the present invention provides a composite analog signal generation system based on direct digital synthesis. The system structure includes: a host computer, a phase accumulator module, a waveform amplitude calculation module, a waveform modulation module DAC digital-to-analog conversion module. Specifically:

[0099] ① Host computer, used to preset and transmit calculation parameters and waveform characteristic functions;

[0100] In this embodiment, when the user generates a composite waveform, the host computer presets calculation parameters such as the initial phase value in the phase accumulator, the bit width, the frequency adjustment word, the target waveform frequency, the sampling frequency generated by the clock generator, and the external input waveform characteristic function in the waveform modulation module. Furthermore, the sampling clock frequency generated by the clock signal generator is a global parameter that specifies the time step between adjacent sampling points.

[0101] ② Phase accumulator module, used to generate a continuous waveform phase sequence through a nonlinear phase accumulation algorithm based on the calculation parameters transmitted by the host computer;

[0102] The system of the present invention builds a high-precision phase accumulator to produce a continuous and smooth phase sequence. s , phase accumulator bit width N and frequency adjustment word K, calculate the frequency f0 of the output waveform signal:

[0103]

[0104] During operation, dynamic frequency modulation can be achieved by adjusting the frequency adjustment word K; after calculating the waveform frequency f0, the waveform phase value P at time t is calculated. t , the traditional linear phase accumulator is prone to phase overflow and harmonic distortion when the frequency changes greatly or the system nonlinearity is strong; the system of the present invention adopts a nonlinear accumulation algorithm, and the phase update formula is:

[0105] P t =P t-1 +K t +αsin(2πP t-1 ), t=1,2…n

[0106] Where, Pt Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t, K t is the frequency adjustment word currently updated; α is the first compensation coefficient set, whose value is determined by the system performance requirements, and controls the amplitude of the nonlinear compensation term. Preferably, the value of α in this embodiment is set to 0.01 to finely control the amplitude of the nonlinear compensation term; sin(2πP t-1 ) is the introduced nonlinear mapping function, n represents the total number of time steps; the phase value P0 at the initial moment is a preset value, which can be customized. Preferably, the value of P0 in this embodiment is set to 0; the system continuously generates subsequent waveform phase sequences P = (P1, P2, ..., P n ) is used for subsequent waveform synthesis.

[0107] A preferred but non-limiting embodiment, in order to cope with the transient jitter caused by frequency changes and ensure the high precision of the output waveform, the present invention supports dynamic adjustment through the frequency adjustment word K. During the operation of the system, if there is a need for dynamic frequency modulation, or the actual output waveform frequency f deviates from the waveform frequency f0, the dynamic frequency adjustment word compensation equation is used to update the current frequency adjustment word, and the frequency adjustment word K t The update formula is as follows:

[0108]

[0109] Where K t-Δt is the frequency adjustment word for the time interval Δt before the current time t, β is the set second compensation coefficient, which determines the sensitivity of the system to the change of frequency deviation. Preferably, the value of β in this embodiment is set to 0.05 to adjust the frequency deviation faster; Δ f It represents the deviation value after dynamic frequency modulation or the deviation value between the actual output frequency f and the target waveform frequency f0; Δt is the time interval from the occurrence of frequency deviation to the current moment; the updated K t Send it to the phase accumulator module to replace the original frequency adjustment word K t-Δt ; Thus, new frequency control is achieved in the subsequent phase accumulation to ensure that the waveform output frequency gradually approaches the target value; wherein, the frequency adjustment word K0 at the initial moment is calculated by the following formula:

[0110]

[0111] Where N is the bit width, f s is the sampling clock frequency, and f0 is the target waveform frequency.

[0112] ③ Waveform amplitude calculation module, which is used to receive the phase sequence output by the phase accumulator module, and calculate the amplitude of each sampling point in combination with the preset waveform characteristic function to generate waveform data;

[0113] It is particularly noted that the waveform amplitude calculation module constructed in the system of the present invention supports the dynamic splicing of pulse waves, trapezoidal waves and custom piecewise functions, receives the continuous phase value sequence P from the phase accumulator, and calculates the phase value P according to the current time t. t The waveform segment in which it is located uses the corresponding mathematical function to calculate the amplitude of the sampling point; refer to Figure 2 As shown, for any waveform shape, the rising edge waveform sample amplitude V at time t t The calculation formula is:

[0114]

[0115] Where, P t Represents the phase value at time t in the rising edge, V H Represents the amplitude of the highest level point (such as Figure 2 The amplitude corresponding to P1 in the figure), V L Represents the amplitude of the lowest level point (usually 0, such as Figure 2 The amplitudes corresponding to P0 and P3 in the figure), T r Represents the duration of the rising edge.

[0116] For any waveform shape, the amplitude of the falling edge waveform sample point V' at time t t The calculation formula is:

[0117]

[0118] Where P′ t Indicates the phase value at time t in the falling edge, T f Represents the duration of the falling edge, T w Represents pulse width.

[0119] For the stable segment, the breakpoint value is calculated in the form of a piecewise function, and the amplitude calculated in each segment is dynamically spliced ​​to form the final waveform sampling point amplitude sequence for subsequent waveform modulation or direct digital generation module. The general form of piecewise function splicing is as follows:

[0120]

[0121] ④ Waveform modulation module, which is used to modulate and optimize the waveform data output by the waveform amplitude calculation module based on the current waveform modulation parameters, including pulse width modulation, frequency modulation and amplitude modulation, and seamlessly splice and superimpose the modulated waveform data to generate a digital waveform signal;

[0122] The waveform modulation module provided by the present invention performs real-time modulation of the waveform based on the waveform sampling point amplitude output by the waveform amplitude calculation module, allowing the system to flexibly adjust the pulse width, frequency, and amplitude, thereby achieving seamless splicing and superposition of multiple waveforms. The formula for pulse width modulation (PWM) is as follows:

[0123] T w (t) = T w0 +γ·m(t)

[0124] Where, T w (t) represents the pulse width conversion function, T w0 Indicates the initial preset pulse width, which is preset by the user. In this embodiment, T w0 It is taken as 0.156ms, that is, the sampling frequency is 6400Hz; γ represents the pulse width modulation sensitivity coefficient, which is an adaptive modulation parameter; m(t) is the modulation waveform signal of the external input, which can usually be a sine wave, square wave, etc., and the range is normalized to [-1,1].

[0125] For example, when T w0 =0.5, γ=0.2, m(t)=sin(2πTt)

[0126] T w (t)=0.5+0.2sin(2πTt)

[0127] Indicates that the pulse width changes periodically within the range of 30%-70%.

[0128] Similarly, the frequency modulation (FM) method process is similar to the pulse width modulation process, and the calculation formula is:

[0129] f(t)=f0+δ·m(t)

[0130] Where f(t) represents the frequency conversion function, f0 represents the initial output waveform signal frequency, δ represents the frequency modulation sensitivity coefficient, which is the adaptive modulation parameter; m(t) is the external input modulation waveform signal.

[0131] Correspondingly, the calculation formula for amplitude modulation (AM) is:

[0132] V(t)=V0+μ·m(t)

[0133] Where V(t) represents the amplitude conversion function, V0 represents the reference amplitude, μ is the amplitude modulation sensitivity coefficient, m(t) is the adaptive modulation parameter, and m(t) is the modulation waveform signal input externally.

[0134] Furthermore, the waveform modulation module provided by the present invention smoothly transitions the start and end time of each waveform segment according to the optimized modulation parameters, and adopts the cosine transition method to transition the waveforms before and after modulation. Assume that the preset waveform transition time before and after the two modulation waveforms is T trans , the transition cosine function w(t) is:

[0135]

[0136] Where, t is [t start ,t start +T trans ] range, t start represents the transition start time step; the synthetic output function V(t) is:

[0137] V(t)=w(t)V1(t)+(1-w(t))V2(t)

[0138] Where V1(t) and V2(t) represent the waveform output signals before and after modulation, respectively.

[0139] The present invention adopts a cosine transition mode to achieve continuous and smooth conversion of the entire waveform between different modulation modes, thereby avoiding distortion caused by sudden changes.

[0140] In a preferred but non-limiting embodiment, the system provided by the present invention further comprises:

[0141] ⑤ Modulation parameter optimization module, used to optimize the waveform modulation parameters using the Q-learning algorithm of reinforcement learning to compensate for the nonlinear error generated by the waveform, and feed back the optimized waveform modulation parameters to the waveform modulation module.

[0142] This embodiment introduces a Q-learning algorithm based on reinforcement learning, and uses real-time feedback information to automatically optimize parameters in the modulation process to compensate for nonlinear errors and other influencing factors during waveform generation.

[0143] Specifically, based on the reinforcement learning method, the system state space s is defined as the waveform output state characteristics measured in real time in each cycle, including the harmonic distortion value THD and amplitude deviation at the current moment; the action a is defined as the adjustment of the modulation parameters, such as changing the increment of the pulse width, frequency and amplitude modulation parameters; the reward r is set as a negative target loss function, so that the optimization process tends to minimize the loss. The target loss function J is:

[0144] J=(∑(V target -V out ) 2 )+λ·THD

[0145] Where V targetIndicates the amplitude of the target waveform signal, V out It represents the amplitude of the waveform signal actually output under the current modulation parameters, THD represents the distortion value of the current harmonic, and λ is a weighting factor used to evaluate the impact of harmonic distortion. Preferably, in this embodiment, the value of λ is set to 0.2 to evaluate the impact of harmonics.

[0146] The reward function r is: r = -((∑(V target -V out ) 2 )+λ·THD).

[0147] Furthermore, the state-action value function Q(s, a) is updated using the Q-learning update formula:

[0148] Q(s,a)←Q(s,a)+α[r+γmaxQ(s′,a′)-Q(s,a)]

[0149] Here, α is the learning rate, which determines the weight of newly acquired information in the update. In this example, the learning rate is set to 0.001. γ is the discount factor, which represents the weight of future rewards. In this example, the discount factor is set to 0.9. maxQ(s′, a′) represents the maximum expected reward for all possible actions in the new state s′. After iterative learning, the system gradually converges to the optimal policy, thus enabling the modulation parameters to be adaptively optimized.

[0150] In a preferred but non-limiting embodiment, the system provided by the present invention further comprises:

[0151] ⑥ Clock adaptation module, which is used to dynamically adjust the sampling clock frequency by judging the phase overflow error, and synchronously update the adjusted sampling clock frequency to the phase accumulator module, waveform amplitude calculation module, waveform modulation module and DAC digital-to-analog conversion module to ensure timing consistency under high-frequency signals.

[0152] It should be noted that, due to the high-frequency signal, phase error accumulation and phase overflow are prone to occur. Among them, phase error accumulation refers to the mismatch between the phase accumulator update speed and the sampling clock, and the waveform sample points are misaligned; phase overflow refers to the phase value exceeding the accumulator bit width range (such as 32-bit overflow), and the waveform periodicity is disrupted. The present invention utilizes a clock adaptive adjustment mechanism to dynamically adjust the sampling clock frequency to match the phase update of the phase accumulator module by predicting phase overflow and cumulative error, ensuring the generation of high-precision waveform signals under high-frequency and large-bandwidth conditions, and reducing signal distortion and waveform inconsistency.

[0153] In the embodiment of the present invention, the calculation formula for dynamically adjusting the sampling clock frequency is as follows:

[0154]

[0155] ε=αsin(2πP T )-αsin(2πP t-1 )

[0156] f s，t+1 =f s,t ·(1+ρ·ΔP t )

[0157] Where ΔP t The frequency adjustment word K at the current time t t The theoretical phase change under s,t is the current sampling clock frequency; ε is the nonlinear compensation error, P t Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t; f s，t+1 is the adjusted sampling clock frequency; ρ is the clock adjustment coefficient. Preferably, in this embodiment, the value of ρ is set to 0.01.

[0158] The new sampling frequency is fed back to the phase accumulator module, ensuring that its updates are strictly synchronized with the sampling clock. If overflow or error accumulation is detected during the phase accumulation process, the system will continue the process, correcting the sampling clock in real time to maintain timing consistency.

[0159] It is further explained that when the current sampling frequency deviates from the preset sampling frequency, a phase error accumulation will occur, and the actual phase change ΔP act is the actual change generated in each clock sampling period, the error accumulation calculation is:

[0160]

[0161] In this embodiment, the sampling clock frequency is adjusted when the phase accumulation error is greater than 10. Through the above continuous monitoring and adjustment, the clock adaptive adjustment mechanism can accurately match the frequency of the phase accumulator module and the sampling clock, thereby effectively reducing the phase accumulation error and phase overflow risk under high frequency and wide bandwidth conditions, and reducing signal distortion and waveform inconsistency.

[0162] ⑦DAC digital-to-analog conversion module, used to convert the digital waveform signal output by the waveform modulation module into a composite analog signal.

[0163] Reference Figure 3As shown, the DAC digital-to-analog conversion module receives the digital waveform signal output by the waveform modulation module through multiple JESD204B interfaces; each JESD204B interface is sequentially connected to a time synchronization unit and a DAC channel unit; each time synchronization unit is used to compensate for the data transmission delay of its channel by adding a timestamp and a forward feedback mechanism; each DAC channel unit is used to convert the digital signal received by its channel into an analog signal.

[0164] In the scenario of multi-channel output, each time synchronization unit has a certain time delay in the data transmission process between each channel. By adding a timestamp to the data of each channel, the data time difference between the data sender and the receiver is Δt, which can be used to preliminarily obtain the data transmission delay of the channel. The multi-channel delay compensation formula is used to process the delay information of the timestamp using the forward feedback mechanism. The details are as follows:

[0165] Calculate the time compensation delay value Δt of each channel separately comp , and based on the Δt of each channel comp Adjust the timestamp of the waveform data in each corresponding channel respectively so that the data of each channel can be aligned, thereby achieving synchronous output of multi-channel signals; among them, the time compensation delay value Δt comp The calculation formula is as follows:

[0166] Δt comp =Δt+k p ·e -t / τ

[0167] Where Δt represents the transmission time difference of the data packet from the sender to the receiver of each channel, k p is the proportional coefficient, which is set to 0.5 in this example to quickly compensate for the time deviation, and τ is the time constant. Preferably, in this embodiment, τ is set to 5 ms, the order of magnitude of which matches the time deviation.

[0168] In a preferred but non-limiting embodiment, the system provided by the present invention is built on a hardware platform with a collaborative computing architecture of FPGA and CPU. The system's computing tasks are distributed, with the FPGA platform primarily responsible for high-speed, real-time phase accumulation and waveform calculation, while the CPU focuses on parameter optimization based on reinforcement learning. Specifically, the phase accumulator module, waveform amplitude calculation module, waveform modulation module, and clock adaptive adjustment module are integrated into the FPGA platform, while the modulation parameter optimization module is integrated into the CPU platform. The FPGA platform is responsible for data processing for phase accumulation, waveform amplitude calculation, pulse width modulation, frequency modulation, amplitude modulation, and updating the sampling clock frequency; the CPU platform is responsible for data processing for optimizing waveform modulation parameters using the reinforcement learning-based Q-learning algorithm.

[0169] The FPGA and CPU collaborative computing architecture established by the present invention utilizes the parallel processing capabilities of the FPGA to quickly execute the update formula of the phase accumulator module within each sampling cycle, calculate the amplitude of the waveform sampling points in real time, and perform modulation processing such as PWM, FM, and AM to generate preliminary waveform data. At the same time, the CPU side runs the Q-learning algorithm based on reinforcement learning to optimize the waveform modulation parameters online. After a certain iterative training strategy is converged, a set of optimal modulation parameter configurations are obtained, and the optimized parameters are promptly fed back to the FPGA. The improved waveform data calculated by the FPGA will be transmitted to the DAC digital-to-analog conversion module through a high-speed data transmission interface using the JESD204B protocol to output the final composite analog signal.

[0170] An embodiment of the present invention further provides a method for generating a composite analog signal based on direct digital synthesis, using the composite analog signal generation system based on direct digital synthesis as described above. The method includes the following steps:

[0171] Step 1: Preset and transmit calculation parameters and waveform characteristic functions through the host computer,

[0172] Step 2: Use the phase accumulator module to generate a continuous waveform phase sequence through a nonlinear phase accumulation algorithm based on the calculation parameters transmitted by the host computer;

[0173] Step 3: Use the waveform amplitude calculation module to receive the phase sequence output by the phase accumulator module, and calculate the amplitude of each sampling point in combination with the preset waveform characteristic function to generate waveform data;

[0174] Step 4: Use the waveform modulation module to modulate and optimize the waveform data output by the waveform amplitude calculation module, including pulse width modulation, frequency modulation and amplitude modulation, and seamlessly splice and superimpose the modulated waveform data to generate a digital waveform signal;

[0175] Step 5: Convert the digital waveform signal output by the waveform modulation module into a composite analog signal through the DAC digital-to-analog conversion module.

[0176] In a preferred but non-limiting embodiment, the calculation parameters include the sampling clock frequency, and the method further includes: optimizing the waveform modulation parameters using a Q-learning algorithm of reinforcement learning through a modulation parameter optimization module to compensate for the nonlinear error generated by the waveform, and feeding back the optimized waveform modulation parameters to the waveform modulation module.

[0177] In a preferred but non-limiting embodiment, the method further includes: utilizing a clock adaptation module to dynamically adjust the sampling clock frequency by determining a phase overflow error to ensure timing consistency for high-frequency signals. In this embodiment, the calculation parameters also include: an initial phase value P0, a bit width N, a frequency adjustment word K, and a target waveform frequency f0.

[0178] Specifically, the expression for generating a continuous waveform phase sequence by the nonlinear phase accumulation algorithm in step 2 is as follows:

[0179] P=(P1, P2, ..., P n )

[0180] P t =P t-1 +K t +αsin(2πP t-1 ), t=1,2…n

[0181] Where P represents the waveform phase sequence, P t Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t, K t is the frequency adjustment word updated at the current time t, α is the first compensation coefficient set, sin(2πP t-1 ) is the introduced nonlinear mapping function, the phase value P0 at the initial moment is the preset value, and n represents the total number of time steps.

[0182] In a preferred but non-limiting embodiment, the frequency adjustment word K t The update formula is as follows:

[0183]

[0184] Where K t-Δt is the frequency adjustment word at αt time intervals before the current time t, β is the set second compensation coefficient; Δ f It represents the deviation value after dynamic frequency modulation or the deviation value between the actual output frequency f and the target waveform frequency f0; Δt is the time interval from the occurrence of frequency deviation to the current moment; the updated K t Send it to the phase accumulator module to replace the original frequency adjustment word K t-Δt ; Among them, the frequency adjustment word K0 at the initial moment is calculated by the following formula:

[0185]

[0186] Where N is the bit width, f s is the sampling clock frequency, and f0 is the target waveform frequency.

[0187] Specifically, the state space s, action space a, and reward function r when optimizing waveform modulation parameters using the reinforcement learning Q-learning algorithm are defined as follows:

[0188] The state space s is the waveform output state characteristics measured in real time in each cycle, including the distortion value THD and amplitude deviation of the current harmonic;

[0189] Action space a is for adjusting the modulation parameters, including changing the increments of pulse width, frequency and amplitude modulation parameters;

[0190] The reward function r is:

[0191] r=-((∑(V target -V out ) 2 )+λ·THD)

[0192] Where V target Indicates the amplitude of the target waveform signal, V out It represents the actual output waveform signal amplitude under the current modulation parameters, λ is the weighting factor, and THD represents the current harmonic distortion value.

[0193] In a preferred but non-limiting embodiment, the calculation formula for dynamically adjusting the sampling clock frequency is as follows:

[0194] f s，t+1 =f s，t ·(1+ρ·ΔP t )

[0195]

[0196] ε=αsin(2πP t )-αsin(2πP t-1 )

[0197] Where ΔP t The frequency adjustment word K at the current time t t The theoretical phase change under s，t is the current sampling clock frequency; ε is the nonlinear compensation error, P t Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t; f s，t+1 is the adjusted sampling clock frequency, and ρ is the clock adjustment coefficient.

[0198] Furthermore, the DAC digital-to-analog conversion module provided in this embodiment receives the digital waveform signal output by the waveform modulation module through multiple JESD204B interfaces; each JESD204B interface is connected to a time synchronization unit and a DAC channel unit in sequence; each of the time synchronization units is used to compensate for the data transmission delay of the channel in which it is located by adding a timestamp and a forward feedback mechanism; each of the DAC channel units is used to convert the digital waveform signal received by the channel in which it is located into a composite analog signal.

[0199] In a preferred but non-limiting embodiment, the specific steps of compensating the data transmission delay of the channel by adding a timestamp and a forward feedback mechanism include:

[0200] Calculate the time compensation delay value Δt of each channel separately comp , and based on the Δt of each channel comp Adjust the timestamp of the waveform data in each corresponding channel respectively so that the data of each channel can be aligned, thereby achieving synchronous output of multi-channel signals; among them, the time compensation delay value Δt comp The calculation formula is as follows:

[0201] Δt comp =Δt+k p ·e -t / τ

[0202] Where Δt represents the transmission time difference of the data packet from the sender to the receiver of each channel, k p is the proportional coefficient, and τ is the time constant.

[0203] In a preferred but non-limiting embodiment, the phase accumulator module, waveform amplitude calculation module, waveform modulation module and clock adaptive adjustment module are integrated into the FPGA platform, and the modulation parameter optimization module is integrated into the CPU platform; the FPGA platform is responsible for data processing of phase accumulation, waveform amplitude calculation, pulse width modulation, frequency modulation, amplitude modulation and updating of sampling clock frequency; the CPU platform is responsible for data processing of optimizing waveform modulation parameters based on reinforcement learning Q-learning algorithm.

[0204] The beneficial effects of the present invention are as follows:

[0205] 1. The phase accumulator module provided by the present invention generates a continuous and smooth phase sequence through a nonlinear phase accumulation algorithm. Combined with dynamic frequency adjustment word compensation, it effectively avoids the problems of phase overflow and harmonic distortion that are easily generated by traditional linear phase accumulators when the frequency changes greatly or the system nonlinearity is strong.

[0206] 2. The modulation parameter optimization module provided by the present invention optimizes waveform modulation parameters by adopting the Q-learning algorithm of reinforcement learning to compensate for the nonlinear errors generated by the waveform. This reduces the threshold of prior knowledge and does not rely on pre-stored data or fixed formula assignments based on artificial prior knowledge. It can achieve adaptive optimization and adjustment of modulation parameters, further improving the accuracy of the modulation waveform and the flexibility of the waveform signal.

[0207] 3. The clock adaptation module provided by the present invention dynamically adjusts the sampling clock frequency by judging the phase overflow error, effectively reducing the phase accumulation error and phase overflow risk under high frequency and large bandwidth conditions, avoiding signal distortion and waveform inconsistency, and improving the timing consistency of signal output.

[0208] 4. The present invention takes into account both real-time performance and computing efficiency by establishing an FPGA and CPU collaborative computing architecture, and utilizes the time synchronization unit in the DAC digital-to-analog conversion module to compensate for the data transmission delay of the channel and ensure the timing and stability of multi-channel signal output.

[0209] In summary, the technologies introduced in the present invention, such as nonlinear phase accumulation, dynamic frequency adjustment word compensation, waveform amplitude calculation and corresponding waveform modulation, waveform modulation parameter optimization control, clock frequency adaptive adjustment and multi-channel time synchronization, effectively solve the storage limitations, phase overflow, clock sampling deviation and multi-channel output time synchronization problems existing in traditional DDS systems, provide an efficient, intelligent and high-fidelity waveform generation path, and realize composite analog signal synthesis and dynamic modulation functions with high timing resolution.

[0210] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0211] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0212] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0213] The computer program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. The computer readable program instructions can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), is personalized by utilizing the state information of the computer readable program instructions, and the electronic circuit can execute the computer readable program instructions, thereby realizing various aspects of the present invention.

[0214] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered by the scope of protection of the claims of the present invention.

Claims

1. A composite analog signal generation system based on direct digital synthesis, characterized in that: The system includes: The host computer is used to preset and transmit calculation parameters and waveform characteristic functions; The phase accumulator module is used to generate a continuous waveform phase sequence through a nonlinear phase accumulation algorithm based on the calculation parameters transmitted by the host computer; The waveform amplitude calculation module is used to receive the phase sequence output by the phase accumulator module and calculate the amplitude of each sampling point in combination with a preset waveform characteristic function to generate waveform data; The waveform modulation module is used to modulate and optimize the waveform data output by the waveform amplitude calculation module based on the current waveform modulation parameters, and seamlessly splice and superimpose the modulated waveform data to generate a digital waveform signal; The DAC digital-to-analog conversion module is used to convert the digital waveform signal output by the waveform modulation module into a composite analog signal.

2. The composite analog signal generation system based on direct digital synthesis according to claim 1, characterized in that: The system further comprises: The modulation parameter optimization module is used to optimize the waveform modulation parameters of the waveform modulation module using the Q-learning algorithm of reinforcement learning to compensate for the nonlinear error generated by the waveform, and feed the optimized waveform modulation parameters back to the waveform modulation module.

3. The composite analog signal generation system based on direct digital synthesis according to claim 2, characterized in that: The calculation parameter includes a sampling clock frequency, and the system further includes: The clock adaptation module is used to dynamically adjust the sampling clock frequency by judging the phase overflow error.

4. The composite analog signal generation system based on direct digital synthesis according to claim 1, characterized in that: The calculation parameters also include: an initial phase value P0, a bit width N, a frequency adjustment word K, and a target waveform frequency f0.

5. The composite analog signal generation system based on direct digital synthesis according to claim 1 or 4, characterized in that: The expression for generating a continuous waveform phase sequence by the nonlinear phase accumulation algorithm is as follows: P=(P1,P2,···,P n ) P t =P t-1 +K t +αsin(2πP t-1 ),t=1.2···n Where P represents the waveform phase sequence, P t Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t, K t is the frequency adjustment word updated at the current time t, α is the first compensation coefficient set, sin(2πP t-1 ) is the introduced nonlinear mapping function, the phase value P0 at the initial moment is the preset value, and n represents the total number of time steps.

6. The composite analog signal generation system based on direct digital synthesis according to claim 5, characterized in that: Frequency adjustment word K t The update formula is as follows: Where K t-Δt is the frequency adjustment word at Δt time intervals before the current time t, β is the set second compensation coefficient; Δ f It represents the deviation value after dynamic frequency modulation or the deviation value between the actual output frequency f and the target waveform frequency f0; Δt is the time interval from the occurrence of frequency deviation to the current moment; the updated K t Send it to the phase accumulator module to replace the original frequency adjustment word K t-Δt ; Among them, the frequency adjustment word K0 at the initial moment is calculated by the following formula: Where N is the bit width, f s is the sampling clock frequency, and f0 is the target waveform frequency.

7. The composite analog signal generation system based on direct digital synthesis according to claim 2, characterized in that: The state space s, action space a, and reward function r when optimizing waveform modulation parameters using the reinforcement learning Q-learning algorithm are defined as follows: The state space s is the waveform output state characteristics measured in real time in each cycle, including the distortion value THD and amplitude deviation of the current harmonic; Action space a is for adjusting the modulation parameters, including changing the increments of pulse width, frequency and amplitude modulation parameters; The reward function r is: r=-((∑(V target -V out ) 2 )+λ·THD) Where V target Indicates the amplitude of the target waveform signal, V out It represents the actual output waveform signal amplitude under the current modulation parameters, λ is the weighting factor, and THD represents the current harmonic distortion value.

8. The composite analog signal generation system based on direct digital synthesis according to claim 3, characterized in that: The calculation formula for dynamically adjusting the sampling clock frequency is as follows: f s,t+1 =f s,t ·(1+ρ·ΔP t ) ε=αsin(2πP t )-αsin(2πP t-1 ) Where ΔP t The frequency adjustment word K at the current time t t The theoretical phase change under s,t is the current sampling clock frequency; ε is the nonlinear compensation error, P t Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t; f s,t+1 is the adjusted sampling clock frequency, and ρ is the clock adjustment coefficient.

9. The composite analog signal generation system based on direct digital synthesis according to claim 1, characterized in that: The DAC digital-to-analog conversion module receives the digital waveform signal output by the waveform modulation module through multiple JESD204B interfaces; each JESD204B interface is sequentially connected to a time synchronization unit and a DAC channel unit; Each of the time synchronization units is used to compensate for the data transmission delay of the channel in which it is located by adding a timestamp and a forward feedback mechanism; Each of the DAC channel units is used to convert a digital waveform signal received by the channel where it is located into a composite analog signal.

10. The composite analog signal generation system based on direct digital synthesis according to claim 9, characterized in that: The method of compensating the data transmission delay of the channel by adding a timestamp and a forward feedback mechanism includes: Calculate the time compensation delay value Δt of each channel separately comp , and based on the Δt of each channel comp Adjust the timestamp of the waveform data in each corresponding channel respectively so that the data of each channel can be aligned, thereby achieving synchronous output of multi-channel signals; among them, the time compensation delay value Δt comp The calculation formula is as follows: Δt comp =Δt+k p ·e -t / τ Where Δt represents the transmission time difference of the data packet from the sender to the receiver of each channel, k p is the proportional coefficient, and τ is the time constant.

11. The composite analog signal generation system based on direct digital synthesis according to claim 3, characterized in that The phase accumulator module, waveform amplitude calculation module, waveform modulation module and clock adaptive adjustment module are integrated into the FPGA platform, and the modulation parameter optimization module is integrated into the CPU platform; The FPGA platform is responsible for data processing of phase accumulation, waveform amplitude calculation, pulse width modulation, frequency modulation, amplitude modulation and updating sampling clock frequency; the CPU platform is responsible for data processing of optimizing waveform modulation parameters based on Q-learning algorithm of reinforcement learning.

12. A composite analog signal generation method based on direct digital synthesis, using the composite analog signal generation system based on direct digital synthesis according to any one of claims 1 to 11, characterized in that: The method comprises the following steps: The calculation parameters and waveform characteristic functions are preset and transmitted by the host computer. The phase accumulator module generates a continuous waveform phase sequence through a nonlinear phase accumulation algorithm according to the calculation parameters transmitted by the host computer; The waveform amplitude calculation module receives the phase sequence output by the phase accumulator module, and calculates the amplitude of each sampling point in combination with the preset waveform characteristic function to generate waveform data; The waveform modulation module is used to modulate and optimize the waveform data output by the waveform amplitude calculation module based on the current waveform modulation parameters, and the modulated waveform data are seamlessly spliced ​​and superimposed to generate a digital waveform signal; The digital waveform signal output by the waveform modulation module is converted into a composite analog signal through the DAC digital-to-analog conversion module.

13. The method for generating a composite analog signal based on direct digital synthesis according to claim 12, wherein: The method further comprises: The waveform modulation parameters are optimized by the modulation parameter optimization module using the Q-learning algorithm of reinforcement learning to compensate for the nonlinear error generated by the waveform, and the optimized waveform modulation parameters are fed back to the waveform modulation module.

14. The method for generating a composite analog signal based on direct digital synthesis according to claim 13, wherein: The calculation parameter includes a sampling clock frequency, and the method further includes: The clock adaptive module is used to dynamically adjust the sampling clock frequency by judging the phase overflow error.

15. The method for generating a composite analog signal based on direct digital synthesis according to claim 12, wherein: The calculation parameters also include: an initial phase value P0, a bit width N, a frequency adjustment word K, and a target waveform frequency f0.

16. The method for generating a composite analog signal based on direct digital synthesis according to claim 15, wherein: The expression for generating a continuous waveform phase sequence by the nonlinear phase accumulation algorithm is as follows: P=(P1,P2,···,P n ) P t =P t-1 +K t +αsin(2πP t-1 ),t=1.2···n Where P represents the waveform phase sequence, P t Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t, K t is the frequency adjustment word updated at the current time t, α is the first compensation coefficient set, sin(2πP t-1 ) is the introduced nonlinear mapping function, the phase value P0 at the initial moment is the preset value, and n represents the total number of time steps.

17. The method for generating a composite analog signal based on direct digital synthesis according to claim 16, wherein: Frequency adjustment word K t The update formula is as follows: Where K t-Δt is the frequency adjustment word at Δt time intervals before the current time t, β is the set second compensation coefficient; Δ f It represents the deviation value after dynamic frequency modulation or the deviation value between the actual output frequency f and the target waveform frequency f0; Δt is the time interval from the occurrence of frequency deviation to the current moment; the updated K t Send it to the phase accumulator module to replace the original frequency adjustment word K t-Δt ; Among them, the frequency adjustment word K0 at the initial moment is calculated by the following formula: Where N is the bit width, f s is the sampling clock frequency, and f0 is the target waveform frequency.

18. The method for generating a composite analog signal based on direct digital synthesis according to claim 13, wherein: The state space s, action space a, and reward function r when optimizing waveform modulation parameters using the reinforcement learning Q-learning algorithm are defined as follows: The state space s is the waveform output state characteristics measured in real time in each cycle, including the distortion value THD and amplitude deviation of the current harmonic; Action space a is for adjusting the modulation parameters, including changing the increments of pulse width, frequency and amplitude modulation parameters; The reward function r is: r=-((∑(V target -V out ) 2 )+λ·THD) Where V target Indicates the amplitude of the target waveform signal, V out It represents the actual output waveform signal amplitude under the current modulation parameters, λ is the weighting factor, and THD represents the current harmonic distortion value.

19. The method for generating a composite analog signal based on direct digital synthesis according to claim 14, wherein: The calculation formula for dynamically adjusting the sampling clock frequency is as follows: f s,t+1 =f s,t ·(1+ρ·ΔP t ) ε=αsin(2πP t )-αsin(2πP t-1 ) Where ΔP t The frequency adjustment word K at the current time t t The theoretical phase change under s,t is the current sampling clock frequency; ε is the nonlinear compensation error, P t Indicates the waveform phase value at the current time t, P t-1 Indicates the waveform phase value of the previous time step at the current time t; f s,t+1 is the adjusted sampling clock frequency, and ρ is the clock adjustment coefficient.

20. The method for generating a composite analog signal based on direct digital synthesis according to claim 12, wherein: The DAC digital-to-analog conversion module receives the digital waveform signal output by the waveform modulation module through multiple JESD204B interfaces; each JESD204B interface is sequentially connected to a time synchronization unit and a DAC channel unit; Each of the time synchronization units is used to compensate for the data transmission delay of the channel in which it is located by adding a timestamp and a forward feedback mechanism; Each of the DAC channel units is used to convert a digital waveform signal received by the channel where it is located into a composite analog signal.

21. The method for generating a composite analog signal based on direct digital synthesis according to claim 20, characterized in that: The method of compensating the data transmission delay of the channel by adding a timestamp and a forward feedback mechanism includes: Calculate the time compensation delay value Δt of each channel separately comp , and based on the Δt of each channel comp Adjust the timestamp of the waveform data in each corresponding channel respectively so that the data of each channel can be aligned, thereby achieving synchronous output of multi-channel signals; among them, the time compensation delay value Δt comp The calculation formula is as follows: Δt comp =Δt+k p ·e -t / τ Where Δt represents the transmission time difference of the data packet from the sender to the receiver of each channel, k p is the proportional coefficient, and τ is the time constant.

22. The method for generating a composite analog signal based on direct digital synthesis according to claim 14, wherein: The phase accumulator module, waveform amplitude calculation module, waveform modulation module and clock adaptive adjustment module are integrated into the FPGA platform, and the modulation parameter optimization module is integrated into the CPU platform; The FPGA platform is responsible for data processing such as phase accumulation, waveform amplitude calculation, pulse width modulation, frequency modulation, amplitude modulation, and updating the sampling clock frequency; The CPU platform is responsible for data processing based on the Q-learning algorithm to optimize waveform modulation parameters.

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