Gated receiver and gated signal generator

Abstract

The invention provides a gated receiver and a gated signal generator. The receiver circuit includes a gated signal generator that receives first and second input signals and a reference voltage to output a gated signal, where the adaptive reference voltage is generated from the first and second input signals and the reference voltage; and a receiver receiving the first and second input signals and the gating signal to provide a receiver output signal. The gating signal deactivates the receiver in response to both the first input signal and the second input signal being higher than the adaptive reference voltage and activates the receiver in response to one of the first input signal and the second input signal being lower than the adaptive reference voltage.

Description

Technical Field

[0001] The present invention relates to a control method for a memory device, and more particularly to a gated receiver and a gated signal generator. Background Art

[0002] In a memory system compatible with the DDR5 specification, data processing requires differential data select signals DQS_t / DQS_c. In the memory system, the data processing process must transmit the data select signal DQS_t / DQS_c to the DQS receiver of the memory system. According to the specifications defined by JEDEC, the data select signal DQS_t / DQS_c can be in a pause period (pause mode) after and before the write operation. During this pause period, both the data select signal DQS_t / DQS_c are pulled up to the power supply voltage VDD. However, at this time, the DQS receiver is still working, and the data select signal DQS_t / DQS_c will be regarded as an input with a 0 volt swing. In this case, an unknown output of the DQS receiver occurs, and the DQS receiver is easily subject to noise interference. The DQS receiver can use this noise interference as an input signal, and anomalies can occur in the DQS receiver.

[0003] However, the DQS receiver must support various inputs, such as Figure 1A The large swing data strobe signal DQS_t / DQS_c and Figure 1B The small swing data strobe signals DQS_t / DQS_c in the CMOS are filtered. Therefore, the input of the strobe signals DQS_t / DQS_c with small swing cannot be directly filtered. For example, the noise attributed to the input with large swing may be a normal input with small swing, rather than noise.

[0004] Therefore, there is a problem of distinguishing the small-swing data strobe signal DQS_t / DQS from noise and making the DQS receiver operate correctly. Summary of the Invention

[0005] As described above, according to one embodiment of the present invention, a gated receiver circuit is provided. The gated receiver circuit includes: a gate signal generator configured to receive a first input signal, a second input signal, and a first reference voltage, and output a gate signal based on the first input signal, the second input signal, and an adaptive reference voltage, wherein the adaptive reference voltage is generated by the first input signal, the second input signal, and the first reference voltage, wherein the first input signal and the second input signal are connected to a power supply voltage; and a receiver configured to receive the first input signal, the second input signal, and the gate signal, and provide a receiver output signal. In response to the first input signal and the second input signal both being greater than the adaptive reference voltage, the receiver is disabled.

[0006] According to another embodiment of the present invention, a gating signal generator is provided. The gating signal generator includes: an adaptive reference voltage generator that receives a first input signal, a second input signal, and a first reference voltage, and generates an adaptive reference voltage based on the first input signal, the second input signal, and the first reference voltage; and a comparator circuit that receives the first input signal, the second input signal, and the adaptive reference voltage, and generates a gating signal. In response to both the first input signal and the second input signal being higher than the adaptive reference voltage, the gating signal generator outputs the gating signal as a disable signal. In response to one of the first input signal and the second input signal being lower than the adaptive reference voltage, the gating signal generator outputs the gating signal as an enable signal.

[0007] According to one embodiment of the present invention, in a gated receiver circuit or a gated signal generator, the gated signal generator further includes: an adaptive reference voltage generator, which receives a first input signal, a second input signal, and a first reference voltage, and generates an adaptive reference voltage based on the first input signal, the second input signal, and the first reference voltage; and a comparator circuit, which receives the first input signal, the second input signal, and the adaptive reference voltage, and generates a gating signal to enable or disable the receiver.

[0008] According to one embodiment of the present invention, in a gated receiver circuit or a gated signal generator, the adaptive reference voltage generator further includes: a minimum value circuit, which receives a first input signal, a second input signal, and a first reference voltage, and outputs a minimum value of the first input signal, the second input signal, and the first reference voltage; a negative peak detector, which is configured to detect a negative peak of the minimum value and output a voltage; and a voltage divider, which is coupled between a power supply voltage and a voltage and is configured to divide the voltage to output an adaptive reference voltage.

[0009] According to one embodiment of the present invention, in a gated receiver circuit or a gated signal generator, the comparator circuit further includes: a first comparator receiving a first input signal and an adaptive reference voltage; a second comparator receiving a second input signal and an adaptive reference voltage; and a logic circuit receiving an output of the first comparator and an output of the second comparator and outputting a gated signal through a logical operation of the outputs of the first comparator and the second comparator. According to one embodiment of the present invention, in the gated receiver circuit, the logic circuit includes an AND gate.

[0010] According to one embodiment of the present invention, in a gated receiver circuit or a gated signal generator, the adaptive reference voltage generator further includes: a first resistor having a first end coupled to a first input signal and a second end coupled to a connection node; a second resistor having a first end coupled to a second input signal and a second end coupled to the connection node; a minimum value circuit receiving a reference voltage and a common-mode voltage at the connection node, and outputting a minimum value of the common-mode voltage and the first reference voltage; a negative peak detector configured to detect a negative peak of the minimum value and output a voltage; and a voltage divider coupled between a power supply voltage and a voltage and configured to divide the voltage to output an adaptive reference voltage.

[0011] According to one embodiment of the present invention, in a gated receiver circuit or a gated signal generator, the comparator circuit further includes: a first comparator receiving a first input signal and an adaptive reference voltage; a second comparator receiving a second input signal and an adaptive reference voltage; and a logic circuit receiving an output of the first comparator and an output of the second comparator and outputting a gated signal through a logical operation of the outputs of the first comparator and the second comparator. According to one embodiment of the present invention, in the gated receiver circuit, the logic circuit includes an AND gate.

[0012] According to one embodiment of the present invention, in a gated receiver circuit or a gated signal generator, the adaptive reference voltage generator further includes: a first resistor having a first end coupled to a first input signal and a second end coupled to a connection node; a second resistor having a first end coupled to a second input signal and a second end coupled to the connection node; a minimum circuit receiving the first reference voltage and a common-mode voltage at the connection node, and outputting a minimum value of the common-mode voltage and the first reference voltage; a negative peak detector configured to detect a negative peak of the minimum value and output a voltage; and a first voltage divider configured to divide the voltage to output an adaptive reference voltage; and a second voltage divider coupled between the power supply voltage and the connection node and generating a second reference voltage.

[0013] According to one embodiment of the present invention, in the gated receiver circuit or the gated signal generator, the adaptive reference voltage generator further includes a capacitor having a first end coupled to the power supply voltage and a second end coupled to the connection node.

[0014] According to one embodiment of the present invention, in a gated receiver circuit or a gated signal generator, the comparator circuit further includes: a first minimum value circuit, which receives a first input signal and a second input signal, and outputs a first minimum value of the first input signal and the second input signal; a second minimum value circuit, which receives a second reference voltage and an adaptive reference voltage, and outputs a second minimum value of the second reference voltage and the second adaptive reference voltage; and a comparator, which is configured to compare the first minimum value with the second minimum value to output a gated signal.

[0015] According to one embodiment of the present invention, in a gated receiver circuit or a gated signal generator, in response to both a first input signal and a second input signal being higher than an adaptive reference voltage and a second reference voltage, the gated signal is disabled, and in response to one of the first input signal and the second input signal being lower than the adaptive reference voltage and the second reference voltage, the gated signal is enabled.

[0016] According to one embodiment of the present invention, in a gated receiver circuit or a gated signal generator, the adaptive reference voltage is lower than the highest voltage of the first input signal and the second input signal, and higher than the lowest voltage of the second reference voltage.

[0017] According to one embodiment of the present invention, in a gated receiver circuit or a gating signal generator, the gated receiver circuit is a data strobe signal receiver of a memory device.

[0018] According to one embodiment of the present invention, in a gated receiver circuit or a gated signal generator, the first input signal and the second input signal are a pair of differential data strobe signals.

[0019] According to one embodiment of the present invention, in the gated receiver circuit or the gating signal generator, the memory device is a DRAM.

[0020] In order to make the foregoing content more easily understood, several embodiments are described in detail below with accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the embodiments, serve to explain the principles of the present invention.

[0022] Figure 1A and Figure 1B shows the waveforms of differential data strobe signals with large swing and small swing;

[0023] Figure 2 A gated receiver circuit according to an embodiment of the present invention is shown;

[0024] Figure 3 Shown Figure 2 A waveform diagram illustrating the operation of a gated receiver circuit having a gate signal generator;

[0025] Figure 4 A gating signal generator of a gated receiver circuit according to another embodiment of the present invention is shown;

[0026] Figure 5 A gating signal generator of a gated receiver circuit according to another embodiment of the present invention is shown;

[0027] Figure 6A 、 Figure 6B and Figure 6C Shown to explain Figure 5 Waveform diagram showing the effect of the capacitor on the adaptive reference voltage generator;

[0028] Figure 7 and Figure 8 Shown with Figure 5 A timing diagram of the operation of the gated receiver circuit of the gating signal generator;

[0029] Figure 9 is a flow chart illustrating a method for receiving a data strobe signal in a memory device according to one embodiment of the present invention;

[0030] Figure 10 is a flowchart illustrating a method for receiving a data strobe signal in a memory device according to another embodiment of the present invention.

[0031] Explanation of Figure Numbers

[0032] 40: First initial VDD state

[0033] 42: First switching area

[0034] 44: Second intermediate VDD state

[0035] 46: Second switching area

[0036] 48: Final VDD status

[0037] 50: Interference

[0038] 100: Gated Receiver Circuit

[0039] 110, 210, 310: Gate signal generator

[0040] 112, 212, 312: Adaptive reference voltage generator

[0041] 112A, 212A, 312A: Minimum circuit

[0042] 112B, 212B, 312B: Negative peak detector

[0043] 112C, 212C, 312C: Voltage divider

[0044] 114, 214, 314: Comparator circuits

[0045] 114A: First comparator

[0046] 114B: Second comparator

[0047] 114C: Logic Circuits

[0048] 120: Receiver

[0049] 314A: First Minimum Circuit

[0050] 314B: Second minimum circuit

[0051] 314C: Comparator

[0052] 314D: Second voltage divider

[0053] C: Capacitor

[0054] DQS_c, DQS_t: Differential data strobe signal

[0055] Gs: gating signal

[0056] IN1: First input signal

[0057] IN2: Second input signal

[0058] MIN: minimum value

[0059] MIN1: First minimum value

[0060] MIN2: Second minimum value

[0061] N1, N2: connection nodes

[0062] OUT: output signal

[0063] R1: first resistor;

[0064] R2: Second resistor

[0065] VDD: power supply voltage

[0066] Vicm: common mode voltage

[0067] Vicm_min: minimum common mode voltage

[0068] VIL: voltage

[0069] Vref, Vref1, Vref2: reference voltage

[0070] Vref_A: adaptive reference voltage DETAILED DESCRIPTION

[0071] Figure 2 FIG. 1 shows a gated receiver circuit according to an embodiment of the present invention. Figure 2In the embodiment, the gated receiver circuit 100 includes a gating signal generator 110 and a receiver 120. The gating signal generator 110 is configured to receive a first input signal IN1, a second input signal IN2, and a reference voltage Vref, and then output a gating signal Gs accordingly. In addition, the receiver 120 is configured to receive a first input signal IN1, a second input signal IN2, and a gating signal, and then output an output signal OUT.

[0072] In one example, the gated receiver circuit 100 can be applied to a memory device, such as a DRAM. The DRAM can be compatible with the DDR5 specification. When the gated receiver circuit 100 is applied to a DRAM that complies with the DDR5 specification, the first input signal IN1 and the second input signal IN2 are a pair of differential data strobe signals DQS_t and DQS_c, respectively.

[0073] Gating signal generator 110 can be referred to as a detector connected to VDD and further includes an adaptive reference voltage generator 112 and a comparator circuit 114. Adaptive reference voltage generator 112 is configured to receive a first input signal IN1, a second input signal IN2, and a reference voltage Vref, and output an adaptive reference voltage Vref_A. Adaptive reference voltage Vref_A is provided to comparator circuit 114. Comparator circuit 114 is configured to receive a first input signal IN1, a second input signal IN2, and the adaptive reference voltage Vref_A, and output a gating signal Gs. In one example, reference voltage Vref can be an internal or external reference voltage used for initial conditions. Reference voltage Vref can be used to limit the maximum value of adaptive reference voltage Vref_A.

[0074] Adaptive reference voltage generator 112 includes a minimum circuit 112A, a negative peak detector 112B, and a voltage divider 112C. Minimum circuit 112A receives a first input signal IN1, a second input signal IN2, and a reference voltage Vref, and outputs a minimum value MIN among the first input signal IN1, the second input signal IN2, and the reference voltage Vref to negative peak detector 112B.

[0075] The negative peak detector 112B is configured to detect the negative peak of the minimum value MIN and output the voltage VIL. Figure 3As shown in FIG, initially, the first input signal IN1 and the second input signal IN2 are connected to the power supply voltage VDD, and then the first input signal IN1 begins to fall to a low level, and the negative peak detector 112B detects this low level of the first input signal IN1 and outputs it as the voltage VIL. Then, as time passes, the first input signal IN1 begins to rise to a high level, while the second input signal IN2 falls to a low level, and similarly, the negative peak detector 112B detects this low level of the second input signal IN2 and outputs it as the voltage VIL. In addition, the voltage can be set within a range from the lowest value of the first input signal IN1 and the second input signal IN2 to the ground voltage (e.g., 0 volts).

[0076] Next, voltage VIL is provided to voltage divider 112C. For example, voltage divider 112C may be configured by connecting multiple resistors in series. In one embodiment, voltage divider 112C is connected between power supply voltage VDD and voltage VIL. Others may use one of the connection nodes between any two resistors as an output node to output adaptive reference voltage Vref_A. The voltage obtained by dividing the voltage drop between power supply voltage VDD and voltage VIL can be set as adaptive reference voltage Vref_A. The generated adaptive reference voltage Vref_A is then output to comparator circuit 114.

[0077] Comparator circuit 114 includes a first comparator 114A, a second comparator 114B, and a logic circuit 114C. In one example, the positive input of first comparator 114A receives a first input signal IN1, and the negative input of first comparator 114A receives an adaptive reference voltage Vref_A. Similarly, the positive input of second comparator 114B receives a second input signal IN2, and the negative input of second comparator 114B receives the adaptive reference voltage Vref_A. Logic circuit 114C is configured to receive the output of first comparator 114A and the output of second comparator 114B, and then output a gate signal Gs through a logical operation. When both first input signal IN1 and second input signal IN2 are greater than adaptive reference voltage Vref_A, the gate signal Gs becomes low. In one example, logic circuit 114C can be implemented using an AND gate or other similar equivalent logic combination.

[0078] When the gating signal Gs becomes low, the receiver 120 is disabled and blocks the first input signal IN1 and the second input signal IN2 received by the receiver 120. In addition, when the gating signal Gs becomes high and enables the receiver, the first input signal IN1 and the second input signal IN2 received by the receiver 120 pass through the receiver 120 as the receiver output signal OUT.

[0079] Figure 3 Shown Figure 2 1 shows a timing diagram of the operation of a gated receiver circuit with a gating signal generator. As shown, the first input signal IN1 and the second input signal IN2 are connected to VDD. When the first input signal IN1 goes low, the adaptive reference voltage Vref_A drops to a level below VDD. In this case, when one of the first input signal IN1 and the second input signal IN2 falls below the adaptive reference voltage Vref_A, the gating signal Gs generated by the gating signal generator 110 goes high. When the gating signal Gs is high, the receiver 120 is enabled and operates normally, and thus the received first input signal IN1 and the second input signal IN2 pass through the receiver 120.

[0080] Furthermore, when noise is present in the first input signal IN1 and the second input signal IN2, and then if both the first input signal IN1 and the second input signal IN2 are higher than the adaptive reference voltage Vref_A, the noise can be properly filtered. In this case, the gating signal Gs generated by the gating signal generator 110 becomes low. When the gating signal Gs is low, the receiver 120 is disabled and its operation is stopped, and thus the received first input signal IN1 and the second input signal IN2 do not pass through the receiver 120. That is, when the gating signal generator 110 detects the presence of noise, the receiver does not operate and will maintain the previous state. Therefore, the receiver circuit 100 can operate normally without being affected by noise and erroneous operation.

[0081] Figure 4 A gating signal generator of a gated receiver circuit according to another embodiment of the present invention is shown. Figure 4 The gate signal generator 210 in Figure 3 The gating signal generator 110 in FIG. 1 is basically the same, but the difference lies in the adaptive reference voltage generator.

[0082] Gating signal generator 210, which can also be referred to as a detector connected to VDD, also includes an adaptive reference voltage generator 212 and a comparator circuit 214. Adaptive reference voltage generator 212 is configured to receive a first input signal IN1, a second input signal IN2, and a reference voltage Vref, and output an adaptive reference voltage Vref_A. Adaptive reference voltage Vref_A is provided to comparator circuit 214. Comparator circuit 214 is configured to receive signal IN1, a second input signal IN2, and the adaptive reference voltage Vref_A, and output a gating signal Gs. In one example, reference voltage Vref can be an internal or external reference voltage used for initial conditions. Reference voltage Vref can be used to limit the maximum value of adaptive reference voltage Vref_A. Figure 4 The comparator circuit 214 in Figure 3 The comparator circuit 114 in FIG. 1 is the same as that in FIG. 1 , and thus the related description is omitted. In the following, only the adaptive reference voltage generator 212 is described.

[0083] exist Figure 4 In the embodiment, the adaptive reference voltage generator 212 includes a first resistor R1, a second resistor R2, a minimum value circuit 212A, a negative peak detector 212B, and a voltage divider 212C. The first resistor R1 has a first end coupled to the first input signal IN1 and a second end coupled to the connection node N1. The second resistor R2 has a first end coupled to the second input signal IN2 and a second end coupled to the connection node N1. In this manner, the first resistor R1 and the second resistor R2 are connected in series. In one example, the resistance of the first resistor R1 and the second resistor R2 can be the same, and the common mode voltage Vicm at the connection node N1 is half the voltage difference between the voltage levels of the first input signal IN1 and the second input signal IN2. In another example, the resistance of the first resistor R1 and the second resistor R2 can be different from each other.

[0084] The minimum value circuit 212A receives the common mode voltage Vicm and the reference voltage Vref, and outputs a minimum value MIN of the common mode voltage Vicm and the reference voltage Vref to the negative peak detector 212B.

[0085] The negative peak detector 212B is configured to detect the negative peak of the minimum value MIN and output the minimum common mode voltage Vicm_min. Figure 3 As shown in FIG, initially, the first input signal IN1 and the second input signal IN2 are connected to the power supply voltage VDD, and then the first input signal IN1 begins to fall to a low level, and the negative peak detector 212B detects this low level of the first input signal IN1 and outputs it as the minimum common-mode voltage Vicm_min. Then, as time passes, the first input signal IN1 begins to rise to a high level, while the second input signal IN2 falls to a low level, and similarly, the negative peak detector 212B detects this low level of the second input signal IN2 and outputs it as the minimum common-mode voltage Vicm_min.

[0086] Next, the minimum common-mode voltage Vicm_min is provided to the voltage divider 212C. For example, the voltage divider 212C may be a configuration in which a plurality of resistors are connected in series. In one example, the voltage divider 212C is connected between the power supply voltage VDD and the minimum common-mode voltage Vicm_min. One can use one of the connection nodes of any two of the resistors as an output node to output the adaptive reference voltage Vref_A. The voltage obtained by dividing the voltage drop between the power supply voltage VDD and the minimum common-mode voltage Vicm_min can be set as the adaptive reference voltage Vref_A. Then, the generated adaptive reference voltage Vref_A is output to the comparator circuit 214. The operation of the comparator circuit 214 can refer to Figure 2 The comparator circuit 214 outputs a gating signal Gs which is further provided to the receiver 120.

[0087] Corresponding to Figure 4 The waveform diagram of the operation of the gated receiver circuit with the gate signal generator can be referred to Figure 3 , but the voltage VIL is replaced by the minimum common-mode voltage Vicm_min. Basically, Figure 2 and Figure 4 The operation of the gate signal generator is the same as that of the

[0088] Figure 5 A gating signal generator for a gated receiver circuit according to another embodiment of the present invention is shown. Gating signal generator 310, which may also be referred to as a detector connected to VDD, further includes an adaptive reference voltage generator 312 and a comparator circuit 314. Adaptive reference voltage generator 312 is configured to receive a first input signal IN1, a second input signal IN2, and a reference voltage (first reference voltage) Vref1, and output an adaptive reference voltage Vref_A. Adaptive reference voltage Vref_A is provided to comparator circuit 314. Comparator circuit 314 is configured to receive a first input signal IN1, a second input signal IN2, the adaptive reference voltage Vref_A, and an active reference voltage (second reference voltage) Vref2, and output a gating signal Gs. In one example, reference voltage Vref1 may be an internal or external reference voltage used for initial conditions of a memory device. Reference voltage Vref1 may be used to limit the maximum value of adaptive reference voltage Vref_A.

[0089] Adaptive reference voltage generator 312 includes a first resistor R1, a second resistor R2, a minimum value circuit 312A, a negative peak detector 312B, a first voltage divider 312C, a second voltage divider 314D, and a capacitor C. First resistor R1 has a first end coupled to first input signal IN1 and a second end coupled to connection node N2. Second resistor R2 has a first end coupled to second input signal IN2 and a second end coupled to connection node N2. In this manner, first resistor R1 and second resistor R2 are connected in series. In one example, the resistances of first resistor R1 and second resistor R2 may be the same, and the common-mode voltage Vicm at connection node N2 is half the voltage difference between the voltage levels of first input signal IN1 and second input signal IN2. In another example, the resistances of first resistor R1 and second resistor R2 may be different.

[0090] The minimum value circuit 312A receives the common mode voltage Vicm at the connection node N2 and the first reference voltage Vref1 , and outputs a minimum value MIN of the common mode voltage Vicm and the first reference voltage Vref1 to the negative peak detector 312B.

[0091] The negative peak detector 312B is configured to detect the negative peak of the minimum value MIN and output the minimum common mode voltage Vicm_min. Figure 6A 、 Figure 6B and Figure 6C As shown in FIG, initially, the first input signal IN1 and the second input signal IN2 are connected to the power supply voltage VDD, and then the first input signal IN1 begins to fall to a low level, and the negative peak detector 312B detects this low level of the first input signal IN1 and outputs it as the minimum common-mode voltage Vicm_min. Then, as time passes, the first input signal IN1 begins to rise to a high level, while the second input signal IN2 falls to a low level, and similarly, the negative peak detector 312B detects this low level of the second input signal IN2 and outputs it as the minimum common-mode voltage Vicm_min.

[0092] Next, the minimum common-mode voltage Vicm_min is provided to the first voltage divider 312C. For example, the first voltage divider 312C may be configured by connecting multiple resistors in series. One of the connection nodes between any two of the resistors may serve as an output node for outputting the adaptive reference voltage Vref_A. The voltage obtained by dividing the voltage drop between the power supply voltage VDD and the minimum common-mode voltage Vicm_min may be set as the adaptive reference voltage Vref_A. The generated adaptive reference voltage Vref_A is then output to the comparator circuit 314.

[0093] The second voltage divider 314D is connected between the power supply voltage VDD and the connection node N2 and operates to output a second reference voltage Vref2. The second reference voltage Vref2 is an active reference voltage. Similar to the first voltage divider 312C, the first voltage divider 312C can be configured by connecting multiple resistors in series. One of the connection nodes of any two of the resistors can be used as an output node to output the second reference voltage Vref2. The voltage obtained by dividing the voltage drop between the power supply voltage VDD and the common-mode voltage Vicm can be set as the second reference voltage Vref2. The generated active reference voltage Vref2 is then output to the comparator circuit 314.

[0094] Furthermore, generally, the voltage range of the active reference voltage Vref2 is set to be close to the midpoint between the first input signal IN1 and the second input signal IN2. The adaptive reference voltage Vref_A is lower than the highest voltage of the first input signal IN1 and the second input signal IN2 (in pause mode) and higher than the lowest voltage of the active reference voltage Vref2. Furthermore, the minimum common-mode voltage Vicm_min can be the lowest value of the adaptive reference voltage Vref_A. In one example, the common-mode voltage Vicm can be set within a range from the lowest voltage of the active reference voltage Vref2 to the highest voltage of the first input signal IN1 and the second input signal IN2 (in pause mode). In another example, the common-mode voltage Vicm can be set within a range from 0.5*VDD to VDD. These voltage ranges can be selected or set as required.

[0095] The capacitor C has a first terminal coupled to the power supply voltage VDD and a second terminal coupled to the connection node N2. The capacitor C is provided at the connection node N2; that is, the second terminal of the capacitor C is coupled to the common mode voltage Vicm. Due to this capacitor C, the timing of generating the active reference voltage Vref2 can be delayed. Figures 6A to 6C Describe the effects of a capacitor.

[0096] Figure 6A Shown Figure 5 A timing diagram of the operation of a gated receiver circuit with a gating signal generator. Figure 6B depiction Figure 6A , which shows that the adaptive reference voltage generator 310 is configured without a capacitor, and Figure 6C depiction Figure 6A FIG. 1 is an enlarged portion of FIG. 3 , which shows that the adaptive reference voltage generator 310 is configured with a capacitor. Figure 6B As shown in Figure 5If the capacitor C in the circuit is not provided at the connection node N2, the transition state of the active reference voltage Vref2 is not delayed. Therefore, the transition state of the active reference voltage Vref2 is completely consistent with the transition state of the first input signal IN1 and the second reference signal IN2. Therefore, the low level state of the gate control signal Gs cannot be confirmed early. In addition, Figure 5 When capacitor C is provided at connection node N2, the transition of active reference voltage Vref2 is delayed. Therefore, the transition of active reference voltage Vref2 is separated from the transitions of first input signal IN1 and second reference signal IN2. Therefore, the low level state of gate control signal Gs can be confirmed early.

[0097] Comparator circuit 314 includes a first minimum circuit 314A, a second minimum circuit 314B, and a comparator 314C. First minimum circuit 314A is configured to receive a first input signal IN1 and a second input signal IN2 and output a first minimum value MIN1 of the first input signal IN1 and the second input signal IN2. Furthermore, second minimum circuit 314B is configured to receive an adaptive reference voltage Vref_A and an active reference voltage Vref2 and output a second minimum value MIN2 of the adaptive reference voltage Vref_A and the active reference voltage Vref2.

[0098] The comparator 314C is configured to receive the first minimum value MIN1 and the second minimum value MIN2, and then output a gating signal Gs based on the comparison result. The gating signal Gs is further provided to the receiver 120. Figure 6A 、 Figure 6B and Figure 6C As shown in FIG, when the gating signal Gs becomes a low level, the receiver 120 is disabled, thereby blocking the first input signal IN1 and the second input signal IN2 received by the receiver 120. In addition, when the gating signal Gs becomes a high level, the receiver 120 is enabled, thereby allowing the first input signal IN1 and the second input signal IN2 received by the receiver 120 to pass through the receiver 120 as the receiver output signal OUT.

[0099] Figure 7 The following diagram shows the process of performing a memory operation between the controller and the memory without interference (noise) during the VDD state (both IN1 and IN2 are connected to VDD period). Figure 5 FIG1 is a timing diagram illustrating the operation of a gated receiver circuit with a gated signal generator. The timing diagram depicts a first initial VDD state 40, a first switching region 42 comprising four cycles of switching, a second intermediate VDD state 44, a second switching region 46 comprising four cycles of switching, and a final VDD state 48.

[0100] During the first initial VDD state 40, the first and second input signals IN1 and IN2 (e.g., DQS_t and DQS_c) are connected to the power supply voltage VDD. When the voltage levels of the first and second input signals IN1 and IN2 are higher than the adaptive reference voltage Vref_A and the active reference voltage Vref2, the gating signal Gs becomes low. The receiver 120 is then disabled.

[0101] Additionally, when the first input signal IN1 is connected to the power supply voltage VDD and the second input signal IN2 is a switching signal, the voltage level of the second input signal IN2 is lower than the adaptive reference voltage Vref_A and the active reference voltage Vref2, and the gate signal Gs becomes high. When the gate signal Gs becomes high, the receiver 120 is enabled and the first input signal IN1 and the second input signal IN2 received by the receiver 120 are then transmitted to the outside as the receiver output OUT.

[0102] Figure 8 The following diagram shows the process of performing a memory operation between the controller and the memory in the presence of interference (noise) during the VDD state. Figure 5 1. A timing diagram of the operation of a gated receiver circuit with a gate signal generator. During a first initial VDD state 40, in the presence of interference (noise) 50, the first input signal IN1 and the second input signal IN2 (eg, DQS_t and DQS_c) are connected to the supply voltage VDD.

[0103] When the voltage levels of the first and second input signals IN1 and IN2 are higher than the adaptive reference voltage Vref_A and the active reference voltage Vref2, the gating signal Gs becomes low. Receiver 120 is disabled, and interference 50 is transmitted only to the active reference voltage Vref2. Additionally, when the first input signal IN1 is connected to the power supply voltage VDD and the active input signal IN2 is a switching signal, the voltage level of the second input signal IN2 is lower than the adaptive reference voltage Vref_A and the active reference voltage Vref2, and the gating signal becomes high to enable receiver 120. When receiver 120 is enabled by the gating signal Gs, the first and second input signals IN1 and IN2 received by receiver 120 are transmitted externally as receiver output OUT.

[0104] Figure 9 is a flow chart illustrating a method for receiving a data strobe signal in a memory device according to an embodiment of the present invention. Figure 2 or Figure 4 The exemplary hardware configuration shown in FIG.

[0105] In step S100, the gating signal generator 110 or the gating signal generator 210 receives a first input signal IN1, a second input signal IN2, and a reference voltage Vref. The first input signal IN1 and the second input signal IN2 may be a pair of differential data strobe signals used in a memory device (eg, a DRAM memory device).

[0106] In step S102, an adaptive reference voltage Vref_A is generated using the first input signal IN1, the second input signal IN2, and the reference voltage Vref. In one example, the adaptive reference voltage Vref_A can be generated by the operation of the minimum circuit 112A (212A), the negative peak detector 112B (212B), and the voltage divider 112C (212C).

[0107] In step S104 , the first input signal IN1 and the second input signal IN2 are compared with the adaptive reference voltage Vref_A to provide a comparison result. Then, in step S106 , a gating signal Gs is generated based on the comparison result and provided to the receiver 120 .

[0108] In this case, in response to both the first input signal IN1 and the second input signal IN2 being higher than the adaptive reference voltage Vref_A, the gate signal Gs becomes a low level. The receiver 120 is then disabled and stops operating, and the first input signal IN1 and the second input signal IN2 received by the receiver 120 are not output from the receiver 120. Alternatively, in response to one of the first input signal IN1 and the second input signal IN2 being lower than the adaptive reference voltage Vref_A, the gate signal Gs becomes a high level. The receiver 120 is then enabled to operate, and the first input signal IN1 and the second input signal IN2 received by the receiver 120 are output from the receiver 120.

[0109] Figure 10 is a flow chart illustrating a method for receiving a data strobe signal in a memory device according to an embodiment of the present invention. Figure 5 The exemplary hardware configuration shown in FIG.

[0110] In step S200, the gating signal generator 310 receives a first input signal IN1, a second input signal IN2, and a first reference voltage Vref1. The first input signal IN1 and the second input signal IN2 may be a pair of differential data strobe signals used in a memory device (eg, a DRAM memory device).

[0111] In step S202 , an adaptive reference voltage Vref_A is generated by the first reference voltage Vref1 and the common mode voltage Vicm of the first and second input signals IN1 and IN2 . In one example, the adaptive reference voltage Vref_A can be generated by the minimum circuit 312A, the negative peak detector 312B, and the first voltage divider 312C.

[0112] In step S204, an active reference voltage Vref2 is generated by the common mode voltage Vicm. For example, the active reference voltage Vref2 can be obtained by the second voltage divider 314D.

[0113] In step S206 , the first minimum value MIN1 of the first input signal IN1 and the second input signal IN2 is obtained by the first minimum value circuit 314A, and the second minimum value MIN2 of the adaptive reference voltage Vref_A and the active reference voltage Vref2 is obtained by the second minimum value circuit 314B.

[0114] In step S208 , the first minimum value MIN1 is compared with the second minimum value MIN2 to provide a comparison result. Then, in step S208 , a gating signal Gs is generated based on the comparison result and provided to the receiver 120 .

[0115] In this case, in response to both the first input signal IN1 and the second input signal IN2 being higher than the adaptive reference voltage Vref_A and the active reference voltage Vref2, the gate signal Gs becomes a low level. The receiver 120 is then disabled and stops operating, and the first input signal IN1 and the second input signal IN2 received by the receiver 120 are not output from the receiver 120. Alternatively, in response to one of the first input signal IN1 and the second input signal IN2 being lower than the adaptive reference voltage Vref_A and the active reference voltage Vref2, the gate signal Gs becomes a high level. The receiver 120 is then enabled to operate, and the first input signal IN1 and the second input signal IN2 received by the receiver 120 are output from the receiver 120.

[0116] It will be apparent to those skilled in the art that various modifications and variations may be made to the embodiments of the invention without departing from the spirit or scope of the invention. In view of the foregoing, it is intended that the present invention encompasses modifications and variations, provided that the modifications and variations fall within the scope of the appended claims and their equivalents.

Claims

1. A gated receiver circuit comprising: a gating signal generator configured to receive a first input signal, a second input signal, and a first reference voltage, and output a gating signal based on the first input signal, the second input signal, and an adaptive reference voltage, wherein the adaptive reference voltage is generated by the first input signal, the second input signal, and the first reference voltage, wherein the first input signal and the second input signal are connected to a power supply voltage; as well as a receiver configured to receive the first input signal, the second input signal, and the gating signal, and to provide a receiver output signal according to the gating signal, In response to the first input signal and the second input signal both being higher than the adaptive reference voltage, the receiver is disabled by the gating signal.

2. The gated receiver circuit of claim 1 , wherein the gating signal generator further comprises: an adaptive reference voltage generator receiving the first input signal, the second input signal, and the first reference voltage, and generating the adaptive reference voltage based on the first input signal, the second input signal, and the first reference voltage; as well as The comparator circuit receives the first input signal, the second input signal, and the adaptive reference voltage, and generates the gating signal to enable or disable the receiver.

3. The gated receiver circuit of claim 2 , wherein the adaptive reference voltage generator further comprises: a minimum circuit receiving the first input signal, the second input signal, and the first reference voltage, and outputting a minimum value of the first input signal, the second input signal, and the first reference voltage; a negative peak detector configured to detect a negative peak of the minimum value and output a voltage; as well as The voltage divider is coupled between the power supply voltage and the voltage and configured to divide the voltage into two voltages to output the adaptive reference voltage.

4. The gated receiver circuit of claim 3 , wherein the comparator circuit further comprises: a first comparator, receiving the first input signal and the adaptive reference voltage; a second comparator, receiving the second input signal and the adaptive reference voltage; as well as The logic circuit receives the output of the first comparator and the output of the second comparator, and outputs the gating signal through a logic operation of the outputs of the first comparator and the second comparator.

5. The gated receiver circuit of claim 4, wherein the logic circuit comprises an AND gate.

6. The gated receiver circuit of claim 2 , wherein the adaptive reference voltage generator further comprises: a first resistor having a first end coupled to the first input signal and a second end coupled to the connection node; a second resistor having a first end coupled to the second input signal and a second end coupled to the connection node; a minimum value circuit receiving the reference voltage and the common mode voltage at the connection node, and outputting a minimum value of the common mode voltage and the first reference voltage; a negative peak detector configured to detect a negative peak of the minimum value and output a voltage; as well as The voltage divider is coupled between the power supply voltage and the voltage and configured to divide the voltage into two voltages to output the adaptive reference voltage.

7. The gated receiver circuit of claim 6 , wherein the comparator circuit further comprises: a first comparator, receiving the first input signal and the adaptive reference voltage; a second comparator, receiving the second input signal and the adaptive reference voltage; as well as The logic circuit receives the output of the first comparator and the output of the second comparator, and outputs the gating signal through a logic operation of the outputs of the first comparator and the second comparator.

8. The gated receiver circuit of claim 7, wherein the logic circuit comprises an AND gate.

9. The gated receiver circuit of claim 2 , wherein the adaptive reference voltage generator further comprises: a first resistor having a first end coupled to the first input signal and a second end coupled to the connection node; a second resistor having a first end coupled to the second input signal and a second end coupled to the connection node; a minimum value circuit receiving the first reference voltage and the common mode voltage at the connection node, and outputting a minimum value of the common mode voltage and the first reference voltage; a negative peak detector configured to detect a negative peak of the minimum value and output a voltage; a first voltage divider configured to divide the voltage into two voltages to output the adaptive reference voltage; as well as The second voltage divider is coupled between the power supply voltage and the connection node and generates a second reference voltage.

10. The gated receiver circuit of claim 9, wherein the adaptive reference voltage generator further comprises: A capacitor has a first end coupled to the power supply voltage and a second end coupled to the connection node.

11. The gated receiver circuit of claim 9 , wherein the comparator circuit further comprises: a first minimum circuit receiving the first input signal and the second input signal and outputting a first minimum value of the first input signal and the second input signal; a second minimum circuit receiving the second reference voltage and the adaptive reference voltage and outputting a second minimum value of the second reference voltage and the adaptive reference voltage; as well as A comparator is configured to compare the first minimum value with the second minimum value to output the gating signal. 12 . The gated receiver circuit of claim 11 , wherein the gating signal disables the receiver in response to the first input signal and the second input signal both being higher than the adaptive reference voltage and the second reference voltage. 13 . The gated receiver circuit of claim 9 , wherein the adaptive reference voltage is lower than a highest voltage of the first input signal and the second input signal, and higher than a lowest voltage of the second reference voltage.

14. The gated receiver circuit of claim 1, wherein the gated receiver circuit is a data strobe signal receiver of a memory device.

15. The gated receiver circuit of claim 14, wherein the first input signal and the second input signal are a pair of differential data strobe signals.

16. The gated receiver circuit of claim 14, wherein the memory device is a DRAM.

17. A gate signal generator, comprising: an adaptive reference voltage generator receiving a first input signal, a second input signal, and a first reference voltage, and generating an adaptive reference voltage based on the first input signal, the second input signal, and the first reference voltage; as well as a comparator circuit receiving the first input signal, the second input signal, and the adaptive reference voltage, and generating a gating signal, wherein in response to the first input signal and the second input signal both being higher than the adaptive reference voltage, the gating signal generator outputs the gating signal as a disable signal, and In response to one of the first input signal and the second input signal being lower than the adaptive reference voltage, the gating signal generator outputs the gating signal as an enable signal.

18. The gating signal generator according to claim 17, wherein the gating signal generator further comprises: an adaptive reference voltage generator receiving the first input signal, the second input signal, and the first reference voltage, and generating the adaptive reference voltage based on the first input signal, the second input signal, and the first reference voltage; as well as The comparator circuit receives the first input signal, the second input signal, and the adaptive reference voltage, and generates the gate signal.

19. The gating signal generator according to claim 18, wherein the adaptive reference voltage generator further comprises: a minimum circuit receiving the first input signal, the second input signal, and the first reference voltage, and outputting a minimum value of the first input signal, the second input signal, and the first reference voltage; a negative peak detector configured to detect a negative peak of the minimum value and output a voltage; as well as The voltage divider is coupled between a power supply voltage and the voltage and configured to divide the voltage into two voltages to output the adaptive reference voltage.

20. The gating signal generator according to claim 19, wherein the comparator circuit further comprises: a first comparator, receiving the first input signal and the adaptive reference voltage; a second comparator, receiving the second input signal and the adaptive reference voltage; as well as The logic circuit receives the output of the first comparator and the output of the second comparator, and outputs the gating signal through a logic operation of the outputs of the first comparator and the second comparator.

21. The gating signal generator of claim 20, wherein the logic circuit comprises an AND gate.

22. The gating signal generator according to claim 18, wherein the adaptive reference voltage generator further comprises: a first resistor having a first end coupled to the first input signal and a second end coupled to the connection node; a second resistor having a first end coupled to the second input signal and a second end coupled to the connection node; a minimum value circuit receiving the reference voltage and the common mode voltage at the connection node, and outputting a minimum value of the common mode voltage and the first reference voltage; a negative peak detector configured to detect a negative peak of the minimum value and output a voltage; as well as The voltage divider is coupled between a power supply voltage and the voltage and configured to divide the voltage into two voltages to output the adaptive reference voltage.

23. The gating signal generator of claim 22, wherein the comparator circuit further comprises: a first comparator, receiving the first input signal and the adaptive reference voltage; a second comparator, receiving the second input signal and the adaptive reference voltage; as well as The logic circuit receives the output of the first comparator and the output of the second comparator, and outputs the gating signal through a logic operation of the outputs of the first comparator and the second comparator.

24. The gating signal generator of claim 23, wherein the logic circuit comprises an AND gate.

25. The gating signal generator according to claim 18, wherein the adaptive reference voltage generator further comprises: a first resistor having a first end coupled to the first input signal and a second end coupled to the connection node; a second resistor having a first end coupled to the second input signal and a second end coupled to the connection node; a minimum value circuit receiving the first reference voltage and the common mode voltage at the connection node, and outputting a minimum value of the common mode voltage and the first reference voltage; a negative peak detector configured to detect a negative peak of the minimum value and output a voltage; as well as a first voltage divider configured to divide the voltage into two voltages to output the adaptive reference voltage; as well as The second voltage divider is coupled between the power supply voltage and the connection node and generates a second reference voltage.

26. The gating signal generator of claim 25, wherein the adaptive reference voltage generator further comprises: A capacitor has a first end coupled to the power supply voltage and a second end coupled to the connection node.

27. The gating signal generator of claim 25, wherein the comparator circuit further comprises: a first minimum circuit receiving the first input signal and the second input signal and outputting a first minimum value of the first input signal and the second input signal; a second minimum circuit receiving the second reference voltage and the adaptive reference voltage and outputting a second minimum value of the second reference voltage and the adaptive reference voltage; as well as A comparator is configured to compare the first minimum value with the second minimum value to output the gating signal.

28. The gated control signal generator of claim 27, wherein in response to the first input signal and the second input signal being higher than the adaptive reference voltage and the second reference voltage, the gated control signal is a disable signal, and In response to one of the first input signal and the second input signal being lower than the adaptive reference voltage and the second reference voltage, the gating signal is an enable signal. 29 . The gating signal generator according to claim 25 , wherein the adaptive reference voltage is lower than a highest voltage of the first input signal and the second input signal, and higher than a lowest voltage of the second reference voltage.

30. The gating signal generator of claim 17, wherein the gating signal is provided to a receiver of a memory device, wherein the receiver is enabled or disabled by the gating signal to transmit or not transmit the first input signal and the second input signal.

31. The gating signal generator of claim 30, wherein the first input signal and the second input signal are a pair of differential data strobe signals.

32. The gating signal generator of claim 30, wherein the memory device is a DRAM.

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