Digital phased-array antenna automatic test system, method and product

Abstract

The invention discloses an automatic test system, method and product for a digital phased-array antenna in the field of antenna testing, and the system is characterized in that an upper computer is connected with a real-time controller, and sends a pre-programmed test instruction sequence to the real-time controller; the real-time controller is connected with the vector network analyzer and sends an analog signal code to the vector network analyzer; connecting with a wave control computer and sending a wave position code to the wave control computer; the switch matrix is connected with the switch matrix and sends switch codes to the switch matrix; the vector network analyzer is connected with an antenna to be tested through the digital-to-analog conversion card, is connected with the test transceiver module, and is used for sending a source signal and receiving an echo signal; the wave control computer is connected with the to-be-tested antenna and controls the wave beam state of the to-be-tested antenna; the switch matrix is provided with a switch corresponding to each to-be-tested channel of the to-be-tested antenna, and the switches control opening or closing of the to-be-tested channels. According to the invention, the test efficiency of the digital phased-array antenna can be significantly improved.

Description

Technical Field

[0001] The present application relates to the field of antenna testing, and specifically to a digital phased array antenna automated testing system, method, and product. Background Art

[0002] Phased array antennas, with their advantages of flexible and controllable beams and strong anti-interference capabilities, are widely used in satellite communications, 5G base stations, military radar, and other fields. With recent developments, digital phased array antennas, due to their performance advantages, have gradually become a major development direction. Based on the principle of phase superposition, digital phased array antennas electronically control the phase and amplitude of each antenna element in the array through digital signals, enabling rapid beam scanning, shaping, control, and multi-target tracking.

[0003] When testing digital phased array antennas, a large number of channels must be tested because they are composed of an array of channels that can be individually controlled and combined. Furthermore, the test items include various parameters such as amplitude and phase consistency, multiple frequencies, multiple beam states, and multiple wave positions for each channel to ensure antenna performance. This results in an exponential increase in the number of combinations that need to be tested, significantly extending test time and reducing test efficiency. For digital phased array antennas with thousands of channels, testing can take tens of hours. This significantly slows down the design, production, and maintenance of digital phased array antennas, impacting their practical use. Summary of the Invention

[0004] The purpose of this application is to overcome the deficiencies of the prior art and to provide a digital phased array antenna automated testing system, method, and product that can significantly improve the testing efficiency of digital phased array antennas.

[0005] In a first aspect, the present application provides an automated test system for digital phased array antennas, which is used to test antennas under test and adopts the following technical solutions: The test system includes a host computer, a real-time controller, a vector network analyzer, a digital-to-analog conversion card, a wave control computer, a switch matrix, and a test transceiver module; The host computer is connected to the real-time controller and sends a pre-programmed test instruction sequence to the real-time controller; The real-time controller is connected to the vector network analyzer to send analog signal codes to the vector network analyzer; is connected to the wave control computer to send wave position codes to the wave control computer; is connected to the switch matrix to send switch codes to the switch matrix; The vector network analyzer is connected to the antenna to be tested through the digital-to-analog conversion card and is connected to the test transceiver module arranged in the test space. The vector network analyzer sends a source signal to the antenna to be tested or the test transceiver module and receives an echo signal. The beam control computer is connected to the antenna to be tested and controls the beam state of the antenna to be tested; The switch matrix is ​​provided with a switch corresponding to each channel to be tested of the antenna to be tested, and the switch controls the opening or closing of the channel to be tested.

[0006] By adopting the above technical solution, a real-time controller is used to call the control instructions of the host computer, and the real-time controller actually executes the hardware-level control of the vector network analyzer, wave control computer and switch matrix, which can fully utilize the performance of each module, increase the response speed, and avoid the test progress being restricted by the delay of the host computer system; the vector network analyzer is connected to the antenna under test through an external digital-to-analog conversion card, which can adapt to the digital interface of the input and output of the antenna under test, stably realize the closed-loop connection between the analog signal side of the vector network analyzer and the digital signal side of the antenna under test, and can improve the accuracy of digital-to-analog conversion; the switch matrix can realize controllable multi-channel parallel testing of the antenna under test, further improving the test efficiency.

[0007] Preferably, the real-time controller includes a logic control area and a cache area, the logic control area imports a pre-programmed test instruction sequence sent by the host computer to the real-time controller, the cache area stores the source signal emitted by the vector network analyzer and the data of the echo signal obtained, and the host computer regularly obtains the data of the source signal and the echo signal from the cache area.

[0008] Through the above technical solution, the real-time controller is partitioned according to function, so that the logic control and data storage of the real-time controller are isolated from each other and do not affect each other; the data of the source signal and the echo signal of the vector network analyzer are stored in the cache area, so that the data does not need to be transmitted and stored to the host computer in real time, avoiding the time wasted waiting for data to interact with the host computer and slowing down the test progress, thereby reducing the test efficiency; the host computer regularly obtains data in batches from the cache area of ​​the real-time controller. This acquisition process is unrelated to the test process of the antenna to be tested and will not affect the test progress.

[0009] Preferably, the switch matrix time division multiplexing controller is connected to a vector network analyzer.

[0010] Through the above technical solution, the time division switching and high-precision synchronization of multiple test channels of the antenna under test can be achieved within a single test path through the time division multiplexing controller, which can realize multi-channel parallel testing of the test channels and improve test efficiency.

[0011] Preferably, the test transceiver module includes a test probe and a horn antenna.

[0012] The above technical solution can achieve closed-loop signal transmission and reception test paths for the antenna under test. During the transmission test of the antenna under test, the vector network analyzer emits an analog source signal, which is converted to a digital signal by a digital-to-analog converter card and input into the digital terminal of the antenna under test. The antenna under test analyzes the signal to generate an RF signal, which is then received by the test probe and input into the vector network analyzer as an echo signal. During the reception test of the antenna under test, the vector network analyzer emits an analog source signal, which is then input into the horn antenna to generate an RF signal, which is then received by the antenna under test and converted into a digital signal. The digital signal is then converted into an analog signal by the digital-to-analog converter card and input into the vector network analyzer as an echo signal.

[0013] In a second aspect, the present application provides an automated testing method for digital phased array antennas, using the above-mentioned testing system, and the technical solution adopted includes the following steps: The host computer sends a pre-programmed test instruction sequence to the real-time controller; The real-time controller sends control codes to the wave control computer, the switch matrix, and the vector network analyzer in units according to the test instruction sequence and with the test set of the test instruction sequence as a unit. The control codes include the wave position codes sent to the wave control computer, the switch codes sent to the switch matrix, and the analog signal codes sent to the vector network analyzer. The wave control computer adjusts the parameters of the channel to be measured according to the wave position code; The switch matrix turns on the switch according to the switch code, turning on the corresponding channel to be tested; the vector network analyzer sends the source signal to the antenna to be tested or the test transceiver module according to the analog signal code, and then receives the echo signal; The vector network analyzer imports the echo signal and the corresponding source signal into the buffer area of ​​the real-time controller, and then sends a test set completion signal to the real-time controller; After the real-time controller receives the test set completion signal, it sends a control code for the next test set as the object until all test instruction sequences are completed; The host computer periodically obtains the data of the source signal and the echo signal from the buffer area.

[0014] Through the above technical solution, the test instruction sequence is composed of the sequence of each test set, and the control instructions are sent to the wave control computer, switch matrix and vector network analyzer in units of test sets through the real-time controller, thereby realizing the automatic and orderly advancement of the full test process projects of the antenna to be tested, and saving the time of each test process cycle.

[0015] Preferably, for any one of the test sets, it is divided into several time slices by the time division multiplexing controller of the switch matrix, and the number of time slices corresponds to the number of channels to be tested corresponding to the synthetic beam in the test set, or the number of channels to be tested corresponding to the receiving beam.

[0016] Preferably, a time division multiplexing controller is used to control the switch matrix and the vector network analyzer, specifically including: The switch matrix selects the range of channels to be tested according to the switch code; The vector network analyzer sends a source signal to the antenna under test or the test transceiver module according to the analog signal code; The switch matrix uses the time division multiplexing controller to sequentially open the switches of the channels to be tested corresponding to the current time slice and close the switches of other channels to be tested until the channels to be tested corresponding to all time slices of the current test set are opened and closed. The vector network analyzer uses the timestamp of each time slice of the time division multiplexing controller as a label and receives the echo signal corresponding to each channel to be tested one by one.

[0017] Through the above technical solution, the test set is divided into several time slices through the time division multiplexing controller, and each time slice corresponds to a channel to be tested; on the same test path, the parameters of the channels to be tested are set to be the same, the source signals are the same, and multiple channels to be tested share the test path, performing time division multiplexing switching and high-precision synchronization, thereby realizing multi-channel parallel testing of the antenna to be tested and improving test efficiency.

[0018] Preferably, for the channel to be tested under any test set, the vector network analyzer sends source signals with different signal source frequencies and signal source powers in sequence according to the analog signal code, then receives the corresponding echo signals, and imports the echo signals and the corresponding source signals into the cache area of ​​the real-time controller; after completing the sending of all source signals and the receiving of echo signals of the current test set, the vector network analyzer sends a test set completion signal to the real-time controller.

[0019] Through the above technical solution, for any test set, a vector network analyzer is used to switch the parameters of the source signal and test multiple source signals, thereby realizing the reuse of the channels to be tested with predetermined parameters, optimizing the test process, making the test process compact, and improving test efficiency.

[0020] Preferably, when the vector network analyzer sends source signals of different frequencies and powers, a delay protection time is reserved for the antenna to be tested to respond when any source signal is switched.

[0021] Through the above technical solution, a delay protection time is reserved for the source signal when switching. The delay protection time is used to stabilize the beams re-established corresponding to different source signals, reserve time for the transmission path and interface response, and establish clock synchronization between the modules of the system, thereby avoiding data coverage or loss, reduced test accuracy, and reduced system stability.

[0022] In a third aspect, the present application provides a computer program product, which includes a computer program or instructions, so that the computer program or instructions can implement the steps in the above-mentioned digital phased array antenna automatic testing method.

[0023] In summary, this application includes at least one of the following beneficial technical effects: 1. This application uses a real-time controller to call the test instruction sequence of the host computer to control the vector network analyzer, wave control computer and switch matrix. The control signal is based on hardware excitation. Compared with the control of the host computer through the operating system, it can avoid the scheduling delay of the operating system and significantly improve the instruction time accuracy. The operation instruction jitter can be controlled at the order of hundreds of nanoseconds, thereby achieving microsecond-level time synchronization between modules, high control accuracy, and high-speed switching of test parameters, thereby improving test efficiency.

[0024] 2. This application uses a real-time controller to cache the source signal and the echo signal to avoid wasting time and slowing down the test progress due to the need to wait for data to interact with the host computer, thereby reducing the test efficiency.

[0025] 3. The vector network analyzer of this application converts analog signals into digital signals through an external, independent digital-to-analog conversion card, establishing a signal path from the analog signal side of the vector network analyzer to the digital signal side of the digital phased array antenna. Furthermore, compared to input signals that rely on the antenna unit's built-in digital-to-analog conversion module for conversion, an independent digital-to-analog conversion card is free from space and power constraints and can use a high-precision ADC / DAC to achieve digital-to-analog signal conversion, thereby reducing quantization errors. A low-jitter clock is generated through an FPGA to ensure strict matching of the sampling frequency with the signal. This allows for noise suppression and enhanced anti-interference capabilities.

[0026] 4. This application uses a switch matrix and a time-division multiplexing controller of the switch matrix to achieve time-division multiplexing switching and high-precision synchronization of each channel to be tested when testing under a specific test set, thereby realizing multi-channel parallel testing of the antenna to be tested; at the same time, this application optimizes the test process, and tests multiple source signals with different parameters for the channel to be tested under the current test set, thereby realizing the multiplexing of the target channel to be tested, making the test process compact and improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of the architecture of a digital phased array antenna automated testing system according to an embodiment of the present application; Figure 2 A schematic flow chart of an automated testing method for a digital phased array antenna according to an embodiment of the present application; Figure 3A schematic diagram of a test instruction sequence of an automated test method for a digital phased array antenna in an embodiment of the present application; Figure 4 Schematic diagram of the specific process of S4 in a digital phased array antenna automated testing method in an embodiment of the present application; Figure 5 is a test loop diagram. DETAILED DESCRIPTION

[0028] This specific embodiment is merely an explanation of the present application and is not a limitation of the present application. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed, but as long as they are within the scope of the present application, they are protected by patent law.

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. It should be noted that in the optional embodiments of the present application, when the embodiments in the present application are applied to specific products or technologies, the object information and other related data involved need to obtain the object's permission or consent, and the collection, use and processing of the relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions. In other words, if the embodiments of the present application involve data related to the object, it needs to be obtained through the authorization and consent of the object, the authorization and consent of the relevant departments, and in compliance with the relevant laws, regulations and standards of the country and region. If personal information is involved in the embodiments, the acquisition of all personal information requires the consent of the individual. If sensitive information is involved, the separate consent of the information subject needs to be obtained. The embodiments also need to be implemented with the authorization and consent of the object.

[0030] The embodiments of the present application are described in further detail below with reference to the accompanying drawings.

[0031] Example 1: See also Figure 1 , an embodiment of the present application is a digital phased array antenna automatic test system for testing an antenna 8 to be tested, including a host computer 1, a real-time controller 2, a vector network analyzer 3, a digital-to-analog conversion card 4, a wave control computer 5, a switch matrix 6 and a test transceiver module 7.

[0032] The real-time controller 2 includes a logic control area 21 and a cache area 22. The logic control area 21 is used to import pre-programmed test instruction sequences sent by the host computer 1 to the real-time controller 2, and the cache area 22 is used to store data of the source signal emitted by the vector network analyzer 3 and the echo signal acquired. The real-time controller 2 is connected to the host computer 1 via Ethernet, relying on high bandwidth to efficiently access and call large amounts of data. In another embodiment, the cache area can also be a separate cache area set up independently of the real-time controller, thereby completely isolating the host computer 1 from reading data from the cache area and the test process.

[0033] The logic control area 21 of the real-time controller 2 connects to the vector network analyzer 3 via a GPIB interface, sending analog signal codes to the vector network analyzer; connects to the wave control computer 5, sending wave position codes to the wave control computer; and connects to the switch matrix 6, sending switch codes to the switch matrix 6. The GPIB interface achieves microsecond-level latency through a hardware-level handshake protocol, ensuring high-precision timing control even with high-frequency test command switching. The buffer area 22 of the real-time controller 2 connects to the vector network analyzer 3 via Ethernet, efficiently acquiring and storing data on the source signal and echo signal emitted by the vector network analyzer 3 for periodic reading by the host computer 1.

[0034] The vector network analyzer 3 is connected to the antenna under test 8 via a digital-to-analog converter card 4. This card, which includes an ADC module, a DAC module, and an FPGA module, converts analog signals into digital signals. This card connects to the antenna under test via an RS422 interface, enabling high-speed, long-distance signal transmission. This allows high-speed, bidirectional signal transmission between the vector network analyzer 3 and the digital-to-analog converter card 4, located on the control side, and the antenna under test 8, located within a test space (e.g., a darkroom).

[0035] It should be noted that a digital phased array antenna in normal operation inherently has the ability to convert analog signals into digital signals, perform multi-beam steering in the digital domain, and then convert them back into analog signals for power amplification and radio frequency transmission. However, due to the space and power consumption limitations of the antenna itself, the resolution and phase control accuracy of the ADC and DAC modules integrated into the antenna are inferior to those of the independent peripheral digital-to-analog converter card 4, and the timing control accuracy cannot meet testing requirements. For channel testing of antennas under test, especially those in the design or maintenance phase, the test itself does not focus on the antenna's digital-to-analog conversion performance. Therefore, in the embodiments of the present application, to focus on testing the transceiver performance of the antenna under test, the signal input and output interfaces of the antenna under test 8 uniformly utilize the digital domain signal ports of the antenna under test 8. At the same time, the independent peripheral digital-to-analog converter card 4 is used as the conversion relay point between digital and analog signals, thereby eliminating signal interference at the digital-to-analog conversion layer and achieving high-resolution, high-precision timing-controlled signal conversion. The digital-to-analog converter card 4 can adapt to complex test scenarios through programming and reconfiguration of the FPGA module. In addition, the independent peripheral digital-to-analog conversion card 4 can be hot-swapped and reused for testing different antennas to be tested.

[0036] The vector network analyzer 3 is also connected to a test transceiver module 7 located within a test space (such as a darkroom). This module includes a test probe and a horn antenna. Testing of the antenna under test 8 includes both transmission and reception tests. For transmission testing, the signal path is as follows: an analog signal is emitted by the vector network analyzer 3, converted to a digital signal by the digital-to-analog converter card 4, and then input to the antenna under test 8 for RF transmission. The RF signal is then collected by the test probe and transmitted back to the vector network analyzer 3 for echo signal collection. For reception testing, the signal path is as follows: an analog signal is emitted by the vector network analyzer 3, transmitted to the horn antenna for RF transmission, received by the antenna under test 8, converted to a digital signal, converted to an analog signal by the digital-to-analog converter card 4, and then transmitted back to the vector network analyzer 3 for echo signal collection.

[0037] The beam control computer 5 is connected to the antenna to be tested 8, and adjusts the parameters of the channel to be tested according to the wave position code, including the phase difference, amplitude weight, amplitude and phase calibration compensation value of each antenna unit, so as to control the beam state and control the transmission / reception switching of the T / R component of the antenna to be tested.

[0038] The switch matrix 6 includes a time division multiplexing controller 61 and switches. The switch matrix 6 is provided with a switch corresponding to each channel to be tested of the antenna to be tested 8, and the time division multiplexing controller 61 is used to control the opening or closing of the channel to be tested.

[0039] For digital phased array antennas, transmitting any RF beam or receiving any RF signal from any beam is accomplished through a subarray consisting of several channels. Traditional testing methods sequentially test each channel, switching to the next channel for testing, and then performing a combined channel test. This is inefficient and significantly slows antenna testing. For example, if testing any channel takes 5 minutes, testing an antenna with thousands of channels would take tens of hours. Furthermore, prolonged testing consumes significant resources and manpower, such as darkroom time.

[0040] In an embodiment of the present application, for any test item with a given beam state, a time-division multiplexing controller 61 is used to time-division multiplex the switches corresponding to each channel under test, enabling multiple channels to be tested in parallel through the same signal path. Signal transmission is performed using a shared signal bus, avoiding the need to configure a separate test environment and signal path for each channel under test. This enables high-speed switching of channel tests, and single clock source control provides high timing control accuracy and stability. The time-division multiplexing controller 61 is also connected to a vector network analyzer 3, so that when the vector network analyzer 3 receives an echo signal, it maps each received echo signal to the channel under test corresponding to the switch that was turned on, based on the timestamp of the time-division multiplexing controller 61, ensuring data correspondence and independence.

[0041] More specifically, in another embodiment, the vector network analyzer 3 is equipped with several parallel echo signal buffers. When the time-division multiplexing controller 61 switches the channels under test at high speed, generating a high-frequency data stream of echo signals, the echo signals are sequentially stored in the echo signal buffers. This achieves time-sharing isolation of echo signal data with different adjacent timestamps, preventing data processing bottlenecks in the vector network analyzer from limiting the test efficiency of the antenna under test or causing data loss, overwriting, and other issues. After all echo signal data is collected, it is transferred to the buffer 22 for storage.

[0042] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0043] Example 2: See also Figure 2The present application discloses an automated testing method for a digital phased array antenna, including a transmission test and a reception test. For these two types of tests, their test logic and intermediate processes are essentially the same, differing only in the direction of their respective signal paths. For the transmission test, a vector network analyzer sends a signal, which is then transmitted through a digital-to-analog converter card to the antenna to be tested. After radio frequency transmission, the signal is then transmitted through the test transceiver module to generate an echo signal that is then received by the vector network analyzer. For the reception test, a vector network analyzer sends a signal, which is then transmitted through the test transceiver module to generate an echo signal that is then received by the antenna to be tested. The signal is then transmitted through the digital-to-analog converter card to generate an echo signal that is then received by the vector network analyzer. Therefore, in this embodiment, to simplify the description, the transmission test is used as an example for detailed description, and the steps of the reception test can be compared with those of the transmission test.

[0044] The launch test specifically includes the following steps: S1: The host computer sends a pre-programmed test command sequence to the real-time controller. This test command sequence is edited and activated by the antenna test software within the host computer system. Once activated, the antenna test software sends the test command sequence to the real-time controller, which then takes over control of the subsequent test process.

[0045] In step S2, the real-time controller sends control codes to the wave control computer, switch matrix, and vector network analyzer, one by one, based on the test instruction sequence and the test set of the test instruction sequence. The control codes include the wave position code sent to the wave control computer, the switch code sent to the switch matrix, and the analog signal code sent to the vector network analyzer. It should be noted that the test instruction sequence is a set of test sets arranged in units of test sets. Each test set contains different specific test cycles. The control codes are the control signals generated for each module to execute different test cycles, such as Figure 3 The principle of setting the test loop of the test set is to maximize the test efficiency, and to use the test loop with high test efficiency and switching efficiency as the inner small loop, and the test loop with low test efficiency and switching efficiency as the outer large loop.

[0046] S3, the wave control computer adjusts the parameters of the channel to be measured according to the wave position code.

[0047] More specifically, the control parameters include the phase difference, amplitude weighting, and amplitude-phase calibration compensation values ​​of each antenna element. A beam control computer controls the parameters of each antenna element of the target antenna under test, thereby testing the performance of the antenna's specific beam shape and beam pointing. During this test, the azimuth angle of the antenna under test is controlled by the mechanical rotation of the turntable, and the position signal of the turntable controller is input into the beam control computer.

[0048] It should be noted that when adjusting the parameters of the antenna unit, the circuit of the antenna unit has a certain response time, and the mechanical rotation of the turntable also takes a certain amount of time. Therefore, the adjustment of the beam shape and beam pointing is the control link with the lowest switching efficiency and is set as the outermost large loop.

[0049] In step S4, after the beam control computer has completed controlling the parameters of the channel under test, the beam shape and direction are determined, along with the range of the channels under test. At this point, the switch matrix opens the corresponding switches according to the switch code, turning on the corresponding channel under test. The vector network analyzer transmits a source signal to the antenna under test based on the analog signal code and then receives the echo signal. The vector network analyzer has a high switching efficiency for the source signal and is set to medium cycle. The switching efficiency of the channel under test is the highest and is set to small cycle.

[0050] In step S5, the vector network analyzer imports the echo signal and the corresponding source signal into the buffer area of ​​the real-time controller, and then sends a test set completion signal to the real-time controller.

[0051] S6, after the real-time controller obtains the test set completion signal, it sends a control code with the next test set as the object; until all test instruction sequences are completed.

[0052] In step S7, the host computer periodically retrieves source and echo signal data from the buffer. This process is independent of the test process and uses different channels, preventing interference. The host computer does not affect test timing or resource usage. The specific interval for the host computer to retrieve data can be set as needed, but it is important to avoid overflow or overwriting of data in the buffer.

[0053] Example 3: Based on Example 2, in this embodiment, a solution for performing multi-channel parallel testing using a time division multiplexer is specifically described.

[0054] For any of the test sets, it is divided into several time slices by the time division multiplexing controller of the switch matrix, and the number of time slices corresponds to the number of channels to be tested corresponding to the synthetic beam in the test set, or the number of channels to be tested corresponding to the receiving beam.

[0055] For a specific test set, after the beam control computer completes the parameter control of the channel to be tested, the shape and direction of the beam are determined, and the range of the channels to be tested is also determined accordingly. In order to improve the efficiency of antenna testing, it is necessary to use a time division multiplexing controller to evenly divide the test path occupancy time of the channels to be tested so that each channel to be tested can share the current test path. Please refer to Figure 4 , the specific steps are: S4.1, the switch matrix selects the range of the channel to be tested according to the switch code.

[0056] S4.2, the vector network analyzer sets the starting frequency, ending frequency and frequency step value of the source signal according to the analog signal code, and then sends the source signal of the starting frequency to the antenna under test, thereby generating a radio frequency beam.

[0057] In S4.3, the switch matrix uses the time-division multiplexing controller to sequentially open the switches of the test channels corresponding to the current time slice within the selected range and close the switches of the other test channels. This process effectively implements single-channel testing of the test channel in the current time slice. Time-division multiplexing enables all test channels to share and test the current test path in parallel, until all test channels corresponding to all time slices in the current test set are opened, closed, and tested.

[0058] In step S4.4, the vector network analyzer uses the timestamp of each time slice of the time division multiplexing controller as a tag to receive the echo signals corresponding to each channel under test, and associates the echo signals with the channels under test. To accommodate the high-frequency on-off switching of the channels under test and the high-frequency information of the echo signals, the vector network analyzer can employ a parallel echo signal buffer structure. The specific implementation method is similar to that described in Example 1 and is not further elaborated here.

[0059] In step S4.5, the vector network analyzer increases the frequency of the source signal according to the frequency step value set by the analog signal code. The analyzer then returns to step S4.3 and re-executes the control loop of the switch matrix's time-division multiplexing controller, scanning the response of the antenna under test channel at different frequencies until the source signal frequency reaches the set end frequency. After completing the transmission of all source signals and the reception of all echo signals for the current test set, the vector network analyzer sends a test set completion signal to the real-time controller.

[0060] It should be noted that when a vector network analyzer sends source signals of different frequencies and powers for signal switching, the internal oscillator (such as a YIG oscillator) requires time to lock the frequency and stabilize the phase noise. The initial stage of the signal source output may contain phase jitter or amplitude fluctuations. At the same time, when the digitally controlled attenuator and amplifier in the circuit adjust the power, the bias voltage of the semiconductor device will also have a response delay. Therefore, a delay protection time is left between the source signals sent at any adjacent intervals to allow the antenna under test to respond. This prevents the antenna under test from receiving distorted data and causing test errors.

[0061] The above technical solution realizes the medium loop of the vector network analyzer's source signal switching and the small loop of the switch matrix switching the channels to be tested. The two are nested in the large loop of the beam control computer for beam shape and beam pointing, forming a test set, realizing the full test process of the antenna to be tested, which can greatly improve the test efficiency of digital phased array antennas. The specific test loop logic of the antenna to be tested is as follows: Figure 5 shown.

[0062] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0063] In another embodiment, a computer program product of the present application includes a computer program or instructions, so that the computer program or instructions can implement the steps in the above-mentioned digital phased array antenna automatic testing method.

[0064] As used in the above embodiments, the term “when” may be interpreted to mean “if” or “after” or “in response to determining that” or “in response to detecting that”, depending on the context. Similarly, the phrases “upon determining that” or “if (stated condition or event) is detected” may be interpreted to mean “if determining that” or “in response to determining that” or “upon detecting (stated condition or event)” or “in response to detecting (stated condition or event)”, depending on the context.

[0065] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state drive).

[0066] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A digital phased array antenna automatic test system for testing an antenna to be tested, characterized in that: It includes host computer, real-time controller, vector network analyzer, digital-to-analog conversion card, wave control computer, switch matrix and test transceiver module; The host computer is connected to the real-time controller and sends a pre-programmed test instruction sequence to the real-time controller; The real-time controller is connected to the vector network analyzer to send analog signal codes to the vector network analyzer; is connected to the wave control computer to send wave position codes to the wave control computer; is connected to the switch matrix to send switch codes to the switch matrix; The vector network analyzer is connected to the antenna to be tested through the digital-to-analog conversion card and is connected to the test transceiver module arranged in the test space. The vector network analyzer sends a source signal to the antenna to be tested or the test transceiver module and receives an echo signal. The beam control computer is connected to the antenna to be tested and controls the beam state of the antenna to be tested; The switch matrix is ​​provided with a switch corresponding to each channel to be tested of the antenna to be tested, and the switch controls the opening or closing of the channel to be tested.

2. The digital phased array antenna automatic test system according to claim 1, characterized in that: The real-time controller includes a logic control area and a buffer area. The logic control area imports a pre-programmed test instruction sequence sent by the host computer to the real-time controller. The buffer area stores the source signal emitted by the vector network analyzer and the data of the echo signal obtained. The host computer regularly obtains the data of the source signal and the echo signal from the buffer area.

3. The digital phased array antenna automatic test system according to claim 1, characterized in that: The switch matrix includes a time division multiplexing controller, which is connected to a vector network analyzer.

4. The digital phased array antenna automatic test system according to claim 1, characterized in that: The test transceiver module includes a test probe and a horn antenna.

5. A digital phased array antenna automated testing method, using the test system according to any one of claims 1 to 4, characterized in that: The steps include: The host computer sends a pre-programmed test instruction sequence to the real-time controller; The real-time controller sends control codes to the wave control computer, the switch matrix, and the vector network analyzer in units according to the test instruction sequence and with the test set of the test instruction sequence as a unit. The control codes include the wave position codes sent to the wave control computer, the switch codes sent to the switch matrix, and the analog signal codes sent to the vector network analyzer. The wave control computer adjusts the parameters of the channel to be measured according to the wave position code; The switch matrix turns on the switch according to the switch code and turns on the corresponding channel to be tested; The vector network analyzer sends a source signal to the antenna under test or the test transceiver module according to the analog signal code, and then receives the echo signal; The vector network analyzer imports the echo signal and the corresponding source signal into the buffer area of ​​the real-time controller, and then sends a test set completion signal to the real-time controller; After the real-time controller receives the test set completion signal, it sends a control code for the next test set as the object until all test instruction sequences are completed; The host computer periodically obtains the data of the source signal and the echo signal from the buffer area.

6. The method for automated testing of digital phased array antennas according to claim 5, wherein: For any of the test sets, it is divided into several time slices by the time division multiplexing controller of the switch matrix, and the number of time slices corresponds to the number of channels to be tested corresponding to the synthetic beam in the test set, or the number of channels to be tested corresponding to the receiving beam.

7. The method for automated testing of digital phased array antennas according to claim 6, wherein: The time division multiplexing controller is used to control the switch matrix and vector network analyzer, including: The switch matrix selects the range of channels to be tested according to the switch code; The vector network analyzer sends a source signal to the antenna under test or the test transceiver module according to the analog signal code; The switch matrix uses the time division multiplexing controller to sequentially open the switches of the channels to be tested corresponding to the current time slice within the selected range, and close the switches of other channels to be tested until the channels to be tested corresponding to all time slices of the current test set are opened and closed; The vector network analyzer uses the timestamp of each time slice of the time division multiplexing controller as a label and receives the echo signal corresponding to each channel to be tested one by one.

8. The method for automated testing of digital phased array antennas according to claim 5, wherein: For any channel to be tested in a test set, the vector network analyzer sends source signals with different signal source frequencies and signal source powers in sequence according to the analog signal code, then receives the corresponding echo signals, and imports the echo signals and the corresponding source signals into the cache area of ​​the real-time controller; after completing the sending of all source signals and the receiving of echo signals in the current test set, the vector network analyzer sends a test set completion signal to the real-time controller.

9. The method for automated testing of digital phased array antennas according to claim 8, wherein: When the vector network analyzer sends source signals of different frequencies and powers, a delay protection time is reserved between switching of any source signal for the antenna to be tested to respond.

10. A computer program product, characterized in that The computer program product includes a computer program or instructions, so that the computer program or instructions can implement the steps in the digital phased array antenna automatic testing method according to any one of claims 5 to 9.

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