Decision feedback equalizer and chip

Abstract

The invention discloses a decision feedback equalizer and a chip. The decision feedback equalizer comprises a first addition module, a sampling module, a delay module, a second addition module and a current output module, and the current output module is used for generating a first bias current and performing shunting processing on the first bias current according to an adjustable shunting proportion to generate a second bias current and a third bias current. The second bias current is output to the first addition module, and the third bias current is output to the second addition module, so that bias currents are provided for the first addition module and the second addition module respectively. According to the decision feedback equalizer provided by the invention, the total current flowing through the first addition module and the second addition module is always kept unchanged, so that the common-mode voltage output by the first adder is always kept consistent; the technical problem that when a traditional decision feedback equalizer starts a plurality of feedback taps, the output common-mode voltage dynamically changes along with the weight, and consequently the common-mode voltage changes along with the weight is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a decision feedback equalizer and chip. Background Art

[0002] In high-speed SERDES systems, the decision feedback equalizer (DFE) is a core module for eliminating inter-symbol interference (ISI). Its performance depends on the adder module. Specifically, the adder module must perform two key functions: first, it adds the feedback signal provided by the feedback tap to the input signal according to the weight to achieve equalization. Second, it provides a stable common-mode voltage for the subsequent sampler module. The weight is achieved by adjusting the amplitude and direction of the feedback signal. However, increasing the weight will cause the output common-mode voltage to drop, which in turn affects the performance of the sampler module.

[0003] In traditional decision feedback equalizers, the addition module often uses a current-mode logic (CML) resistive-load adder. This adder has the advantage of a simple structure. However, its disadvantage is that the output common-mode voltage varies dynamically with the weight. The larger the weight, the smaller the common-mode voltage, which degrades the performance of the subsequent sampler module. To stabilize the common-mode voltage, traditional feedback equalizers typically incorporate a common-mode feedback (CMFB) circuit. However, due to the bandwidth limitations of the common-mode feedback loop, the introduction of a CMFB circuit is not conducive to the operation of decision feedback equalizers in high-speed transmission environments and also increases circuit power consumption and area overhead. Summary of the Invention

[0004] In view of the above problems, the present application provides a decision feedback equalizer and chip to solve the above technical problems.

[0005] In a first aspect, the present application provides a decision feedback equalizer, comprising:

[0006] a first adding module, configured to receive the weighted differential signal and the first differential signal, and perform signal superposition processing on the first differential signal and the weighted differential signal to generate a second differential signal;

[0007] a sampling module, configured to sample the second differential signal and convert the second differential signal into a digital signal;

[0008] a delay module, configured to receive the digital signal, and perform delay processing and conversion processing on the digital signal to generate the delayed differential signal, wherein the conversion processing is configured to convert the digital signal into a differential signal;

[0009] a second adding module, configured to receive the delayed differential signal, and perform weighted processing on the delayed differential signal to generate the weighted differential signal;

[0010] A current output module is configured to generate a first bias current, shunt the first bias current according to an adjustable shunt ratio to generate a second bias current and a third bias current, and output the second bias current to the first adding module and the third bias current to the second adding module to provide bias currents for the first adding module and the second adding module, respectively. The shunt ratio can be adjusted from 0% to 100%.

[0011] In a second aspect, the present application provides a chip comprising the decision feedback equalizer described in the first aspect above.

[0012] The decision feedback equalizer provided in the present application proportionally divides the bias current generated by the current output module and provides it to the first adding module and the second adding module. That is, the first bias current generated by the current output module is divided to generate a second bias current and a third bias current, and serves as the bias current of the first adding module and the second adding module, respectively. In this way, regardless of whether the weight of the second bias current provided by the output current module to the second adding module changes, the total current flowing through the first adding module and the second adding module will always remain unchanged, thereby ensuring that the common-mode voltage output by the first adder remains consistent. This solves the technical problem that when a traditional decision feedback equalizer enables multiple feedback taps, the output common-mode voltage will dynamically change with the weight, causing the common-mode voltage to change accordingly.

[0013] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 This is a schematic diagram of the addition module of the traditional decision feedback equalizer.

[0016] Figure 2 A schematic diagram of a decision feedback equalizer provided in an embodiment of the present application is shown.

[0017] Figure 3 A schematic diagram of a first adding module provided in an embodiment of the present application is shown.

[0018] Figure 4 A schematic diagram of a second adding module provided in an embodiment of the present application is shown.

[0019] Figure 5 A schematic diagram of a current output unit provided in an embodiment of the present application is shown.

[0020] Figure 6 Another schematic diagram of the current output unit provided in an embodiment of the present application is shown.

[0021] Figure 7 A schematic diagram of a second adding module and a current output module provided in an embodiment of the present application is shown.

[0022] Figure 8 Another schematic diagram of a decision feedback equalizer provided in an embodiment of the present application is shown.

[0023] Figure 9 A schematic diagram of a chip provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0025] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0026] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0027] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0028] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0029] Figure 1 This is a schematic diagram of the addition module of the traditional decision feedback equalizer, such as Figure 1 As shown in the figure, in a traditional decision feedback equalizer, the adding module includes two identical loads RL1 and RL2, a differential amplifier unit, and a current mirror I that provides bias current for the differential amplifier unit. The adding module includes multiple tapx, where x = [1, n], providing feedback taps. Specifically, each tap typically consists of a pair of amplifier transistors connected to a common source and a tail current source responsible for weighting. When the adding module enables multiple taps, because each tap is independent of the adding module, the common-mode voltage output by the adding module will dynamically change with the weight. Specifically, the weight is a coefficient that adjusts the magnitude and direction of the feedback signal output by the tap to the adding module. An increase in the weight means a larger amplitude of the feedback signal, which changes the balance of the differential signal output by the adding module, resulting in a decrease in the common-mode voltage, ultimately deteriorating the performance of the subsequent sampler module. In order to stabilize the common-mode voltage, traditional feedback equalizers usually add a common-mode feedback module (CMFB) at the output end of the adding module. However, due to the bandwidth limitation of the common-mode feedback loop, the introduction of common-mode feedback (CMFB) is not conducive to the operation of the decision feedback equalizer in a high-speed transmission environment, and will also increase the circuit power consumption and area overhead.

[0030] In view of the above problems, an embodiment of the present application provides a decision feedback equalizer, Figure 2 FIG. 4 shows a schematic diagram of a decision feedback equalizer provided in an embodiment of the present application. Figure 2 As shown, the decision feedback equalizer provided in the embodiment of the present application includes:

[0031] The first adding module is configured to receive the weighted differential signal and the first differential signal, and perform signal superposition processing on the first differential signal and the weighted differential signal to generate a second differential signal. Optionally, the first differential signal is a differential signal provided by an external circuit, which is typically provided by a preceding stage circuit of a SERDSE (SERializer / DESerializer) in which the decision feedback equalizer is located. For example, in some applications, the preceding stage circuit of the decision feedback equalizer is a continuous-time linear equalizer module. In this case, the first differential signal is the output of the continuous-time linear equalizer module, and the first adding module is configured to superimpose the first differential signal and the weighted differential signal according to the weights to achieve equalization in the decision feedback equalizer.

[0032] The sampling module is used to sample the second differential signal and convert the second differential signal into a digital signal.

[0033] The delay module is used to receive digital signals, perform delay processing and conversion processing on the digital signals to generate delayed differential signals. The delay processing is used to make the delay module output the signal after a certain delay time, and the conversion processing is used to convert the digital signal into a differential signal.

[0034] The second adding module is configured to receive the delayed differential signal and perform weighted processing on the delayed differential signal to generate a weighted differential signal. Optionally, the second adding module is configured in the decision feedback equalizer to provide a feedback signal having a corresponding weight to the first adding module by performing weighted processing on the delayed differential signal output by the delay module to generate the weighted differential signal.

[0035] The current output module is configured to generate a first bias current, shun the first bias current at an adjustable shunting ratio to generate a second bias current and a third bias current, and output the second bias current to the first adding module and the third bias current to the second adding module, respectively, to provide bias currents for the first adding module and the second adding module. The shunting ratio can be adjusted from 0% to 100%. Optionally, the third bias current flowing to the second adding module is used to weight the weighted differential signal generated by the second adding module. Because the total current flowing through the first and second adders remains constant regardless of the shunting ratio of the current output module, the common-mode voltage at the output of the first adder remains constant regardless of how the weights of the weighted differential signal are adjusted.

[0036] The decision feedback equalizer provided in the embodiment of the present application proportionally divides the bias current generated by the current output module and provides it to the first adding module and the second adding module. That is, the first bias current generated by the current output module is divided to generate the second bias current and the third bias current, and respectively serves as the bias current of the first adding module and the second adding module. In this way, the total current flowing through the first adding module and the second adding module will always remain unchanged, thereby ensuring that the common-mode voltage output by the first adder always remains consistent and is not affected by changes in weights. This solves the technical problem that when a traditional decision feedback equalizer enables multiple feedback taps, the common-mode voltage output will dynamically change with the weights, causing the common-mode voltage to change accordingly.

[0037] It can be understood that the purpose of the embodiment of the present application is to solve the technical problem that the common-mode voltage output by the first adding module of the decision feedback equalizer will change dynamically with the weight, causing the common-mode voltage to change accordingly. The specific structure of the sampling module and the delay module will not limit the embodiment of the present application in solving this technical problem. Therefore, the embodiment of the present application does not limit the specific structure of the sampling module and the delay module, and the embodiment of the present application does not limit the order of delay processing and conversion processing of the delay module. As long as it can realize the functions of the above-mentioned sampling module and delay module, for example, the sampling module can use a sampler or a related circuit with sampling function composed of logic devices, and the delay module can use a device with delay and conversion of digital signals into differential signals, such as a latch, or a related circuit with the same function composed of logic devices.

[0038] In some embodiments, in the decision feedback equalizer provided in the embodiments of the present application, the decision feedback equalizer includes multiple second addition modules and multiple current output modules, wherein each delay module is respectively connected to a different second addition module, and each second addition module is respectively connected to a different current output module, that is, one delay module is correspondingly connected to one second addition module, and one second addition module is also correspondingly connected to one current output module. Optionally, the decision feedback equalizer of an embodiment of the present application includes at least one second addition module for providing a weighted differential signal with a certain weight to the first addition module. The function of the second addition module is to compensate for the inter-code interference of the decision feedback equalizer. In order to compensate for the inter-code interference at different positions in the decision feedback equalizer, the decision feedback equalizer preferably includes multiple delay modules and multiple second addition modules to compensate for the inter-code interference at different positions, and the delay time set for each delay module is different. The current output module is used to provide a bias current for the second addition module. The bias current determines the weight of the weighted differential signal. When the decision feedback includes multiple second addition modules, it should also include multiple current output modules. Because each current output module is an independent module, the diversion ratio of each current output module can also be set separately.

[0039] In some embodiments, Figure 3 FIG. 1 shows a schematic diagram of a first adding module provided in an embodiment of the present application, as shown in FIG. Figure 3 As shown, the first adding module includes a first transistor M1 and a second transistor M2, a first load R1 and a second load R2, a first current mirror IL1, and a second current mirror IL2.

[0040] The gates of the first transistor M1 and the second transistor M2 are used to receive the first differential signal. The sources of the first transistor M1 and the second transistor M2 are both connected to the first current mirror IL1 and the second current mirror IL2, and are both connected to the current output module. The drains of the first transistor M1 and the second transistor M2 are respectively connected to the first load R1 and the second load R2, and are also connected to the second adding module. Optionally, the first transistor M1 and the second transistor M2 are a pair of differential transistors, whose gates receive the first differential signal, whose sources receive bias currents from the first current mirror IL1 and the second current mirror IL2, and receive the second bias current Il2 from the current output module, and whose drains are connected to the first load R1 and the second load R2 to output the second differential signal.

[0041] The first ends of the first load R1 and the second load R2 are connected to the power supply VDD, and the second ends of the first load R1 and the second load R2 are connected to the first transistor M1 and the second transistor M2, respectively, and are connected to the second adding module. Optionally, the first load R1 and the second load R2 are configured to convert the second differential signal in the form of a current output from the drains of the first transistor M1 and the second transistor M2 into a second differential signal in the form of a voltage, and the first load R1 and the second load R2 are further configured to convert the weighted differential signal in the form of a current output from the second adding module into a weighted differential signal in the form of a voltage.

[0042] One end of the first current mirror IL1 is grounded, and the other end is connected to the source of the first transistor to provide a bias current IL_M1 for the first transistor. One end of the second current mirror IL2 is grounded, and the other end is connected to the source of the second transistor to provide a bias current IL_M2 for the second transistor. Optionally, the first transistor M1 and the second transistor M2 are used to provide a bias current for the differential pair that implements the addition function. The bias currents IL_M1 and IL_M2 generated by them should be equal to establish a suitable static operating point for the first addition module itself and to ensure that the first transistor M1 and the second transistor M2 operate in the saturation region, thereby maintaining the required gain of the first addition module.

[0043] As an implementation manner, the first load R1 and the second load R2 are equal.

[0044] In the decision feedback equalizer provided in an embodiment of the present application, in addition to the bias currents IL_M1 and IL_M2 provided by the first adding module itself, the first adding module also receives a second bias current Il2 provided by the current output module, so that the current flowing through the first adding module is related to the current flowing through the second adding module. In this way, the total current flowing through the first adding module and the second adding module will always remain unchanged, thereby ensuring that the common-mode voltage output by the first adder always remains consistent. This solves the technical problem that when a traditional decision feedback equalizer enables multiple feedback taps, the output common-mode voltage will dynamically change with the weight, causing the common-mode voltage to change accordingly.

[0045] In some embodiments, Figure 4 Schematic diagram of the second addition module provided in the embodiment of the present application is shown as follows: Figure 4 As shown, the second adding module includes a pair of a third transistor M3 and a fourth transistor M4 connected with a common source.

[0046] The gates of the third transistor M3 and the fourth transistor M4 are used to receive the delayed differential signal. The sources of the third transistor M3 and the fourth transistor M4 are both connected to the current output module to receive the third bias current Il3 provided by the current output module. The drains of the third transistor M3 and the fourth transistor M4 are respectively connected to the first transistor M1 and the second transistor M2 to output the weighted differential signal to the first adding module. Optionally, the second adding module and the current output module together constitute a feedback tap portion in the decision feedback device, which is used to provide a feedback tap, i.e., a weighted differential signal, to the first adding module. The magnitude of the third bias current Il3 received by the third transistor M3 and the fourth transistor M4 determines the weight of the weighted differential signal. The magnitude of this third bias current Il3 is determined by its corresponding shunt ratio.

[0047] For example, according to Figure 4 The schematic diagram of the second adding module shown in FIG. 1 illustrates the decision feedback device provided in the embodiment of the present application. Figure 4 As shown, the second adding module includes n pairs of third transistors M3 and fourth transistors M4 connected with common sources. For any pair of third transistors M3 and fourth transistors M4, assuming their corresponding first bias current is Il1, the sum of the first bias current Il1 and the bias currents IL_M1 and IL_M2 output by the first current mirror IL1 and the second current mirror IL2 of the first adding module is Iall = Il1 + IL_M1 + IL_M2 = Il2 + Il3 + IL_M1 + IL_M2.

[0048] When, for any pair of the third transistor M3 and the fourth transistor M4, the first bias current Il1 entirely flows into the first adding module and the weight is 0, the pair of the third transistor M3 and the fourth transistor M4 do not provide a feedback tap to the first adding module, and the current flowing through the first load R1 and the second load R2 is both Iall / 2. When it is known that R=R1=R2, the common-mode voltage Vcm output by the first adding module should be Vcm=[(VDD-Ir1*R)+(VDD-Ir2*R)] / 2=VDD-[(Ir1+Ir2) / 2]*R=VDD-R*Iall / 2, where the symbol “ / ” represents a division symbol, the symbol “*” represents a multiplication symbol, Ir1 represents the current flowing through the first load R1, and Ir2 represents the current flowing through the second load R2.

[0049] When, for any pair of the third transistor M3 and the fourth transistor M4, the first bias current all flows into the second adding module and the weight is the largest, at this time, the pair of the third transistor M3 and the fourth transistor M4 provide a feedback tap to the first adding module and the maximum current is Il1. Taking the third transistor M4 being turned on when the weight is the largest as an example, at this time, the first bias current Il1 all flows into the third transistor M3 or the fourth transistor M4. Specifically, it can be designed to flow into the third transistor M3 or the fourth transistor M4. Here, it is assumed that it flows into the fourth transistor M4. Then, the first bias current Il1 flows through the fourth transistor M3. Transistor M4 flows into the second load R2. At this time, the currents flowing through the first load R1 and the second load R2 are IL_M1 and IL_M2+Il1, respectively. At this time, the common-mode voltage is Vcm=[(VDD-Ir1*R)+(VDD-Ir2*R)] / 2. Because IL_M1=IL_M2, the common-mode voltage can be obtained as Vcm=VDD-R*Iall / 2, where the symbol " / " represents the division symbol, the symbol "*" represents the multiplication symbol, Ir1 represents the current flowing through the first load R1, and Ir2 represents the current flowing through the second load R2.

[0050] It can be understood that in the decision feedback equalizer provided in the embodiment of the present application, each second adding module and each current output module are the same. Therefore, it is obvious that when it is verified based on one of the second adding modules and the current output module corresponding to the second adding module that the common-mode voltage output by the first adding module does not change due to the change in weight, when multiple second adding modules and multiple current output modules are used, the common-mode voltage output by the first adding module will inevitably not change due to the change in weight.

[0051] From the above description, it can be seen that the decision feedback equalizer provided in the embodiment of the present application has a constant total current of the first adding module and the second adding module. Therefore, no matter how the diversion ratio of the first bias current is adjusted, the common-mode voltage output by the first adding module will remain unchanged, thereby solving the technical problem that when a traditional decision feedback equalizer enables multiple feedback taps, the common-mode voltage output will dynamically change with the weight, causing the common-mode voltage to change accordingly.

[0052] In some embodiments, Figure 5 Schematic diagram of the current output unit provided in the embodiment of the present application is shown in FIG. Figure 5 As shown, the current output module includes at least one current output unit, and the current output unit includes a first current source It1 and an output selection unit.

[0053] The first current source It1 is used to generate a first current I1.

[0054] The output selection unit is connected to the first current source It1 , and is configured to receive a selection signal sel and the first current I1 , and output the first current I1 to the first adding module or the second adding module according to the selection signal sel.

[0055] Among them, the sum of the first currents I1 generated by each current output unit is the first bias current, the sum of the first currents I1 output by each current output unit to the first adding module is the second bias current Il2, and the sum of the first currents I1 output by each current output unit to the second adding module is the third bias current Il3.

[0056] Optionally, the current output unit is used to control the weighted differential signal of the second adding module. Specifically, the current output unit is connected to the source of a pair of third and fourth transistors M3 and M4 having a common source, thereby providing a bias current, namely, a third bias current Il3, to the third and fourth transistors M3 and M4 having a common source. All current output units are connected to the first transistor M1 and the second transistor M2 of the first adding module to provide an additional bias current, namely, a second bias current Il2, to the first adding module.

[0057] It should be clear that the embodiments of the present application do not limit the source of the selection signal sel. For example, each output selection unit can be set to connect to a level generating circuit to receive a selection signal. For example, it can also be set to output the selection signal through binary coding. For example, a 3-bit binary code can output 8 selection signals, thereby controlling multiple output selection units through binary coding.

[0058] The decision feedback equalizer provided in the embodiment of the present application sets multiple current sources and output selection units for the current output unit, so that the first bias current is shunted through the selection signal sel received by each output selection unit. In other words, the adjustable shunting ratio is determined by each selection signal sel, and ultimately the total current of the first adding module and the second adding module is kept constant, which solves the technical problem that when the traditional decision feedback equalizer enables multiple feedback taps, the output common-mode voltage will dynamically change with the weight, causing the common-mode voltage to change accordingly.

[0059] As a preferred embodiment, in the decision feedback equalizer provided in the embodiment of the present application, each current output unit is connected to a digital-to-analog converter, so that the digital-to-analog converter provides a selection signal to it in a binary encoding manner. Exemplarily, for any current output module, when it includes multiple current output units, the sum of the first bias currents generated by the current output module is x*I1, where x represents the number of bits of the digital-to-analog converter. For example, a 3-bit digital-to-analog converter can provide 8 selection signals sel, that is, a 3-bit digital-to-analog converter supports the current output module to include 8 current output units. The second bias current Il2 and the third bias current Il3 generated by the first bias current shunt are controlled by the level state of each selection signal sel, that is, the number of binary values ​​of each bit in the digital-to-analog converter that are 1 and 0 is determined. Specifically, it can be set that when the selection signal is high, that is, the binary value is 1, the corresponding current output unit transmits the bias current to the first adding module, and when it is low, that is, the binary value is 1, the corresponding current output unit transmits the bias current to the second adding module. It can also be set that when the selection signal is at a high level, the corresponding current output unit transmits the bias current to the second adding module, and when it is at a low level, the corresponding current output unit transmits the bias current to the first adding module.

[0060] In some embodiments, Figure 6 Another schematic diagram of the current output unit provided in the embodiment of the present application is shown in FIG. Figure 6 As shown, the first current source It1 includes a fifth transistor M5.

[0061] The source of the fifth transistor M5 is grounded, the drain of the fifth transistor M5 is connected to the output selection unit, and the gate of the fifth transistor M5 is configured to receive a preset voltage, which is configured to control the drain of the fifth transistor M5 to generate the first current I1. Optionally, the magnitude of the preset voltage determines the magnitude of the first current I1 output by the drain of the fifth transistor M5.

[0062] In some embodiments, as Figure 6 As shown, the output selection unit includes a sixth transistor M6, a seventh transistor M7 and a first inverter INV1.

[0063] The gate of the sixth transistor M6 is used to receive the selection signal sel, the source of the sixth transistor M6 is connected to the first current source It1, and the drain of the sixth transistor M6 is connected to one of the first adding module and the second adding module. Specifically, the drain of the sixth transistor M6 is connected to the source of the first transistor M1 and the second transistor of the first adding module to provide a second bias current therefor, and the drain of the sixth transistor M6 is connected to the source of the third transistor M3 and the fourth transistor M4 to provide a third bias current therefor.

[0064] The gate of the seventh transistor M7 is connected to the output terminal of the first inverter INV1, the source of the seventh transistor M7 is connected to the first current source It1, and the drain of the seventh transistor M7 is connected to the other of the second adding module and the first adding module. The input terminal of the first inverter INV1 is used to receive the selection signal.

[0065] Specifically, the sixth transistor M6, the seventh transistor M7 and the first inverter INV1 form a selector. When the selection signal sel is at a high level, the first current I1 generated by the fifth transistor M5 is output from the sixth transistor M6. When the selection signal sel is at a low level, the first current I1 generated by the fifth transistor M5 is output from the seventh transistor M7.

[0066] In some embodiments, Figure 7 A schematic diagram of the second adding module and the current output module provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, a matching transistor M8 is further included between the second adding module and the current output module. The gate of the matching transistor M8 is used to receive the common-mode signal of the first differential signal to ensure that the gate voltage of the matching transistor M8 is consistent with that of the first transistor M1 and the second transistor M2. The drain of the matching transistor M8 is connected to the second adding module, and the source of the matching transistor M8 is connected to the current output module to receive a third bias current.

[0067] In the decision feedback equalizer provided in an embodiment of the present application, a matching transistor M8 is added between the third transistor M3 and the fourth transistor M4 connected to the common source and the output selection unit to ensure that the output selection unit and the third transistor M3 and the fourth transistor M4 connected to the common source can all operate in the linear region, so that they have a small impedance, thereby ensuring that the currents before and after the second bias current Il2 and the third bias current Il3 remain consistent each time, further stabilizing the common-mode voltage output by the first adding module.

[0068] As an implementation manner, the matching transistor M8 is matched with the third transistor M3 and the first transistor M1 in proportion. Specifically, the ratio of the matching transistor M8 to the third transistor M3 / the first transistor M1 is 2Il1:IL_M1.

[0069] As a preferred implementation, in the embodiment of the present application, each transistor (M1 to M8) is an NMOS transistor, but it should be clear that since the source and drain of the transistor can be symmetrical in structure, their source and drain can be structurally indistinguishable. In other words, the designer has the ability to make each transistor (M1 to M8) a PMOS transistor by resetting the circuit, but such replacement obviously does not deviate from the concept of the present application.

[0070] In some embodiments, Figure 8 Another schematic diagram of the decision feedback equalizer provided in the embodiment of the present application is shown in FIG. Figure 8 As shown, in the decision feedback equalizer provided in an embodiment of the present application, the delay module includes a latch, and the latches of each delay module are connected in cascade. The input end of the first-stage latch is used to receive the digital signal, wherein the delay time of the delayed differential signal output by each stage of the latch is different. Specifically, the latch includes an input end and two output ends. One output end of each stage of the latch is connected to the input end of the latch of the next stage, and the other output end of each stage of the latch is connected to the second adding module to output the delayed differential signal to the second adding module. The input end of the first stage latch is used to receive the digital signal.

[0071] It is understandable that the embodiments of the present application do not limit the delay and conversion principle of the latch. For example, the internal circuit of the latch can be configured as follows: the first-level latch converts the digital signal it receives into a differential signal, and then delays the differential signal and outputs it to the second adding module, and transmits the differential signal to the first input end of the next-level latch, and the subsequent latches at each level delay processing the differential signal. For another example, the internal circuit of the latch can be configured as follows: the first-level latch converts the digital signal it receives into a differential signal, and then delays the differential signal and outputs it to the second adding module, while the digital signal it receives is still output to the next-level latch, and the subsequent latches at each level need to transmit the digital signal to the next-level latch in the same way as the first-level latch, and convert the digital signal into a differential signal and transmit it to the second adding module after delay processing.

[0072] In specific implementations, the modules / units included in the various devices and products described in the above embodiments may be software modules / units or hardware modules / units, or may be partially software modules / units and partially hardware modules / units.

[0073] For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The unit can be implemented in the form of a software program, which runs on the processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on the processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0074] The embodiment of the present application further provides a chip 90, Figure 9 A schematic diagram of a chip provided in an embodiment of the present application is shown, wherein the chip 90 includes the aforementioned phase-locked loop circuit. An integrated circuit (IC) is also referred to as an integrated circuit. Such chips include, but are not limited to, SOC (System on Chip), SIP (System in Package), and FPGA (Field-Programmable Gate Array). FPGAs, as programmable logic devices, can implement user-customized logic functions through hardware description languages ​​and are widely used in communications, industry, data centers, and other fields.

[0075] The above content is a further detailed description of the present application in conjunction with specific implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, they can make several simple deductions or substitutions without departing from the concept of the present application, which should be considered as the scope of protection of the present application.

Claims

1. A decision feedback equalizer, characterized in that: include: a first adding module, configured to receive the weighted differential signal and the first differential signal, and perform signal superposition processing on the first differential signal and the weighted differential signal to generate a second differential signal; a sampling module, configured to sample the second differential signal and convert the second differential signal into a digital signal; a delay module, configured to receive the digital signal, and perform delay processing and conversion processing on the digital signal to generate the delayed differential signal, wherein the conversion processing is configured to convert the digital signal into a differential signal; a second adding module, configured to receive the delayed differential signal, and perform weighted processing on the delayed differential signal to generate the weighted differential signal; A current output module is configured to generate a first bias current, shunt the first bias current according to an adjustable shunt ratio to generate a second bias current and a third bias current, and output the second bias current to the first adding module and the third bias current to the second adding module to provide bias currents for the first adding module and the second adding module, respectively. The shunt ratio can be adjusted from 0% to 100%.

2. The decision feedback equalizer according to claim 1, wherein The decision feedback equalizer includes a plurality of delay modules, a plurality of second adding modules and a plurality of current output modules; Each of the delay modules is connected to a different second adding module, and each of the second adding modules is further connected to a different current output module.

3. The decision feedback equalizer according to claim 2, wherein: The first addition module includes: a first transistor and a second transistor, wherein the gates of the first transistor and the second transistor are used to receive the first differential signal, the sources of the first transistor and the second transistor are respectively connected to a first current mirror and a second current mirror, and are connected to the current output module, and the drains of the first transistor and the second transistor are respectively connected to a first load and a second load, and are connected to the second adding module; The first ends of the first load and the second load are connected to a power supply, and the second ends of the first load and the second load are connected to the first transistor and the second transistor respectively, and are connected to the second adding module; One end of the first current mirror is grounded, and the other end is connected to the first transistors to provide bias current for the first transistors; One end of the second current mirror is grounded, and the other end is connected to the second transistor to provide a bias current for the second transistor; The bias currents generated by the first current mirror and the second current mirror are equal.

4. The decision feedback equalizer according to claim 3, wherein: The second adding module includes a pair of third and fourth transistors connected to a common source; The gates of the third transistor and the fourth transistor are used to receive the delayed differential signal, the sources of the third transistor and the fourth transistor are connected to the current output module, and the drains of the third transistor and the fourth transistor are connected to the first transistor and the second transistor respectively.

5. The decision feedback equalizer according to claim 2, wherein: The current output module includes at least one current output unit, and the current output unit includes: A first current source, configured to generate a first current; an output selection unit, configured to receive a selection signal and the first current, and output the first current to the first adding module or the second adding module according to the selection signal; Among them, the sum of the first currents generated by each of the current output units is the first bias current, the sum of the first currents output by each of the current output units to the first adding module is the second bias current, and the sum of the first currents output by each of the current output units to the second adding module is the third bias current.

6. The decision feedback equalizer according to claim 5, wherein: The first current source comprises: A fifth transistor, wherein the source of the fifth transistor is grounded, the drain of the fifth transistor is connected to the output selection unit, and the gate of the fifth transistor is used to receive a preset voltage, and the preset voltage is used to control the drain of the fifth transistor to generate the first current.

7. The decision feedback equalizer according to claim 5, wherein: The output selection unit includes a sixth transistor, a seventh transistor and a first inverter; The gate of the sixth transistor is used to receive the selection signal, the source of the sixth transistor is connected to the first current source, and the drain of the sixth transistor is connected to one of the first adding module and the second adding module; The gate of the seventh transistor is connected to the output terminal of the first inverter, the source of the seventh transistor is connected to the first current source, and the drain of the seventh transistor is connected to the other of the second adding module and the first adding module; The input terminal of the first inverter is used to receive the selection signal.

8. The decision feedback equalizer according to claim 2, wherein: A matching transistor is further included between the second adding module and the current output module; The gate of the matching transistor is used to receive the common mode signal of the first differential signal, the source of the matching transistor is connected to the current output module to receive the third bias current, and the drain of the matching transistor is connected to the second adding module to output the third bias current to the second adding module.

9. The decision feedback equalizer according to claim 2, wherein: The delay module includes a latch, and the latches of the delay modules are connected in cascade, and the input end of the first stage latch is used to receive the digital signal; The delay time of the delayed differential signal output by each stage of the latch is different.

10. A chip, characterized in that: The invention comprises the decision feedback equalizer described in any one of claims 1 to 9.

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