Network-on-chip message transmission method and device, and storage medium

Abstract

The invention relates to the technical field of integrated circuit system-on-chip communication, and discloses an on-chip network message transmission method and device and a storage medium, and the method comprises the steps that a processor transmits parameters and data in a parallel transmission mode, parameters are transmitted to the sending control state register module and the receiving control state register module through interfaces, and data are transmitted to the AXISlave module through an interface. The sending control state register module and the AXISlave module respectively transmit configuration parameters and data to a packaging module and package the configuration parameters and the data into a message format for transmission, and the message is transmitted in the router module of each node; and when the router module transmits the message to the unpacking module, unpacking is carried out, and unpacked configuration parameters and data are respectively transmitted to the sending control state register module and the AXISlave module. According to the invention, the transmission efficiency and the overall performance of the network-on-chip can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit system-on-chip communication technology, for example, to a method, device, and storage medium for transmitting network-on-chip messages. Background Art

[0002] With the continuous advancement of integrated circuit technology, the number of processor cores, memories, and various functional modules integrated into systems-on-chip (SoCs) has grown exponentially. Traditional bus architectures are no longer able to meet the increasingly complex demands of on-chip communication. Against this backdrop, on-chip networks (NOCs), as a new on-chip communication architecture, draw on the design concepts of computer networks to transmit data in packets. With advantages such as strong scalability, high parallelism, and low power consumption, they have become a core communication solution for modern high-performance SoCs.

[0003] In a NoC system, message transmission efficiency directly impacts the performance of the entire SoC. Currently, common message transmission methods suffer from high data processing latency and low system throughput. With the increasing demand for chip computing power in fields such as artificial intelligence and high-performance computing, the complexity and transmission pressure of on-chip data communication have increased significantly. Traditional transmission methods are no longer able to meet the real-time and high-efficiency requirements.

[0004] Therefore, the existing transmission methods have the problem of poor real-time performance and transmission efficiency.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of this application. Summary of the Invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The on-chip network message transmission method, device, and storage medium provided by the embodiments of the present disclosure solve the problems of poor real-time performance and transmission efficiency in existing transmission methods.

[0008] The method for transmitting network-on-chip messages in an embodiment of the present disclosure includes:

[0009] The processor uses parallel transmission to transmit parameters and data. The parameters are transmitted through the AXI-lite interface with the transmit control status register module and the receive control status register module, and the data is transmitted through the AXI-full interface with the AXI_Slave module.

[0010] The sending control status register module and the AXI_Slave module respectively transmit the configuration parameters including the target address, source address, and number of messages and the data to the packet assembly module, which are packaged into the message format for transmission. The message is transmitted in the router module of each node;

[0011] When the router module transmits the message to the depacketization module, it is depacketized and the configuration parameters and data including the destination address, source address, and message quantity are transmitted to the sending control status register module and the AXI_Slave module respectively.

[0012] In some embodiments, the transmission process corresponding to the above transmission method adopts a handshake protocol to ensure seamless connection and transmission stability of data, and the configuration parameters and data are transmitted separately in parallel.

[0013] In some embodiments, the above message is transmitted using a bit width of 1026 bits and includes three types:

[0014] Among them, the first type of Head_flit message includes the target node address, message quantity, and transaction type. It is used to transmit all parameters required in the entire process and is used for control and judgment during the NOC transmission process; the second type of Body_flit message transmits 1024 bits of data each time; the third type of Tail_flit message is used to transmit 1024 bits of data.

[0015] In some embodiments, the three types of data above represent a complete data packet, wherein the Head_flit message represents the beginning of the data packet and the Tail_flit message represents the end of the data packet, so that a complete data packet can be stably transmitted in the NOC.

[0016] In some embodiments, the transmission control status register module and the AXI_Slave module respectively transmit configuration parameters including the target address, source address, and number of messages and data to the packetization module and package them into a message format, including:

[0017] When the Resp signal from the router module is high, the sending control status register module starts to transmit parameters;

[0018] The Valid signal from the sending control status register module is generated into a single pulse period signal Valid_paulse. When the Valid_paulse signal is high, the parameters including the target node address, message quantity, and transaction type are spliced ​​into data Cont_data and sent to the add message type and send module;

[0019] After adding the Head flag to the Cont_data signal, it forms a Head_flit message and sends it to the router module;

[0020] When the Resp signal generated by the control signal module is high, the AXI_Slave module starts to send data and combines the Pkt_size signal from the message quantity calculation module and the Cont_sign signal from the control signal module. The Pkt_size signal is decremented by 1 after each message is sent. When the Cont_sign signal is high and Pkt_size>0, the Body flag is added to the data to form a Body_flit message and sent to the router module. When the Cont_sign signal is high and Pkt_size=0, the Tail flag is added to the data to form a Tail_flit message.

[0021] In some embodiments, the above method further comprises:

[0022] The resp signal is used to control the data transmission. When the parameters arrive, the Resp signal level sent to the AXI_Slave module is set to 1 to prevent the data from being sent to the packet assembly module before the parameters.

[0023] In some embodiments, the above unpacking process includes:

[0024] The state machine is in the starting state Rcsr_state, receiving the Resp signal from the receive control status register module. When the Resp signal is high, it receives the message from the router module and judges the message type. When it is a Head_flit message, it splits the corresponding message to obtain parameters including the target node address, message quantity, and transaction type, and sends them to the rcv_csr module, and sends the message quantity to the state machine.

[0025] In some embodiments, the above method further comprises:

[0026] When the number of messages = 0, maintain the current state Rcsr_state; when the number of messages > 0, enter the Slave_state state and start receiving the Resp signal from the AXI_slave module. When the Resp signal is high, split the Body_flit and Tail_flit from the router module in turn, obtain the data and send it to the AXI_slave module. At this time, the state is converted according to the flit type. When the flit type is Body, maintain the Slave_state state. When the flit type is Tail, convert to the Rcsr_state state.

[0027] An electronic device provided by an embodiment of the present disclosure includes at least one processor;

[0028] and a memory communicatively coupled to the at least one processor;

[0029] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the above-mentioned on-chip network message transmission method.

[0030] The storage medium provided by the embodiment of the present disclosure stores program instructions, which, when run, execute the above-mentioned on-chip network message transmission method.

[0031] The on-chip network message transmission method, device, and storage medium provided by the embodiments of the present disclosure can achieve the following technical effects:

[0032] In the message transmission architecture, the processor transmits parameters and data in parallel, which are then packaged into a message format. The messages are then transmitted in the NOC as messages, and finally returned to the processor after being unpacked. The handshake protocol is used throughout the process, improving transmission efficiency while ensuring efficient and stable transmission.

[0033] In the message composition structure, a complete data packet is divided into multiple message types for transmission, and the payload bit width of each message transmission can support up to 1024 bits, which improves the NOC throughput.

[0034] The packaging module packages the parameters and data into messages respectively. The unpacking module is controlled by the state machine to split the message and transmit the transmission parameters and data separately, thus realizing efficient packaging, unpacking and transmission of the message.

[0035] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,

[0037] Figure 1 This is a flow chart of a method for transmitting network-on-chip messages provided by an embodiment of the present disclosure;

[0038] Figure 2 This is a diagram of a message transmission architecture provided by an embodiment of the present disclosure;

[0039] Figure 3 This is a diagram of a message composition structure provided by an embodiment of the present disclosure;

[0040] Figure 4 This is a message packet grouping logic design diagram provided by an embodiment of the present disclosure;

[0041] Figure 5 This is a message depacketization logic design diagram provided by an embodiment of the present disclosure;

[0042] Figure 6 It is a structural diagram of a network-on-chip message transmission device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0044] The terms "first," "second," and the like in the embodiments of the present disclosure are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to facilitate the description of the embodiments of the present disclosure herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0045] Unless otherwise stated, the term "plurality" means two or more.

[0046] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.

[0047] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0048] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0049] In order to solve the above problems, the present disclosure provides a method, device, and storage medium for transmitting on-chip network messages.

[0050] The following describes the on-chip network message transmission method, device, and storage medium provided by the embodiments of the present disclosure in conjunction with the accompanying drawings.

[0051] Figure 1This is a flow chart of a method for transmitting network-on-chip messages provided by an embodiment of the present disclosure.

[0052] like Figure 1 As shown, the method for transmitting an on-chip network message may include:

[0053] S101, the processor uses parallel transmission to transmit parameters and data, transmits parameters to the transmit control status register module and the receive control status register module through the AXI-lite interface, and transmits data to the AXI_Slave module through the AXI-full interface;

[0054] S102, the sending control status register module and the AXI_Slave module respectively transmit the configuration parameters including the target address, source address, and number of messages and the data to the packaging module, which are packaged into a message format for transmission. The message is transmitted in the router module of each node;

[0055] S103, when the router module transmits the message to the depacketization module, it depackets the message and transmits the unpacked configuration parameters and data including the destination address, source address, and message quantity to the transmission control status register module and the AXI_Slave module respectively.

[0056] In some embodiments, the transmission process corresponding to the above transmission method adopts a handshake protocol to ensure seamless connection and transmission stability of data, and the configuration parameters and data are transmitted separately in parallel.

[0057] In some embodiments, the above message is transmitted using a bit width of 1026 bits and includes three types:

[0058] Among them, the first type of Head_flit message includes the target node address, message quantity, and transaction type. It is used to transmit all parameters required in the entire process and is used for control and judgment during the NOC transmission process; the second type of Body_flit message transmits 1024 bits of data each time; the third type of Tail_flit message is used to transmit 1024 bits of data.

[0059] In some embodiments, the three types of data above represent a complete data packet, wherein the Head_flit message represents the beginning of the data packet and the Tail_flit message represents the end of the data packet, so that a complete data packet can be stably transmitted in the NOC.

[0060] In some embodiments, the transmission control status register module and the AXI_Slave module respectively transmit configuration parameters including the target address, source address, and number of messages and data to the packetization module and package them into a message format, including:

[0061] When the Resp signal from the router module is high, the sending control status register module starts to transmit parameters;

[0062] The Valid signal from the sending control status register module is generated into a single pulse period signal Valid_paulse. When the Valid_paulse signal is high, the parameters including the target node address, message quantity, and transaction type are spliced ​​into data Cont_data and sent to the add message type and send module;

[0063] After adding the Head flag to the Cont_data signal, it forms a Head_flit message and sends it to the router module;

[0064] When the Resp signal generated by the control signal module is high, the AXI_Slave module starts to send data and combines the Pkt_size signal from the message quantity calculation module and the Cont_sign signal from the control signal module. The Pkt_size signal is decremented by 1 after each message is sent. When the Cont_sign signal is high and Pkt_size>0, the Body flag is added to the data to form a Body_flit message and sent to the router module. When the Cont_sign signal is high and Pkt_size=0, the Tail flag is added to the data to form a Tail_flit message.

[0065] In some embodiments, the above method further comprises:

[0066] The resp signal is used to control the data transmission. When the parameters arrive, the Resp signal level sent to the AXI_Slave module is set to 1 to prevent the data from being sent to the packet assembly module before the parameters.

[0067] In some embodiments, the above unpacking process includes:

[0068] The state machine is in the starting state Rcsr_state, receiving the Resp signal from the receive control status register module. When the Resp signal is high, it receives the message from the router module and judges the message type. When it is a Head_flit message, it splits the corresponding message to obtain parameters including the target node address, message quantity, and transaction type, and sends them to the rcv_csr module, and sends the message quantity to the state machine.

[0069] In some embodiments, the above method further comprises:

[0070] When the number of messages = 0, maintain the current state Rcsr_state; when the number of messages > 0, enter the Slave_state state and start receiving the Resp signal from the AXI_slave module. When the Resp signal is high, split the Body_flit and Tail_flit from the router module in turn, obtain the data and send it to the AXI_slave module. At this time, the state is converted according to the flit type. When the flit type is Body, maintain the Slave_state state. When the flit type is Tail, convert to the Rcsr_state state.

[0071] Figure 2 This is a diagram of a message transmission architecture provided by an embodiment of the present disclosure. Figure 3 This is a diagram of a message structure provided by an embodiment of the present disclosure. Figure 4 This is a message packet logic design diagram provided by an embodiment of the present disclosure. Figure 5 This is a message depacketization logic design diagram provided by the embodiment of the present disclosure. Figures 2 to 5 ,right Figure 1 The transmission method of the on-chip network message is further described.

[0072] Figure 2 The message transmission process is described in detail. First, the processor (Process Element, PE) uses parallel transmission to transmit parameters and data. The parameters are transmitted through the AXI-lite interface with the Send Control and Status Registers module (snd_csr) and the Receive Control and Status Registers module (rcv_csr), and the data is transmitted through the AXI-full interface with the AXI_Slave module. Then, the snd_csr module and the AXI_Slave module respectively transmit configuration parameters and data such as the target address, source address, and number of messages to the packet assembly module (packet_pro), which are packaged into the message (flit) format for transmission. Subsequently, the message is transmitted in the router module (router) of each node. When the router transmits the message to the depacketization module (packet_decode), it starts to depacketize it. Finally, the depacketized configuration parameters and data such as the target address, source address, and number of messages are transmitted to the snd_csr module and the AXI_Slave module respectively. The entire transmission process uses a handshake protocol to ensure seamless data connection and transmission stability, and the configuration parameters and data are transmitted separately in parallel, which can reduce latency and improve data transmission efficiency.

[0073] Figure 3 The flit structure is described in detail. In this example, flit uses a bit width of 1026 bits for transmission. Figure 3 As shown, there are three types of flits: the first, the Head_flit message, contains parameters such as the destination node address, message quantity, and transaction type. It can be used to transmit all parameters required for the entire process and is used for control and judgment during NOC transmission, such as using the destination node address to determine direction in the routing algorithm. The second, the Body_flit message, can be used to transmit 1024 bits of data at a time. The third, the Tail_flit message, is also used to transmit 1024 bits of data. These three types of data represent a complete data packet, with the Head_flit message indicating the beginning of a data packet and the Tail_flit message indicating the end of a data packet. These markers enable a complete data packet to be transmitted stably within the NOC. At the same time, the 1024-bit payload data width significantly improves the NOC's throughput.

[0074] Figure 4 The message packaging process is described in detail. First, when the Resp signal from the router module is high, the snd_csr module starts to transmit parameters; then the Valid signal from the snd_csr module generates a single pulse periodic signal Valid_paulse. When this signal is high, the target node address, message quantity, transaction type and other parameters are spliced ​​into data Cont_data and sent to the add flit type and send module; then the Cont_data signal is added with the Head flag to form a Head_flit message and sent to the router module; then when the control signal module generates When the Resp signal is high, the AXI_Slave module begins sending data. Combining the Pkt_size signal from the message count calculation module and the Cont_sign signal from the control signal module, the Pkt_size signal is decremented by 1 after each message is sent. When the Cont_sign signal is high and Pkt_size > 0, the Body flag is added to the data to form a Body_flit message, which is then sent to the router module. When the Cont_sign signal is high and Pkt_size = 0, the Tail flag is added to the data to form a Tail_flit message. In this design, to prevent data from being sent to the packet assembly module before the parameters arrive, the Resp signal is used to control data transmission. When the parameters arrive, the Resp signal level sent to the AXI_Slave module is set to 1. Furthermore, combined with the message count calculation module, the addition of message types is precisely controlled, resulting in efficient packet assembly and transmission.

[0075] Figure 5 The message unpacking process is described in detail. The message unpacking process is controlled by a state machine, which controls the Resp signal from the rcv_csr module and AXI_slave, thereby controlling the transmission of parameters and data. This can prevent the next unpacked parameter from being sent to the rcv_csr module, overwriting the previous parameter that was not fully transmitted to the PE. First, the state machine is in the starting state Rcsr_state and receives the Resp signal from the rcv_csr module. When this signal is high, it receives the message from the router module and determines the message type. If it is a Head_flit message, it splits the message to obtain parameters such as the target node address, message number, and transaction type, and sends them to the rcv_csr module. The message number is also sent to the state machine. Next, the next state is determined. If the number of packets is 0, the current state remains in Rcsr_state. If the number of packets exceeds 0, the state enters Slave_state and begins receiving the Resp signal from the AXI_slave module. When this signal is high, the Body_flit and Tail_flit from the router module are sequentially split, obtaining the data and sending it to the AXI_slave module. At this point, the state transitions based on the flit type. If the flit type is Body, the state remains in Slave_state. If the flit type is Tail, the state transitions to Rcsr_state. This effectively completes the unpacking and transmission of packets.

[0076] The solution provided by the present disclosure designs a message transmission architecture, proposes a message composition structure, and designs a message packaging and depacketization module.

[0077] In the message transmission architecture, the processor transmits parameters and data in parallel, which are then packaged into a message format. The messages are then transmitted in the NOC as messages, and finally returned to the processor after being unpacked. The handshake protocol is used throughout the process, improving transmission efficiency while ensuring efficient and stable transmission.

[0078] In the message composition structure, a complete data packet is divided into multiple message types for transmission, and the payload bit width of each message transmission can support up to 1024 bits, which improves the NOC throughput.

[0079] The packaging module packages the parameters and data into messages respectively. The unpacking module is controlled by the state machine to split the message and transmit the transmission parameters and data separately, thus realizing efficient packaging, unpacking and transmission of the message.

[0080] The on-chip network message transmission method provided by the present disclosure can reduce latency and increase throughput, thereby meeting the requirements of real-time and high efficiency, achieving large bit width support, and further improving the transmission efficiency and overall performance of the on-chip network.

[0081] Combine Figure 6 As shown, the embodiment of the present disclosure also provides a device 600 for transmitting network-on-chip messages, including a processor 604 and a memory 601. Optionally, the system may further include a communication interface 602 and a bus 603. The processor 604, the communication interface 602, and the memory 601 may communicate with each other via the bus 603. The communication interface 602 may be used for information transmission. The processor 604 may call the logic instructions in the memory 601 to execute the method for transmitting network-on-chip messages of the above embodiment.

[0082] In addition, the logic instructions in the memory 601 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0083] Memory 601, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present disclosure. Processor 604 executes the program instructions / modules stored in memory 601 to execute functional applications and data processing, thereby implementing the on-chip network message transmission method in the above-mentioned embodiments.

[0084] The memory 601 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Furthermore, the memory 601 may include a high-speed random access memory and a non-volatile memory.

[0085] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute a method for transmitting network-on-chip (NOC) messages.

[0086] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0087] The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of the embodiments of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program code, or a transient storage medium.

[0088] The above description and accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Unless expressly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replaced with portions and features of other embodiments. As used in the description of the embodiments, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms as well. Similarly, the term "and / or" as used in this application means including any and all possible combinations of one or more of the associated listed items. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. In the absence of further limitations, the phrase "comprising a..." does not preclude the presence of other identical elements in the process, method, or device comprising the elements. In this document, each embodiment may focus on the differences from other embodiments, and similar parts between the embodiments can be referenced to each other. For methods, products, etc. disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referenced to the description of the method section.

[0089] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units can be merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, the functional units in the embodiments of the present disclosure may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0090] The flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the systems, methods and computer program products according to the embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of the code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in an order different from that disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A method for transmitting network-on-chip messages, characterized in that: The method comprises: The processor uses parallel transmission to transmit parameters and data. The parameters are transmitted through the AXI-lite interface with the transmit control status register module and the receive control status register module, and the data is transmitted through the AXI-full interface with the AXI_Slave module. The sending control status register module and the AXI_Slave module respectively transmit the configuration parameters including the target address, source address, and number of messages and the data to the packet assembly module, which are packaged into the message format for transmission. The message is transmitted in the router module of each node; When the router module transmits the message to the depacketization module, it is depacketized and the configuration parameters and data including the destination address, source address, and message quantity are transmitted to the sending control status register module and the AXI_Slave module respectively.

2. The method according to claim 1, characterized in that The transmission process corresponding to the transmission method adopts a handshake protocol to ensure seamless connection and transmission stability of data, and the configuration parameters and data are transmitted separately in a parallel manner.

3. The method according to claim 1, characterized in that The message is transmitted using a bit width of 1026 bits and includes three types: Among them, the first type of Head_flit message includes the target node address, message quantity, and transaction type. It is used to transmit all parameters required in the entire process and is used for control and judgment during the NOC transmission process; the second type of Body_flit message transmits 1024 bits of data each time; the third type of Tail_flit message is used to transmit 1024 bits of data.

4. The method according to claim 3, characterized in that The three types of data represent a complete data packet, wherein the Head_flit message represents the beginning of the data packet and the Tail_flit message represents the end of the data packet, so that a complete data packet can be stably transmitted in the NOC.

5. The method according to claim 1, wherein The sending control status register module and the AXI_Slave module respectively transmit the configuration parameters including the target address, source address, and number of messages and the data to the packaging module and package them into the message format, including: When the Resp signal from the router module is high, the sending control status register module starts to transmit parameters; The Valid signal from the sending control status register module is generated into a single pulse period signal Valid_paulse. When the Valid_paulse signal is high, the parameters including the target node address, message quantity, and transaction type are spliced ​​into data Cont_data and sent to the add message type and send module; After adding the Head flag to the Cont_data signal, it forms a Head_flit message and sends it to the router module; When the Resp signal generated by the control signal module is high, the AXI_Slave module starts to send data and combines the Pkt_size signal from the message quantity calculation module and the Cont_sign signal from the control signal module. The Pkt_size signal is decremented by 1 after each message is sent. When the Cont_sign signal is high and Pkt_size>0, the Body flag is added to the data to form a Body_flit message and sent to the router module. When the Cont_sign signal is high and Pkt_size=0, the Tail flag is added to the data to form a Tail_flit message.

6. The method according to claim 5, characterized in that The method further comprises: The resp signal is used to control the data transmission. When the parameters arrive, the Resp signal level sent to the AXI_Slave module is set to 1 to prevent the data from being sent to the packet assembly module before the parameters.

7. The method according to claim 1, characterized in that The unpacking process includes: The state machine is in the starting state Rcsr_state, receiving the Resp signal from the receive control status register module. When the Resp signal is high, it receives the message from the router module and judges the message type. When it is a Head_flit message, it splits the corresponding message to obtain parameters including the target node address, message quantity, and transaction type, and sends them to the rcv_csr module, and sends the message quantity to the state machine.

8. The method according to claim 7, characterized in that The method further comprises: When the number of messages = 0, maintain the current state Rcsr_state; when the number of messages > 0, enter the Slave_state state and start receiving the Resp signal from the AXI_slave module. When the Resp signal is high, split the Body_flit and Tail_flit from the router module in turn, obtain the data and send it to the AXI_slave module. At this time, the state is converted according to the flit type. When the flit type is Body, maintain the Slave_state state. When the flit type is Tail, convert to the Rcsr_state state.

9. An electronic device, characterized in that: include: at least one processor; and a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-8.

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