Method for realizing cross-chip unified memory space access based on Ethernet

Abstract

The invention discloses a method for realizing cross-chip unified memory space access based on Ethernet, which comprises the following steps: an on-chip network of a source chip in an HBD domain receives a bus data request message of cross-chip access in the HBD domain sent by a source computing unit of the chip, a corresponding C2C subsystem sending the bus data request message to a source chip obtains a chip ID of a target chip according to target address information carried in the bus data request message, obtains a target MAC address according to the chip ID of the target chip, converts the bus data request message into an Ethernet message load, carries out Ethernet head packaging, and sends the Ethernet message load to the source chip; the obtained Ethernet data message is sent to an exchange chip through a C2C subsystem physical layer; and the C2C subsystem of the target chip receives the Ethernet data message from the exchange chip, judges that the target MAC is the own MAC address, strips the Ethernet head package, restores the Ethernet message load into a bus data request message, and sends the bus data request message to the target calculation unit of the chip through the on-chip network of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of cross-chip memory access, and more particularly to a method for realizing cross-chip unified memory space access based on Ethernet. BACKGROUND

[0002] With the growth of the parameter scale of AI large models, the computing power demand for computing power chips is rapidly growing, and the computing power of current single computing power chip is significantly lagging behind the development of the parameter quantity of large models. The specific form of AI chips can be GPU, TPU, NPU, CGRA, etc. AI clusters are usually used to meet the computing power demand. AI clusters use distributed computing technology to decompose training tasks into multiple subtasks, assign them to different computing nodes for parallel processing. By using a high-speed interconnection network (Scale-up network) with super large bandwidth, multiple AI chips are interconnected together to form a HBD (High Bandwidth Domain, HBD), so as to improve the computing efficiency of multiple computing power chips. This is a common AI cluster design method in the industry. Within the HBD domain, some parts are generally used to process high-frequency data interaction, such as tensor parallelism and expert parallelism. These parallel communication traffic needs a high-speed, low-latency interconnection network to handle it in order to reduce communication costs. In addition, in order to improve programming ease of use and access efficiency, memory space unified addressing and memory semantic access instructions such as Load / Store (L / S) are also needed to implement data movement between remote memory and registers / cache. Through the Load operation, the required instructions or data are moved from the main memory to the vicinity of the AI chip core processing unit, so as to facilitate fast access and processing of the data. Store is used to write the results processed by the AI chip computing unit back to the memory.

[0003] The interface for directly interconnecting or interconnecting through a switching chip between AI chips in a high bandwidth domain is called a C2C (chip to chip) interface. The C2C subsystem of NVIDIA supports a private NVLINK protocol. Since the Ethernet standard is open, it has good interoperability and the port rate evolves quickly. However, its interconnection between super-node internal computing power chips based on Ethernet technology only supports Roce protocol and RDMA semantics, and does not support memory semantic access instructions such as load / store. SUMMARY

[0004] In view of the deficiencies of the prior art, the present application provides a method for realizing cross-chip unified memory space access based on Ethernet.

[0005] According to one aspect of the present application, a method for realizing cross-chip unified memory space access based on Ethernet is provided, comprising:

[0006] The on-chip network of the source chip in the HBD domain receives a bus data request message sent by the source computing unit of the chip, which is sent to the corresponding C2C subsystem on the source chip for cross-chip access in the HBD domain;

[0007] The corresponding C2C subsystem on the source chip obtains the chip ID of the destination chip according to the destination address information carried in the bus data request message, obtains the destination MAC address according to the chip ID of the destination chip, converts the bus data request message into an Ethernet message payload, performs Ethernet header encapsulation, and sends the obtained Ethernet data message to the switch chip through the C2C subsystem physical layer. The destination address information includes the memory space address of the destination computing unit, and the destination MAD address carries the chip ID of the destination chip.

[0008] The C2C subsystem of the destination chip receives the Ethernet data message from the switch chip, judges that the destination MAC is the MAC address of itself, removes the Ethernet header encapsulation, then restores the Ethernet message payload into a bus data request message, and sends the bus data request message to the destination computing unit of the chip through the on-chip network of the chip.

[0009] Among them, all chips in the HBD domain are allocated with a unique chip ID, and all chips are uniformly addressed in the HBD domain. The memory space address of each computing unit of each chip contains the chip ID of the chip.

[0010] Optionally, the bus data request message carries a transaction ID and a source MAC address, and the method further comprises:

[0011] The C2C subsystem of the destination chip records the transaction ID and the source MAC address carried in the bus data request message;

[0012] After the destination computing unit processes the bus data request message, a bus data response message is sent, and the bus data response message carries a transaction ID;

[0013] The on-chip network of the destination chip forwards the bus data response message to the C2C subsystem of the destination chip;

[0014] The C2C subsystem of the destination chip converts the bus data response message into an Ethernet message payload, finds the corresponding source MAC address according to the transaction ID, sets the source MAC address as the destination MAC address of the bus data response message, sets the MAC address of the C2C subsystem of the C2C subsystem as the source MAC address of the bus data response message, then performs Ethernet header encapsulation, and sends the bus data response message to the switch chip through the C2C subsystem physical layer.

[0015] Optionally, the memory space address of the computing unit includes a chip ID, a computing unit ID, and a memory address.

[0016] Optionally, the destination MAC address is obtained according to the chip ID of the destination chip, comprising:

[0017] a mapping relationship table of the chip ID and the MAC address is searched to determine the destination MAC address corresponding to the chip ID of the destination chip; or,

[0018] the destination MAC address containing the chip ID of the destination chip is generated according to a predetermined rule.

[0019] Optionally, the method further comprises:

[0020] the Eth type of the Ethernet data packet is identified by the switching chip, and the priority of the Ethernet data packet is determined according to the Eth type, and the Ethernet data packet is forwarded to the destination chip according to the priority.

[0021] Optionally, if the source chip has multiple C2C subsystems, the on-chip network of the source chip implements load balancing of traffic among different C2C subsystems according to a pre-configured address interleaving algorithm, wherein the address interleaving method is based on low-bit address interleaving or based on a hash algorithm.

[0022] According to another aspect of the present application, a device for realizing cross-chip unified memory space access based on Ethernet is provided, comprising:

[0023] a receiving module, configured to receive, by the on-chip network of the source chip in the HBD domain, a bus data request packet for cross-chip access in the HBD domain sent by the source computing unit of the chip, and send the bus data request packet to the corresponding C2C subsystem on the source chip;

[0024] an obtaining module, configured to obtain, by the corresponding C2C subsystem on the source chip, the chip ID of the destination chip according to the destination address information carried in the bus data request packet, obtain the destination MAC address according to the chip ID of the destination chip, convert the bus data request packet into an Ethernet packet payload, perform Ethernet header encapsulation, and send the obtained Ethernet data packet to the switching chip through the C2C subsystem physical layer, wherein the destination address information comprises the memory space address of the destination computing unit, and the destination MAC address carries the chip ID of the destination chip;

[0025] a judging module, configured to receive, by the C2C subsystem of the destination chip, the Ethernet data packet from the switching chip, judge that the destination MAC is the MAC address of itself, remove the Ethernet header encapsulation, then restore the Ethernet packet payload into the bus data request packet, and send the bus data request packet to the destination computing unit of the chip through the on-chip network of the chip.

[0026] In the present application, all chips in the HBD domain are assigned a unique chip ID, and all chips are uniformly addressed in the HBD domain, and the memory space address of each computing unit of each chip contains the chip ID of the chip.

[0027] According to still another aspect of the present application, there is provided a computer readable storage medium storing a computer program for performing the method according to any one of the preceding aspects of the present application.

[0028] According to still another aspect of the present application, there is provided an electronic device comprising: a processor; a memory for storing instructions executable by the processor; and the processor configured to read the executable instructions from the memory and execute the instructions to implement the method according to any one of the preceding aspects of the present application.

[0029] Thus, the present application uniformly addresses the chip memory space within the HBD domain, and for the data message accessed across chips, the destination chip ID and Ethernet MAC address are one-to-one mapped and the original message is encapsulated with an Ethernet header, and sent to the destination chip through an external Ethernet network, thereby realizing cross-chip interconnection based on uniform memory semantics, which helps to improve the C2C interconnection bandwidth between two chips and improve reliability. BRIEF DESCRIPTION OF DRAWINGS

[0030] The exemplary embodiments of the present application can be more fully understood with reference to the following drawings:

[0031] Figure 1 is a flowchart of a method for realizing cross-chip uniform memory space access based on Ethernet according to an exemplary embodiment of the present application;

[0032] Figure 2a is a schematic diagram of a chip interconnection architecture through Ethernet switching according to an exemplary embodiment of the present application;

[0033] Figure 2b is a schematic diagram of a single chip architecture according to an exemplary embodiment of the present application;

[0034] Figure 3 is a schematic diagram of a chip memory space uniform addressing method according to an exemplary embodiment of the present application;

[0035] Figure 4 is a schematic diagram of realizing traffic load sharing when accessing across chips according to an exemplary embodiment of the present application;

[0036] Figure 5 、 Figure 6 and Figure 7 is a schematic diagram of a mapping method for multiple target MACs according to an exemplary embodiment of the present application;

[0037] Figure 8 is a schematic diagram of a device for realizing cross-chip uniform memory space access based on Ethernet according to an exemplary embodiment of the present application;

[0038] Figure 9 is a structure of an electronic device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0039] Hereinafter, exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. It should be apparent that these described embodiments are merely exemplary of the present application and should not be considered limiting the scope of the present application. Therefore, the disclosure of these exemplary embodiments is intended to be illustrative, and not to be limiting of the scope of the present application.

[0040] It should be noted that the relative arrangement of the components and steps, numbers expressed, and numerical values shown in these embodiments are not limitations of the scope of the present application unless otherwise specifically stated.

[0041] Those skilled in the art can understand that the terms "first", "second" and the like in the embodiments of the present application are only used to distinguish different steps, devices or modules and the like, neither represent any specific technical meaning nor indicate their logical order.

[0042] It should also be understood that "a plurality of" in the embodiments of the present application can mean two or more, and "at least one" can mean one, two or more.

[0043] It should also be understood that for any component, data or structure mentioned in the embodiments of the present application, one or more can be generally understood unless specifically limited or given the opposite implication by the context.

[0044] In addition, the term "and / or" in the present application is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. In addition, the character " / " in the present application generally represents an "or" relationship between the front and rear associated objects.

[0045] It should also be understood that the description of each embodiment of the present application emphasizes the differences between each embodiment, and the same or similar parts can be referred to each other, and for the sake of brevity, will not be repeated.

[0046] At the same time, it should be understood that, for the convenience of description, the size of each part shown in the drawings is not drawn according to the actual proportion relationship.

[0047] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way limiting of the scope of the application or its applications or uses.

[0048] Techniques, methods, and apparatus known to those of ordinary skill in the relevant art can not be discussed in detail herein, but should be considered as part of the specification for the present application.

[0049] It should be noted that like numerals and letters refer to like items throughout the drawings, and once an item is defined in one drawing, further discussion of that item need not occur in subsequent drawings.

[0050] Embodiments of the present application can be applied to terminal devices, computer systems, servers, and other electronic devices, which can operate with many other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with terminal devices, computer systems, servers, and other electronic devices include, but are not limited to, personal computers, server computers, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, minicomputers, mainframe computers, and distributed cloud computing technology environments that include any of the above systems, and the like.

[0051] Terminal devices, computer systems, servers, and other electronic devices can be described in the general context of computer system-executable instructions, such as program modules, being executed by the computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, and the like, which perform particular tasks or implement particular abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules can be located in local or remote computer system storage media including storage devices.

[0052] Exemplary method

[0053] Figure 1 The flowchart of the method for implementing cross-chip unified memory space access based on Ethernet provided by an exemplary embodiment of the present application is shown. The present embodiment can be applied to electronic devices such as Figure 1 As shown in the figure, the method 100 for implementing cross-chip unified memory space access based on Ethernet includes the following steps:

[0054] In step 101, the on-chip network of the source chip in the HBD domain receives a bus data request packet for cross-chip access in the HBD domain sent by the source computing unit of the chip, and sends it to the corresponding C2C subsystem on the source chip.

[0055] Step 102, the corresponding C2C subsystem on the source chip acquires the chip ID of the destination chip according to the destination address information carried in the bus data request message, obtains the destination MAC address according to the chip ID of the destination chip, converts the bus data request message into an Ethernet message payload, performs Ethernet header encapsulation, and sends the obtained Ethernet data message to the switching chip through the C2C subsystem physical layer; the destination address information includes the memory space address of the destination computing unit, and the destination MAD address carries the chip ID of the destination chip.

[0056] Step 103, the C2C subsystem of the destination chip receives the Ethernet data message from the switching chip, judges that the destination MAC is the own MAC address, removes the Ethernet header encapsulation, then restores the Ethernet message payload into the bus data request message, and sends the bus data request message to the destination computing unit of the chip through the on-chip network of the chip.

[0057] Wherein, all chips in the HBD domain are allocated with a unique chip ID, and all chips are uniformly addressed in the HBD domain, and the memory space address of each computing unit of each chip contains the chip ID of the chip.

[0058] Specifically, in view of the technical problems in the background art, the application realizes the interconnection between AI chips through the C2C subsystem and the standard Ethernet switching chip, wherein the AI chip can be but is not limited to a GPU chip. The embodiment of the application takes the GPU chip as an example to describe the invention content. The memory spaces of the GPU chips are uniformly addressed, and the memory space uniform access is supported through the Load / Store, DMA (direct memory access) and other instructions. The C2C subsystem can automatically add an Ethernet header according to the inter-chip access content, so that it can pass through the Ethernet network to reach the destination chip and continue to perform the on-chip forwarding. In addition, the load sharing of the memory space access traffic between the AI chips is supported. The end-to-end reliability and congestion control of the access traffic between the AI chips are supported.

[0059] The specific implementation process is as follows:

[0060] 1. As shown in Figure 2a and Figure 2b , the GPU chips in each HBD domain are not directly connected through the C2C subsystem, but are connected to the Ethernet switching chip through the C2C subsystem, and the interconnection between the GPU chips is realized through the Ethernet switching chip. The upper layer protocol carried by the C2C subsystem is the load / store, DMA (direct memory access) and other memory semantic access instructions. As shown in Figure 2b , the C2C subsystem and the computing unit are not in one-to-one correspondence, and the number of C2C subsystems is M.

[0061] Each GPU chip contains a computing unit AI Core, a network on chip NoC Router, a C2C subsystem, an AI Core processing matrix and convolution operations, and has a local memory, a cache and a register. The network on chip Router performs intra-chip or inter-chip routing based on a memory address. The C2C subsystem includes address mapping, an Ethernet MAC layer and a physical layer processing function.

[0062] 2. The chip ID in the HBD domain is uniformly addressed, such as from 1 to 128, to ensure that the chip ID is unique in the scale up domain. The entire HBD domain memory space extended by the C2C interconnection is uniformly addressed, and the respective physical address spaces of different chips are distinguished by the chip ID.

[0063] Further, the entire HBD domain memory space extended by the C2C interconnection is uniformly addressed, and the respective physical address spaces of different chips are distinguished by the chip ID (chip ID). For example, if 4K chips are interconnected, each chip contains 4 computing units, and each computing unit has 1 GB of physical memory, a high 12-bit chip ID can be used, followed by 2 bits representing an AI Core ID, and a low 30-bit physical memory space address of each AI Core. The uniform addressing mode is as shown in Figure 3 .

[0064] 3. Each C2C subsystem is pre-configured with a MAC address, and the MAC address and the chip ID of the chip can be one-to-one mapped.

[0065] 4. The C2C subsystem receives a cross-chip memory space access data packet sent by the NoC, and according to the target chip ID, if it is not the chip ID of the chip, a target MAC is generated according to the configured MAC prefix and the target chip ID, or a pre-configured chip ID and MAC one-to-one mapping table item is searched, the source MAC is the MAC of the C2C subsystem, the Eth type corresponding to the C2C communication is set, the Ethernet header is encapsulated (including the source MAC and the destination MAC), and then sent out through the C2C subsystem physical layer.

[0066] 5. After the Ethernet switch chip receives the data packet, it is forwarded based on the target MAC, and the packet is sent to the target GPU chip. The chip can perform high-priority forwarding of the packet by recognizing the Eth type.

[0067] 6. The target GPU chip judges that the packet target MAC is itself, then removes the Ethernet header, restores the original data packet, and sends it to the NoC for further intra-chip forwarding and access to the corresponding memory space.

[0068] In one embodiment of the present application, the implementation process of cross-chip access based on Ethernet is as follows:

[0069] 1. The on-chip network NoC receives the memory semantic data packet sent by the AI chip 1 through the on-chip interconnection interface, finds the routing table item according to the target memory address in the packet header, judges that the target chip ID is not equal to the chip chip ID, and then sends the packet to the off-chip through the C2C subsystem. The packet is sent to the C2C processing module. If there are multiple C2C subsystems, the traffic load balancing between different C2C subsystems can be realized according to the configured address interleaving algorithm.

[0070] Specifically, for the case that a chip has multiple C2C subsystems, the on-chip network NoC Router on the chip can load share between different C2C subsystems based on the access address through the address interleaving method. Each C2C subsystem is still mapped to the target MAC address based on the chip ID and sent to the external Ethernet network. The specific example of traffic load sharing during cross-chip access is shown in Figure 4

[0071] Through the interconnection of multiple C2C subsystems, the interconnection bandwidth between chips can be improved, which is conducive to improving the data transfer efficiency between chips. At this time, multiple C2C subsystems can still be interconnected through an Ethernet switch. All C2C subsystems of the chip can be used for interconnection between any two chips, which helps to improve the C2C interconnection bandwidth between two chips and improve the reliability. Figure 4 In the above embodiment, the communication between the AI Core of chip 1 and chip 2 can be load shared between 8 C2C subsystems.

[0072] 1) The NoC on the AI chip can load share between different C2C subsystems based on the access address through the address interleaving method. The address interleaving granularity (256B, 512B, 1KB, 2KB…) can be dynamically configured. The interleaving method can be based on low address interleaving or based on hash algorithm:

[0073] a. When interleaving based on low address, the specific C2C port is selected based on the address bits above the interleaving granularity, for example, there are 8 C2C ports, and the interleaving granularity is 4KB. The address PA[14:12] is taken to determine the C2C subsystem.

[0074] b. When interleaving based on hash, the specific C2C port is selected based on the hash value of the effective address bits, for example, there are 8 C2C ports, and the interleaving granularity is 4KB. The value of PA[14:12]^PA[17:15]^PA[20:18]... hash is taken to determine the C2C subsystem.

[0075] ​2) When the NoC Router receives a cross-chip access data packet, the NoC Router looks up the NoC forwarding table item according to the memory address accessed, and sends the packet to the corresponding C2C subsystem.

[0076] 2. The C2C subsystem obtains the chip ID of the access target, obtains the target MAC, encapsulates the Ethernet header, and then sends the packet to the Ethernet switch chip through the physical layer. When encapsulating, the corresponding EthType can also be carried according to the configuration (used for high-priority scheduling, fault positioning, and other processing of the switch chip according to the EthType). According to the configured MAC address prefix, the destination address (i.e., the MAC address) containing the chip ID of the destination chip can be generated according to a predetermined rule, as shown in Figure 5 or Figure 6 The MAC address of the destination chip can also be obtained by looking up the mapping table item as shown in Figure 7

[0077] 3. After the Ethernet switch chip receives the packet from the port connected to chip 1, the Ethernet switch chip looks up the forwarding table item according to the target MAC, and sends the data packet from the port connected to chip 2.

[0078] 4. After chip 2 receives the packet, it is determined that the target MAC is the local port MAC, and the Ethernet packet is terminated, i.e., the Ethernet header is removed, and the original memory semantic packet is sent to the NoC of the destination chip.

[0079] 5. The NoC on the destination chip performs intra-chip forwarding based on the memory access address of the data packet, and sends the packet to the target AI Core 2 according to the AI Core ID for processing.

[0080] Thus, the application uniformly addresses the chip memory space in the HBD domain, and for a cross-chip access data packet, the destination chip ID and the Ethernet MAC address are one-to-one mapped and the original packet is encapsulated with an Ethernet header, and then sent to the destination chip through an external Ethernet network, thereby realizing cross-chip interconnection based on a unified memory semantic, which helps to improve the C2C interconnection bandwidth between two chips and improve reliability.

[0081] Exemplary apparatus

[0082] Figure 8 is a structural schematic diagram of an apparatus for realizing cross-chip unified memory space access based on Ethernet provided by an exemplary embodiment of the application. As shown in Figure 8 , the apparatus 800 includes:

[0083] ​The receiving module 810 is configured to receive, by an on-chip network of a source chip in an HBD domain, a bus data request packet transmitted by a source computing unit of the chip, the bus data request packet being for cross-chip access in the HBD domain and being sent to a corresponding C2C subsystem of the source chip;

[0084] The obtaining module 820 is configured to obtain, by the corresponding C2C subsystem of the source chip, a chip ID of a destination chip according to destination address information carried in the bus data request packet, obtain a destination MAC address according to the chip ID of the destination chip, convert the bus data request packet into an Ethernet packet payload, perform Ethernet header encapsulation, and send the obtained Ethernet data packet to the switch chip through a C2C subsystem physical layer, the destination address information including a memory space address of a destination computing unit, and the destination MAC address carrying the chip ID of the destination chip.

[0085] The judging module 830 is configured to receive, by the C2C subsystem of the destination chip, the Ethernet data packet from the switch chip, judge that the destination MAC is a MAC address of the C2C subsystem, remove the Ethernet header encapsulation, restore the Ethernet packet payload into the bus data request packet, and send the bus data request packet to the destination computing unit of the chip through the on-chip network of the chip.

[0086] In the HBD domain, all chips are assigned a unique chip ID, and all chips are uniformly addressed in the HBD domain, and the memory space address of each computing unit of each chip includes the chip ID of the chip.

[0087] Optionally, the bus data request packet carries a transaction ID and a source MAC address, and the device 800 further includes:

[0088] The recording module is configured to record, by the C2C subsystem of the destination chip, the transaction ID and the source MAC address carried in the bus data request packet.

[0089] The sending module is configured to send, by the destination computing unit, a bus data response packet after processing the bus data request packet, the bus data response packet carrying the transaction ID.

[0090] The forwarding module is configured to forward, by the on-chip network of the destination chip, the bus data response packet to the C2C subsystem of the destination chip.

[0091] The setting module is configured to convert, by the C2C subsystem of the destination chip, the bus data response packet into an Ethernet packet payload, find the corresponding source MAC address according to the transaction ID, set the source MAC address as a destination MAC address of the bus data response packet, set a MAC address of the C2C subsystem of the C2C subsystem of the chip as a source MAC address of the bus data response packet, perform Ethernet header encapsulation, and send the bus data response packet to the switch chip through the C2C subsystem physical layer.

[0092] Optionally, the memory space address of the computing unit comprises a chip ID, a computing unit ID and a memory address.

[0093] Optionally, the obtaining of the destination MAC address according to the chip ID of the destination chip in the obtaining module 820 comprises:

[0094] The finding sub-module is configured to find a pre-configured mapping relationship table of chip ID and MAC address, and determine the destination MAC address corresponding to the chip ID of the destination chip; or,

[0095] The generating sub-module is configured to generate the destination MAC address containing the chip ID of the destination chip according to a predetermined rule.

[0096] Optionally, the apparatus 800 further comprises:

[0097] The identifying module is configured to exchange the Eth type of the Ethernet data packet of the chip, and determine the priority of the Ethernet data packet according to the Eth type, and forward the Ethernet data packet to the destination chip according to the priority.

[0098] Optionally, if the source chip has multiple C2C subsystems, the on-chip network of the source chip implements load balancing of traffic among different C2C subsystems according to a pre-configured address interleaving algorithm, wherein the address interleaving method is based on low-bit address interleaving or based on a hash algorithm.

[0099] Exemplary electronic device

[0100] Figure 9 The electronic device 90 is an example of an electronic device provided by an example embodiment of the present disclosure. As shown in FIG. 1, the electronic device 90 includes one or more processors 91 and a memory 92. Figure 9

[0101] The processor 91 can be a central processing unit (CPU) or other form of processing unit that has data processing and / or instruction execution capabilities, and can control other components in the electronic device to perform desired functions.

[0102] ​The memory 92 can include one or more computer program products that can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory, for example, can include random access memory (RAM), cache memory, and / or the like. The non-volatile memory, for example, can include read only memory (ROM), hard disk, flash memory, and / or the like. One or more computer program instructions can be stored on the computer-readable storage media, and the processor 91 can execute the program instructions to implement the methods of the software programs of the various embodiments of the present application described above and / or other desired functions. In one example, the electronic device can further include an input device 93 and an output device 94, which are interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0103] In addition, the input device 93 can include, for example, a keyboard, a mouse, and / or the like.

[0104] The output device 94 can output various information to the outside. The output device 94 can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and / or the like.

[0105] Of course, in order to simplify, Figure 9 Only some of the components of the electronic device related to the present application are shown in FIG. 1, and components such as a bus, an input / output interface, and the like are omitted. In addition to this, the electronic device can further include any other appropriate components according to the specific application.

[0106] Exemplary computer program product and computer readable storage medium

[0107] In addition to the above-mentioned methods and devices, embodiments of the present application can also be a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods according to various embodiments of the present application described in the above "Exemplary Methods" section of the specification.

[0108] The computer program product can be written in any combination of one or more programming languages, including an object-oriented programming language such as Java, C++, and / or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote cloud device or server.

[0109] In addition, an embodiment of the present application can also be a computer readable storage medium, having stored thereon computer program instructions which, when executed by a processor, cause the processor to carry out the steps described in the above "Exemplary Method" section of this specification of the methods according to various embodiments of the present application.

[0110] The computer readable storage medium can be any combination of one or more computer readable medium(s). The computer readable medium can be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, or apparatus or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0111] The above describes the basic principles of the present application in conjunction with specific embodiments, but it should be noted that the advantages, benefits, effects and the like mentioned in the present application are only examples and are not limiting, and these advantages, benefits, effects and the like cannot be considered as necessary for each embodiment of the present application. In addition, the above specific details are only for the purpose of example and for the purpose of understanding, and are not limiting, and the above details do not limit the present application to the above specific details.

[0112] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between each embodiment can be mutually referred to. For system embodiments, since they basically correspond to method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0113] The block diagrams of the devices, systems, apparatuses, systems involved in the present application are only illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be as shown in the block diagrams. As those skilled in the art will recognize, these devices, systems, apparatuses, systems can be connected, arranged, configured in any manner. Words such as "include", "contain", "have" and the like are open-ended words, mean "including but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.

[0114] The methods and systems of the present invention may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of the present invention are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, the present invention may also be implemented as a program recorded on a recording medium, the program comprising machine-readable instructions for implementing the methods according to the present invention. Thus, the present invention also covers recording media storing programs for performing the methods according to the present invention.

[0115] It should also be noted that in the systems, apparatus, and methods of the present invention, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered equivalents of the present invention. The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the invention. Therefore, the invention is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0116] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the invention to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method for achieving cross-chip unified memory space access based on Ethernet, characterized in that, include: The on-chip network of the source chip within the HBD domain receives a bus data request message for cross-chip access within the HBD domain sent by the source computing unit of this chip, and sends it to the corresponding C2C subsystem on the source chip. The C2C subsystem on the source chip obtains the chip ID of the destination chip based on the destination address information carried in the bus data request message, obtains the destination MAC address based on the destination chip ID, converts the bus data request message into an Ethernet message payload, performs Ethernet header encapsulation, and sends the obtained Ethernet data message to the switching chip through the physical layer of the C2C subsystem. The destination address information includes the memory space address of the destination computing unit, and the destination MAC address carries the chip ID of the destination chip. The C2C subsystem of the destination chip receives an Ethernet data packet from the switching chip, determines that the destination MAC is its own MAC address, removes the Ethernet header encapsulation, and then restores the Ethernet packet payload into a bus data request packet, which is then sent to the destination computing unit of the chip through the chip's on-chip network. In this context, all chips within the HBD domain are assigned a unique chip ID, and all chips are uniformly addressed in the HBD domain. The memory space address of each computing unit of each chip contains the chip ID of that chip.

2. The method according to claim 1, characterized in that, The bus data request message carries a transaction ID and a source MAC address, and the method further includes: The target chip's C2C subsystem associates and records the transaction ID and source MAC address carried in the bus data request message; After the destination computing unit completes processing the bus data request message, it sends a bus data response message, which carries the transaction ID. The on-chip network of the destination chip forwards the bus data response message to the C2C subsystem of the destination chip; The destination chip's C2C subsystem converts the bus data response message into an Ethernet message payload, finds the corresponding source MAC address based on the transaction ID, sets the source MAC address as the destination MAC address of the bus data response message, sets the MAC address of this C2C subsystem as the source MAC address of the bus data response message, encapsulates it with an Ethernet header, and sends it to the switching chip through the C2C subsystem's physical layer.

3. The method according to claim 1, characterized in that, The memory space address of the computing unit includes: chip ID, computing unit ID, and memory address.

4. The method according to claim 3, characterized in that, Obtain the destination MAC address based on the chip ID of the destination chip, including: Look up the pre-configured mapping table between chip IDs and MAC addresses to determine the destination MAC address corresponding to the chip ID of the target chip; or, According to predetermined rules, a destination MAC address containing the chip ID of the target chip is generated.

5. The method according to claim 4, characterized in that, Also includes: The switching chip identifies the Eth type of the Ethernet data packet, determines the priority of the Ethernet data packet based on the Eth type, and forwards the Ethernet data packet to the destination chip according to the priority.

6. The method according to claim 1, characterized in that, If the source chip has multiple C2C subsystems, the on-chip network of the source chip achieves load balancing of traffic among different C2C subsystems according to a pre-configured address interleaving algorithm, wherein the address interleaving method is based on low-bit address interleaving or based on a hash algorithm.

7. A device for enabling cross-chip unified memory space access based on Ethernet, characterized in that, include: The receiving module is used to receive bus data request messages for cross-chip access within the HBD domain from the source computing unit of the source chip within the HBD domain, and then send them to the corresponding C2C subsystem on the source chip. The acquisition module is used by the C2C subsystem on the source chip to obtain the chip ID of the destination chip based on the destination address information carried in the bus data request message, obtain the destination MAC address based on the chip ID of the destination chip, convert the bus data request message into an Ethernet message payload, encapsulate it with an Ethernet header, and send the obtained Ethernet data message to the switching chip through the physical layer of the C2C subsystem. The destination address information includes the memory space address of the destination computing unit, and the destination MAC address carries the chip ID of the destination chip. The judgment module is used when the C2C subsystem of the destination chip receives an Ethernet data packet from the switching chip, determines that the destination MAC is its own MAC address, removes the Ethernet header encapsulation, and then restores the Ethernet packet payload into a bus data request packet, which is then sent to the destination computing unit of the chip through the chip's on-chip network. In this context, all chips within the HBD domain are assigned a unique chip ID, and all chips are uniformly addressed in the HBD domain. The memory space address of each computing unit of each chip contains the chip ID of that chip.

8. The apparatus according to claim 7, characterized in that, The bus data request message carries a transaction ID and a source MAC address. The device also includes: The recording module is used to associate and record the transaction ID and source MAC address carried in the bus data request message of the destination chip's C2C subsystem. The sending module is used to send a bus data response message after the destination computing unit has finished processing the bus data request message, wherein the bus data response message carries the transaction ID; The forwarding module is used for the on-chip network of the destination chip to forward the bus data response message to the C2C subsystem of the destination chip; The configuration module is used by the C2C subsystem of the destination chip to convert the bus data response message into an Ethernet message payload, find the corresponding source MAC address according to the transaction ID, set the source MAC address as the destination MAC address of the bus data response message, set the MAC address of the C2C subsystem as the source MAC address of the bus data response message, encapsulate the Ethernet header, and send it to the switching chip through the physical layer of the C2C subsystem.

9. A computer-readable storage medium, characterized in that, The storage medium stores a computer program for performing the method described in any one of claims 1-6.

10. An electronic device, characterized in that, The electronic device includes: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method described in any one of claims 1-6.

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