EtherCAT data link layer communication method and device based on bare computer system

Abstract

The invention provides an EtherCAT data link layer communication method and device based on a bare computer system, and the method comprises the steps: an EtherCAT master station user program obtains pre-sent frame data in a master station memory space based on a cache mechanism, carries out the framing of the pre-sent frame data, and writes a data frame formed by the framing back to the memory space; the Ethernet controller obtains the data frames in the memory space through DMA copying, and sends the data frames to the EtherCAT slave station through an Ethernet physical layer chip; after the Ethernet physical layer chip receives the data frame sent by the EtherCAT slave station, the Ethernet controller writes the data frame into the memory space of the EtherCAT master station through DMA copy; and the EtherCAT master station user program obtains the data frames received in the memory space of the master station based on a cache mechanism, and writes the data frames back to the memory space after deframing the received data frames. Through the scheme, the load of the processor can be reduced, the frame data processing efficiency and stability of the master station are improved, and the real-time performance of the EtherCAT master station is guaranteed.

Description

Technical Field

[0001] The present invention belongs to the field of communication technology, and in particular relates to an EtherCAT data link layer communication method and device based on a bare metal system. Background Art

[0002] With the rapid development of industrial automation and robotic control technologies in recent years, traditional pulse-based and analog fieldbus control methods have become inadequate for current application requirements due to limitations in data transmission rates, insufficient communication bandwidth, long system response times, and poor scalability. To achieve high-speed, real-time control, new fieldbus systems based on Industrial Ethernet have rapidly become the mainstream development direction for industrial communications. By integrating standard Ethernet technology into industrial control systems, these new industrial fieldbuses, while retaining its low cost and broad compatibility, offer improved communication speeds and bandwidth capacity, enhanced network topology flexibility, and greater system integration capabilities. Beckhoff's EtherCAT (Ethernet for Control Automation Technology) protocol, with its low latency, high synchronization, and flexible architecture, has become one of the leading real-time Ethernet protocols. Currently, EtherCAT master systems are developing in two main directions: one is commercial software platforms such as TwinCAT, which have high functional completeness and maturity, but have limitations in software licensing, hardware adaptation, and technical openness; the other is open source master solutions built on Linux / Windows platforms, which overcome the technical limitations of solutions such as TwinCAT, have good versatility and scalability, and have broad prospects for domestic applications. However, in EtherCAT master systems built on general operating systems such as Linux and Windows, the data communication process faces performance bottlenecks caused by context switching and data copying, such as Figure 1 As shown in the figure, during data transmission, the master application needs to access the underlying network resources through system calls. Each call requires a context switch from user mode to kernel mode, and then returns to user mode after the task is completed. This process typically takes tens of nanoseconds to several microseconds to complete a single switch on a domestic chip platform. The resulting performance loss will reduce the processing efficiency of periodic process data, resulting in poor real-time performance of the master system.

[0003] Furthermore, data is copied twice in the transmit path: the CPU first copies user-space data to the kernel buffer, where it is then transferred by the DMA engine to the Ethernet controller's TXFIFO. In the receive path, data is similarly transferred from the RXFIFO to the kernel buffer and then back to user space. This CPU-involved data transfer consumes significant resources, increases the master station's response latency, and can also lead to poor real-time performance. Summary of the Invention

[0004] In view of this, an embodiment of the present invention provides an EtherCAT data link layer communication method and apparatus based on a bare metal system, which is used to solve the problem of poor real-time performance of the current EtherCAT master station.

[0005] In a first aspect of an embodiment of the present invention, a bare metal system-based EtherCAT data link layer communication method is provided, comprising: The EtherCAT master user program obtains the pre-sent frame data in the master memory space based on the cache mechanism, frames the pre-sent frame data, and writes the framed data back to the memory space. The Ethernet controller obtains the data frame in the memory space through DMA copy and sends the data frame to the EtherCAT slave through the Ethernet physical layer chip; Correspondingly, after the Ethernet physical layer chip receives the data frame sent by the EtherCAT slave, the Ethernet controller writes the data frame into the EtherCAT master memory space through DMA copy; The EtherCAT master user program obtains the received data frames in the master memory space based on the cache mechanism, deframes the received data frames, and writes the data frames back to the memory space.

[0006] In a second aspect of an embodiment of the present invention, an EtherCAT data link layer communication device based on a bare metal system is provided, including an EtherCAT master station and an EtherCAT slave station, wherein the EtherCAT master station includes: The EtherCAT master user program is configured to obtain, based on a high-speed cache mechanism, pre-sent frame data in the master memory space during data transmission and to frame the pre-sent frame data; and, based on a high-speed cache mechanism, to obtain received data frames in the master memory space and to deframe the received data frames during data reception. The master station memory is used to store pre-sent frame data and cache the data frames formed by framing, as well as cache the data frames sent by the EtherCAT slave station and store the frame data after deframing; The Ethernet controller is configured to obtain data frames in the master station memory space through DMA copying and transmit the data frames to the Ethernet physical layer chip; and write the received data frames into the master station memory space through DMA copying; Ethernet physical layer chip, used to send data frames to EtherCAT slaves or receive data frames sent by EtherCAT slaves.

[0007] In a third aspect of an embodiment of the present invention, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the steps of the method described in the first aspect of the embodiment of the present invention when executing the computer program.

[0008] In a fourth aspect of an embodiment of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method provided in the first aspect of the embodiment of the present invention are implemented.

[0009] In an embodiment of the present invention, by skipping the traditional operating system's user-mode and kernel-mode switching paths and directly accessing underlying hardware resources based on cache, the overhead associated with context switching is eliminated, a zero-copy data interaction path is constructed, and data copy operations involving the CPU are avoided, thereby improving communication efficiency and responsiveness. During data transmission, the master station system directly transfers data between memory and the network interface through the Ethernet controller's built-in DMA engine, thereby reducing processor load and communication latency. This reduces master station response latency, improves frame data processing efficiency, ensures the real-time performance of the EtherCAT master station, and enhances the master station's stability and throughput in high-real-time scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 A schematic flow chart of an operating system-based EtherCAT data link layer communication method provided by one embodiment of the present invention; Figure 2 A schematic diagram of the principle of an EtherCAT data link layer communication method based on a bare metal system provided by one embodiment of the present invention; Figure 3A schematic flow chart of an EtherCAT data link layer communication method based on a bare metal system provided by one embodiment of the present invention; Figure 4 A schematic structural diagram of an EtherCAT data link layer communication system based on a bare metal system is provided in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0012] In order to make the purpose, features, and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0013] It should be understood that the terms "including" and similar expressions in the specification, claims, and drawings of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, or apparatus comprising a series of steps or units is not limited to the listed steps or units. Furthermore, the terms "first" and "second" are used to distinguish between different objects and are not intended to describe a specific order.

[0014] In one embodiment of the invention, Figure 2 The figure below provides a schematic diagram of the EtherCAT data link layer communication principle based on a bare-metal system. The figure shows an EtherCAT master station consisting of a master user program, master memory, an Ethernet controller, and an Ethernet physical layer chip. During data transmission, the EtherCAT master user program retrieves frame data from the master's memory, frames the frame data, writes the resulting data frame back to the memory, performs a DMA copy via the Ethernet controller, and transmits it via the Ethernet physical layer chip. During data reception, after the Ethernet physical layer chip receives a data frame from an EtherCAT slave, the Ethernet controller writes the data frame to the master's memory via DMA copy. The EtherCAT master user program retrieves the data frame from the memory, deframes it, and writes the deframed frame data back to the memory. This reduces processor load and communication latency, improving the real-time performance of the EtherCAT master station.

[0015] See also Figure 3 , a flowchart of an EtherCAT data link layer communication method based on a bare metal system provided by an embodiment of the present invention includes: S301, the EtherCAT master station user program obtains the pre-sent frame data in the master station memory space based on the cache mechanism, frames the pre-sent frame data, and writes the framed data back to the memory space; The EtherCAT master is the core control unit in an Ethernet communication system, responsible for coordinating and managing the slave devices in the entire EtherCAT network. It can send commands and monitor slave status. EtherCAT slaves receive and respond to master commands, reading and writing data or controlling devices. The EtherCAT master user program controls and manages the EtherCAT master, such as controlling the data sent by the master and parsing received data frames.

[0016] A cache mechanism is a technology that improves memory access efficiency and is implemented between the processor and main memory. Framing involves grouping and encapsulating pre-transmitted data into frames according to specific protocol rules. In this embodiment, the master user program can frame the pre-transmitted data based on the EtherCAT protocol.

[0017] S302, the Ethernet controller obtains the data frame in the memory space through DMA copy, and sends the data frame to the EtherCAT slave station through the Ethernet physical layer chip; Direct Memory Access (DMA) copying is a technology that allows hardware devices to directly access system memory without CPU intervention. In this embodiment, the DMA controller can directly access the EtherCAT master's memory and copy data frames for data transmission. The Ethernet physical layer chip is a highly integrated physical interface transceiver (PHY) used to receive and transmit data frames.

[0018] The data frames in the Ethernet controller are transmitted to the Ethernet physical layer chip based on the RGMII (Reduced Gigabit Media Independent Interface) interface.

[0019] S303, after the Ethernet physical layer chip receives the data frame sent by the EtherCAT slave station, the Ethernet controller writes the data frame into the memory space of the EtherCAT master station through DMA copy; S304 , the EtherCAT master station user program obtains the received data frame in the master station memory space based on the high-speed cache mechanism, deframes the received data frame, and writes the data frame back to the memory space.

[0020] In this embodiment, the master station application directly accesses the underlying hardware resources based on the cache, eliminating the overhead caused by context switching from user mode to kernel mode, and directly completes the transmission from memory to the network interface through the built-in DMA engine of the Ethernet controller, reducing the processor load and reducing communication delay, thereby improving the real-time performance of the EtherCAT master station and enhancing the efficiency and stability of the master station frame data processing.

[0021] It should be understood that the sequence numbers of the steps in the above embodiments do not imply a specific order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0022] In some embodiments, a descriptor state of a pre-sent data frame is configured, wherein the descriptor is used to represent a storage address, length, and owner information of the data frame; The data frame descriptor is stored in a non-cached memory mapping manner so that the DMA controller can directly access the latest data frame descriptor.

[0023] In some embodiments, a descriptor state of a received data frame is configured, wherein the descriptor is used to represent a storage address, length, and owner information of the data frame; The data frame descriptor is stored in a non-cached memory mapping manner to enable the EtherCAT master user program to directly access the latest data frame descriptor.

[0024] In the communication path based on the DMA mechanism to directly access the main memory, it is easy to cause inconsistency problems between the main memory and the cache data. If the processor has not refreshed the data in the cache back to the main memory, the DMA will start to read data from the main memory for the transmission of the EtherCAT frame, which may cause the data content to be invalid or erroneous; similarly, if the DMA completes data reception but does not synchronize it to the cache in time, it may also cause the processor to read old data. This type of cache inconsistency problem will affect the correctness of the communication data and the real-time response capability of the system. In this embodiment, the cache mechanism is enabled for the transmit and receive data buffer, and the spatial and temporal locality characteristics of the cache are used to accelerate the processor's access to the send and receive data; while for the transmit and receive descriptors, the cache is disabled, and a non-cached memory mapping method is used to ensure that the DMA controller can directly access the latest transmit and receive descriptors, avoiding data invalidation or communication anomalies due to cache lags. Through a hybrid storage mechanism that combines cache and non-caching, the accuracy and consistency of the DMA transmission process are guaranteed while improving data access. In one embodiment, a timer is constructed to periodically determine whether a data frame returned by the EtherCAT slave is received. The timer includes a primary timer and a secondary timer. The primary timer runs at a frequency of 1 MHz, and the secondary timer runs at a frequency of 1 Hz. If the waiting time exceeds a preset threshold, a reception error is reported and the waiting is suspended.

[0025] During master operation, after sending a data frame, the master station immediately enters a polling state, continuously monitoring the arrival of frames transmitted from the slave station. A timeout detection mechanism prevents infinite waiting and enables timely exit from the polling process. This embodiment employs a dual 32-bit timer cascade structure. The first-level timer runs at 1 MHz, providing 1 μs time resolution and triggering an update event once per second, which serves as the clock input for the second-level timer. The second-level timer counts at 1 Hz, accumulating system runtime in seconds. This cascade mechanism allows the system to achieve continuous timing of up to approximately 42.95 million seconds (approximately 136 years) while maintaining microsecond-level timing accuracy.

[0026] In one embodiment, based on a timer, the EtherCAT master uses an interrupt masking mechanism to execute periodic communication tasks.

[0027] Because periodic process data communication has strict hard real-time constraints, the master system must schedule communication tasks within a fixed period and maintain period jitter within ±10% to maintain control system stability and consistent response. To address this scheduling requirement, a communication task management mechanism based on timer interrupt triggering can be designed in bare-metal processor systems such as the RK3568. This mechanism uses an interrupt-driven strategy for task scheduling, independent of the traditional operating system scheduler. Periodic process data communication is tied to a high-precision timer interrupt, ensuring precise triggering of communication tasks according to the set period. Aperiodic mailbox communication tasks are then handled in an event-driven manner within the main loop, completing status queries and processing configuration instructions. This allows for time-sharing multiplexing and coordinated coordination of periodic and aperiodic communication tasks.

[0028] To ensure the atomicity of periodic process data communication, this embodiment employs an interrupt masking mechanism during periodic task execution. This mechanism temporarily masks global interrupts to isolate interference from other interrupt sources and prevent critical tasks from being interrupted during execution. Upon task completion, interrupt responsiveness is immediately restored, ensuring the timing accuracy of communication tasks while also balancing the overall system's interrupt responsiveness and execution efficiency.

[0029] Compared with traditional scheduling methods that rely on software schedulers and frequent memory reads and writes, this solution uses CPU hardware to automatically save and restore key contexts, with only the interrupt service routine handling necessary logic. This builds a context switching process that collaborates with software and hardware, reduces CPU resource usage and interrupt response latency, and improves the system's response speed and communication real-time performance under high-frequency tasks and sudden loads. Figure 4 A schematic structural diagram of an EtherCAT data link layer communication device based on a bare metal system provided in an embodiment of the present invention includes an EtherCAT master station 410 and an EtherCAT slave station 420. The EtherCAT master station 410 includes: The EtherCAT master user program 4101 is configured to obtain, based on a high-speed cache mechanism, pre-sent frame data in the master memory space during data transmission and to frame the pre-sent frame data; and, based on a high-speed cache mechanism, to obtain received data frames in the master memory space and to deframe the received data frames during data reception. Optionally, the EtherCAT master user program 4101 is further used to: Configuring a descriptor state of a pre-sent data frame, wherein the descriptor is used to characterize a storage address, length, and owner information of the data frame; The data frame descriptor is stored in a non-cached memory mapping manner so that the DMA controller can directly access the latest data frame descriptor.

[0030] Optionally, the EtherCAT master user program 4101 is further used to: Configuring a descriptor state of a received data frame, wherein the descriptor is used to characterize a storage address, length, and owner information of the data frame; The data frame descriptor is stored in a non-cached memory mapping manner to enable the EtherCAT master user program to directly access the latest data frame descriptor.

[0031] The master station memory 4102 is used to store pre-sent frame data and cache the data frames formed by framing, as well as cache the data frames sent by the EtherCAT slave station and store the frame data after deframing; Ethernet controller 4103, configured to obtain data frames in the master station memory space through DMA copy and transmit the data frames to the Ethernet physical layer chip; and write the received data frames into the master station memory space through DMA copy; The Ethernet physical layer chip 4104 is used to send data frames to the EtherCAT slave station, or receive data frames sent by the EtherCAT slave station.

[0032] The data frame in the Ethernet controller 4103 is transmitted to the Ethernet physical layer chip 4104 based on the RGMII interface.

[0033] Preferably, the sending of the data frame to the EtherCAT slave station via the Ethernet physical layer chip further comprises: A timer is constructed to periodically determine whether a data frame transmitted back by the EtherCAT slave 420 is received. The timer includes a primary timer and a secondary timer. The primary timer runs at a frequency of 1 MHz, and the secondary timer runs at a frequency of 1 Hz. If the waiting time exceeds the preset threshold, a reception error is reported and the waiting is suspended.

[0034] Optionally, based on a timer, the EtherCAT master 410 uses an interrupt masking mechanism to execute periodic communication tasks.

[0035] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0036] A person skilled in the art will understand that all or part of the steps in the above-mentioned embodiment method can be implemented by an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed, it implements part or all of the processes in steps S301 to S304.

[0037] Those skilled in the art will also understand that all or part of the steps in the above-described method can be implemented by instructing related hardware through a program. The program can be stored in a computer-readable storage medium. When executed, the program implements part or all of the processes in steps S301 to S304. The storage medium includes, for example, ROM / RAM. In the above-described embodiments, the description of each embodiment has its own emphasis. For portions not described or described in detail in one embodiment, reference can be made to the relevant descriptions of other embodiments.

[0038] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0039] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0040] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An EtherCAT data link layer communication method based on a bare metal system, characterized in that: include: The EtherCAT master user program obtains the pre-sent frame data in the master memory space based on the cache mechanism, frames the pre-sent frame data, and writes the framed data back to the memory space. The Ethernet controller obtains the data frame in the memory space through DMA copy and sends the data frame to the EtherCAT slave through the Ethernet physical layer chip; Correspondingly, after the Ethernet physical layer chip receives the data frame sent by the EtherCAT slave, the Ethernet controller writes the data frame into the EtherCAT master memory space through DMA copy; The EtherCAT master user program obtains the received data frames in the master memory space based on the cache mechanism, deframes the received data frames, and writes the data frames back to the memory space.

2. The method according to claim 1, characterized in that Writing the data frame formed by framing back to the memory space further includes: Configuring a descriptor state of a pre-sent data frame, wherein the descriptor is used to characterize a storage address, length, and owner information of the data frame; The data frame descriptor is stored in a non-cached memory mapping manner so that the DMA controller can directly access the latest data frame descriptor.

3. The method according to claim 1, characterized in that The Ethernet controller writes the data frame into the EtherCAT master station memory space through DMA copying, and further comprises: Configuring a descriptor state of a received data frame, wherein the descriptor is used to characterize a storage address, length, and owner information of the data frame; The data frame descriptor is stored in a non-cached memory mapping manner to enable the EtherCAT master user program to directly access the latest data frame descriptor.

4. The method according to claim 1, wherein The Ethernet controller obtains the data frame in the memory space through DMA copy and sends the data frame to the EtherCAT slave station through the Ethernet physical layer chip, including: The data frame in the Ethernet controller is transmitted to the Ethernet physical layer chip based on the RGMII interface.

5. The method according to claim 1, characterized in that The sending of the data frame to the EtherCAT slave station via the Ethernet physical layer chip further comprises: Construct a timer to periodically determine whether a data frame sent back by the EtherCAT slave is received. The timer includes a primary timer and a secondary timer. The primary timer runs at a frequency of 1 MHz, and the secondary timer runs at a frequency of 1 Hz. If the waiting time exceeds the preset threshold, a reception error is reported and the waiting is suspended.

6. The method according to claim 5, characterized in that The construction timer also includes: Based on the timer, the EtherCAT master uses an interrupt masking mechanism to perform periodic communication tasks.

7. An EtherCAT data link layer communication device based on a bare metal system, characterized in that: The EtherCAT master station includes an EtherCAT master station and an EtherCAT slave station. The EtherCAT master station includes: The EtherCAT master user program is configured to obtain, based on a high-speed cache mechanism, pre-sent frame data in the master memory space during data transmission and to frame the pre-sent frame data; and, based on a high-speed cache mechanism, to obtain received data frames in the master memory space and to deframe the received data frames during data reception. The master station memory is used to store pre-sent frame data and cache the data frames formed by framing, as well as cache the data frames sent by the EtherCAT slave station and store the frame data after deframing; The Ethernet controller is configured to obtain data frames in the master station memory space through DMA copying and transmit the data frames to the Ethernet physical layer chip; and write the received data frames into the master station memory space through DMA copying; Ethernet physical layer chip, used to send data frames to EtherCAT slaves or receive data frames sent by EtherCAT slaves.

8. The device according to claim 7, characterized in that The EtherCAT master user program is also used to: Configuring a descriptor state of a pre-sent data frame, wherein the descriptor is used to characterize a storage address, length, and owner information of the data frame; The data frame descriptor is stored in a non-cached memory mapping manner so that the DMA controller can directly access the latest data frame descriptor.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the EtherCAT data link layer communication method based on a bare metal system as described in any one of claims 1 to 6 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed, the steps of the EtherCAT data link layer communication method based on a bare metal system are implemented as described in any one of claims 1 to 6.

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