A dual-to-single and single-to-dual transmission method and a HDMI dual-pixel transmission method and device

Abstract

The application provides a double-to-single and single-to-double transmission method, a HDMI double-pixel transmission method and a device. The FIFO and the state machine are matched, so that when the video stream is converted from double pixels to single pixels, the phenomenon that the asynchronous FIFO reading clock is faster than the writing clock and the FIFO is easily read empty is avoided. The writing request signal of the two asynchronous FIFO writing enables controlled by the two levels opposite to the flip signal is set, so that the subsequent asynchronous FIFO processing video stream is prevented from being full and the data is covered when the writing clock is faster than the reading clock and the FIFO depth is insufficient. The pixel conversion is performed outside the transmitter IP core and the receiver IP core of the HDMI interface, so that the double-pixel transmission function is realized under the condition that the original IP core input bit width is unchanged. The bit width of the data bus is increased through the double-pixel transmission, the working clock frequency of the physical layer IP core of the serial deserializer is significantly reduced, and the data throughput is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of FPGA, and particularly relates to a double-to-single and single-to-double transmission method and a HDMI double-pixel transmission method and device. BACKGROUND

[0002] In an HDMI interface, the transmission and reception of digital signals are realized through a transmitter TX and a receiver RX. The main function of the transmitter TX is to encode and parallel-to-serial convert the original digital audio and video signals into an HDMI signal for transmission, and the main function of the receiver RX is to receive and decode the HDMI signal and restore the original audio and video data. When double pixels are transmitted per clock on a data bus, in order to match the data bus, the bit width of the input port of an HDMI IP core is expanded accordingly, so as to ensure double-pixel transmission. However, if the width of the HDMI IP core port is fixed, only one pixel can be transmitted per clock, and the structure of the transmitter IP core and the receiver IP core cannot be changed, how to reduce the working clock frequency of the physical layer IP core of the serial deserializer and improve the bandwidth throughput. SUMMARY

[0003] The main problem solved by the application is how to reduce the working clock frequency of the physical layer IP core of the serial deserializer and improve the bandwidth throughput, and a double-to-single and single-to-double transmission method and a HDMI double-pixel transmission method and device are provided.

[0004] To solve the above technical problems, the technical scheme adopted is:

[0005] A double-pixel-to-single-pixel transmission method, comprising the following steps:

[0006] receiving a double-pixel signal;

[0007] converting the double-pixel signal from a low-frequency clock domain to a high-frequency clock domain through an asynchronous FIFO; the asynchronous FIFO is provided with a write enable signal WINC and a read enable signal RINC, and the write enable signal WINC is kept at a high level during the operation of the asynchronous FIFO;

[0008] a read request signal RINCR is set and connected with the read enable signal RINC in the asynchronous FIFO;

[0009] a first state machine is set, and when in a state state0, the high-bit data data[2m-1:m] of the double-pixel signal data read out from the asynchronous FIFO is output as a pixel point 1, and the double-pixel signal is stored, 2m represents the data bit width of the double-pixel signal, the read request signal RINCR is set to a high level, the state machine jumps to a state state1, and the working frequency of the first state machine is the same as the frequency of the high-frequency clock domain;

[0010] The low bit data data_temp[m-1:0] of the double-pixel signal data is output as pixel point 2 in state1, the read request signal RINCR is set to low level, and the state is switched to state0, the data is continuously read from the asynchronous FIFO, and the corresponding single-pixel is output under the switching of the state machine.

[0011] Further, when the double-pixel signal is a video source with a timing signal, the timing signal is stored for one time after being read from the asynchronous FIFO after being converted from the low-frequency clock domain to the high-frequency clock domain.

[0012] The application also provides a double-pixel to single-pixel unit, which is encoded and set on an FPGA, comprising an asynchronous FIFO unit, a single-pixel output unit and a first state machine.

[0013] The asynchronous FIFO unit is used for converting the input double-pixel signal WDATA from the low-frequency clock domain to the high-frequency clock domain; the write enable signal WINC and the read enable signal RINC are set in the asynchronous FIFO, and the write enable signal WINC is kept at high level during the operation of the asynchronous FIFO.

[0014] The single-pixel output unit is used for reading and outputting the single-pixel after processing the double-pixel data from the asynchronous FIFO under the cooperation of the first state machine; in state0 of the first state machine, the high bit data data[2m-1:m] of the double-pixel signal data RDATA read from the asynchronous FIFO is output as pixel point 1, the read double-pixel signal is stored, 2m represents the data bit width of the double-pixel signal, the read request signal RINCR is set to high level, the read request signal RINCR is connected with the read enable signal RINC in the asynchronous FIFO, the first state machine is switched to state1, the working frequency of the first state machine is the same as the frequency of the high-frequency clock domain; in state1, the low bit data data_temp[m-1:0] of the double-pixel signal data is output as pixel point 2, the read request signal RINCR is set to low level, and the state is switched to state0; the data is continuously read from the asynchronous FIFO, and the corresponding single-pixel is output under the switching of the state machine.

[0015] Further, when the double-pixel signal is a video source with a timing signal, the timing signal is stored for one time after being read from the asynchronous FIFO after being converted from the low-frequency clock domain to the high-frequency clock domain.

[0016] The application also provides a single-pixel to double-pixel transmission method, comprising the following steps:

[0017] Receiving a single-pixel signal;

[0018] The single-pixel signal is input to the two asynchronous FIFO units respectively, so that the signal is converted from the high-frequency clock domain to the low-frequency clock domain, and the read enable signal RINC of the two asynchronous FIFO units is always high;

[0019] Two write request signals WINCR1 and WINCR2 with opposite levels are set, the levels of the two write request signals WINCR1 and WINCR2 are switched by a flip-flop signal, the flip-flop period of the flip-flop signal is consistent with the high-frequency side clock period of the asynchronous FIFO unit, the write request signal WINCR1 is connected with the write enable signal WINC of the first asynchronous FIFO unit, the write request signal WINCR2 is connected with the write enable signal WINC of the second asynchronous FIFO unit, and the two asynchronous FIFO units are written when the write enable signal WINC is high.

[0020] The double-pixel signal is output, the data read out from the first asynchronous FIFO unit is first stored for one beat, and then is spliced with the data newly read out from the second asynchronous FIFO unit at the same time and then is output.

[0021] The application further provides a single-pixel to double-pixel unit, a write request unit, two asynchronous FIFO units and a double-pixel output unit are set on an FPGA.

[0022] The write request unit is used for sending two write request signals WINCR1 and WINCR2 with opposite levels, the levels of the two write request signals WINCR1 and WINCR2 are switched by a flip-flop signal, the flip-flop period of the flip-flop signal is consistent with the high-frequency side clock period of the asynchronous FIFO unit, the write request signal WINCR1 is connected with the write enable signal WINC of the first asynchronous FIFO unit, the write request signal WINCR2 is connected with the write enable signal WINC of the second asynchronous FIFO unit, and the two asynchronous FIFO units are written when the write enable signal WINC is high.

[0023] The two asynchronous FIFO units are used for converting the input single-pixel signal from the high-frequency clock domain to the low-frequency clock domain, and making the read enable signal RINC of the two asynchronous FIFO units always high.

[0024] The double-pixel output unit is used for storing the data read out from the first asynchronous FIFO unit for one beat, splicing the data with the data newly read out from the second asynchronous FIFO unit at the same time and then outputting.

[0025] The application further provides an HDMI double-pixel transmission method, which comprises the following steps:

[0026] Step 1: receiving a double-pixel video source signal;

[0027] Step 2: the data signal of the video source signal is input into the transmitter IP core after being processed by the double-pixel to single-pixel method, and the video timing signal of the video source signal is converted from the low-frequency clock domain to the high-frequency clock domain through the asynchronous FIFO and is input into the transmitter IP core after being stored for one beat;

[0028] Step 3: the signal transmitted by the transmitter IP core is input into the physical layer IP core of the serial deserializer after being processed by the single-pixel to double-pixel method;

[0029] Step 4: the data passing through the physical layer IP core of the serial deserializer is input into the receiver IP core after being processed by the double-pixel to single-pixel method.

[0030] The application further provides a double-pixel transmission device of an HDMI interface, comprising the following units, and the functions of the units are realized by encoding on an FPGA:

[0031] a receiving unit, which is used for receiving a video source signal;

[0032] a first double-pixel to single-pixel unit, which is used for converting the video data signal in the received video source signal into a single-pixel signal by using a double-pixel to single-pixel method;

[0033] a cache unit, which is used for reading out the video timing signal of the video source signal from the low-frequency clock domain to the high-frequency clock domain through the asynchronous FIFO unit in the first double-pixel to single-pixel unit and then inputting the video timing signal into the transmitter IP core after being cached for one beat in the cache unit;

[0034] a transmitter IP core, which is used for encoding and outputting the converted single-pixel signal and the timing signal converted into the high-frequency clock domain;

[0035] a single-pixel to double-pixel unit, which is used for processing the signal encoded and output by the transmitter IP core into a double-pixel signal by using a single-pixel to double-pixel method;

[0036] a physical layer IP core of a serial deserializer, which is used for converting the parallel data output by the transmitter IP core into serial data through the single-pixel to double-pixel unit and transmitting the serial data in a physical channel, and converting the serial data transmitted in the physical channel into parallel data and sending the parallel data to the second double-pixel to single-pixel unit;

[0037] a second double-pixel to single-pixel unit, which is used for processing the received double-pixel signal into a single-pixel signal by using a double-pixel to single-pixel method;

[0038] a receiver IP core, which is used for receiving the single-pixel parallel data signal output by the physical layer IP core of the serial deserializer and converted by the second double-pixel to single-pixel unit, decoding and processing the parallel data signal and recovering the clock.

[0039] The technical scheme has the following beneficial effects:

[0040] The application provides a double-to-single and single-to-double transmission method, a double-pixel transmission method and a device. The application prevents the phenomenon that the asynchronous FIFO reading clock is faster than the writing clock and the FIFO is easily emptied when the video stream is converted from double pixels to single pixels. The application can realize the double-pixel transmission function without changing the original input bit width of the IP core, and can increase the bit width of the data bus through the double-pixel transmission, thereby significantly reducing the working clock frequency of the physical layer IP core of the serial deserializer and improving the data throughput. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 FIG. 1 is a schematic diagram of a double-to-single pixel unit;

[0042] Figure 2 FIG. 2 is a schematic diagram of a double-to-single pixel unit with a timing signal;

[0043] Figure 3 FIG. 3 is a schematic diagram of a single-to-double pixel unit;

[0044] Figure 4 FIG. 4 is a schematic diagram of an HDMI interface double-pixel transmission device. DETAILED DESCRIPTION

[0045] The technical scheme of the application will be described clearly and completely below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments. Based on the embodiments of the application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.

[0046] Embodiment 1

[0047] Figure 1 A specific embodiment of a double-to-single pixel transmission method is shown, which includes the following steps:

[0048] receiving a double-pixel signal;

[0049] The double-pixel signal is converted from the low-frequency clock domain to the high-frequency clock domain through an asynchronous FIFO; a write enable signal WINC and a read enable signal RINC are arranged in the asynchronous FIFO, and the write enable signal WINC is kept at a high level during the operation of the asynchronous FIFO;

[0050] A read request signal RINCR is arranged and connected with the read enable signal RINC in the asynchronous FIFO;

[0051] A first state machine is arranged, and high-bit data data[2m-1:m] of the double-pixel signal data read out from the asynchronous FIFO is output as a pixel point 1 in state state0, and the double-pixel signal is registered, 2m represents the data bit width of the double-pixel signal, the read request signal RINCR is set to a high level, and the state machine jumps to state1, and the working frequency of the first state machine is the same as the frequency of the high-frequency clock domain;

[0052] The low-bit data data_temp[m-1:0] of the double-pixel signal data is output as a pixel point 2 in state1, the read request signal RINCR is set to a low level, and jumps to state0, and the data is continuously read out from the asynchronous FIFO and output as corresponding single-pixel under the jumping of the first state machine.

[0053] The video source data signal can be converted from the low-frequency clock domain to the high-frequency clock domain through the asynchronous FIFO, and then when the data is read out from the asynchronous FIFO, the read empty phenomenon is prone to occur because the read clock is faster than the write clock, the read request signal RINCR is connected with the read enable signal of the asynchronous FIFO unit, the data reading from the asynchronous FIFO unit is controlled by the read request signal, and the read empty phenomenon is avoided.

[0054] In the embodiment, as shown in Figure 2 When the double-pixel signal is a video source with a timing signal, the timing signal is output after being registered for one beat when being read out from the asynchronous FIFO after being converted from the low-frequency clock domain to the high-frequency clock domain. The timing signal does not need to be converted from double to single, and is directly registered for one beat after being successfully converted from the asynchronous FIFO unit across the time domain to the high-frequency time domain, so that the split single-pixel data is synchronized with the timing signal.

[0055] Embodiment two

[0056] The application further provides a double-pixel to single-pixel unit, as shown in Figure 1 The asynchronous FIFO unit, the single-pixel output unit and the first state machine are encoded and arranged on the FPGA;

[0057] The asynchronous FIFO unit is used for converting the input double-pixel signal WDATA from a low-frequency clock domain to a high-frequency clock domain; the write enable signal WINC and the read enable signal RINC are set in the asynchronous FIFO, and the write enable signal WINC is kept at a high level during the operation of the asynchronous FIFO;

[0058] The single-pixel output unit is used for reading out double-pixel data from the asynchronous FIFO and outputting single-pixel under the cooperation of the first state machine; when the first state machine is in the state state0, the high-bit data data[2m-1:m] of the double-pixel signal data RDATA read out from the asynchronous FIFO is outputted as pixel point 1, 2m represents the data bit width of the double-pixel signal, the read request signal RINCR is set to a high level, the read request signal RINCR is connected with the read enable signal RINC in the asynchronous FIFO, the first state machine is jumped to the state state1, and the working frequency of the first state machine is the same as the frequency of the high-frequency clock domain; when the state is state1, the low-bit data data_temp[m-1:0] of the double-pixel signal data is outputted as pixel point 2, the read request signal RINCR is set to a low level, and the state is jumped to state0; the data is continuously read out from the asynchronous FIFO and outputted as corresponding single-pixel under the jumping of the state machine.

[0059] In this embodiment, as shown in Figure 2 When the double-pixel signal is a video source with a timing signal, the timing signal is converted from a low-frequency clock domain to a high-frequency clock domain through the asynchronous FIFO, and a cache unit is set on the FPGA to make the timing signal output after being stored in the cache unit for one beat when being read out from the asynchronous FIFO.

[0060] In this embodiment, the asynchronous FIFO unit and the single-pixel output unit are realized by coding on the FPGA, and the write enable signal WINC and the read enable signal RINC are set on the asynchronous FIFO; when the asynchronous FIFO crosses the clock domain, the phenomenon of slow writing and fast reading occurs, so the write enable signal WINC is kept at a high level, and the read enable signal RINC is connected with the read request signal RINCR set in the single-pixel output unit; the read request signal is set to a high level in the state state0 to read data from the asynchronous FIFO, and is set to a low level in the state state1 to avoid the phenomenon of reading empty.

[0061] In this embodiment, as shown in Figure 2As shown, when the dual-pixel signal is a video source with a timing signal, the timing signal is converted from a low-frequency clock domain to a high-frequency clock domain through an asynchronous FIFO, and a cache unit is set on the FPGA, so that the timing signal is stored for one beat in the cache unit after being read out from the asynchronous FIFO and then output. Through the output after being stored for one beat, the video timing signal can be synchronized with the data signal output by the single-pixel output unit.

[0062] Embodiment three

[0063] The application also provides a single-pixel to dual-pixel transmission method, comprising the following steps:

[0064] receiving a single-pixel signal;

[0065] inputting the single-pixel signal into two asynchronous FIFO units to convert the signal from a high-frequency clock domain to a low-frequency clock domain, and keeping the read enable signal RINC of the two asynchronous FIFO units high;

[0066] setting two write request signals WINCR1 and WINCR2 with opposite levels, and jumping the levels of the two write request signals WINCR1 and WINCR2 through a flip signal, wherein the flip period of the flip signal is consistent with the high-frequency side clock period of the asynchronous FIFO unit, the write request signal WINCR1 is connected with the write enable signal WINC of the first asynchronous FIFO unit, the write request signal WINCR2 is connected with the write enable signal WINC of the second asynchronous FIFO unit, and the write enable signal WINC of the two asynchronous FIFO units is high when writing;

[0067] outputting a dual-pixel signal, storing the data read out from the first asynchronous FIFO unit for one beat, and then splicing the data with the newly read data from the second asynchronous FIFO unit at the same time and outputting.

[0068] In this embodiment, in order to convert a single pixel into a dual pixel, an asynchronous FIFO unit is used to perform cross-clock domain conversion, and then the clock domain is converted from the high-frequency clock domain to the low-frequency clock domain. However, since the write clock is faster than the read clock, the asynchronous FIFO may be overwritten. If new data continues to arrive after it is full, the later data may overwrite the earlier data. Moreover, if the burst length of the video source is too long, such as when the video resolution is 1920*1080, the required minimum FIFO depth is 7425000 bytes. Simply increasing the depth will occupy a large amount of storage resources, increase power consumption, and cause timing problems. Therefore, this embodiment provides write request signals WINCR1 and WINCR2 with opposite levels. These two write request signals are then connected to the write enable signals of the two asynchronous FIFOs. Because the two write request signals have opposite high levels (i.e., one is high when the other is low), the asynchronous FIFO units can only write when the write enable signal is high. When one asynchronous FIFO is writing, the other cannot. This ensures that the average data write rate of each asynchronous FIFO is equal to the average read clock rate. This method prevents subsequent asynchronous FIFO processing from being filled up and data being overwritten when continuing write operations due to the write clock being faster than the read clock and the FIFO depth being insufficient. By storing the data read from the first asynchronous FIFO for one beat and then splicing it with the data read from the second asynchronous FIFO at the same time, the data output from the two asynchronous FIFOs can be effectively combined into two pixels within one clock cycle.

[0069] Example 4

[0070] The present invention also provides a single pixel to double pixel unit, such as Figure 3 As shown, a write request unit, two asynchronous FIFO units, and a dual-pixel output unit are coded and set on the FPGA;

[0071] The write request unit is used to send two write request signals WINCR1 and WINCR2 with opposite levels. The levels of the two write request signals WINCR1 and WINCR2 are jumped by a set flip signal. The flip cycle of the flip signal is consistent with the high-frequency side clock cycle of the asynchronous FIFO unit. The write request signal WINCR1 is connected to the write enable signal WINC of the first asynchronous FIFO unit, and the write request signal WINCR2 is connected to the write enable signal WINC of the second asynchronous FIFO unit. Writing is performed when the write enable signal WINC of the two asynchronous FIFO units is high;

[0072] The two asynchronous FIFO units are used to convert the input single pixel signal from the high-frequency clock domain to the low-frequency clock domain; the read enable signal RINC of the two asynchronous FIFO units is always high;

[0073] The double-pixel output unit is used for storing the data read from the first asynchronous FIFO unit for one clock cycle, and then splicing the data read from the second asynchronous FIFO unit at the same time and outputting.

[0074] In the embodiment, two write request signals with opposite levels are used to send write request signals to the write enable signals of the two asynchronous FIFO units. Since the two write request signals have opposite levels, that is, one is high level and the other is low level, the asynchronous FIFO units can only write when the write enable signals are high level. When one asynchronous FIFO can write, the other asynchronous FIFO cannot write, so that the average rate of writing data of the asynchronous FIFOs is equal to the average rate of the read clock. By this method, the situation that the subsequent asynchronous FIFO processing causes the write clock to be faster than the read clock and the FIFO depth to be insufficient, and the data is overwritten when the write operation continues, is prevented. By storing the data read from the first asynchronous FIFO for one clock cycle, and then splicing the data read from the second asynchronous FIFO at the same time and outputting, the data output by the two asynchronous FIFOs can be effectively combined into two pixel points in one clock cycle.

[0075] Embodiment five

[0076] The application also provides an HDMI double-pixel transmission method, comprising the following steps:

[0077] Step 1: receiving a double-pixel video source signal;

[0078] Step 2: processing the data signal of the video source signal using a double-pixel to single-pixel method, and then inputting the processed signal into the transmitter IP core of the HDMI; processing the video timing signal of the video source signal through an asynchronous FIFO, and then inputting the processed signal into the transmitter IP core after converting the signal from a low-frequency clock domain to a high-frequency clock domain and storing the signal for one clock cycle;

[0079] Step 3: processing the signal transmitted by the transmitter IP core using a single-pixel to double-pixel method, and then inputting the processed signal into the physical layer IP core of the serial deserializer;

[0080] Step 4: processing the data through the physical layer IP core of the serial deserializer using a double-pixel to single-pixel method, and then inputting the processed data into the receiver IP core.

[0081] In the embodiment, since the transmitter IP core and the receiver IP core of the HDMI interface can only work in the single-pixel transmission mode, and the input bit width of the IP core cannot be changed, in order to reduce the clock working frequency of the physical layer IP core of the serial deserializer, the double-pixel transmission mode is considered to be adopted, the development is carried out in the periphery of the IP core, the data entering the transmitter IP core and the receiver IP core is single-pixel, and the data is double-pixel in other cases. Therefore, the double-pixel to single-pixel conversion or the single-pixel to double-pixel conversion needs to be carried out. However, since the write coverage or the read empty phenomenon caused by the use of the asynchronous FIFO unit in the double-to-single or single-to-double process, the double-pixel to single-pixel method provided in the foregoing, the double-pixel to single-pixel unit, the single-pixel to double-pixel method, or the single-pixel to double-pixel unit is used to realize.

[0082] Embodiment six

[0083] The application further provides an HDMI interface double-pixel transmission device, as shown in the figure, comprising the following units, and the functions of the units are realized by coding on an FPGA. Figure 4

[0084] A receiving unit is used for receiving a video source signal.

[0085] A first double-pixel to single-pixel unit is used for converting the video data signal in the received video source signal into a single-pixel signal by using a double-pixel to single-pixel method.

[0086] ​The cache unit is used for caching the video timing signal of the video source signal after reading out from the low frequency clock domain to the high frequency clock domain through the asynchronous FIFO unit in the first double-pixel to single-pixel unit and then inputting to the transmitter IP core after one frame caching in the cache unit. The video source data signal DATA0 and the video timing signal (the row synchronization signal HSYNC0, the field synchronization signal VSYNC0 and the pixel data enable signal DE0) are packaged together and sent to the asynchronous FIFO unit in the double-pixel to single-pixel unit to convert from the low frequency clock domain to the high frequency clock domain, and are output in the form of DATAR, HSYNCR, VSYNCR and DER respectively, and WINC is always high; DATAR is split into one pixel point per clock after the double-pixel to single-pixel unit, and the specific method is that DATAR (for example, the bit width is 2m) outputs the high bit data data[2m-1:m] as pixel point 1 in state0, latches the video source data as data_temp[2m:0], at the same time, RINCR is set to 1, and jumps to state1; in state1, the low bit data data_temp[m-1:0] of the temporarily stored video source is output as pixel point 2, at the same time, RINCR is set to 0, and jumps to state0. This method effectively prevents the situation that the current data cannot be output as pixel point 2 when the next moment data is updated, and avoids the phenomenon that the asynchronous FIFO read clock is faster than the write clock and is easy to read empty. In order to keep the synchronization of the split data signal, the video timing signal needs to be registered and output after one frame.

[0087] The transmitter IP core is used for performing 8b / 10b encoding on the converted single-pixel signal DATA1 and the timing signal converted into the high frequency clock domain, and then outputting.

[0088] The single-pixel to double-pixel unit is used for processing the signal output from the transmitter IP core into a double-pixel signal by using a single-pixel to double-pixel method. In this embodiment, the single-pixel signal DATA2 output from the transmitter IP core also needs to be converted into a double-pixel signal in order to input into the physical layer IP core of the serial deserializer, and the single-pixel to double-pixel method is used for conversion. As shown in the figure, Figure 4As shown, the single-pixel signal DATA2 is input to two asynchronous FIFO units at the same time, under the action of the write request signals with opposite levels issued by the write request unit, so that the average rate of writing data of the two asynchronous FIFOs is equal to the average rate of the read clock, preventing the situation that the data is overwritten when the write clock is faster than the read clock and the FIFO depth is insufficient when the write operation continues, and when reading out the data from the two asynchronous FIFOs, the data read out from the first asynchronous FIFO is stored for one beat first, and then the data stored for one beat and the data read out from the second asynchronous FIFO are spliced at the same time, so that the data output by the two asynchronous FIFOs is effectively combined into two pixel points in one clock cycle.

[0089] The physical layer IP core of the serial deserializer: used for converting the parallel data converted into double pixels by the single-pixel-to-double-pixel unit into serial data for transmission in the physical channel, and converting the serial data transmitted in the physical channel into parallel data and sending to the second double-pixel-to-single-pixel unit.

[0090] The second double-pixel-to-single-pixel unit: used for outputting the single-pixel signal after processing the received double-pixel signal using the double-pixel-to-single-pixel method. Considering that the output double-pixel of the serial deserializer physical layer IP core and the receiver IP core can only receive single-pixel per clock, the second double-pixel-to-single-pixel unit is added between the serial deserializer physical layer IP core and the receiver IP core, and the bit width conversion and frequency conversion are performed on each output channel (3 output channels) of the serial deserializer physical layer IP core. The frequency conversion considers clock multiplication (such as PLL) and is not generated by the physical layer IP core PHY of the serial deserializer. Taking one channel as an example, the specific method is that DATA4 (such as bit width of 2n) is converted from the low-frequency clock domain to the high-frequency clock domain through the asynchronous FIFO, and the data is read out from the asynchronous FIFO unit, and WINC is always high; in the double-pixel-to-single-pixel unit, using the first state machine, outputting the high-bit data data[2n-1:n] as pixel point 1 in state0, latching the video source data as data_temp[2n:0], at the same time, RINCR is set to 0, and jump to state1; in state1, output the low-bit data data_temp[n-1:0] of the temporarily stored video source as pixel point 2, at the same time, RINCR is set to 1, and jump to state0, and the above RINCR is output to the asynchronous FIFO as the read request flag signal.

[0091] The receiver IP core: used for receiving the single-pixel parallel data signal output by the physical layer IP core of the serial deserializer and converted by the second double-pixel-to-single-pixel unit, and decoding and processing the parallel data signal and recovering the clock.

[0092] The first double-pixel to single-pixel unit and the single-pixel to double-pixel unit are used in the periphery of the transmitter IP core, the second double-pixel to single-pixel unit is used in the periphery of the receiver IP core, so that the SERDES PHY clock working frequency is reduced, and the structure of the HDMI interface IP core is not changed.

[0093] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A dual-pixel to single-pixel transmission method, characterized in that: The following steps are involved: receiving a dual-pixel signal; The dual-pixel signal is converted from a low-frequency clock domain to a high-frequency clock domain through an asynchronous FIFO; a write enable signal WINC and a read enable signal RINC are provided in the asynchronous FIFO, and the write enable signal WINC is kept at a high level during the operation of the asynchronous FIFO; Set the read request signal RINCR and connect it to the read enable signal RINC in the asynchronous FIFO; Set the first state machine to output the high-order data data[2m-1:m] of the dual-pixel signal data read from the asynchronous FIFO as pixel point 1 in state 0, and register the dual-pixel signal at the same time. 2m represents the data bit width of the dual-pixel signal. Set the read request signal RINCR to a high level to make the state machine jump to state 1. The operating frequency of the first state machine is the same as the frequency of the high-frequency clock domain. In state1, the low-order data data_temp[m-1:0] of the dual-pixel signal data is output as pixel point 2, the read request signal RINCR is set to a low level, and jumps to state0, continues to read data from the asynchronous FIFO and outputs the corresponding single pixel under the jump of the first state machine.

2. The dual-pixel to single-pixel transmission method according to claim 1, wherein: When the dual-pixel signal is a video source with a timing signal, after the timing signal is converted from a low-frequency clock domain to a high-frequency clock domain through an asynchronous FIFO, the timing signal is stored for one beat when read out from the asynchronous FIFO and then output.

3. A dual-pixel to single-pixel unit, characterized in that: Encoding and setting an asynchronous FIFO unit, a single pixel output unit, and a first state machine on the FPGA; The asynchronous FIFO unit is used to convert the input dual-pixel signal WDATA from a low-frequency clock domain to a high-frequency clock domain; the asynchronous FIFO is provided with a write enable signal WINC and a read enable signal RINC, and during the operation of the asynchronous FIFO, the write enable signal WINC is kept at a high level; The single-pixel output unit is used to read out dual-pixel data from the asynchronous FIFO and output a single pixel after processing in cooperation with the first state machine; in state state0 of the first state machine, output the high-order data data[2m-1:m] of the dual-pixel signal data RDATA read out from the asynchronous FIFO as pixel point 1, and at the same time register the read dual-pixel signal, 2m represents the data bit width of the dual-pixel signal, set the read request signal RINCR to a high level, and the read request signal RINCR is connected to the read enable signal RINC in the asynchronous FIFO, so that the first state machine jumps to state state1, and the operating frequency of the first state machine is the same as the frequency of the high-frequency clock domain; in state1, output the low-order data data_temp[m-1:0] of the dual-pixel signal data as pixel point 2, set the read request signal RINCR to a low level, and jump to state state0; continue to read data from the asynchronous FIFO and output the corresponding single pixel when the state machine jumps.

4. The dual-pixel to single-pixel unit according to claim 3, characterized in that: When the dual-pixel signal is a video source with a timing signal, after the timing signal is converted from the low-frequency clock domain to the high-frequency clock domain through the asynchronous FIFO, a cache unit is set on the FPGA so that the timing signal is output after being stored in the cache unit for one beat when read out from the asynchronous FIFO.

5. A single pixel to dual pixel transmission method, characterized in that: The following steps are involved: receiving a single pixel signal; Inputting a single pixel signal into two asynchronous FIFO units respectively converts the signal from a high-frequency clock domain to a low-frequency clock domain, so that the read enable signal RINC of the two asynchronous FIFO units is always high; Two write request signals WINCR1 and WINCR2 with opposite levels are set. The levels of the two write request signals WINCR1 and WINCR2 are jumped by a flip signal. The flip cycle of the flip signal is consistent with the high-frequency side clock cycle of the asynchronous FIFO unit. The write request signal WINCR1 is connected to the write enable signal WINC of the first asynchronous FIFO unit, and the write request signal WINCR2 is connected to the write enable signal WINC of the second asynchronous FIFO unit. Writing is performed when the write enable signal WINC of the two asynchronous FIFO units is high; Outputting a dual-pixel signal, storing the data read out from the first asynchronous FIFO unit for one beat, splicing it with the data newly read out from the second asynchronous FIFO unit at the same time and then outputting it.

6. A single-pixel to dual-pixel unit, characterized in that: Code and set up a write request unit, two asynchronous FIFO units, and a dual-pixel output unit on the FPGA; The write request unit is used to send two write request signals WINCR1 and WINCR2 with opposite levels. The levels of the two write request signals WINCR1 and WINCR2 are jumped by a set flip signal. The flip cycle of the flip signal is consistent with the high-frequency side clock cycle of the asynchronous FIFO unit. The write request signal WINCR1 is connected to the write enable signal WINC of the first asynchronous FIFO unit, and the write request signal WINCR2 is connected to the write enable signal WINC of the second asynchronous FIFO unit. Writing is performed when the write enable signal WINC of the two asynchronous FIFO units is high; The two asynchronous FIFO units are used to convert the input single-pixel signal from the high-frequency clock domain to the low-frequency clock domain; Make the read enable signal RINC of the two asynchronous FIFO units always high; The dual-pixel output unit is used to store the data read out from the first asynchronous FIFO unit for one beat, and then splice it with the data newly read out from the second asynchronous FIFO unit at the same time and output it.

7. An HDMI dual-pixel transmission method, characterized in that: Step 1: Receive dual-pixel video source signal; Step 2: The data signal of the video source signal is processed using a dual-pixel to single-pixel method and then input into the HDMI transmitter IP core. The video timing signal of the video source signal is converted from a low-frequency clock domain to a high-frequency clock domain through an asynchronous FIFO and stored for one beat before being input into the transmitter IP core. Step 3: The signal transmitted by the transmitter IP core is processed using the single-pixel to dual-pixel method and then input into the physical layer IP core of the serializer-deserializer; Step 4: The data from the physical layer IP core of the serializer-deserializer is processed using the dual-pixel to single-pixel method and then input into the receiver IP core.

8. An HDMI interface dual-pixel transmission device, characterized in that: It includes the following units, and the functions of each unit are implemented by coding on FPGA: A receiving unit, configured to receive a video source signal; A first double-pixel to single-pixel conversion unit is configured to convert a video data signal in a received video source signal into a single-pixel signal using a double-pixel to single-pixel conversion method; A cache unit, configured to convert the video timing signal of the video source signal from a low-frequency clock domain to a high-frequency clock domain through an asynchronous FIFO unit in the first dual-pixel to single-pixel unit, read the signal, cache it for one beat in the cache unit, and then input the signal to the transmitter IP core; Transmitter IP core: used to encode and output the converted single-pixel signal and the timing signal converted into the high-frequency clock domain; Single-pixel to dual-pixel unit: used to process the signal encoded and output from the transmitter IP core into a dual-pixel signal using the single-pixel to dual-pixel method; The physical layer IP core of the serial deserializer is used to convert the parallel data of the transmitter IP core that is converted into dual pixels by the single-pixel to dual-pixel unit into serial data for transmission on the physical channel, and convert the serial data transmitted through the physical channel into parallel data and send it to the second dual-pixel to single-pixel unit; A second dual-pixel to single-pixel conversion unit is configured to process the received dual-pixel signal using a dual-pixel to single-pixel conversion method and then output a single-pixel signal; Receiver IP core: used to receive the single-pixel parallel data signal output by the physical layer IP core of the serial deserializer and converted by the second dual-pixel to single-pixel unit, and perform decoding and clock recovery on the parallel data signal.

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