89results about "Conversion with storage device usage" patented technology

An electronic endoscopic apparatus having various sorts of electronic endoscopes mounting a CCD with a different number of pixels, for example, 410,000 pixels, 270,000 pixels or 190,000 pixels that are connectable to a processor. A CCD drive and signal processing circuit drives all the CCDs at a frequency set up for the CCD with 410,000 pixels, and an information quantity conversion circuit expands an image acquired by the CCD with 270,000 pixels or 190,000 pixels by pixel interpolation in a horizontal direction or a vertical direction to form an image with an aspect ratio of 4 to 3. Also, a video signal acquired in an NTSC system is converted into a video signal of a PAL system by using a television standard conversion circuit, thereby displaying an excellent PAL video without any bar noise.

An overtaking prediction method of, when input and output of data to and from a common memory are being performed with an input frame frequency and an output frame frequency made different from each other, predicting a frame in which overtaking occurs between the input and the output of the data to and from the memory. The overtaking prediction method includes a step of predicting the frame in which the overtaking occurs between the input and the output of the data, on the basis of a first parameter corresponding to a difference amount between a progress speed of a write address and a progress speed of a read address and a second parameter corresponding to a difference between a write address and a read address at an overtaking prediction point and to an offset address difference amount between an input offset address and an output offset address.

An LCD driver starts reading a digital image signal of one frame from a VRAM in response to a reproduction timing signal. A driving timing signal generator generates a driving timing signal in response to a synchronizing signal, whose phase is shifted by a delay time from the reproduction timing signal. So a phase difference corresponding to the delay time is provided between the driving timing signal and the reproduction timing signal. Synchronously with the driving timing signal, an image sensor is driven to shoot a subject and output an analog image signal of one frame. After being converted into a digital form, the image signal is written in the VRAM sequentially from the first line of one frame. The phase difference is determined so that the LCD driver starts reading the image signal sequentially from the first line, immediately after the first line is written in the VRAM.

A video signal converting apparatus converts a low-resolution video signal from a host into a different-resolution video signal capable of being displayed on the entire screen of a high-resolution supporting display device. The apparatus has a memory for storing the digital video signals and a horizontal output generator. The horizontal output generator receives first and second data signals and a horizontal synchronization signal and generates a horizontal output signal for enabling the digital video signals corresponding to each horizontal line of the second display to be stored or read from the memory. A number of pixels per cycle of the horizontal output signal is equal to a value of the first data signal, and a number of pixels per pulse width of the horizontal output signal is equal to a value of the second data signal. The apparatus has a memory controller for controlling reading and storing operations of the memory in accordance with the horizontal and vertical synchronization signals, the horizontal output signal, the first data signal, a third data signal determined according to frequencies of the horizontal and vertical synchronization signals, a first pixel clock signal for a write operation of the memory and a second pixel clock signal for a read operation of the memory.

An image signal generator generates an imaging signal having a frame rate that is controlled to be variable. A frame rate converter generates a monitor image signal. Upon receiving communication information from an external source, a controller controls the operations of the image signal generator and the frame rate converter on the basis of the communication information. When an instruction to specify the frame rate of the monitor image signal is given from a user interface, the controller controls the frame rate converter to generate a monitor image signal having a specified frame rate by giving priority to this instruction over the communication information.

In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

An image shooting unit 21 generates an image signal DVb having an image shooting frame rate. A main line image processing block 40 performs frame addition on the image signal DVb having the image shooting frame rate, and generates a main line image signal having a desired output frame rate. Based on the image signal DVb, a monitor image processing block 50 generates a monitor image signal having a frame rate independent of the frame rate of the main line image signal. Since the frame rate of the main line image signal and that of the monitor image signal are independent of each other, shooting an image while varying the frame rate of the main line image signal allows a monitor image at an image shooting time to be displayed at a predetermined frame rate using the monitor image signal DVr.

An imaging apparatus which images pictures using a solid-state imaging device includes a picture conversion unit converting pictures imaged at a high-speed screen rate by the solid-state imaging device into a picture in which n-pieces (''n'' is an integer of 2 or more) of continuous imaged pictures are arranged in one screen and outputting the converted picture at a low-speed screen rate which is 1 / n of the high-speed screen rate, a signal processing unit performing predetermined picture-quality compensation processing to the picture from the picture conversion unit, a display picture cutting unit cutting one of n-pieces of imaged pictures from pictures processed by the signal processing unit and outputting the picture at the low-speed screen rate, and a display processing unit generating picture signals for displaying the picture outputted from the display picture cutting unit at a display device.

The video format bridging device has no overflow and underflow and output frame rate matched with input frame rate ensured via several technological measures. The bridging device can settle residual line problem and input and output pulse frequency variation problem, and can regulate the ratio between the input and output line numbers each frame and ratio between the input and output pixel numbers each line within the output unit size. One single IC is provided for several technological aims, including enabling or disabling some specific bridging operation. The bridging logic produces serial output video signal flow in the output frame rate matching with the input frame rate, and the output frames have at least one frame with lines having different pixels and / or one set of several frame with different line numbers.

An overtaking prediction method of, when input and output of data to and from a common memory are being performed with an input frame frequency and an output frame frequency made different from each other, predicting a frame in which overtaking occurs between the input and the output of the data to and from the memory. The overtaking prediction method includes a step of predicting the frame in which the overtaking occurs between the input and the output of the data, on the basis of a first parameter corresponding to a difference amount between a progress speed of a write address and a progress speed of a read address and a second parameter corresponding to a difference between a write address and a read address at an overtaking prediction point and to an offset address difference amount between an input offset address and an output offset address.