Semiconductor structure and preparation method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method of the semiconductor structure and a memory system, and the semiconductor structure comprises a substrate which comprises a first device region and a second device region; the first active region is located in the first device region, the second active region is located in the second device region, the first active region and the second active region both extend into the substrate from the first surface of the substrate, and the first surface is one of two opposite main surfaces of the substrate; a first silicide layer and a second silicide layer; the first contact structure is located on one side of the first silicide layer, the second contact structure is located on one side of the second silicide layer, the first silicide layer is connected with the first active region and the first contact structure, and the second silicide layer is connected with the second active region and the second contact structure; and the resistivity of the second silicide layer is smaller than that of the first silicide layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for preparing a semiconductor structure, and a memory system. Background Art

[0002] Memory is a key component in electronic systems. Taking memory as an example, a semiconductor structure may include a memory array and a driver circuit connected to the memory array. The driver circuit is used to drive the memory array for erasing, writing, and reading. The driver circuit includes transistors. Different regions of the driver circuit operate at different voltages. For example, the driver circuit may include a high-voltage operating region and a low-voltage operating region, which have different performance requirements for transistors.

[0003] However, as the size of semiconductor structures continues to shrink, how to balance the comprehensive performance of semiconductor structures including high-voltage operating regions and low-voltage operating regions is an important research direction in this field. Summary of the Invention

[0004] The present application provides a semiconductor structure, a method for preparing a semiconductor structure, and a memory system that can at least partially solve the above-mentioned problems or other problems in the field.

[0005] On the one hand, the present application provides a semiconductor structure, comprising: a substrate, comprising a first device region and a second device region; a first active region located in the first device region and a second active region located in the second device region, wherein the first active region and the second active region both extend from a first surface of the substrate into the substrate, the first surface being one of two opposite main surfaces of the substrate; a first silicide layer and a second silicide layer; a first contact structure located on one side of the first silicide layer and a second contact structure located on one side of the second silicide layer, wherein the first silicide layer connects the first active region and the first contact structure, and the second silicide layer connects the second active region and the second contact structure; and the resistivity of the second silicide layer is less than the resistivity of the first silicide layer.

[0006] In one embodiment of the present application, the first contact structure and the second contact structure extend to the first silicide layer and the second silicide layer respectively along a first direction, wherein in a direction intersecting with the first direction, a size of the first silicide layer is smaller than a size of the second silicide layer.

[0007] In one embodiment of the present application, at least a portion of the first silicide layer is located in the first active region; and the second silicide layer is located on a side of the second active region close to the first surface.

[0008] In one embodiment of the present application, the first contact structure extends to the first silicide layer along a first direction, wherein, in a direction intersecting the first direction, a size of a portion of the first contact structure in contact with the first silicide layer is greater than or equal to a size of the first silicide layer.

[0009] In one embodiment of the present application, the second contact structure extends to the second silicide layer along a first direction, wherein, in a direction intersecting the first direction, a size of a portion of the second contact structure in contact with the second silicide layer is smaller than a size of the second silicide layer.

[0010] In one embodiment of the present application, the second contact structure extends into the second silicide layer.

[0011] In one embodiment of the present application, the first contact structure includes a first conductive layer and a first adhesive layer surrounding the first conductive layer, wherein the first silicide layer and the first adhesive layer contain the same metal element.

[0012] In one embodiment of the present application, the second contact structure includes a second conductive layer and a second adhesive layer surrounding the second conductive layer, wherein the second silicide layer and the second adhesive layer contain different metal elements; and the first adhesive layer and the second adhesive layer include the same conductive material.

[0013] In one embodiment of the present application, the semiconductor structure further includes a first gate structure and a second gate structure, the first gate structure extends along a first direction and is located on one side of the first device region, and the second gate structure extends along the first direction and is located on one side of the second device region, wherein, in a direction intersecting with the first direction, the size of the first gate structure is larger than the size of the second gate structure; and / or the size of the first gate structure in the first direction is larger than the size of the second gate structure in the first direction.

[0014] In one embodiment of the present application, the semiconductor structure further includes a third silicide layer and a fourth silicide layer, wherein the third silicide layer is located at the end of the first gate structure away from the substrate, and the fourth silicide layer is located at the end of the second gate structure away from the substrate; and the third silicide layer and the fourth silicide layer contain the same metal element.

[0015] In one embodiment of the present application, the second silicide layer, the third silicide layer, and the fourth silicide layer contain the same metal element.

[0016] In one embodiment of the present application, in a direction intersecting with the first direction, a size of the third silicide layer is smaller than a size of the fourth silicide layer.

[0017] In one embodiment of the present application, the first gate structure includes at least one of a metal material gate and a semiconductor material gate; and / or the second gate structure includes at least one of a metal material gate and a semiconductor material gate.

[0018] In one embodiment of the present application, the semiconductor structure also includes a shallow trench isolation structure located between the first device region and the second device region, wherein, in a direction intersecting with the first direction, the second silicide layer extends from one side of the second gate structure to a side of the shallow trench isolation structure facing the second gate structure.

[0019] In one embodiment of the present application, the first silicide layer includes titanium silicide and the second silicide layer includes nickel silicide.

[0020] On the other hand, the present application provides a method for preparing a semiconductor structure, comprising: providing a substrate, the substrate comprising a first device region and a second device region; forming a first active region and a second active region extending from a first surface of the substrate into the first device region and the second device region, respectively; forming a first silicide layer at least partially located within the first active region, and forming a first contact structure on one side of the first silicide layer; and forming a second silicide layer on one side of the second active region, and forming a second contact structure on one side of the second silicide layer; wherein the resistivity of the second silicide layer is less than the resistivity of the first silicide layer.

[0021] In one embodiment of the present application, the first contact structure includes a first conductive layer and a first adhesive layer surrounding the first conductive layer, forming a first silicide layer at least partially located in the first active area, and forming a first contact structure on one side of the first silicide layer includes: forming a first contact hole extending into the first active area along a first direction, wherein the first contact hole exposes the first active area; and forming the first adhesive layer on the hole wall of the first contact hole, and forming the first conductive layer on the surface of the first adhesive layer, wherein the first silicide layer is formed in the process of forming the first adhesive layer.

[0022] In one embodiment of the present application, in the process of forming the first adhesion layer, forming the first silicide layer includes: forming an initial first adhesion layer in the first contact hole; and annealing the initial first adhesion layer so that the initial first adhesion layer reacts with a portion of the first active area to form the first silicide layer and the first metal layer, wherein the unreacted initial first adhesion layer and the first metal layer form the first adhesion layer.

[0023] In one embodiment of the present application, forming a second silicide layer on a side of the second active area close to the first surface includes: forming an initial dielectric barrier layer covering at least the first surface; removing a portion of the initial dielectric barrier layer covering the second active area to expose the second active area; forming a second metal layer on one side of the exposed second active area, and annealing the second metal layer so that the second metal layer reacts with a portion of the second active area to form a second silicide layer.

[0024] In one embodiment of the present application, the method further includes: forming a first gate structure extending along a first direction on one side of the first device region, and forming a second gate structure extending along the first direction on one side of the second device region; and forming a third silicide layer at an end of the first gate structure away from the substrate, and forming a fourth silicide layer at an end of the second gate structure away from the substrate.

[0025] In one embodiment of the present application, the initial dielectric barrier layer includes a first portion covering the end of the first gate structure away from the substrate, and forming the third silicide layer includes: removing a portion of the first portion to expose a portion of the first gate structure; forming a third metal layer on one side of the exposed portion of the first gate structure, and annealing the third metal layer so that the third metal layer reacts with a portion of the first gate structure to form the third silicide layer.

[0026] In one embodiment of the present application, the method further includes: forming a first protection layer covering the third silicide layer.

[0027] In one embodiment of the present application, the initial dielectric barrier layer also includes a second portion covering the end of the second gate structure away from the substrate, and forming the fourth silicide layer includes: removing the second portion to expose the second gate structure; forming a fourth metal layer on one side of the exposed second gate structure, and annealing the fourth metal layer so that the fourth metal layer reacts with a portion of the second gate structure to form the fourth silicide layer.

[0028] In one embodiment of the present application, the method further includes: forming a second protection layer covering the fourth silicide layer.

[0029] In one embodiment of the present application, the second silicide layer and the third silicide layer contain the same metal element; and / or the second silicide layer and the fourth silicide layer contain the same metal element.

[0030] In one embodiment of the present application, the second contact structure includes a second conductive layer and a second adhesive layer surrounding the second conductive layer, a second silicide layer is formed on one side of the second active area, and forming a second contact structure on one side of the second silicide layer includes: forming a second contact hole extending into the second silicide layer along the first direction, wherein the second contact hole exposes the second silicide layer; and forming the second adhesive layer on the hole wall of the second contact hole, and forming the second conductive layer on the surface of the second adhesive layer, wherein the second adhesive layer is formed in the process of forming the first adhesive layer.

[0031] In another aspect, the present application provides a memory system, comprising: the semiconductor structure provided in one aspect of the present application; and a controller coupled to the semiconductor structure and configured to control the semiconductor structure to store data.

[0032] According to at least one embodiment of the present application, a semiconductor structure, a method for manufacturing a semiconductor structure, and a memory system are provided. The semiconductor structure includes a first silicide layer connecting a first active area and a first contact structure, and a second silicide layer connecting a second active area and a second contact structure, wherein the resistivity of the second silicide layer is less than the resistivity of the first silicide layer. The relatively low resistivity of the second silicide layer enables a transistor including the second silicide layer to have a higher switching speed, a higher on-state current, and a faster response speed than a transistor including the first silicide layer, thereby improving the overall performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0034] Figure 1 is a schematic cross-sectional view of a semiconductor structure according to an exemplary embodiment of the present application;

[0035] Figure 2 yes Figure 1 An enlarged schematic diagram of a dotted box A in the semiconductor structure shown;

[0036] Figure 3 yes Figure 1An enlarged schematic diagram of a dotted box B in the semiconductor structure shown;

[0037] Figure 4 is a schematic top view of a semiconductor structure according to an embodiment;

[0038] Figure 5 is a schematic top view of a semiconductor structure according to an embodiment;

[0039] Figure 6 is a flow chart of a method for preparing a semiconductor structure according to one embodiment of the present application;

[0040] Figures 7 to 13 are schematic structural diagrams of a semiconductor structure preparation process according to one embodiment of the present application; and

[0041] Figure 14 is a schematic diagram of a memory system according to one embodiment of the present application. DETAILED DESCRIPTION

[0042] For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teachings of this application, the first silicide layer discussed in this application can also be referred to as the second silicide layer, and vice versa.

[0044] In the accompanying drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The accompanying drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximations, not degrees, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0045] It should also be understood that expressions such as "comprises," "including," "having," "includes," and / or "comprising" are open rather than closed expressions in this specification, indicating the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplary" is intended to refer to an example or illustration.

[0046] Unless otherwise defined, all words used herein (including engineering terms and scientific and technological terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having the same meaning as they do in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0047] It should be noted that, unless there is a conflict, the embodiments and features of the embodiments in this application may be combined with each other. In addition, unless explicitly limited or inconsistent with the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but may be performed in any order or in parallel.

[0048] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0049] The present application will be described in detail below with reference to the accompanying drawings and in combination with implementation methods.

[0050] Some embodiments of the present application provide a semiconductor structure. Figure 1 is a cross-sectional view of a semiconductor structure 1000 according to an exemplary embodiment of the present application. Figure 2 yes Figure 1 An enlarged schematic diagram of the dotted box A in the semiconductor structure 1000 is shown. Figure 3 yes Figure 1 An enlarged schematic diagram of the dotted box B in the semiconductor structure 1000 is shown.

[0051] Combined with reference Figure 1 、 Figure 2 and Figure 3The semiconductor structure 1000 includes a substrate 100 , a first active region 111 , a second active region 121 , a first silicide layer 210 , a second silicide layer 220 , a first contact structure 310 , and a second contact structure 320 .

[0052] The substrate 100 includes a first device region 110 and a second device region 120, wherein a first active region 111 is located in the first device region 110, and a second active region 121 is located in the second device region 120. The first active region 111 and the second active region 121 both extend from a first surface of the substrate 100 into the substrate 100, and the first surface is one of the two opposing main surfaces of the substrate 100. The substrate 100 includes main surfaces opposite to each other in the thickness direction (e.g., the z-direction), namely, a first main surface 101 and a second main surface 102, and the first surface may be one of the two opposing main surfaces of the substrate 100. It should be noted that Figure 1 The first main surface 101 is illustratively used as the first surface. In other embodiments, the second main surface 102 may also be used as the first surface.

[0053] The first contact structure 310 is located on one side of the first silicide layer 210, and the second contact structure 320 is located on one side of the second silicide layer 220, wherein the first silicide layer 210 connects the first active area 111 and the first contact structure 310, and the second silicide layer 220 connects the second active area 121 and the second contact structure 320, and the resistivity of the second silicide layer 220 is less than the resistivity of the first silicide layer 210.

[0054] In at least one embodiment of the present application, a semiconductor structure includes a first silicide layer connecting a first active area and a first contact structure, and a second silicide layer connecting a second active area and a second contact structure, wherein the resistivity of the second silicide layer is less than the resistivity of the first silicide layer. The relatively low resistivity of the second silicide layer enables a transistor including the second silicide layer to have a higher switching speed, a higher on-state current, and a faster response speed than a transistor including the first silicide layer, thereby improving the overall performance of the semiconductor structure.

[0055] In semiconductor structures, the resistivity of the silicide layer connecting the active area and the contact structure can affect parameters such as the resistivity, on-state current, and switching speed of the transistor structure in which the silicide layer is located. For example, a relatively low resistivity silicide layer can reduce the resistivity of the transistor and increase its on-state current and switching speed. However, due to process limitations, the preparation process for silicide layers with low resistivity is generally more complicated, and the size of the silicide layer in the semiconductor structure is also relatively large.

[0056] Figure 4 FIG. 1 is a schematic top view of a semiconductor structure 1 according to an embodiment. Figure 5FIG. 1 is a schematic top view of a semiconductor structure 1 according to an embodiment.

[0057] Specifically, if Figure 4 and Figure 5 As shown, the semiconductor structure 1 includes a first active region 11 and a second active region 12 located in a substrate 10. In addition, the semiconductor structure 1 also includes a first contact structure 31, a second contact structure 32, a first gate structure 41 and a second gate structure 42. Figure 4 In the semiconductor structure 1 shown, the silicide layer connecting the first active area 11 and the first contact structure 31 and the silicide layer connecting the second active area 12 and the second contact structure 32 are both silicide layers with relatively low resistivity, such as nickel silicide layer 22. Figure 5 In the semiconductor structure 1 shown, the silicide layer connecting the first active area 11 and the first contact structure 31 and the silicide layer connecting the second active area 12 and the second contact structure 32 are both silicide layers with relatively high resistivity, such as the titanium silicide layer 21, wherein the titanium silicide layer 21 has a small size in the xy plane intersecting with the thickness direction of the substrate 10 (for example, the z direction), so that the cross-section of the titanium silicide layer 21 in the xy plane can be completely covered by the first contact structure 31 or the second contact structure 32.

[0058] Compared with the nickel silicide layer 22, the titanium silicide layer 21 has a higher resistivity. However, the titanium silicide layer 21 is smaller in the xy plane. Therefore, the distance d2 between the gate structure of the semiconductor structure and the contact structure of its active area does not increase due to the titanium silicide layer 21, and the overall size of the semiconductor structure is relatively small. The nickel silicide layer 22 can reduce the resistivity of the transistor and increase the on-state current and switching speed of the transistor. However, the preparation process of the nickel silicide layer 22 is relatively complicated, and its size in the xy plane is larger, thereby increasing the distance d1 between the gate structure of the semiconductor structure and the contact structure of its active area, which in turn causes the overall size of the semiconductor structure to increase.

[0059] To improve this situation, a semiconductor structure in at least one embodiment of the present application includes two silicide layers with different resistivities, wherein the resistivity of the second silicide layer is lower than that of the first silicide layer. Consequently, transistors including the second silicide layer have higher switching speeds, higher on-state currents, and faster response speeds, while transistors including the first silicide layer have relatively smaller sizes. This improves the overall performance of the semiconductor structure while maintaining a balanced overall size.

[0060] Specifically, refer again to Figure 1In some embodiments of the present application, the material of the substrate 100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0061] The substrate 100 includes a first device region 110 and a second device region 120. The operating voltage of the transistor corresponding to the first device region 110 is different from the operating voltage of the transistor corresponding to the second device region 120. Exemplarily, the operating voltage of the transistor corresponding to the first device region 110 is higher than the operating voltage of the transistor corresponding to the second device region 120.

[0062] Optionally, the first active region 111 includes a first source region 111-1 and a first drain region 111-2. The second active region 121 includes a second source region 121-1 and a second drain region 121-2. The first active region 111 extends from the first surface of the first device region 110 of the substrate 100 into the first device region 110 of the substrate 100. The second active region 121 extends from the first surface of the second device region 120 of the substrate 100 into the second device region 120 of the substrate 100.

[0063] The first silicide layer 210 connects the first active region 111 and the first contact structure 310, thereby reducing the contact resistance between the first contact structure 310 and the first active region 111. The second silicide layer 220 connects the second active region 121 and the second contact structure 320, thereby reducing the contact resistance between the second contact structure 320 and the second active region 121.

[0064] Optionally, in one exemplary embodiment, the first contact structure 310 includes a first conductive layer 312 and a first adhesive layer 311 surrounding the first conductive layer 312. In other words, the first adhesive layer 311 may surround at least the sidewalls of the first conductive layer 312. The first adhesive layer 311 surrounds the sidewalls of the first conductive layer 312 and does not surround a side surface of the first conductive layer 312 facing the substrate 100. In other exemplary embodiments, the first adhesive layer surrounds both the sidewalls of the first conductive layer and a side surface of the first conductive layer facing the substrate.

[0065] In one exemplary embodiment, the material of the first conductive layer 312 includes any one or a combination of tungsten, cobalt, copper, and aluminum. Furthermore, the material of the first conductive layer 312 may include a semiconductor material such as crystalline silicon or an alloy material such as silicide. The material of the first adhesion layer 311 includes at least one of titanium (Ti) and titanium nitride (TiN).

[0066] In one exemplary embodiment, the first silicide layer 210 and the first adhesion layer 311 include the same metal element. For example, the material of the first adhesion layer 311 may include at least one of Ti and TiN, the material of the first silicide layer 210 may include titanium silicide, and both the first silicide layer 210 and the first adhesion layer 311 include the Ti element.

[0067] The first contact structure 310 and the second contact structure 320 extend along a first direction (e.g., z-direction) to the first silicide layer 210 and the second silicide layer 220, respectively. Optionally, the first contact structure 310 extends along the z-direction to the first silicide layer 210, and the second contact structure 320 extends along the z-direction to the second silicide layer 220.

[0068] The resistivity of the second silicide layer 220 is lower than that of the first silicide layer 210. The lower resistivity of the second silicide layer 220 enables a transistor including the second silicide layer 220 to have higher switching speed, higher on-state current, and faster response speed.

[0069] Optionally, the first silicide layer 210 and the second silicide layer 220 may be made of different materials. Since the first silicide layer 210 and the second silicide layer 220 are made of different materials, the first silicide layer 210 and the second silicide layer 220 may be formed in different process steps, respectively.

[0070] In addition, combined Figure 1-Figure 3 In some embodiments of the present application, in a direction intersecting with the z direction (for example, the x direction or the y direction), the size D1 of the first silicide layer 210 is smaller than the size D2 of the second silicide layer 220, thereby reducing the overall size of the transistor including the first silicide layer 210, thereby reducing the overall size of the semiconductor structure 1000.

[0071] In one exemplary embodiment, the first silicide layer 210 includes titanium silicide, and the second silicide layer 220 includes nickel silicide. In other embodiments, the first and second silicide layers may be made of other materials, without limitation, provided that the resistivity of the second silicide layer is less than that of the first silicide layer.

[0072] like Figure 2As shown, in one exemplary embodiment, at least a portion of the first silicide layer 210 is located in the first active region 111. This is because the first silicide layer 210 is formed in a first contact hole (not shown) that accommodates the first contact structure 310. During the process of forming the first contact hole using, for example, an etching process, the etching process may over-etch the first active region 111. The first contact hole may extend into the first active region 111 along the z-direction. Therefore, the first silicide layer 210 formed in the first contact hole may be at least partially embedded in the first active region 111. In other exemplary embodiments, the first silicide layer may not be embedded in the first active region. For example, the first silicide layer may be located on a side of the first active region close to the first surface.

[0073] like Figure 3 As shown, in an exemplary embodiment, the second silicide layer 220 is located on a side of the second active region 121 close to the first surface. For example, the second silicide layer 220 is located on the substrate 100 (eg, Figure 1 1 . This is because the second silicide layer 220 and the first silicide layer 210 are prepared using different processes. The second silicide layer 220 can be formed on the side of the second active region 121 close to the first surface by, for example, a deposition process. In other exemplary embodiments, the second silicide layer can also be at least partially embedded in the second active region.

[0074] Figure 1 In this example, at least a portion of the first silicide layer 210 is located in the first active region 111 , and the second silicide layer 220 is located on a side of the second active region 121 close to the first surface.

[0075] Reference again Figure 2 In one exemplary embodiment, the first contact structure 310 extends to the first silicide layer 210 along the z-direction, wherein in the x-direction or y-direction, the dimension D3 of the portion of the first contact structure 310 in contact with the first silicide layer 210 is greater than or equal to the dimension D1 of the first silicide layer 210. This improves the contact performance between the first contact structure 310 and the first silicide layer 210. Furthermore, the cross-section of the first silicide layer 210 in the xy plane may be completely covered by the first contact structure 310, thereby preventing the size of the transistor including the first silicide layer 210 from being increased due to the size of the first silicide layer 210. In other exemplary embodiments, in a direction intersecting the first direction, the dimension of the portion of the first contact structure in contact with the first silicide layer may be smaller than the dimension of the first silicide layer.

[0076] Reference again Figure 3In an exemplary embodiment, the second contact structure 320 extends to the second silicide layer 220 along the z direction, wherein a dimension D4 of a portion of the second contact structure 320 in contact with the second silicide layer 220 in the x direction or the y direction is smaller than a dimension D2 of the second silicide layer 220 .

[0077] In one exemplary embodiment, the second contact structure 320 extends into the second silicide layer 220, so that a portion of the sidewalls of the second contact structure 320 and a surface of the second contact structure 320 facing the substrate 100 are in contact with the second silicide layer 220. This increases the contact area between the second contact structure 320 and the second silicide layer 220, thereby improving the contact performance between the second contact structure 320 and the second silicide layer 220. In other exemplary embodiments, a surface of the second contact structure facing the substrate is in contact with the second silicide layer, and the sidewalls of the second contact structure are not in contact with the second silicide layer.

[0078] like Figure 1 As shown, in one exemplary embodiment, the second contact structure 320 includes a second conductive layer 322 and a second adhesive layer 321 surrounding the second conductive layer 322. In other words, the second adhesive layer 321 surrounds at least the sidewalls of the second conductive layer 322. The second adhesive layer 321 surrounds the sidewalls of the second conductive layer 322 and a side surface of the second conductive layer 322 facing the substrate 100. In other exemplary embodiments, the second adhesive layer surrounds the sidewalls of the second conductive layer but does not surround a side surface of the second conductive layer facing the substrate.

[0079] In one exemplary embodiment, the material of the second conductive layer 322 includes any one or a combination of tungsten, cobalt, copper, and aluminum. Furthermore, the material of the second conductive layer 322 may include a semiconductor material such as crystalline silicon or an alloy material such as silicide. The material of the second adhesion layer 321 includes at least one of Ti and TiN.

[0080] In one exemplary embodiment, the second silicide layer 220 and the second adhesion layer 321 include different metal elements. For example, the material of the second adhesion layer 321 includes at least one of Ti and TiN, the material of the second silicide layer 220 is nickel silicide, and the nickel (Ni) element in the second silicide layer 220 and the Ti element in the second adhesion layer 321 are different.

[0081] In one exemplary embodiment, the first adhesive layer 311 and the second adhesive layer 321 include the same conductive material. For example, the material of the first adhesive layer 311 includes Ti, and the material of the second adhesive layer 321 includes Ti. For another example, the material of the first adhesive layer 311 includes TiN, and the material of the second adhesive layer 321 includes TiN. For another example, the first adhesive layer 311 includes Ti and TiN, and the second adhesive layer 321 includes Ti and TiN.

[0082] like Figure 1 As shown, the semiconductor structure 1000 further includes a first gate structure 410 and a second gate structure 420 . The first gate structure 410 extends along the z direction and is located on one side of the first device region 110 . The second gate structure 420 extends along the z direction and is located on one side of the second device region 120 .

[0083] As an option, the first gate structure 410 may include at least one of a metal gate and a semiconductor gate; as another option, the second gate structure 420 may include at least one of a metal gate and a semiconductor gate; as yet another option, the first gate structure 410 may include at least one of a metal gate and a semiconductor gate, and the second gate structure 420 may include at least one of a metal gate and a semiconductor gate. Optionally, the semiconductor gate includes a polysilicon gate.

[0084] like Figure 1 As shown, optionally, the first gate structure 410 includes a first gate dielectric layer 410a located on a first surface side of the substrate 100, and a first gate electrode layer 410b located on a side of the first gate dielectric layer 410a facing away from the substrate 100. In addition, the second gate structure 420 includes a second gate dielectric layer 420a located on a first surface side of the substrate 100, and a second gate electrode layer 420b located on a side of the second gate dielectric layer 420a facing away from the substrate 100.

[0085] Alternatively, the first gate dielectric layer 410a may be made of silicon oxide or a high-k dielectric material. The second gate dielectric layer 420a may be made of silicon oxide or a high-k dielectric material. For example, k is greater than 3.9. Furthermore, the first gate electrode layer 410b may include at least one of a metal material and a semiconductor material. The second gate electrode layer 420b may include at least one of a metal material and a semiconductor material.

[0086] Optionally, the thickness of the first gate dielectric layer 410 a in the z direction may be greater than the thickness of the second gate dielectric layer 420 a in the z direction.

[0087] As an option, in a direction intersecting the z-direction (e.g., the x-direction or the y-direction), the dimension D5 of the first gate structure 410 may be larger than the dimension D6 of the second gate structure 420; as another option, the dimension H1 of the first gate structure 410 in the z-direction may be larger than the dimension H2 of the second gate structure 420 in the z-direction; as yet another option, in a direction intersecting the z-direction (e.g., the x-direction or the y-direction), the dimension D5 of the first gate structure 410 may be larger than the dimension D6 of the second gate structure 420, and the dimension H1 of the first gate structure 410 in the z-direction may be larger than the dimension H2 of the second gate structure 420 in the z-direction, which may enable the transistor including the first gate structure to adapt to a larger operating voltage.

[0088] like Figure 1 As shown, in an exemplary embodiment, the semiconductor structure 1000 further includes a third silicide layer 230 and a fourth silicide layer 240, wherein the third silicide layer 230 is located at an end of the first gate structure 410 away from the substrate 100, and the fourth silicide layer 240 is located at an end of the second gate structure 420 away from the substrate 100. Specifically, the third silicide layer 230 is located at an end of the first gate electrode layer 410b away from the substrate 100, and the fourth silicide layer 240 is located at an end of the second gate electrode layer 420b away from the substrate 100.

[0089] like Figure 1 As shown, in one exemplary embodiment, the semiconductor structure 1000 further includes a third contact structure 330 and a fourth contact structure 340. The third contact structure 330 is located on a side of the third silicide layer 230 facing away from the first gate structure 410, and the fourth contact structure 340 is located on a side of the fourth silicide layer 240 facing away from the second gate structure 420. The third silicide layer 230 can reduce the contact resistance between the third contact structure 330 and the first gate electrode layer 410b. The fourth silicide layer 240 can reduce the contact resistance between the fourth contact structure 340 and the second gate electrode layer 420b.

[0090] Optionally, the third silicide layer 230, the fourth silicide layer 240, and the second silicide layer 220 may be made of the same material. The third silicide layer, the fourth silicide layer, and the second silicide layer are made of the same silicide layer with a relatively low resistivity. This simplifies the fabrication process while enabling the transistor including the second silicide layer, the third silicide layer, and the fourth silicide layer to have a higher switching speed, a higher on-state current, and a faster response speed.

[0091] like Figure 1As shown, in one exemplary embodiment, the third contact structure 330 includes a third conductive layer 332 and a third adhesive layer 331 surrounding the third conductive layer 332. In other words, the third adhesive layer 331 surrounds at least the sidewalls of the third conductive layer 332. The third adhesive layer 331 surrounds the sidewalls of the third conductive layer 332 and a side surface of the third conductive layer 332 facing the substrate 100. In other exemplary embodiments, the third adhesive layer surrounds the sidewalls of the third conductive layer but does not surround a side surface of the third conductive layer facing the substrate.

[0092] like Figure 1 As shown, in one exemplary embodiment, the fourth contact structure 340 includes a fourth conductive layer 342 and a fourth adhesive layer 341 surrounding the fourth conductive layer 342. In other words, the fourth adhesive layer 341 surrounds at least the sidewalls of the fourth conductive layer 342. The fourth adhesive layer 341 surrounds the sidewalls of the fourth conductive layer 342 and a side surface of the fourth conductive layer 342 facing the substrate 100. In other exemplary embodiments, the fourth adhesive layer surrounds the sidewalls of the fourth conductive layer but does not surround a side surface of the fourth conductive layer facing the substrate.

[0093] In one exemplary embodiment, the material of the third conductive layer 332 includes any one or a combination of tungsten, cobalt, copper, and aluminum. The material of the third conductive layer 332 may also include a semiconductor material such as crystalline silicon or an alloy material such as silicide. Furthermore, the material of the third adhesion layer 331 includes at least one of Ti and TiN. Alternatively, the material of the fourth conductive layer 342 includes any one or a combination of tungsten, cobalt, copper, and aluminum. The material of the fourth conductive layer 342 may also include a semiconductor material such as crystalline silicon or an alloy material such as silicide. Furthermore, the material of the fourth adhesion layer 341 includes at least one of Ti and TiN.

[0094] In one exemplary embodiment, the third silicide layer 230 and the fourth silicide layer 240 include the same metal element. For example, the material of the third silicide layer 230 includes nickel silicide, the material of the fourth silicide layer 240 includes nickel silicide, and both the third silicide layer 230 and the fourth silicide layer 240 include nickel. The materials of the third silicide layer 230 and the fourth silicide layer 240 can be the same or different, and this application is not limited thereto.

[0095] In one exemplary embodiment, the second silicide layer 220, the third silicide layer 230, and the fourth silicide layer 240 include the same metal element. For example, the material of the second silicide layer 220 includes nickel silicide, the material of the third silicide layer 230 includes nickel silicide, and the material of the fourth silicide layer 240 includes nickel silicide. The second silicide layer 220, the third silicide layer 230, and the fourth silicide layer 240 all include nickel. In other exemplary embodiments, the materials of the second silicide layer 220, the third silicide layer 230, and the fourth silicide layer 240 can be the same, partially the same, or completely different, and this application is not limited thereto.

[0096] refer to Figure 2 and Figure 3 In one exemplary embodiment, because the dimension D1 of the first silicide layer 210 is smaller than the dimension D2 of the second silicide layer 220, the dimension D1 of the first silicide layer 210 is smaller, thereby reducing the spacing between adjacent first gate structures 410. For example, the spacing between adjacent first gate structures 410 along the x-direction is 80 nm to 120 nm, such as 100 nm, and the spacing between adjacent first gate structures 410 along the y-direction is 550 nm to 650 nm, such as 600 nm.

[0097] like Figure 1 As shown, in an exemplary embodiment, the semiconductor structure 1000 further includes a first dielectric barrier layer 620. The first dielectric barrier layer 620 covers at least the sidewall surfaces of the first gate electrode layer 410b, a surface of the first gate electrode layer 410b facing away from the substrate 100, and the first active region 111. The material of the first dielectric barrier layer 620 includes at least one of silicon oxide (SiO2), silicon oxynitride (SiON), and silicon nitride (Si3N4).

[0098] like Figure 1 As shown, in one exemplary embodiment, the semiconductor structure 1000 further includes a second dielectric barrier layer 621. The second dielectric barrier layer 621 covers the sidewall surfaces of the second gate structure 420 and does not cover the second silicide layer 220. In other exemplary embodiments, the second dielectric barrier layer may also cover the surface of the second gate electrode layer facing away from the substrate. In other exemplary embodiments, the second dielectric barrier layer may also cover a portion of the substrate 100. The material of the second dielectric barrier layer 621 includes at least one of SiO2, SiON, and Si3N4. The material of the first dielectric barrier layer 620 and the second dielectric barrier layer 621 may be the same or different, and this is not limited in this application.

[0099] like Figure 1As shown, in an exemplary embodiment, in the x-direction or the y-direction, a dimension D7 of the third silicide layer 230 is smaller than a dimension D8 of the fourth silicide layer 240. The edge region of the first gate electrode layer 410b on the side facing away from the substrate 100 and the sidewall surface of the first gate electrode layer 410b are covered by the first dielectric barrier layer 620. Thus, the corner of the first gate electrode layer 410b on the side facing away from the substrate 100 is better protected, thereby improving the anti-breakdown capability of the interlayer dielectric layer 400 between the corner of the first gate electrode layer 410b on the side facing away from the substrate 100 and the first contact structure 310.

[0100] like Figure 1 As shown, in one exemplary embodiment, the semiconductor structure 1000 further includes a shallow trench isolation structure 500 located between the first device region 110 and the second device region 120. A portion of the shallow trench isolation structure 500 is embedded in the substrate 100, and another portion of the shallow trench isolation structure 500 protrudes from the first surface of the substrate 100. Optionally, the material of the shallow trench isolation structure 500 includes silicon oxide.

[0101] In one exemplary embodiment, in the x-direction or the y-direction, the second silicide layer 220 extends from one side of the second gate structure 420 to a side of the shallow trench isolation structure 500 facing the second gate structure 420. Specifically, the second silicide layer 220 extends from a side of the second gate structure 420 away from the shallow trench isolation structure 500 to a side of the shallow trench isolation structure 500 facing the second gate structure 420.

[0102] In an exemplary embodiment, the first silicide layer 210 and the shallow trench isolation structure 500 may be spaced apart.

[0103] like Figure 1 As shown, in one exemplary embodiment, the semiconductor structure 1000 further includes a first protective layer 640. The first protective layer 640 is located on a surface of the third silicide layer 230 facing away from the first gate structure 410. Furthermore, the first protective layer 640 covers the first dielectric barrier layer 620. The material of the first protective layer 640 includes silicon nitride. In other exemplary embodiments, the first protective layer is located on a surface of the third silicide layer facing away from the first gate structure, and the first protective layer does not cover the first dielectric barrier layer.

[0104] refer to Figure 1 In one exemplary embodiment, the semiconductor structure 1000 further includes a second protective layer 650, which is located on a surface of the fourth silicide layer 240 facing away from the second gate structure 420. Furthermore, the second protective layer 650 may also cover the second dielectric barrier layer 621, the second silicide layer 220, and a portion of the substrate 100. The material of the second protective layer 650 includes silicon nitride.

[0105] refer to Figure 1 In one exemplary embodiment, the semiconductor structure 1000 further includes a third protective layer 630, which may cover the surface of the portion of the shallow trench isolation structure 500 protruding from the substrate 100. Optionally, the material of the third protective layer 630 includes silicon nitride.

[0106] refer to Figure 1 In one exemplary embodiment, the semiconductor structure 1000 further includes an interlayer dielectric layer 400. The interlayer dielectric layer 400 may cover at least the first gate structure 410 and the second gate structure 420. Optionally, the interlayer dielectric layer 400 may cover the first protective layer 640, the second protective layer 650, and the third protective layer 630. Optionally, the material of the interlayer dielectric layer 400 includes at least one of SiO2, SiON, and Si3N4.

[0107] Optionally, the third contact structure 330 extends in the interlayer dielectric layer 400 along the z-direction, penetrates a portion of the first protective layer 640 located on a side of the first gate electrode layer 410b facing away from the substrate 100, and connects to the third silicide layer 230. Furthermore, the fourth contact structure 340 extends in the interlayer dielectric layer 400 along the z-direction, penetrates a portion of the second protective layer 650 located on a side of the second gate electrode layer 420b facing away from the substrate 100, and connects to the fourth silicide layer 240.

[0108] Figure 6 2000 is a flow chart of a method for preparing a semiconductor structure according to one embodiment of the present application. Figure 7-13 Each of them is a process schematic diagram of a method for preparing a semiconductor structure according to one embodiment of the present application.

[0109] On the other hand, the present application also provides a method 2000 for preparing a semiconductor structure. Figure 6 As shown, the method 2000 for preparing a semiconductor structure may include:

[0110] S1, providing a substrate, the substrate including a first device region and a second device region.

[0111] S2 , forming a first active region and a second active region extending from the first surface of the substrate into the first device region and the second device region respectively.

[0112] S3 , forming a first silicide layer at least partially located in the first active region, and forming a first contact structure on one side of the first silicide layer.

[0113] S4 forms a second silicide layer on one side of the second active region, and forms a second contact structure on one side of the second silicide layer, wherein the resistivity of the second silicide layer is lower than the resistivity of the first silicide layer.

[0114] The following will be combined Figure 7-14 The specific process of each step of the above-mentioned preparation method 2000 in this application is described in detail.

[0115] Step S1

[0116] Figure 7 1 is a schematic cross-sectional view of a structure formed after forming the first active region 111 and the second active region 121 according to one embodiment of the present application.

[0117] refer to Figure 7 Step S1 provides a substrate, and the substrate includes a first device region and a second device region. The step may include, for example: forming a substrate 100 ; and forming a shallow trench isolation structure 500 in the substrate 100 .

[0118] In an exemplary embodiment, the material of the substrate 100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0119] In one exemplary embodiment, the substrate 100 may be, for example, a composite substrate for supporting a device structure thereon. The substrate 100 may be formed by sequentially forming multiple layers made of different materials using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0120] In an exemplary embodiment, the substrate 100 includes opposite main surfaces in the thickness direction (e.g., z-direction), namely, a first main surface 101 and a second main surface 102. The first surface is one of the two opposite main surfaces of the substrate 100. It should be noted that Figure 7 The first main surface 101 is illustratively used as the first surface. In other embodiments, the second main surface 102 can be used as the first surface.

[0121] The substrate 100 includes a first device region 110 and a second device region 120. The operating voltage of the transistor corresponding to the first device region 110 is different from the operating voltage of the transistor corresponding to the second device region 120. Exemplarily, the operating voltage of the transistor corresponding to the first device region 110 is higher than the operating voltage of the transistor corresponding to the second device region 120.

[0122] refer to Figure 7After forming the substrate 100, a shallow trench isolation structure 500 at least partially located in the substrate 100 may be formed. In other words, a portion of the shallow trench isolation structure 500 is embedded in the substrate 100, and another portion of the shallow trench isolation structure 500 protrudes from the first surface of the substrate 100. Alternatively, the material used to form the shallow trench isolation structure 500 may include silicon oxide.

[0123] Specifically, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed to form a shallow trench (not shown) extending along the z direction in the substrate 100. After the shallow trench is formed, a shallow trench isolation structure 500 can be formed by at least one thin film deposition process, and the thin film deposition process includes but is not limited to a thin film deposition process of CVD, PVD, ALD, or any combination thereof. Optionally, the shallow trench isolation structure 500 is filled in the shallow trench and covers a portion of the first surface of the substrate 100. In addition, the structure and preparation process of the shallow trench isolation structure 500 can adopt existing conventional processes and be prepared according to actual needs, which will not be described in detail in this application.

[0124] Optionally, the shallow trench isolation structure 500 can be used to isolate the first device region 110 and the second device region 120, so that the shallow trench isolation structure 500 can be located between the first device region 110 and the second device region 120 along the x-direction or the y-direction; or, the shallow trench isolation structure 500 can be located in the portion of the first device region 110 adjacent to the second device region 120 or the portion of the second device region 120 adjacent to the first device region 110.

[0125] Step S2

[0126] Continue to refer Figure 7 Step S2 of forming the first active region and the second active region extending from the first surface of the substrate to the first device region and the second device region respectively may, for example, include: in a partial area of ​​the substrate 100, through ion implantation or diffusion process, active regions formed by doping with N-type or P-type dopants, such as the first active region 111 and the second active region 121.

[0127] Alternatively, the dopant may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb); or any one or a combination of boron (B), gallium (Ga), or indium (In). In some embodiments of the present application, the active region may be prepared using the same dopant or different dopants. Furthermore, the doping concentrations of the active region may be the same or different, and this application does not limit this.

[0128] The first active region 111 extends from the first surface of the substrate 100 into the first device region 110. The second active region 121 extends from the first surface of the substrate 100 into the second device region 120. The first active region 111 includes a first source region 111-1 and a first drain region 111-2. The second active region 121 includes a second source region 121-1 and a second drain region 121-2.

[0129] In addition, in an exemplary embodiment, the method 2000 for preparing a semiconductor structure further includes: forming a first gate structure 410 extending along the z direction on one side of the first device region 110 , and forming a second gate structure 420 extending along the z direction on one side of the second device region 120 .

[0130] The first source region 111-1 and the first drain region 111-2 may be separated in the z direction by the first gate structure 410, and the second source region 121-1 and the second drain region 121-2 may be separated in the z direction by the second gate structure 420. In other words, the gate structure is formed between the source and the drain along the z direction.

[0131] For example, the first gate structure 410 and the second gate structure 420 may be formed before the first active region 111 and the second active region 121 are formed.

[0132] refer to Figure 7 The first gate dielectric layer 410a and the second gate dielectric layer 420a can be formed by at least one thin film deposition process. The thin film deposition process includes, but is not limited to, CVD, PVD, ALD, or any combination thereof. Alternatively, the first gate dielectric layer 410a can be made of silicon oxide or a high-k dielectric material. The second gate dielectric layer 420a can be made of silicon oxide or a high-k dielectric material. For example, k is greater than 3.9.

[0133] Optionally, the thickness of the first gate dielectric layer 410 a in the z direction may be greater than the thickness of the second gate dielectric layer 420 a in the z direction.

[0134] After forming the first gate dielectric layer 410a and the second gate dielectric layer 420a, a first gate electrode layer 410b and a second gate electrode layer 420b may be formed by at least one thin film deposition process, thereby forming a first gate structure 410 including the first gate dielectric layer 410a and the first gate electrode layer 410b, and a second gate structure 420 including the second gate dielectric layer 420a and the second gate electrode layer 420b. The thin film deposition process includes, but is not limited to, a thin film deposition process using CVD, PVD, ALD, or any combination thereof. Optionally, the material used to form the first gate electrode layer 410b or the second gate electrode layer 420b may include at least one of a metal material and a semiconductor material.

[0135] Optionally, when the material of the first gate electrode layer 410b or the second gate electrode layer 420b includes a semiconductor material, the first gate electrode layer 410b and the second gate electrode layer 420b may also be formed by an epitaxial growth process. The epitaxial growth process includes: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof. The semiconductor material for preparing the first gate electrode layer 410b or the second gate electrode layer 420b may include at least one of silicon, silicon germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials.

[0136] The first gate structure 410 includes a first gate dielectric layer 410a located on one side of the first surface of the substrate 100, and a first gate electrode layer 410b located on a side of the first gate dielectric layer 410a facing away from the substrate 100. The second gate structure 420 includes a second gate dielectric layer 420a located on one side of the first surface of the substrate 100, and a second gate electrode layer 420b located on a side of the second gate dielectric layer 420a facing away from the substrate 100. The first source region 111-1 and the first drain region 111-2 are respectively located in portions of the substrate 100 on either side of the first gate electrode layer 410b. The second source region 121-1 and the second drain region 121-2 are respectively located in portions of the substrate 100 on either side of the second gate electrode layer 420b.

[0137] Continue to refer Figure 7 Optionally, an initial dielectric barrier layer 610 covering at least the first surface is formed by at least one thin film deposition process, and the thin film deposition process includes but is not limited to CVD, PVD, ALD or any combination thereof.

[0138] In an exemplary embodiment, the initial dielectric barrier layer 610 covers at least the sidewalls of the first gate electrode layer 410 b , the sidewalls of the second gate structure 420 , the first active region 111 , the second active region 121 , and the portion of the shallow trench isolation structure 500 protruding from the substrate 100 .

[0139] In an exemplary embodiment, the material of the initial dielectric barrier layer 610 may include one of SiO 2 , SiON, and Si 3 N 4 .

[0140] Figure 8 3 is a schematic cross-sectional view of a structure formed after forming the first dielectric barrier layer 620 according to one embodiment of the present application.

[0141] refer to Figure 7 and Figure 8, formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove the portion of the initial dielectric barrier layer 610 covering the second active area 121, thereby exposing the second active area 121.

[0142] In addition, the above process can also be performed to remove the first portion of the initial dielectric barrier layer 610 covering the end of the first gate structure 410 away from the substrate 100 and the second portion of the initial dielectric barrier layer 610 covering the end of the second gate structure 420 away from the substrate 100, thereby exposing the first gate electrode layer 410b and the second gate electrode layer 420b.

[0143] Specifically, the initial dielectric barrier layer 610 includes a first portion covering the end of the first gate structure 410 away from the substrate 100. Optionally, the aforementioned process may be performed to remove a portion of the first portion, thereby exposing a portion of the first gate electrode layer 410b of the first gate structure 410. In other exemplary embodiments, the aforementioned process may also be performed to remove the entire first portion, which is not limited in this application. The remaining portion of the initial dielectric barrier layer 610 located on one side of the first device region 110 forms the first dielectric barrier layer 620.

[0144] In one exemplary embodiment, the initial dielectric barrier layer 610 includes a second portion covering an end portion of the second gate structure 420 away from the substrate 100. Optionally, the above process may be performed to remove the second portion, exposing the second gate structure 420. For example, the surface of the second gate electrode layer 420b facing away from the substrate 100 is exposed.

[0145] In addition, the initial dielectric barrier layer 610 further includes a third portion covering the surface of the second device region 120. Optionally, the aforementioned process can be performed to remove the third portion, exposing the surface of the second device region 120. The remaining portion of the initial dielectric barrier layer 610 located on the sidewalls of the second gate structure 420 is formed as a second dielectric barrier layer 621.

[0146] Optionally, the above process may be further performed to remove the portion of the initial dielectric barrier layer 610 covering the shallow trench isolation structure 500 , exposing the shallow trench isolation structure 500 .

[0147] Steps S3 and S4

[0148] Figure 9 FIG. 1 is a schematic cross-sectional view of a structure formed after forming the second silicide layer 220 according to one embodiment of the present application. Figure 10 FIG. 5 is a schematic cross-sectional view of a structure formed after forming the second protective layer 650 according to one embodiment of the present application. Figure 114 is a schematic cross-sectional view of a structure formed after forming an interlayer dielectric layer 400 according to one embodiment of the present application. Figure 12 3 is a schematic cross-sectional view of a structure formed after forming the first to fourth contact holes 310 a to 340 a according to one embodiment of the present application. Figure 13 3 is a schematic cross-sectional view of a structure formed after forming the first silicide layer 210 , the first contact structure 310 , and the second contact structure 320 according to one embodiment of the present application.

[0149] In some embodiments of the present application, step S3 may be performed first, and then step S4; in other embodiments of the present application, step S4 may be performed first, and then step S3; in still other embodiments of the present application, steps S3 and S4 may be performed in one process. For the purpose of reducing production costs and shortening process steps, the following will take the execution of steps S3 and S4 in one process as an example, and describe in detail the preparation process of the first silicide layer, the second silicide layer, the first contact structure, and the second contact structure in conjunction with the accompanying drawings. However, it will be understood by those skilled in the art that the present application does not limit the execution order of steps S3 and S4, and the characteristics, implementation principles, and technical effects of the structures obtained by completing steps S3 and S4 in any order are similar.

[0150] like Figure 8-Figure 9 As shown, in some embodiments of the present application, forming a second silicide layer on one side of the second active region may include: forming a second metal layer (not shown) on one side of the second active region; and annealing the second metal layer to form a second silicide layer 220.

[0151] A second metal layer may be formed on one side of the exposed second active region 121 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. For example, the material used to form the second metal layer may include nickel. After the second metal layer is formed, the second metal layer may be annealed to react with a portion of the second active region 121 to form a second silicide layer 220. The second silicide layer 220 is located on the side of the second active region 121 that is close to the first surface.

[0152] In an exemplary embodiment, the method 2000 for preparing a semiconductor structure further includes forming a third silicide layer 230 at an end of the first gate structure 410 away from the substrate 100 , and forming a fourth silicide layer 240 at an end of the second gate structure 420 away from the substrate 100 .

[0153] Combine Figure 7-Figure 9In an exemplary embodiment, the initial dielectric barrier layer 610 includes a first portion covering an end portion of the first gate structure 410 away from the substrate 100 . Removing a portion of the first portion may expose a portion of the first gate structure 410 .

[0154] A third metal layer (not shown) may be formed on one side of the exposed portion of the first gate structure 410 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. After the third metal layer is formed, the third metal layer is annealed to react with a portion of the first gate structure 410, such as the first gate electrode layer 410 b, to form a third silicide layer 230.

[0155] In an exemplary embodiment, the initial dielectric barrier layer 610 further includes a second portion covering an end portion of the second gate structure 420 away from the substrate 100 . The second gate structure 420 can be exposed by removing the second portion.

[0156] A fourth metal layer (not shown) may be formed on one side of the exposed second gate structure 420 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. After the fourth metal layer is formed, the fourth metal layer may be annealed to react with a portion of the second gate structure 420, such as the second gate electrode layer 420 b, to form a fourth silicide layer 240.

[0157] In one exemplary embodiment, the second metal layer, the third metal layer, and the fourth metal layer can be formed in the same step, thereby simplifying the production process and cost of preparing the semiconductor structure. In addition, the materials of the second metal layer, the third metal layer, and the fourth metal layer can be the same. For example, the materials for preparing the second metal layer, the third metal layer, and the fourth metal layer all include nickel. In other embodiments, the materials of the second metal layer, the third metal layer, and the fourth metal layer can be partially the same or completely different, and this application is not limited to this.

[0158] In an exemplary embodiment, the steps of annealing the second metal layer, annealing the third metal layer, and annealing the fourth metal layer can be performed in the same process, thereby simplifying the production process and cost of preparing the semiconductor structure.

[0159] Optionally, the second silicide layer 220 and the third silicide layer 230 formed by the above embodiment may contain the same metal element; optionally, the second silicide layer 220 and the fourth silicide layer 240 formed by the above embodiment may contain the same metal element; optionally, the second silicide layer 220, the third silicide layer 230 and the fourth silicide layer 240 formed by the above embodiment may contain the same metal element.

[0160] For example, the material of the second silicide layer 220 is nickel silicide, the material of the third silicide layer 230 is nickel silicide, and the second silicide layer 220 and the third silicide layer 230 both contain nickel. Alternatively, the material of the second silicide layer 220 is nickel silicide, the material of the fourth silicide layer 240 is nickel silicide, and the second silicide layer 220 and the fourth silicide layer 240 both contain nickel. Alternatively, the material of the second silicide layer 220 is nickel silicide, the material of the third silicide layer 230 is nickel silicide, and the material of the fourth silicide layer 240 is nickel silicide, and the second silicide layer 220, the third silicide layer 230, and the fourth silicide layer 240 all contain nickel. In addition, the materials of the third silicide layer 230 and the fourth silicide layer 240 may be the same or different; the materials of the second silicide layer 220, the third silicide layer 230 and the fourth silicide layer 240 may be the same, partially the same or completely different, which is not limited in this application.

[0161] refer to Figure 9 and Figure 10 In some embodiments of the present application, after the third silicide layer 230 and the fourth silicide layer 240 are formed, a first protective layer 640 covering the third silicide layer 230 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and the first protective layer 640 is located at least on the side surface of the third silicide layer 230 away from the first gate structure 410; and a second protective layer 650 covering the fourth silicide layer 240 is formed, and the second protective layer 650 is located at least on the side surface of the fourth silicide layer 240 away from the second gate structure 420.

[0162] Optionally, the material of the first protective layer 640 illustratively includes silicon nitride. The material of the second protective layer 650 illustratively includes silicon nitride.

[0163] refer to Figure 10 The first protection layer 640 may further cover the first dielectric barrier layer 620 . In addition, the second protection layer 650 may further cover the second dielectric barrier layer 621 and the second silicide layer 220 .

[0164] In other exemplary embodiments, the first protective layer is located on a surface of the third silicide layer facing away from the first gate structure, and the first protective layer does not cover the first dielectric barrier layer. In other exemplary embodiments, the second protective layer covers the fourth silicide layer, and the second protective layer does not cover the second dielectric barrier layer and the second silicide layer.

[0165] refer to Figure 9 and Figure 10 In one exemplary embodiment, the method 2000 for preparing a semiconductor structure further includes forming a third protective layer 630. The third protective layer 630 is formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to cover the surface of the portion of the shallow trench isolation structure 500 protruding from the substrate 100. Optionally, the material of the third protective layer 630 illustratively includes silicon nitride.

[0166] In an exemplary embodiment, the first protective layer 640 , the second protective layer 650 , and the third protective layer 630 are formed in the same process, thereby simplifying the production process and cost of manufacturing the semiconductor structure.

[0167] refer to Figure 10 Figure 11 The method 2000 for preparing a semiconductor structure further includes forming an interlayer dielectric layer 400 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The interlayer dielectric layer 400 may cover the first gate structure 410, the second gate structure 420, and the substrate 100. For example, the interlayer dielectric layer 400 may cover the first protective layer 640, the second protective layer 650, the third protective layer 630, and the first surface. The material of the interlayer dielectric layer 400 includes at least one of SiO2, SiON, and Si3N4.

[0168] refer to Figure 11 and Figure 12 In some embodiments of the present application, a first contact hole 310 a is formed extending along the z-direction to the first active region 111, and the first contact hole 310 a exposes the first active region 111. In addition, a second contact hole 320 a is further formed extending along the z-direction to the second silicide layer 220, and the second contact hole 320 a exposes the second silicide layer 220.

[0169] Alternatively, the first contact hole 310a and the second contact hole 320a may be formed by, for example, a dry etching process or a combination of dry and wet etching processes.

[0170] Optionally, the first contact hole 310a penetrates the interlayer dielectric layer 400 along the z-direction and extends into the first active region 111. Optionally, the second contact hole 320a penetrates the interlayer dielectric layer 400 along the z-direction and extends into the second silicide layer 220. In other exemplary embodiments, the first contact hole may penetrate the interlayer dielectric layer along the z-direction and not extend into the first active region. In other exemplary embodiments, the second contact hole may penetrate the interlayer dielectric layer along the z-direction and not extend into the second silicide layer.

[0171] In one exemplary embodiment, the second contact hole 320a is formed during the formation of the first contact hole 310a, thereby simplifying the production process and cost of manufacturing the semiconductor structure. In other exemplary embodiments, the first contact hole and the second contact hole may be formed in separate steps, such that the second contact hole is formed after the first contact hole is formed, or the first contact hole is formed after the second contact hole is formed.

[0172] refer to Figure 11 and Figure 12 In an exemplary embodiment, the method 2000 for preparing a semiconductor structure further includes: forming a third contact hole 330 a and forming a fourth contact hole 340 a .

[0173] In one exemplary embodiment, the third and fourth contact holes 330 a and 340 a may be formed by, for example, a dry etching process or a combination of dry and wet etching processes.

[0174] In one exemplary embodiment, the third contact hole 330a extends along the z-direction into the third silicide layer 230. In one exemplary embodiment, the fourth contact hole 340a extends along the z-direction into the fourth silicide layer 240. In other exemplary embodiments, the third contact hole may not extend into the third silicide layer. In other exemplary embodiments, the fourth contact hole may not extend into the fourth silicide layer.

[0175] In one exemplary embodiment, the fourth contact hole 340a can be formed during the formation of the third contact hole 330a, thereby simplifying the production process and cost of manufacturing the semiconductor structure. In other exemplary embodiments, the third contact hole and the fourth contact hole can be formed in different steps, such as forming the fourth contact hole after forming the third contact hole, or forming the third contact hole after forming the fourth contact hole.

[0176] In addition, as an option, the first contact hole 310a, the second contact hole 320a, the third contact hole 330a and the fourth contact hole 340a may also be formed in the same process.

[0177] refer to Figure 1 、 Figure 12 and Figure 13 , forming a first silicide layer 210 at least partially located in the first active region 111 , and forming a first contact structure 310 on one side of the first silicide layer 210 ; and forming a second contact structure 320 on one side of the second silicide layer 220 .

[0178] The step of forming the first contact structure 310 may include: forming a first adhesive layer 311 on the hole wall of the first contact hole 310a, and forming a first conductive layer 312 on the surface of the first adhesive layer 311; the step of forming the second contact structure 320 may include: forming a second adhesive layer 321 on the hole wall of the second contact hole 320a, and forming a second conductive layer 322 on the surface of the second adhesive layer 321.

[0179] In one exemplary embodiment, the first silicide layer 210 may be formed during the process of forming the first adhesive layer 311 .

[0180] Illustratively, an initial first adhesion layer 311' is formed on the sidewall surface of the first contact hole 310a and the surface of the first source and drain region 111 exposed by the first contact hole 310a; the initial first adhesion layer 311' is annealed to react with a portion of the first active region 111 to form a first silicide layer 210 and a first metal layer, and the unreacted initial first adhesion layer 311' and the first metal layer form the first adhesion layer 311.

[0181] In one exemplary embodiment, the second adhesive layer 321 is formed during the process of forming the first adhesive layer 311, thereby simplifying the production process and cost of manufacturing the semiconductor structure. In other exemplary embodiments, the first adhesive layer 311 and the second adhesive layer 321 may be formed separately in different processes.

[0182] For example, the second adhesive layer can be formed during the step of forming the initial first adhesive layer 311'. For example, the step of forming the initial first adhesive layer 311' and the second adhesive layer 321 can include: forming an adhesive film (not shown) on the inner walls of the first contact hole 310a and the second contact hole 320a and on the surface of the interlayer dielectric layer 400 facing away from the substrate 100; removing the adhesive film from the surface of the interlayer dielectric layer 400 facing away from the substrate 100, so that the adhesive film on the inner wall of the first contact hole 310a forms the initial first adhesive layer 311', and the adhesive film on the inner wall of the second contact hole 320a forms the second adhesive layer 321. The process for forming the adhesive film includes a deposition process, including but not limited to CVD, PVD, ALD, or any combination thereof. The process for removing the adhesive film from the surface of the interlayer dielectric layer 400 facing away from the substrate 100 includes an etching process, such as any one or a combination of a wet etching process and a dry etching process.

[0183] In other exemplary embodiments, the initial first adhesive layer 311 ′ and the second adhesive layer 321 may be formed sequentially in different steps. For example, the second adhesive layer 321 may be formed after the initial first adhesive layer 311 ′, or the initial first adhesive layer 311 ′ may be formed after the second adhesive layer 321 is formed.

[0184] In one exemplary embodiment, after forming the first adhesive layer 311, a first conductive layer 312 is formed in the first contact hole 310a on a surface of the first adhesive layer 311. After forming the second adhesive layer 321, a second conductive layer 322 is formed in the second contact hole 320a on a surface of the second adhesive layer 321.

[0185] refer to Figure 13 In an exemplary embodiment, the method further includes: forming a third contact structure 330 in the third contact hole 330a; and forming a fourth contact structure 340 in the fourth contact hole 340a.

[0186] refer to Figure 13 The step of forming the third contact structure 330 in the third contact hole 330a may include: forming a third adhesive layer 331 on the hole wall of the third contact hole 330a; forming a third conductive layer 332 on the surface of the third adhesive layer 331 in the third contact hole 330a, with the third adhesive layer 331 surrounding the third conductive layer 332. The step of forming the fourth contact structure 340 in the fourth contact hole 340a may include: forming a fourth adhesive layer 341 on the hole wall of the fourth contact hole 340a; forming a fourth conductive layer 342 on the surface of the fourth adhesive layer 341 in the fourth contact hole 340a, with the fourth adhesive layer 341 surrounding the fourth conductive layer 342.

[0187] In one exemplary embodiment, the second adhesive layer 321, the third adhesive layer 331, and the fourth adhesive layer 341 are formed in the step of forming the initial first adhesive layer 311'. For example, in the step of forming the adhesive film, the adhesive film is also formed on the inner wall of the third contact hole 330a and the inner wall of the fourth contact hole 340a. After the adhesive film is formed on the surface of the interlayer dielectric layer 400 facing away from the substrate 100, the adhesive film on the inner wall of the third contact hole 330a forms the third adhesive layer 331, and the adhesive film on the inner wall of the fourth contact hole 340a forms the fourth adhesive layer 341.

[0188] In one exemplary embodiment, the steps of forming the first conductive layer 312, the second conductive layer 322, the third conductive layer 332, and the fourth conductive layer 342 may include: forming a conductive film (not shown) on the first contact hole 310a, the second contact hole 320a, the third contact hole 330a, the fourth contact hole 340a, and the surface of the interlayer dielectric layer 400 facing away from the substrate 100; and planarizing the conductive film until the surface of the interlayer dielectric layer 400 facing away from the substrate 100 is exposed, thereby forming the first conductive layer 312, the second conductive layer 322, the third conductive layer 332, and the fourth conductive layer 342. The process of planarizing the conductive film may include a chemical mechanical polishing process.

[0189] In one exemplary embodiment, the resistivity of the second silicide layer 220 is less than that of the first silicide layer 210. The material of the first silicide layer 210 includes titanium silicide, and the material of the second silicide layer 220 includes nickel silicide.

[0190] According to at least one embodiment of the present application, a method for fabricating a semiconductor structure is provided, wherein the semiconductor structure includes a first silicide layer connecting a first active area and a first contact structure, and a second silicide layer connecting a second active area and a second contact structure, wherein the resistivity of the second silicide layer is less than the resistivity of the first silicide layer. The relatively low resistivity of the second silicide layer enables a transistor including the second silicide layer to have a higher switching speed, a higher on-state current, and a faster response speed than a transistor including the first silicide layer, thereby improving the overall performance of the semiconductor structure.

[0191] Figure 14 It is a structural diagram of a memory system according to one embodiment of the present application.

[0192] like Figure 14 As shown, at least one embodiment of yet another aspect of the present application further provides a memory system 500. Memory system 500 includes a semiconductor structure 504 and a controller 506. Controller 506 is coupled to semiconductor structure 504 and is configured to control semiconductor structure 504 to store data. Semiconductor structure 504 can be the same as the semiconductor structure described in any of the embodiments above, and this application will not further describe this.

[0193] The semiconductor structure 504 may be a driver circuit chip. The semiconductor structure 504 may also include a structure in which a memory array chip and a driver circuit chip are combined. The driver circuit chip and the memory array chip are electrically connected, and the driver circuit chip is used to drive the memory array chip to erase, write, and read. The memory array chip includes a dynamic random access memory chip. The memory array chip and the driver circuit chip are stacked in different planes. The memory array chip may be a two-dimensional memory array or a three-dimensional memory array, or even a portion of a two-dimensional memory array or a portion of a three-dimensional memory array. Alternatively, the three-dimensional memory array may include at least one of a three-dimensional NAND memory array and a three-dimensional NOR memory array.

[0194] The memory system 500 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device located therein. Figure 14 As shown in FIG, memory system 500 further includes a host 508. Host 508 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system-on-chip (SoC), such as an application processor (AP). Host 508 can be configured to send or receive data to or from semiconductor structure 504.

[0195] According to some embodiments, controller 506 is coupled to semiconductor structure 504 and host 508 and is configured to control semiconductor structure 504. Controller 506 can manage data stored in semiconductor structure 504 and communicate with host 508. In some embodiments, controller 506 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, controller 506 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Controller 506 can be configured to control operations of semiconductor structure 504, such as read, erase, and program operations. The controller 506 may also be configured to manage various functions related to data stored in or to be stored in the semiconductor structure 504, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the controller 506 is further configured to process error correction code (ECC) associated with data read from or written to the semiconductor structure 504. Any other suitable functions may also be performed by the controller 506, such as formatting the semiconductor structure 504. The controller 506 may communicate with an external device (e.g., a host 508) according to a particular communication protocol. For example, the controller 506 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, high-speed PCI (PCI-express, PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0196] Although the exemplary fabrication method and structure of the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced, or added to the structure of the semiconductor structure. In addition, the materials of the various layers illustrated are merely exemplary.

[0197] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of protection encompassed by this application is not limited to the technical solutions formed by the selected combination of the aforementioned technical features, but also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents without departing from the technical concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising a first device region and a second device region; a first active region located in the first device region and a second active region located in the second device region, wherein the first active region and the second active region both extend from a first surface of the substrate into the substrate, the first surface being one of two opposing major surfaces of the substrate; a first silicide layer and a second silicide layer; a first contact structure located on one side of the first silicide layer and a second contact structure located on one side of the second silicide layer, wherein the first silicide layer connects the first active area and the first contact structure, and the second silicide layer connects the second active area and the second contact structure; and The resistivity of the second silicide layer is lower than the resistivity of the first silicide layer.

2. The semiconductor structure according to claim 1, wherein The first contact structure and the second contact structure extend along a first direction to the first silicide layer and the second silicide layer respectively. In a direction intersecting with the first direction, a size of the first silicide layer is smaller than a size of the second silicide layer.

3. The semiconductor structure according to claim 1, wherein At least a portion of the first silicide layer is located in the first active region; and The second silicide layer is located on a side of the second active region close to the first surface.

4. The semiconductor structure according to claim 1, wherein The first contact structure extends along a first direction to the first silicide layer, In a direction intersecting with the first direction, a size of a portion of the first contact structure in contact with the first silicide layer is greater than or equal to a size of the first silicide layer.

5. The semiconductor structure according to claim 1, wherein The second contact structure extends along the first direction to the second silicide layer, In a direction intersecting with the first direction, a size of a portion of the second contact structure in contact with the second silicide layer is smaller than a size of the second silicide layer. The semiconductor structure according to claim 5 , wherein: The second contact structure extends into the second silicide layer.

7. The semiconductor structure according to claim 1, wherein The first contact structure includes a first conductive layer and a first adhesive layer surrounding the first conductive layer. The first silicide layer and the first adhesive layer contain the same metal element.

8. The semiconductor structure according to claim 7, wherein: The second contact structure includes a second conductive layer and a second adhesive layer surrounding the second conductive layer, wherein the second silicide layer and the second adhesive layer contain different metal elements; and The first adhesive layer and the second adhesive layer include the same conductive material.

9. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a first gate structure and a second gate structure, wherein the first gate structure extends along a first direction and is located on one side of the first device region, and the second gate structure extends along the first direction and is located on one side of the second device region. Wherein, in a direction intersecting with the first direction, a size of the first gate structure is larger than a size of the second gate structure; and / or A size of the first gate structure in the first direction is greater than a size of the second gate structure in the first direction.

10. The semiconductor structure according to claim 9, wherein The semiconductor structure further includes a third silicide layer and a fourth silicide layer, The third silicide layer is located at an end of the first gate structure away from the substrate, and the fourth silicide layer is located at an end of the second gate structure away from the substrate; and The third silicide layer and the fourth silicide layer include the same metal element.

11. The semiconductor structure according to claim 10, wherein The second silicide layer, the third silicide layer, and the fourth silicide layer contain the same metal element.

12. The semiconductor structure according to claim 10, wherein In a direction intersecting the first direction, a size of the third silicide layer is smaller than a size of the fourth silicide layer.

13. The semiconductor structure according to claim 9, wherein The first gate structure includes at least one of a metal material gate and a semiconductor material gate; and / or The second gate structure includes at least one of a gate made of a metal material and a gate made of a semiconductor material.

14. The semiconductor structure according to claim 9, wherein The semiconductor structure further includes a shallow trench isolation structure located between the first device region and the second device region. Wherein, in a direction intersecting with the first direction, the second silicide layer extends from one side of the second gate structure to a side of the shallow trench isolation structure facing the second gate structure.

15. The semiconductor structure according to claim 1, wherein The first silicide layer includes titanium silicide and the second silicide layer includes nickel silicide.

16. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate includes a first device region and a second device region; forming a first active region and a second active region extending from the first surface of the substrate into the first device region and the second device region respectively; forming a first silicide layer at least partially located in the first active region, and forming a first contact structure on one side of the first silicide layer; as well as forming a second silicide layer on one side of the second active region, and forming a second contact structure on one side of the second silicide layer; The resistivity of the second silicide layer is smaller than the resistivity of the first silicide layer.

17. The method according to claim 16, wherein The first contact structure includes a first conductive layer and a first adhesive layer surrounding the first conductive layer, forming a first silicide layer at least partially located in the first active area, and forming a first contact structure on one side of the first silicide layer includes: forming a first contact hole extending into the first active region along a first direction, wherein the first contact hole exposes the first active region; and forming the first adhesive layer on the hole wall of the first contact hole, and forming the first conductive layer on the surface of the first adhesive layer, In the process of forming the first adhesive layer, the first silicide layer is formed.

18. The method according to claim 17, wherein In the process of forming the first adhesive layer, forming the first silicide layer includes: forming an initial first adhesive layer in the first contact hole; and annealing the initial first adhesion layer to allow the initial first adhesion layer to react with a portion of the first active region to form the first silicide layer and the first metal layer; The unreacted initial first adhesive layer and the first metal layer form the first adhesive layer.

19. The method according to claim 16, wherein Forming a second silicide layer on a side of the second active region close to the first surface includes: forming an initial dielectric barrier layer covering at least the first surface; removing a portion of the initial dielectric barrier layer covering the second active area to expose the second active area; and A second metal layer is formed on one side of the exposed second active region, and the second metal layer is annealed to allow the second metal layer to react with a portion of the second active region to form the second silicide layer.

20. The method according to claim 19, wherein The method further comprises: forming a first gate structure extending along a first direction on one side of the first device region, and forming a second gate structure extending along the first direction on one side of the second device region; and A third silicide layer is formed at an end portion of the first gate structure away from the substrate, and a fourth silicide layer is formed at an end portion of the second gate structure away from the substrate.

21. The method according to claim 20, wherein The initial dielectric barrier layer includes a first portion covering an end portion of the first gate structure away from the substrate, and forming the third silicide layer includes: removing a portion of the first portion to expose a portion of the first gate structure; and A third metal layer is formed on one side of the exposed portion of the first gate structure, and the third metal layer is annealed to allow the third metal layer to react with a portion of the first gate structure to form the third silicide layer.

22. The method according to claim 20, wherein The initial dielectric barrier layer further includes a second portion covering an end portion of the second gate structure away from the substrate, and forming the fourth silicide layer includes: removing the second portion to expose the second gate structure; and A fourth metal layer is formed on one side of the exposed second gate structure, and the fourth metal layer is annealed to allow the fourth metal layer to react with a portion of the second gate structure to form the fourth silicide layer.

23. The method according to claim 20, wherein The second silicide layer and the third silicide layer contain the same metal element; and / or The second silicide layer and the fourth silicide layer contain the same metal element.

24. The method according to claim 17, wherein The second contact structure includes a second conductive layer and a second adhesive layer surrounding the second conductive layer, a second silicide layer is formed on one side of the second active region, and a second contact structure is formed on one side of the second silicide layer. forming a second contact hole extending into the second silicide layer along the first direction, wherein the second contact hole exposes the second silicide layer; and forming the second adhesive layer on the hole wall of the second contact hole, and forming the second conductive layer on the surface of the second adhesive layer; Wherein, during the process of forming the first adhesive layer, the second adhesive layer is formed.

25. A memory system, characterized in that: include: At least one semiconductor structure according to any one of claims 1 to 15; as well as The controller is coupled to the semiconductor structure and is used to control the semiconductor structure to store data.

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