Semiconductor structure and manufacturing method thereof, memory device and memory system

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, a memory device and a memory system, and the manufacturing method of the semiconductor structure comprises the steps: providing a substrate; the substrate comprises a first region and a second region; forming a first stacking structure on the surface of the first region, and forming a second stacking structure on the surface of the second region; forming a first isolation structure between the first stack structure and the second stack structure; forming a first interconnection structure, a second interconnection structure and a third interconnection structure; wherein the first interconnection structure and the second interconnection structure are connected with the side, away from the first area, of the first stacking structure, and the third interconnection structure is connected with the side, away from the second area, of the second stacking structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof, a memory device, and a memory system. Background Art

[0002] Flash memory has seen rapid development in recent years. Its key features include its ability to retain stored information for long periods without power, high integration, fast access speeds, and ease of erasure and rewriting. Consequently, it has found widespread application in a variety of fields, including microcomputers and automated control. In related technologies, memory can include peripheral circuits and a memory cell array. The peripheral circuits control the memory cell array's read and write operations. However, as flash memory continues to develop, the peripheral circuits present numerous challenges that require urgent resolution. Summary of the Invention

[0003] To address one or more of the aforementioned issues, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, as well as a memory device and a memory system. The semiconductor structure provided by embodiments of the present disclosure includes: a substrate comprising a first region and a second region; a first stacked structure located on a surface of the first region; and a second stacked structure located on a surface of the second region; and a first isolation structure located at least between the first and second stacked structures. The first stacked structure is connected to a first interconnect structure and a second interconnect structure on a side away from the first region, respectively, and the second stacked structure is connected to a third interconnect structure on a side away from the second region.

[0004] In some embodiments, the first stacked structure includes a resistor structure, a first conductive structure located on a side of the resistor structure away from the first region and connected to a first end of the resistor structure, a second conductive structure located on a side of the resistor structure away from the first region and connected to a second end of the resistor structure, and an insulating structure located between the first conductive structure and the second conductive structure; wherein the first conductive structure is connected to the first interconnect structure, and the second conductive structure is connected to the second interconnect structure.

[0005] In some embodiments, the resistor structure includes a dielectric material layer and a resistor material layer located on a side of the dielectric material layer away from the first region.

[0006] In some embodiments, the dielectric material layer comprises hafnium oxide (HfO 2 ); and the resistive material layer comprises titanium nitride (TiN).

[0007] In some embodiments, the first conductive structure and the second conductive structure both include: a first material layer, a second material layer covering the surface of the first material layer, and a third material layer covering the surface of the second material layer; wherein, at least part of the bottom surface of the first material layer is in contact with the resistive material layer; the surface and the bottom surface of the first material layer are respectively two opposite surfaces of the first material layer in the thickness direction of the substrate.

[0008] In some embodiments, the second stacked structure includes a dielectric layer, a protective layer located on a side of the dielectric layer away from the second region, a fourth material layer located on a side of the protective layer away from the dielectric layer, a fifth material layer located on a side of the fourth material layer away from the protective layer, and a gate layer located on a side of the fifth material layer away from the fourth material layer; wherein the gate layer is connected to the third interconnect structure; and at least a portion of the bottom surface of the fourth material layer is in contact with the protective layer.

[0009] In some embodiments, the semiconductor structure further includes: one of the source regions / drain regions, located in the second region and on one side of the second stacking structure; the other of the source regions / drain regions, located in the second region and on one side of the second stacking structure away from one of the source regions / drain regions.

[0010] In some embodiments, the semiconductor structure further includes: a second isolation structure located on the surface of the first region and covering the sidewalls of the first stacked structure; and a third isolation structure located on the surface of the second region and covering the sidewalls of the second stacked structure.

[0011] In some embodiments, the first stacking structure and the second stacking structure are formed in the same process.

[0012] The embodiments of the present disclosure further provide a memory device, comprising: a memory cell array and a peripheral circuit, wherein the peripheral circuit comprises the semiconductor structure as described in the above embodiments of the present disclosure.

[0013] An embodiment of the present disclosure further provides a memory system, comprising: a memory device as described in the above embodiment of the present disclosure; and a memory controller connected to the memory device and configured to control the memory device.

[0014] An embodiment of the present disclosure also proposes a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; the substrate comprising a first region and a second region; forming a first stacking structure on the surface of the first region, and forming a second stacking structure on the surface of the second region; forming a first isolation structure between the first stacking structure and the second stacking structure; forming a first interconnection structure, a second interconnection structure and a third interconnection structure; wherein the first interconnection structure and the second interconnection structure are connected to a side of the first stacking structure away from the first region, and the third interconnection structure is connected to a side of the second stacking structure away from the second region.

[0015] In some embodiments, the first stacking structure formed on the surface of the first region includes: forming a resistance structure on the surface of the first region; forming a first conductive structure on the side of the resistance structure away from the first region, the first conductive structure being connected to the first end of the resistance structure; forming a second conductive structure on the side of the resistance structure away from the first region, the second conductive structure being connected to the second end of the resistance structure; forming an insulating structure between the first conductive structure and the second conductive structure; wherein the first conductive structure is connected to the first interconnection structure; and the second conductive structure is connected to the second interconnection structure.

[0016] In some embodiments, forming a resistance structure on the surface of the first region includes: forming a dielectric material layer on the surface of the first region; and forming a resistance material layer on a side of the dielectric material layer away from the first region.

[0017] In some embodiments, the dielectric material layer comprises hafnium oxide (HfO 2 ); and the resistive material layer comprises titanium nitride (TiN).

[0018] In some embodiments, the forming of the first conductive structure, or the forming of the second conductive structure, includes: forming a first material layer on a side of the resistive material layer away from the dielectric material layer; forming a second material layer on a side of the first material layer away from the resistive material layer; forming a third material layer on a side of the second material layer away from the first material layer; wherein, at least a portion of the bottom surface of the first material layer is in contact with the resistive material layer; and the surface of the first material layer and the bottom surface of the first material layer are respectively two opposite surfaces of the first material layer in the thickness direction of the substrate.

[0019] In some embodiments, the second stacked structure is formed on the surface of the second region, including: forming a dielectric layer on the surface of the second region; forming a protective layer on a side of the dielectric layer away from the second region; forming a fourth material layer on a side of the protective layer away from the dielectric layer; forming a fifth material layer on a side of the fourth material layer away from the protective layer; forming a gate layer on a side of the fifth material layer away from the fourth material layer; wherein the gate layer is connected to the third interconnect structure; and at least a portion of the bottom surface of the fourth material layer is in contact with the protective layer.

[0020] In some embodiments, the first stacking structure is formed on the surface of the first region, and the second stacking structure is formed on the surface of the second region, including: forming a first sub-material layer on one side of the substrate; forming a second sub-material layer on the side of the first sub-material layer away from the substrate; wherein the first sub-material layer located on the surface of the first region forms the dielectric material layer; the second sub-material layer located on the surface of the dielectric material layer forms the resistive material layer; and the first sub-material layer located on the surface of the second region forms the dielectric layer; and the second sub-material layer located on the surface of the dielectric layer forms the protective layer.

[0021] In some embodiments, the method further includes: forming one of the source / drain regions in the second region and on one side of the second stacking structure; and forming the other of the source / drain regions in the second region and on one side of the second stacking structure away from one of the source / drain regions.

[0022] In some embodiments, the method further includes: forming a second isolation structure on a surface of the first region covering sidewalls of the first stacked structure; and forming a third isolation structure on a surface of the second region covering sidewalls of the second stacked structure.

[0023] An embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing the same, wherein the method for manufacturing the semiconductor structure comprises: providing a substrate; the substrate comprising a first region and a second region; forming a first stacking structure on the surface of the first region, and forming a second stacking structure on the surface of the second region; forming a first isolation structure between the first stacking structure and the second stacking structure; forming a first interconnection structure, a second interconnection structure, and a third interconnection structure; wherein the first interconnection structure and the second interconnection structure are connected to a side of the first stacking structure away from the first region, and the third interconnection structure is connected to a side of the second stacking structure away from the second region. In the embodiment of the present disclosure, by forming a first interconnection structure and a second interconnection structure connected to the first stacking structure and forming a third interconnection structure connected to the second stacking structure on the surfaces of two different regions of the substrate, and isolating the first stacking structure from the second stacking structure by forming a first isolation structure, materials and structures can be reasonably utilized to save area. Furthermore, when the first stacking structure and the second stacking structure have the same structure but different functions, the second stacking structure can be formed at the same time as the first stacking structure is formed during the process of manufacturing the semiconductor structure, and the third interconnection structure connected to the second stacking structure can be formed at the same time as the first interconnection structure and the second interconnection structure connected to the first stacking structure. In this way, the second stacking structure can be formed at the same time as the first stacking structure is formed, which saves the process flow and reduces the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1a A schematic structural diagram of an NMOS transistor provided in an embodiment of the present disclosure;

[0025] Figure 1b A schematic structural diagram of a PMOS transistor provided in an embodiment of the present disclosure;

[0026] Figure 2a-2f A schematic cross-sectional view of a manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 3 A schematic flow chart of another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 4a-4j A schematic cross-sectional view of the manufacturing process of another semiconductor structure provided in an embodiment of the present disclosure.

[0029] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0030] To make the technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although the accompanying drawings show exemplary implementation methods of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0031] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0032] It will be understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0033] Furthermore, for ease of description, spatially relative terms such as "on," "over," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0034] In the embodiments of the present disclosure, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0035] In the disclosed embodiments, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0036] In the embodiments of the present disclosure, the terms "first," "second," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0037] The semiconductor structure involved in the embodiments of the present disclosure is at least a portion of a final device structure that will be used in subsequent manufacturing processes. The final device may include memory, including but not limited to dynamic random access memory (DRAM), three-dimensional NAND memory, and the like, which are not limited in this disclosure.

[0038] It should be understood that a memory typically includes a memory controller and a memory device. The memory controller is used to control the memory device to perform operations such as read, write, and erase. The memory controller and the memory device can be coupled in any suitable manner. The memory device includes a memory cell array and peripheral circuits. The memory cell array is used to store data, and the peripheral circuits are used to interact with the memory controller and control the writing / reading of data from the memory cell array.

[0039] In practical applications, peripheral circuits are integrated circuits based on complementary metal oxide semiconductors (CMOS), which are designed and manufactured around field effect transistors (FETs). There are two basic types of field effect transistors: junction field effect transistors (JFETs) and metal-oxide semiconductor field effect transistors (MOSFETs). Integrated circuits can include metal gate N-channel metal oxide semiconductor (NMOS) transistors (such as Figure 1a ), and metal gate P-channel metal oxide semiconductor (PMOS) transistors (as Figure 1b(as shown in Figure 2) and may include components such as inverters, logic gates, and static random access memory (SRAM) cells. Furthermore, integrated circuits may include resistor structures, which act as voltage dividers when MOS transistors are rapidly turned on to prevent breakdown of surrounding devices. However, as memory devices become smaller, the distance between devices decreases, and the resistance of the resistor structures increases. To precisely control the resistance of the resistor structures, high-resistance resistor structures were introduced starting at the 28nm node.

[0040] Exemplarily, the present disclosure provides a method for manufacturing a semiconductor structure, wherein the semiconductor structure includes a resistor structure, referring to Figures 2a to 2f , Figures 2a to 2f The cross-sectional diagram of the manufacturing process of the semiconductor structure is shown below. Figures 2a to 2f , a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is described in detail.

[0041] Before introducing the embodiments of the present disclosure, various directions that may be used to describe the semiconductor structure in the embodiments of the present disclosure are defined. The thickness direction of the substrate is defined as the Z direction, that is, the direction perpendicular to the substrate surface is defined as the Z-axis direction. In a plane perpendicular to the Z direction, intersecting X-axis directions and Y-axis directions are defined, that is, the X-axis direction and the Y-axis direction are parallel to the substrate surface. In some embodiments, the X-axis direction and the Y-axis direction may be perpendicular to each other. In other embodiments, the X-axis direction and the Y-axis direction may not be perpendicular. In the embodiments of the present disclosure, the X-axis direction, the Y-axis direction and the Z-axis direction are perpendicular to each other. 2a to Figure 2f Shown is a schematic diagram of the semiconductor structure in the XZ cross section.

[0042] refer to Figure 2a A substrate 201 is provided, an isolation structure 202 is formed in the substrate, and a gate structure 203 is formed on the surface of the substrate 201. The substrate 201 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The isolation structure 202 is used to isolate the active regions of multiple devices fabricated on the substrate into independent regions.

[0043] The isolation structure 202 may include shallow trench isolation (STI). The isolation structure may be formed by forming an isolation oxide layer, depositing a nitride, forming a mask layer and a shallow trench isolation structure, etching the shallow trench isolation structure, then filling the shallow trench isolation region with oxide, and finally removing the nitride and polishing the filled oxide, such as silicon oxide (SiO2).

[0044] The gate structure 203 may include a stacked gate oxide layer and a gate, and may also include a protective layer located between the gate oxide layer and the gate. The method of forming the gate oxide layer and the gate includes but is not limited to chemical vapor deposition (CVD, Chemical Vapor Deposition), physical vapor deposition (PVD, Physical Vapor Deposition) or atomic layer deposition (ALD, Atomic Layer Deposition), etc.

[0045] It should be noted that the semiconductor structure in the embodiment of the present disclosure may include multiple gate structures 203 at the same time, and the multiple gate structures 203 are isolated by the isolation structure 202 to achieve independent operation. Figure 2a Only one gate structure 203 is shown as an example.

[0046] Next, insulating material is deposited on a portion of the surface of the substrate 201, the top surface of the isolation structure 202, and around the gate structure 203. The insulating material includes but is not limited to silicon oxide. The deposition process includes but is not limited to CVD, PVD, or ALD.

[0047] The insulating material is subjected to a chemical mechanical polishing (CMP) process to expose the top surface of the gate structure 203. The remaining insulating material forms an insulating layer 204. Here, the top surface of the insulating layer 204 is coplanar (i.e., coplanar) or substantially flush with the top surface of the gate structure 203. The insulating layer 204 is used to protect the gate structure 203 from damage.

[0048] In other embodiments, an insulating layer 204 can be first formed on a portion of the surface of the substrate 201 and the top surface of the isolation structure 202, and then a gate structure 203 can be formed in the insulating layer 204. In other words, the order of forming the insulating layer 204 and the gate structure 203 can be selected according to actual needs and is not limited in this disclosure.

[0049] refer to Figure 2bA first dielectric layer 205 is formed on a side of the insulating layer 204 away from the substrate 201. The first dielectric layer 205 also covers the top surface of the gate structure 203. The material of the first dielectric layer 205 includes but is not limited to silicon oxide, wherein the silicon source for forming the silicon oxide includes but is not limited to tetraethyl orthosilicate (TEOS). The method for forming the first dielectric layer includes but is not limited to processes such as CVD, PVD, or ALD.

[0050] refer to Figure 2c A resistor layer 206 is formed on a surface of the first dielectric layer 205 away from the insulating layer 204, a nitride layer 207 is formed on a surface of the resistor layer 206 away from the first dielectric layer 205, and an oxide layer 208 is formed on a surface of the nitride layer 207 away from the resistor layer 206. The material of the resistor layer 206 includes, but is not limited to, titanium nitride (TiN) or high-resistance titanium nitride (HR TiN), the material of the nitride layer 207 includes, but is not limited to, silicon nitride (SiN), and the material of the oxide layer 208 includes, but is not limited to, silicon oxide. Methods for forming the resistor layer 206, the nitride layer 207, and the oxide layer 208 include, but are not limited to, CVD, PVD, or ALD processes.

[0051] refer to Figure 2d A photoresist layer (PR) 209 is formed on the surface of the oxide layer 208 away from the nitride layer 207. Here, the photoresist layer 209 only covers a portion of the surface of the oxide layer 208. Methods for forming the photoresist layer include, but are not limited to, a coating process.

[0052] refer to Figure 2e Based on the photoresist layer 209, an etching process is used to remove part of the resistor layer 206, part of the nitride layer 207, and part of the oxide layer 208. In other words, another part of the resistor layer 206, another part of the nitride layer 207, and another part of the oxide layer 208 covered by the photoresist layer 209 are not removed. Here, the remaining other part of the resistor layer 206 and another part of the nitride layer 207 constitute a resistor structure with a high resistance. It should be noted that the resistance value of the resistor in the resistor structure can be changed by adjusting the thickness of the resistor layer 206, and other suitable resistor materials can also be used to control the resistance value of the resistor. Here, the etching process includes but is not limited to dry etching, wet etching, or a combination thereof.

[0053] Next, the photoresist layer 209 is removed, and a silicon source (e.g., TEOS) is deposited on the surface of the remaining oxide layer 208 to form a silicon oxide layer 210. The silicon oxide layer 210 covers the surface of the remaining oxide layer 208 and the surface of a portion of the first dielectric layer 205 away from the insulating layer. The deposition process includes, but is not limited to, CVD, PVD, or ALD processes.

[0054] Next, the silicon oxide layer 210 is polished by a CMP process. The silicon oxide layer 210 is used to protect the resistor structure from being damaged.

[0055] refer to Figure 2f , forming a first contact 211 that penetrates the silicon oxide layer 210 and is connected to the gate structure 203, and forming a second contact 212 that penetrates the silicon oxide layer 210 and the oxide layer 208 and is connected to the resistor structure. The first contact 211 is used to achieve electrical interconnection between the gate structure 203 and the external circuit, and the second contact 212 is used to achieve electrical interconnection between the resistor structure and the external circuit. It should be noted that the second contact 212 is in contact with the nitride layer 207 in the resistor structure. In this way, the gate structure 203 and the first contact 211 electrically interconnected with the gate structure 203, as well as the resistor structure and the second contact 212 electrically interconnected with the resistor structure can be formed by the above method, so that after the gate structure 203 is quickly energized, the voltage is divided by the resistor structure to reduce the probability of other devices being broken down.

[0056] However, the formation of the resistor structure and the chemical mechanical polishing process used in the above solution increase the manufacturing cost of the semiconductor structure. In order to reduce the manufacturing cost, the embodiment of the present disclosure also provides another method for manufacturing a semiconductor structure, referring to Figure 3 , Figure 3 A schematic flow chart of a method for forming another semiconductor structure according to an embodiment of the present disclosure is provided. Figure 3 As shown, the method includes the following steps:

[0057] S301: providing a substrate; the substrate includes a first region and a second region.

[0058] S302: forming a first stacking structure on the surface of the first region, and forming a second stacking structure on the surface of the second region.

[0059] S303: forming a first isolation structure between the first stacking structure and the second stacking structure.

[0060] S304: forming a first interconnection structure, a second interconnection structure, and a third interconnection structure; wherein the first interconnection structure and the second interconnection structure are connected to a side of the first stacking structure away from the first region, and the third interconnection structure is connected to a side of the second stacking structure away from the second region.

[0061] Figure 4a-4j This is a cross-sectional diagram of another semiconductor structure manufacturing process provided by the embodiment of the present disclosure. It should be understood that Figure 3 The operations shown in the figure are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Figure 3 、 Figure 4a-4j The method for forming the semiconductor structure of this embodiment is described.

[0062] In step S301, refer to Figure 4a , providing a substrate 401, which can be the same as the substrate 201, as mentioned above and will not be repeated here. Preferably, the substrate 401 is a silicon substrate. The substrate 401 includes a first region 401a and a second region 401b adjacent to each other along a first direction (X-axis direction). A shallow trench isolation structure STI402 is also provided in the first region 401a. Here, the shallow trench isolation structure STI402 is used to isolate the active areas between multiple devices formed in the substrate into independent areas. The method for forming the shallow trench isolation structure STI402 includes forming a trench in the first region 401a, and depositing an oxide, such as silicon oxide, in the trench to form a shallow trench isolation structure STI402. The deposition method includes but is not limited to processes such as CVD, PVD or ALD.

[0063] It should be noted that during the deposition process, oxide is also deposited on the surface of the substrate 401 and the surface of the shallow trench isolation structure STI402. After CMP treatment, a second dielectric layer 403 is formed on the surface of the substrate 401 and the surface of the shallow trench isolation structure STI402.

[0064] Execute step S302 and step S303 to form a first stacking structure on the surface of the first region and a second stacking structure on the surface of the second region. The first stacking structure and the second stacking structure can be formed together in the same process or in different processes. In the embodiment of the present disclosure, the first stacking structure and the second stacking structure are formed together in the same process, so that the manufacturing process flow can be reduced, thereby reducing the manufacturing cost. Figure 4b-4j The formation process of the first stacking structure and the second stacking structure is described in detail.

[0065] refer to Figure 4b A first sub-material layer 404 is formed on a surface of the second dielectric layer 403 that is away from the substrate 401 (i.e., away from the second dielectric layer 403), and a second sub-material layer 405 is formed on a surface of the first sub-material layer 404 that is away from the substrate 401. The first sub-material layer 404 includes, but is not limited to, a high-K dielectric material, such as hafnium oxide, and the second sub-material layer 405 includes, but is not limited to, titanium nitride (TiN), high-resistance titanium nitride (HR TiN), etc. It should be understood that in a subsequent etching process, the second sub-material layer 405 can be used as an etch stop layer for the first sub-material layer 404 to protect the first sub-material layer 404 from being etched.

[0066] refer to Figure 4cA sacrificial layer 406 is formed on the surface of the second sub-material layer 405 away from the first sub-material layer 404. The material of the sacrificial layer 406 is but not limited to polysilicon (Poly), and the method of forming the sacrificial layer 406 includes but is not limited to CVD, PVD or ALD processes.

[0067] refer to Figure 4d , part of the first sub-material layer 404, part of the second sub-material layer 405, and part of the sacrificial layer 406 are removed. At this time, part of the first sub-material layer 404 located on the surface of the first region 401a (specifically, the surface of the second dielectric layer 403) forms a dielectric material layer 4041; part of the second sub-material layer 405 located on the surface of the dielectric material layer 4041 forms a resistive material layer 4051; part of the sacrificial layer 406 located on the surface of the resistive material layer 4051 forms a first sub-sacrificial layer 4061; and part of the first sub-material layer 404 located on the surface of the second region 401b forms a dielectric layer 4042; part of the second sub-material layer 405 located on the surface of the dielectric layer 4042 forms a protective layer 4052; and part of the sacrificial layer 406 located on the surface of the protective layer 4052 forms a second sub-sacrificial layer 4062. Here, the constituent materials of the dielectric material layer 4041 and the dielectric layer 4042 include hafnium oxide, the constituent materials of the resistance material layer 4051 and the protective layer 4052 include titanium nitride, high-resistance titanium nitride, etc., and the constituent materials of the first sub-sacrificial layer 4061 and the second sub-sacrificial layer 4062 include polysilicon; wherein the removal process includes dry etching, wet etching or a combination thereof.

[0068] It should be noted that the dielectric material layer 4041 and the resistor material layer 4051 form a resistor structure. The resistance value of the resistor structure can be precisely adjusted according to the thickness of the resistor material layer to achieve a resistor structure with a high resistance value.

[0069] refer to Figure 4e , forming an isolation layer 407, which includes a first sub-isolation layer 4071 and a second sub-isolation layer 4072. The first sub-isolation layer 4071 is located on the surface of the first region 401a and covers the sidewalls of the dielectric material layer 4041, the resistive material layer 4051, and the first sub-sacrificial layer 4061, as well as the surface of the first sub-sacrificial layer 4061 away from the resistive material layer 4051. The second sub-isolation layer 4072 is located on the surface of the second region 401b and covers the sidewalls of the dielectric layer 4042, the protective layer 4052, and the second sub-sacrificial layer 4062, as well as the surface of the second sub-sacrificial layer 4062 away from the protective layer 4052. The constituent materials of the isolation layer 407 include, but are not limited to, silicon nitride.

[0070] Furthermore, an interlayer dielectric layer 408 is formed. Interlayer dielectric layer 408 is located on the surface of second dielectric layer 403 away from substrate 401 and in the gap between isolation layer 407. Interlayer dielectric layer 408, located between first sub-isolation layer 4071 and second sub-isolation layer 4072, is used to form first isolation structure 408a in subsequent processes. Materials for interlayer dielectric layer 408 include, but are not limited to, silicon oxide. Methods for forming interlayer dielectric layer 408 include, but are not limited to, CVD, PVD, or ALD processes.

[0071] refer to Figure 4f A mask layer 409 is formed on the surface of the isolation layer 407 facing away from the substrate, and on the surface of the interlayer dielectric layer 408 facing away from the substrate. The mask layer material includes, but is not limited to, high-resistance polysilicon (HR Poly), photoresist PR, etc. Methods for forming the mask layer 409 include, but are not limited to, a coating process. The pattern of the mask layer 409 can be selected and set according to actual needs and is not limited in this disclosure.

[0072] Next, a first groove 4101, a second groove 4102, and a third groove 4103 are formed through the mask layer 409. The first groove 4101 and the second groove 4102 penetrate the first sub-sacrificial layer 4061 and the first sub-isolating layer 4071 located above the first sub-sacrificial layer 4061. In other words, during the formation of the first groove 4101 and the second groove 4102, portions of the first sub-sacrificial layer 4061 and the first sub-isolating layer 4071 are removed. The remaining first sub-sacrificial layer now constitutes the insulating structure 412. The third groove 4103 penetrates the second sub-sacrificial layer 4062 and the second sub-isolating layer 4072 located above the second sub-sacrificial layer 4062. Methods for forming the first groove 4101, the second groove 4102, and the third groove 4103 include, but are not limited to, etching, such as dry etching, wet etching, or a combination thereof.

[0073] refer to Figure 4g The remaining second sacrificial sub-layer 4062 is removed through the third groove 4103 to form a gap 411 in situ. The removal process may include, but is not limited to, dry etching, wet etching, or a combination thereof.

[0074] refer to Figure 4hA first material layer 413 is formed on the surface of the resistive material layer 4051 away from the dielectric material layer 4041 using the first groove 4101 and the second groove 4102. A second material layer 414 is formed on the surface of the first material layer 413 away from the resistive material layer 4051. A third material layer 415 is formed on the surface of the second material layer 414 away from the first material layer 413. At least a portion of the bottom surface of the first material layer 413 is in contact with the resistive material layer 4051. The top surface and the bottom surface of the first material layer 413 are two opposing surfaces of the first material layer 413 in the thickness direction (Z-axis direction) of the substrate.

[0075] like Figure 4h As shown, the first material layer 413 , the second material layer 414 , and the third material layer 415 located in the first groove 4101 constitute a first conductive structure 419 , and the first material layer 413 , the second material layer 414 , and the third material layer 415 located in the second groove 4102 constitute a second conductive structure 420 .

[0076] Similarly, a fourth material layer 416 is formed on the side of the protective layer 4052 away from the dielectric layer 4042 using the third groove 4103 and the gap 411, a fifth material layer 417 is formed on the side of the fourth material layer 416 away from the protective layer 4052, and a gate layer 418 is formed on the side of the fifth material layer 417 away from the fourth material layer 416. At least a portion of the bottom surface of the fourth material layer 416 is in contact with the protective layer 4502. Figure 4h As shown, the fourth material layer 416 , the fifth material layer 417 , and the gate layer 418 constitute a third conductive structure 421 .

[0077] Here, the first material layer 413 and the fourth material layer 416 can be formed in the same process, the second material layer 414 and the fifth material layer 417 can be formed in the same process, and the third material layer 415 and the gate layer 418 can be formed in the same process, thus saving process technology.

[0078] Similarly, the constituent materials of the first material layer 413 and the fourth material layer 416 may be the same, which may include but are not limited to tantalum nitride (TaN); the constituent materials of the second material layer 414 and the fifth material layer 417 may be the same, which may include but are not limited to titanium nitride (TiN); the constituent materials of the third material layer 415 and the gate layer 418 may be the same, which may include but are not limited to titanium aluminum (TiAl), aluminum (Al) or a combination of titanium aluminum and aluminum (TiAl / Al).

[0079] In the embodiment of the present disclosure, the cross-sectional shape of the first material layer 413, the second material layer 414, the fourth material layer 416, and the fifth material layer 417 in the XZ plane is U-shaped, and the cross-sectional shape of the third material layer 415 and the gate layer 418 in the XZ plane is I-shaped. In other embodiments, the cross-sectional shape of the above layers can also be other shapes, which are not limited by the present disclosure. The methods for forming the first material layer 413, the second material layer 414, the third material layer 415, the fourth material layer 416, the fifth material layer 417, and the gate layer 418 include, but are not limited to, CVD, PVD, or ALD processes.

[0080] Here, an insulating structure 412 is provided between the first conductive structure 419 and the second conductive structure 420, and the insulating structure 412 is used to electrically isolate the first conductive structure 419 from the second conductive structure 420; in other words, the first conductive structure 419 is connected to the first end of the resistance structure (such as the resistance material layer 4051), and the second conductive structure 420 is connected to the second end of the resistance structure (such as the resistance material layer 4051), and the first conductive structure 419 and the second conductive structure 420 can be used to realize the input or output of electrical signals of the resistance structure.

[0081] Continue to refer Figure 4h , remove the mask layer 409 and the first sub-isolation layer 4071 located above the insulating structure 412, and the second sub-isolation layer 4072 located above the gap 411, wherein the remaining first sub-isolation layer 4071 constitutes the second isolation structure 422, and the remaining second sub-isolation layer 4072 constitutes the third isolation structure 423.

[0082] At this time, the dielectric material layer 4041, the resistance material layer 4051, the insulation structure 412, the first conductive structure 419, and the second conductive structure 420 constitute a first stacked structure 500. The dielectric layer 4042, the protective layer 4052, the fourth material layer 416, the fifth material layer 417, and the gate layer 418 constitute a second stacked structure 600. Figure 4h As shown, the second isolation structure 422 covers the sidewalls of the first stacked structure 500, and the third isolation structure 423 covers the sidewalls of the second stacked structure 600. The portion of the interlayer dielectric layer 408 located between the first stacked structure 500 and the second stacked structure 600 constitutes the first isolation structure 408a. In other words, the first isolation structure 408a is used to isolate the first stacked structure 500 from the second stacked structure 600.

[0083] Execute step S304, refer to Figure 4iA third dielectric layer 424 is formed on the surface of the first stacked structure 500, the second stacked structure 600, and the first isolation structure 408a away from the substrate 401. The third dielectric layer 424 can be used to protect the first stacked structure 500 and the second stacked structure 600. The material of the third dielectric layer 424 includes, but is not limited to, silicon oxide, and the method of forming the third dielectric layer 424 includes, but is not limited to, CVD, PVD, or ALD processes.

[0084] Next, a first interconnect structure 425, a second interconnect structure 426, and a third interconnect structure 427 are formed through the third dielectric layer 424. The first interconnect structure 425 is connected to the first conductive structure 419, the second interconnect structure 426 is connected to the second conductive structure 420, and the third interconnect structure 427 is connected to the third conductive structure 421. Specifically, the first interconnect structure 425 is connected to the third material layer 415 in the first conductive structure 419, the second interconnect structure 426 is connected to the third material layer 415 in the second conductive structure 420, and the third interconnect structure 427 is connected to the gate layer 418 in the third conductive structure 421. The first interconnect structure 425 is used to implement electrical signal transmission between the first conductive structure 419 and the resistor structure, the second interconnect structure 426 is used to implement electrical signal transmission between the second conductive structure 420 and the resistor structure, and the third interconnect structure 427 is used to implement electrical signal transmission in the second stacked structure 600.

[0085] In some embodiments, the method further includes: forming one of the source / drain regions in the second region and on one side of the second stack structure; and forming the other of the source / drain regions in the second region and on one side of the second stack structure away from one of the source / drain regions.

[0086] refer to Figure 4j , the positions of the source region 428 and the drain region 429 can be interchanged. The source region 428 and the drain region 429 are located in the second region 401b and are respectively located on both sides of the second stacked structure 600. Methods for forming the source region 428 and the drain region 429 include but are not limited to ion implantation, ion diffusion and other processes. Here, the source region 428 and the drain region 429 and the second stacked structure 600 constitute a transistor, and the second stacked structure 600 can be used as a control gate (which can be called a metal gate (MG)) of the source region 428 and the drain region 429. In addition, the doping ion type of the source region 428 and the drain region 429 can be selected according to the type of transistor, such as N-type or P-type, which has been mentioned above and will not be repeated here.

[0087] Based on this, in the embodiment of the present disclosure, in the process of manufacturing the semiconductor structure, by forming the second stacking structure at the same time as forming the first stacking structure, and forming the first interconnection structure and the second interconnection structure connected to the first stacking structure, a third interconnection structure connected to the second stacking structure is formed. In this way, the first stacking structure and the second stacking structure can be formed in a unified process, saving the process flow and reducing the manufacturing cost. In addition, the use of titanium nitride (or high-resistance titanium nitride) as the material of the resistor structure can increase the resistance value of the resistor structure; and the resistance value of the resistor structure can also be accurately adjusted according to the thickness of the resistor material layer to achieve a resistor structure with a high resistance value, thereby improving the performance of the resistor structure. In other words, the above method of forming a semiconductor structure can reasonably utilize the structure and materials, reduce process steps, and save production costs.

[0088] Based on the above-mentioned method for manufacturing a semiconductor structure, a semiconductor structure is also provided in an embodiment of the present disclosure, including: a substrate, the substrate including a first region and a second region; a first stacking structure located on the surface of the first region and a second stacking structure located on the surface of the second region; a first isolation structure, located at least between the first stacking structure and the second stacking structure; wherein the side of the first stacking structure away from the first region is connected to the first interconnection structure and the second interconnection structure respectively, and the side of the second stacking structure away from the second region is connected to the third interconnection structure.

[0089] In some embodiments, the first stacked structure includes a resistor structure, a first conductive structure located on a side of the resistor structure away from the first region and connected to a first end of the resistor structure, a second conductive structure located on a side of the resistor structure away from the first region and connected to a second end of the resistor structure, and an insulating structure located between the first conductive structure and the second conductive structure; wherein the first conductive structure is connected to the first interconnect structure, and the second conductive structure is connected to the second interconnect structure.

[0090] In some embodiments, the resistor structure includes a dielectric material layer and a resistor material layer located on a side of the dielectric material layer away from the first region.

[0091] In some embodiments, the dielectric material layer comprises hafnium oxide (HfO 2 ); and the resistive material layer comprises titanium nitride (TiN).

[0092] In some embodiments, the first conductive structure and the second conductive structure both include: a first material layer, a second material layer covering the surface of the first material layer, and a third material layer covering the surface of the second material layer; wherein, at least part of the bottom surface of the first material layer is in contact with the resistive material layer; the surface and the bottom surface of the first material layer are respectively two opposite surfaces of the first material layer in the thickness direction of the substrate.

[0093] In some embodiments, the second stacked structure includes a dielectric layer, a protective layer located on a side of the dielectric layer away from the second region, a fourth material layer located on a side of the protective layer away from the dielectric layer, a fifth material layer located on a side of the fourth material layer away from the protective layer, and a gate layer located on a side of the fifth material layer away from the fourth material layer; wherein the gate layer is connected to the third interconnect structure; and at least a portion of the bottom surface of the fourth material layer is in contact with the protective layer.

[0094] In some embodiments, the semiconductor structure further includes: one of the source regions / drain regions, located in the second region and on one side of the second stacking structure; the other of the source regions / drain regions, located in the second region and on one side of the second stacking structure away from one of the source regions / drain regions.

[0095] In some embodiments, the semiconductor structure further includes: a second isolation structure located on the surface of the first region and covering the sidewalls of the first stacked structure; and a third isolation structure located on the surface of the second region and covering the sidewalls of the second stacked structure.

[0096] In some embodiments, the first stacking structure and the second stacking structure are formed in the same process.

[0097] Based on the above-described semiconductor structure and its fabrication method, embodiments of the present disclosure further provide a memory device comprising: a memory cell array and peripheral circuitry, wherein the peripheral circuitry comprises the semiconductor structure described in the above-described embodiments of the present disclosure. In other words, the semiconductor structure is used to form the peripheral circuitry of a three-dimensional NAND memory.

[0098] It should be noted that the first stacked structure can be used as a resistance structure in a peripheral circuit, and the second stacked structure can be used as a control gate of a transistor in the peripheral circuit.

[0099] Based on the above semiconductor structure and its manufacturing method, an embodiment of the present disclosure further provides a memory system, including: a memory device as described in the above embodiment of the present disclosure; and a memory controller connected to the memory device and used to control the memory device.

[0100] Based on this, in the above-mentioned embodiment of the present disclosure, by forming a first interconnection structure and a second interconnection structure connected to the first stacking structure on the surface of two different regions of the substrate, and forming a third interconnection structure connected to the second stacking structure, and isolating the first stacking structure from the second stacking structure by forming a first isolation structure, it is possible to rationally utilize materials and structures to save area. Furthermore, when the first stacking structure and the second stacking structure have the same structure but different functions, the second stacking structure can be formed at the same time as the first stacking structure is formed during the process of manufacturing the semiconductor structure, and the third interconnection structure connected to the second stacking structure can be formed at the same time as the first interconnection structure and the second interconnection structure connected to the first stacking structure. In this way, the second stacking structure can be formed at the same time as the first stacking structure is formed, saving process flow and reducing manufacturing costs.

[0101] In addition, the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0102] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first region and a second region; a first stacking structure located on the surface of the first region and a second stacking structure located on the surface of the second region; a first isolation structure, located at least between the first stacking structure and the second stacking structure; The first stacking structure has a side away from the first region connected to the first interconnection structure and the second interconnection structure respectively, and the second stacking structure has a side away from the second region connected to the third interconnection structure.

2. The semiconductor structure according to claim 1, wherein: The first stacked structure includes a resistor structure, a first conductive structure located on a side of the resistor structure away from the first region and connected to a first end of the resistor structure, a second conductive structure located on a side of the resistor structure away from the first region and connected to a second end of the resistor structure, and an insulating structure located between the first conductive structure and the second conductive structure; The first conductive structure is connected to the first interconnection structure, and the second conductive structure is connected to the second interconnection structure.

3. The semiconductor structure according to claim 2, wherein: The resistance structure includes a dielectric material layer and a resistance material layer located on a side of the dielectric material layer away from the first region.

4. The semiconductor structure according to claim 3, wherein: The dielectric material layer is made of hafnium oxide; the resistance material layer is made of titanium nitride.

5. The semiconductor structure according to claim 3, wherein: The first conductive structure and the second conductive structure both include: A first material layer, a second material layer covering a surface of the first material layer, and a third material layer covering a surface of the second material layer; At least a portion of the bottom surface of the first material layer is in contact with the resistance material layer; the surface of the first material layer and the bottom surface are two opposite surfaces of the first material layer in the thickness direction of the substrate. The semiconductor structure according to claim 1 , wherein: The second stacked structure includes a dielectric layer, a protection layer located on a side of the dielectric layer away from the second region, a fourth material layer located on a side of the protection layer away from the dielectric layer, a fifth material layer located on a side of the fourth material layer away from the protection layer, and a gate layer located on a side of the fifth material layer away from the fourth material layer; The gate layer is connected to the third interconnect structure; and at least a portion of the bottom surface of the fourth material layer is in contact with the protective layer.

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: One of the source region and the drain region is located in the second region and on one side of the second stacked structure; The other of the source / drain regions is located in the second region and on a side of the second stack structure that is away from one of the source / drain regions.

8. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: a second isolation structure, located on a surface of the first region and covering a sidewall of the first stacked structure; The third isolation structure is located on the surface of the second region and covers the sidewalls of the second stacked structure.

9. The semiconductor structure according to claim 1, wherein: The first stacking structure and the second stacking structure are formed together in the same process.

10. A memory device, characterized in that: include: A memory cell array and a peripheral circuit, wherein the peripheral circuit comprises the semiconductor structure according to any one of claims 1 to 9.

11. A memory system, characterized in that: include: The memory device according to claim 10; and a memory controller connected to the memory device and configured to control the memory device.

12. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: Providing a substrate; the substrate includes a first region and a second region; forming a first stacking structure on the surface of the first region, and forming a second stacking structure on the surface of the second region; forming a first isolation structure between the first stacking structure and the second stacking structure; A first interconnect structure, a second interconnect structure and a third interconnect structure are formed; wherein the first interconnect structure and the second interconnect structure are connected to a side of the first stack structure away from the first region, and the third interconnect structure is connected to a side of the second stack structure away from the second region.

13. The manufacturing method according to claim 12, characterized in that: The forming of a first stacked structure on the surface of the first region includes: forming a resistive structure on a surface of the first region; forming a first conductive structure on a side of the resistor structure away from the first region, wherein the first conductive structure is connected to the first end of the resistor structure; forming a second conductive structure on a side of the resistor structure away from the first region, wherein the second conductive structure is connected to the second end of the resistor structure; forming an insulating structure between the first conductive structure and the second conductive structure; The first conductive structure is connected to the first interconnection structure; and the second conductive structure is connected to the second interconnection structure.

14. The manufacturing method according to claim 13, characterized in that: The forming of a resistance structure on the surface of the first region includes: forming a dielectric material layer on the surface of the first region; A resistive material layer is formed on a side of the dielectric material layer away from the first region.

15. The manufacturing method according to claim 14, characterized in that: The dielectric material layer is made of hafnium oxide; the resistance material layer is made of titanium nitride.

16. The manufacturing method according to claim 14, characterized in that: The forming of the first conductive structure or the forming of the second conductive structure includes: forming a first material layer on a side of the resistive material layer away from the dielectric material layer; forming a second material layer on a side of the first material layer away from the resistive material layer; forming a third material layer on a side of the second material layer away from the first material layer; At least part of the bottom surface of the first material layer is in contact with the resistance material layer; the surface of the first material layer and the bottom surface of the first material layer are respectively two opposite surfaces of the first material layer in the thickness direction of the substrate.

17. The manufacturing method according to claim 14, characterized in that: The forming of a second stacked structure on the surface of the second region includes: forming a dielectric layer on a surface of the second region; forming a protective layer on a side of the dielectric layer away from the second region; forming a fourth material layer on a side of the protective layer away from the dielectric layer; forming a fifth material layer on a side of the fourth material layer away from the protective layer; forming a gate layer on a side of the fifth material layer away from the fourth material layer; The gate layer is connected to the third interconnect structure; and at least a portion of the bottom surface of the fourth material layer is in contact with the protective layer.

18. The manufacturing method according to claim 17, characterized in that: The forming of a first stacking structure on the surface of the first region and the forming of a second stacking structure on the surface of the second region include: forming a first sub-material layer on one side of the substrate; forming a second sub-material layer on a side of the first sub-material layer away from the substrate; The first sub-material layer located on the surface of the first region forms the dielectric material layer; the second sub-material layer located on the surface of the dielectric material layer forms the resistance material layer; and The first sub-material layer located on the surface of the second region forms the dielectric layer; and the second sub-material layer located on the surface of the dielectric layer forms the protective layer.

19. The manufacturing method according to claim 14, characterized in that: The method further comprises: forming one of a source region and a drain region in the second region and on one side of the second stacked structure; The other of the source / drain regions is formed in the second region and on a side away from one of the source / drain regions among the two sides of the second stack structure.

20. The manufacturing method according to claim 14, characterized in that: The method further comprises: A second isolation structure is formed on the surface of the first region and covers the sidewalls of the first stacked structure; and a third isolation structure is formed on the surface of the second region and covers the sidewalls of the second stacked structure.

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