Improved vertical 3D memory device and access method

Abstract

The invention relates to an improved vertical 3D memory device and an access method. The invention provides a memory device and an access / deselection method thereof. The memory device includes: a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, in which the memory cells are accessed via word lines and digital lines orthogonal to each other, and the digital lines are in the form of vertically extending conductive pillars; a pillar selection layer formed under the memory layer and in which a thin film transistor (TFT) for accessing a memory cell is formed; and a peripheral circuit layer formed under the pillar selection layer and having sense amplifiers and decoding circuitry for word lines and bit lines, in which TFTs are configured for each pillar.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 202080101330.3, application date May 25, 2020, and invention name “Improved vertical 3D memory device and access method”.

[0003] Cross-references

[0004] This patent application is a national phase application of International Patent Application No. PCT / IB2020 / 020028, filed by Villa et al. on May 25, 2020, entitled “IMPROVED VERTICAL 3D MEMORY DEVICE AND ACCESSING METHOD,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field relates to improved vertical 3D memory devices and access methods. Background Art

[0006] The following disclosure relates generally to the field of electronic devices, and more particularly to an improved vertical 3D (three-dimensional) memory device structure and a related access method.

[0007] Electronic memory devices (hereinafter simply referred to as "memory devices") are widely used to store data in various electronic devices, such as tablets, computers, wireless communication devices (eg, smartphones), cameras, digital displays, and the like.

[0008] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states in the memory device. For example, binary devices most commonly store one of two states, often represented by a logical 1 or a logical 0. Other devices can store more than two states. To access stored information, a component of the device can read or sense at least one stored state in the memory device. To store information, a component of the device can write or program a state in the memory device.

[0009] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), other chalcogenide-based memories, and other memory devices. Memory devices can be volatile or non-volatile.

[0010] In general, improving memory devices may include increasing memory cell density, improving read / write speeds, enhancing reliability, extending data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Solutions may be needed for saving space in a memory array, increasing memory cell density, or reducing the overall power usage of a memory array having a three-dimensional vertical architecture.

[0011] An object of the present disclosure is to provide an improved memory device with additional selection elements, and an efficient method for accessing memory cells of a memory device. Summary of the Invention

[0012] A memory device is described. In some examples, the memory device may include: a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein the memory cells are configured to be accessed via word lines and digit lines that are orthogonal to each other, and the digit lines are in the form of vertically extending conductive pillars; a pillar selection layer formed below the memory layer and having at least one thin film transistor (TFT) formed therein for accessing the memory cells; and a peripheral circuit layer formed below the pillar selection layer and having sense amplifiers and decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.

[0013] A memory device is described. In some examples, the memory device may include: a memory array of memory cells structured as a vertical 3D memory, including a plurality of word lines arranged orthogonally to a plurality of digit lines, each digit line crossing at least one pair of word lines; and at least one select transistor located at one end of a corresponding digit line, the select transistor being a thin film transistor (TFT) for selecting the corresponding digit line and accessing at least a memory cell associated with the corresponding digit line.

[0014] A method for accessing a memory cell of a memory device is described. In some examples, the method may include: applying a first voltage to a selected word line while other word lines are at a predetermined voltage; applying a second voltage to gate regions of TFTs associated with other memory cells that share the selected word line with the memory cell; applying the second voltage to source regions of the TFTs associated with the memory cells that share the selected word line while source regions of the other TFTs are at the predetermined voltage; and applying a third voltage to the gate region of the TFT associated with the memory cell.

[0015] A method for deselecting unaddressed memory cells in a 3D memory array is described, wherein a plurality of word lines extend horizontally across a plurality of stacks and a plurality of array digit lines extend vertically, with each memory cell located at the intersection of a word line and an array digit line. In some examples, the method may include floating the array digit lines of the plurality of array digit lines that are coupled to the unaddressed memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 An example of an example memory array supporting vertical 3D memory devices with NMOS TFT selectors is shown according to examples as disclosed herein.

[0017] Figures 2A to 2F Various views of an example memory array supporting vertical 3D memory devices with NMOS TFT selectors are shown according to examples as disclosed herein.

[0018] Figures 3A to 3I Various views of an example memory array supporting vertical 3D memory devices with NMOS TFT selectors are shown according to examples as disclosed herein.

[0019] Figure 4A and 4B Various views are shown of another example memory array supporting vertical 3D memory devices with NMOS TFT selectors according to examples as disclosed herein.

[0020] Figure 5 Another example memory array supporting vertical 3D memory devices with NMOS TFT selectors is shown according to examples as disclosed herein.

[0021] Figure 6 An example NMOS TFT according to examples as disclosed herein is shown.

[0022] Figures 7A to 7C Various views of an example NMOS TFT selector are shown according to examples as disclosed herein.

[0023] Figures 8A to 8D Various diagrams are shown for accessing memory cells of a vertical 3D memory device with NMOS TFT selectors according to examples as disclosed herein.

[0024] Figure 9 A flow chart illustrating a method for accessing a vertical 3D memory device with an NMOS TFT selector is shown according to examples as disclosed herein. DETAILED DESCRIPTION

[0025] The present disclosure relates to a vertical 3D memory device with an NMOS TFT selector and an access method thereof. The memory device may include: a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein the memory cells are accessed via orthogonal word lines and digit lines, and wherein the digit lines are in the form of vertically extending conductive pillars; a pillar selection layer formed below the memory layer and having thin-film transistors (TFTs) formed therein for accessing the memory cells; and a peripheral circuit layer formed below the pillar selection layer and having sense amplifiers and decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar. In some cases, the TFT is an n-type metal oxide semiconductor (NMOS) transistor, wherein the drain region is coupled to the pillar. In some cases, the channel region of the TFT extends to a first predetermined value. In some cases, the TFT has two gate regions, one parallel to a gate oxide located on one side of the channel region and the other to the other side of the channel region. In some cases, the channel region is formed below the drain region, and the source region is formed below the channel region. In some cases, the length of the channel region is extended to a second predetermined value. In some cases, the first predetermined value is 120 nm. In some cases, the second predetermined value is 220 nm. In some cases, the conductive pillar further includes a first sub-pillar and a second sub-pillar separated from each other, and two TFTs are configured for the conductive pillar, one for the first sub-pillar and the other for the second sub-pillar. In some cases, the spacing of the TFTs matches the spacing of the pillars.

[0026] In some examples, a matrix of thin film transistors (TFTs), one transistor per digit line, is provided below and / or above the digit lines, with peripheral circuitry including sense amplifiers and decoding circuitry for word and bit lines formed below the matrix.

[0027] Thus, the matrix of thin film transistors is formed in a polysilicon layer, and the peripheral circuit layer is implemented in a silicon substrate layer; in some instances, the peripheral circuit layer may be located below the polysilicon layer, and the polysilicon layer may be located below the 3D memory array.

[0028] In some examples, the memory device may include an arrangement of conductive contacts and openings through alternating layers of conductive and insulating materials that can reduce the spacing between the memory cells while maintaining a dielectric thickness to hold a voltage to be applied to the memory array of the memory device, and the memory device may also include a select transistor coupled to each conductive contact, which is the NMOS TFT that enables decoding of the vertical 3D memory device.

[0029] In some examples, the memory device may include a substrate having a set of contacts arranged in a pattern (e.g., a geometric pattern) and a first insulating material (e.g., a dielectric material) formed on the substrate. A set of planes of conductive material may be separated from each other by a second insulating material (e.g., a dielectric material) and formed on the substrate material. That is, alternating planes of conductive and insulating material may be formed on the substrate. The planes of conductive material may be examples of word lines.

[0030] During the fabrication of a memory device, one or more trenches can be formed by etching alternating planes of conductive and insulating material. The trenches can extend parallel to one another and expose the substrate. In some examples, the planes of conductive and dielectric material can form the sidewalls of the trenches. The planes of conductive material can be etched such that the planes of dielectric and conductive material form a collection of recesses, each of which can be configured to receive a memory element material (e.g., a chalcogenide material). A sacrificial layer (e.g., a conformal material) can be deposited in the trenches, and in some cases, the sacrificial layer fills the recesses. Insulating material can be deposited in the trenches on top of the sacrificial layer.

[0031] Portions of the sacrificial layer and the insulator may be removed to form a first opening. The first opening may expose portions of the substrate, at least some of the set of conductive contacts, and portions of the plane of conductive material and the plane of dielectric material. A memory element material (e.g., a chalcogenide material) may be deposited in the first opening. The memory element material may fill a recess formed by the plane of dielectric material and the plane of conductive material. The memory element material may be partially removed from the first opening, thereby retaining the memory element material in the recess. The memory element material positioned in the recess may be a memory element component (e.g., a chalcogenide component).

[0032] Conductive pillars can be formed in the first opening including the storage element in the recess. The conductive pillars can be arranged to extend through the plane of the conductive material (e.g., substantially perpendicular to the plane of the conductive material) and contact the substrate. Each conductive pillar can contact two storage element components, each of which in turn contacts the same plane of the conductive material. Each conductive pillar can further be coupled to one or two conductive contacts, and thus an NMOS TFT can be associated with each conductive pillar. In some cases, the pillars can be formed from a barrier material and a conductive material. In some cases, a single NMOS TFT can be provided for each pillar.

[0033] Portions of the conductive pillars may be removed to form a second opening. The second opening may divide each pillar into a first pillar and a second pillar. The first and second pillars may be examples of digital lines. The first pillar may contact a first storage element component coupled to a plane of conductive material, and the second pillar may contact a second storage element component coupled to a plane of conductive material. In some cases, each of the first pillar and the second pillar may be coupled to a different conductive contact on the substrate. In some other cases, each of the first pillar may be coupled to a different conductive contact on the substrate, and each of the second pillar may be coupled to a different conductive contact on a second substrate formed above the first substrate. In some cases, each of the first pillar and the second pillar may be associated with a corresponding NMOS TFT. In other words, one pillar may be coupled to a single NMOS TFT.

[0034] In some cases, an NMOS TFT may be formed below the array of memory cells, specifically, below each pillar. In some cases, the drain region of the NMOS TFT may be coupled to the pillar. In some cases, the active area of ​​the NMOS TFT (i.e., the polysilicon channel) may be extended to a predetermined value (e.g., 120 nm). In some cases, the NMOS TFT may have two gate regions, with a gate oxide on one side of the channel region and another gate oxide on the other side of the channel region, thereby doubling the width of the NMOS TFT. In some cases, the first bottom silicon layer of the memory device may be dedicated to sense amplifiers and decoding circuitry for word lines and bit lines. In some cases, epitaxial growth of polysilicon may be provided above the first silicon layer, and in this polysilicon layer, the NMOS TFT may be provided as a matrix below the pillar.

[0035] The present disclosure further relates to a method for accessing memory cells of a vertical 3D memory device having an NMOS TFT selector. Generally speaking, cells of a 3D memory array can be addressed via word lines and bit lines. To address a target cell, a positive bias voltage can be applied to the digit line (which can be the vertical portion of the bit line), and a negative bias voltage can be applied to the word line plate. However, the word line receiving the negative bias voltage may be shared by all other cells associated with the same word line plate and linked to other pillars (i.e., the vertical portion of the bit line). Therefore, it is necessary to determine the desired bit line.

[0036] It is possible to select a single cell having a single NMOS TFT while deselecting all others according to the access method described in detail below. Thus, it is also possible to bias the set voltage or program and reset voltages as well as the read voltage. The disclosed solution is also suitable for selecting a single cell when a negative bias voltage is applied to the digit line (which may be the vertical portion of the bit line) and a positive bias voltage is applied to the word line plate.

[0037] Figure 1 An example of a memory array 100 (e.g., a three-dimensional (3D) memory array) supporting vertical 3D memory devices with NMOS TFT selectors according to examples as disclosed herein is shown. The memory array 100 can include a first array or stack 105 of memory cells positioned above a substrate 104 and a second array or stack 108 of memory cells on top of the first array or stack 105.

[0038] The memory array 100 may include word lines 110 and digit lines 115. The memory cells of the first and second stacks 105 and 108 may each have one or more self-selected memory cells. Figure 1 Some of the elements included therein are marked with numerical indicators, and other corresponding elements are not marked but are the same or will be understood to be similar.

[0039] The stack of memory cells may include a first dielectric material 120, a storage element material 125 (e.g., a chalcogenide material), a second dielectric material 130, a storage element material 135 (e.g., a chalcogenide material), and a third dielectric material 140. In some examples, the self-selected memory cells of the first and second stacks 105, 108 may have a common conductive line such that the corresponding self-selected memory cells of each stack 105 and 108 may share a digit line 115 or a word line 110.

[0040] In some examples, a memory cell can be programmed by applying an electrical pulse to the cell, which may include a memory storage element. The pulse may be applied via a first access line (e.g., word line 110) or a second access line (e.g., digit line 115), or a combination thereof. In some cases, after applying the pulse, ions may migrate within the memory storage element, depending on the polarity of the memory cell. Thus, the concentration of ions relative to the first or second side of the memory storage element may be based at least in part on the polarity of the voltage between the first and second access lines. In some cases, asymmetrically shaped memory storage elements may cause ions to be more crowded in portions of the element with larger areas. Certain portions of the memory storage element may have higher resistivity and, therefore, may result in a higher threshold voltage than other portions of the memory storage element. This description of ion migration represents an example of a mechanism for self-selecting memory cells to achieve the results described herein. This example of a mechanism should not be considered limiting. The present disclosure also includes other examples of mechanisms for self-selecting memory cells to achieve the results described herein.

[0041] The architecture of memory array 100 may be referred to as a cross-point architecture, in which, in some cases, memory cells are formed at topological intersections, such as between word lines 110 and digit lines 115. This cross-point architecture can provide relatively high-density data storage with lower production costs compared to other memory architectures. For example, the cross-point architecture can have memory cells with a reduced area and, therefore, increased memory cell density compared to other architectures.

[0042] Although Figure 1 The example of FIG. 1 shows two memory stacks 105 and 108, but other configurations are possible. In some examples, a single memory stack of self-selecting memory cells can be constructed above substrate 104, which can be referred to as a two-dimensional memory. In some examples, three or four memory stacks of memory cells can be similarly configured in a three-dimensional cross-point architecture.

[0043] Memory array 100 can include a substrate 104 having a set of contacts arranged in a grid or staggered pattern. In some cases, the set of contacts can extend through the substrate and couple with access lines of memory array 100. Memory array 100 can include an additional substrate 104 (e.g., positioned above both stacks 105 and 108). The additional substrate 104 can have a set of contacts (e.g., extending through the substrate) that couple with access lines of memory array 100.

[0044] The memory array 100 may include a set of planes of conductive material separated from each other by a second insulating material formed on a first insulating material on a substrate material. Each of the planes of conductive material may include a set of recesses formed therein. The planes, such as word line plates corresponding to one or more word lines 110 on the same stack (e.g., memory stack 105, memory stack 108), may be obtained through a reset process by using a sacrificial layer (e.g., a conformal layer) for etching during a stack deposition process step, removing the conformal layer after cell definition, and replacing the conformal layer with a more conductive material.

[0045] A set of conductive pillars can be formed in the openings, extending generally perpendicular to the plane of the conductive material and the substrate. The set of conductive pillars can be divided into a set of pillar pairs. Each pillar in the pair can be coupled to a different one of the conductive contacts. In some cases, each pillar in the pair can be coupled to a conductive contact on substrate 104. Additionally or alternatively, one pillar of each pair can be coupled to a conductive contact on substrate 104, and the other pillar of each pair can be coupled to a conductive contact on a different substrate 104 (e.g., positioned above memory stacks 105 and 108).

[0046] In some examples, memory stacks 105 and 108 may include a chalcogenide material configured to store a logic state. For example, the memory cells of memory stacks 105 and 108 may be examples of self-selecting memory cells. The chalcogenide material may be formed in the set of recesses such that the chalcogenide material in each respective one of the set of recesses is at least partially in contact with one pillar of the set of pillar pairs.

[0047] Figures 2A to 2F Various views of example memory arrays 200-a, 200-b, 200-c, and 200-d are shown during a series of steps or processes that may be performed to form a stacked memory device according to examples as disclosed herein. Specifically, Figures 2A to 2F , showing the process of forming the word line plane, depositing the sacrificial layer and the insulating material.

[0048] Figure 2A A side view of an example memory array 200 - a is shown. Figure 2B Shown in Figure 2A During the process steps following the process steps shown in Figure 2A A top view of an example memory array 200 - b taken along section line AA′. Figure 2C Shown along Figure 2B The memory array 200-b (eg, as shown in FIG. 1 ) is cut off by the cross-section line BB'. Figure 2B A cross-sectional view of the ). Figure 2D Shown in Figure 2B and2C During the process steps following the process steps shown in Figure 2B FIG. 2 is a cross-sectional view of the memory array 200 - c taken along section line BB′. Figure 2E Shown in Figure 2D During the process steps following the process steps shown in Figure 2B FIG. 2 is a cross-sectional view of the memory array 200 - d taken along section line BB′.

[0049] Figure 2F Shown along Figure 2E Example memory array 200-d (eg, as shown in FIG. 1 ) of section line AA′ Figure 2D ) shown in the top view.

[0050] Figure 2A A side view of an example memory array 200-a according to examples as disclosed herein is shown; for example, memory array 200-a can support a vertical 3D memory device with an NMOS TFT selector. Memory array 200-a can include a collection of conductive contacts 235 extending through substrate 104-a or 104-b. Memory array 200-a can further include alternating layers of material 240 and insulating material 245 (e.g., insulating material layers, dielectric layers). In some cases, material 240 can be a conductive material (e.g., to form a conductive layer). In other cases, material 240 can be a sacrificial insulating material (e.g., different from insulating material 245).

[0051] The substrate 104 may be a dielectric material, such as a dielectric film.A single conductive contact of the set of conductive contacts 235 may be configured to couple any single vertical pillar (eg, a digit line) with a transistor (eg, a select transistor or a digit line selector).

[0052] In some examples, conductive contacts 235 may be formed in both substrates 104-a and 104-b. For example, conductive contact 235-a may couple a first leg of a pair of legs (e.g., corresponding to a digit line) to a transistor. Conductive contact 235-c may couple a second leg of the pair of legs to a transistor. Conductive contact 235-b and conductive contact 235-d may each couple one leg of the second pair of legs to a transistor. Additionally or alternatively, each of conductive contacts 235 may extend through substrate 104-b (e.g., conductive contacts 235-c and 235-d may be formed through substrate 104-b). For example, conductive contact 235-a may couple a first leg of a pair of legs to a transistor, and contact 235-b may couple a second leg of the pair of legs to a transistor.

[0053] The set of conductive contacts 235 can be arranged in a grid pattern. In some examples, a respective one of the set of conductive contacts 235 can be surrounded by up to eight other conductive contacts 235. Additionally or alternatively, the set of conductive contacts 235 can be arranged in a staggered pattern or a hexagonal pattern. For example, a respective one of the set of conductive contacts 235 can be surrounded by up to six other conductive contacts 235.

[0054] The memory array 200-a may also include a set of stacked planes of insulating material 245 and a set of stacked planes of material 240 (e.g., wordline planes or wordline plates), where material 240 may be a conductive material or an insulating material (e.g., Figure 2A 104 - b ). The stacked planes of material 240 may be separated from each other in the z-direction (e.g., vertically separated) by a set of planes of insulating material 245. For example, a first plane (e.g., a bottom plane) of second insulating material 245 may be formed (e.g., deposited) on a plane of substrate 104 - b , and then a plane of material 240 may be formed on the first plane of second insulating material 245. In some examples, a layer of first insulating material 245 may be deposited on substrate 104 - b . In some examples, material 240 may be a layer of conductive carbon or other conductive layer compatible with the active material. In some examples, material 240 may include conductive layers separated by active material passing through a protective barrier. Each layer of material 240 may be configured to serve as at least one word line plate. In some examples, material 240 and insulating material 245 form a set of layers, such as alternating layers.

[0055] Alternatively, material 240 may be a sacrificial insulating material. Here, memory array 200-a may include a set of stacked planes of sacrificial insulating material 240 and a set of stacked planes of insulating material 245. Sacrificial insulating material 240 may be a material different from insulating material 245 (e.g., an oxide material and a nitride material, respectively). Figure 2A During process steps subsequent to the process steps shown in , sacrificial insulating material 240 may be removed and replaced with a conductive material (eg, a conductive carbon layer, or other conductive layer compatible with the active material).

[0056] The additional plane of the second insulating material 245 may be as Figure 2A 104 - a ) are formed on material 240 in an alternating manner as shown in FIG. The second insulating material 245 can be a dielectric material, such as a dielectric film or layer. In some examples, the second insulating material 245 and the substrate 104 - a can be the same type of insulating material. Examples of insulating materials disclosed herein include, but are not limited to, dielectric materials such as silicon oxide.

[0057] Each respective one of the set of planes of material 240 can be located at (e.g., form) a different level of memory array 200-a. The individual planes of material forming memory cells can be referred to as a stack of 3D memory array 200-a. Material 240 (e.g., a conductive material) can include (e.g., be formed from) a metallic (or semi-metallic) material or a semiconductor material such as doped polysilicon, among others. In some examples, material 240 can be a plane of conductive carbon.

[0058] Figure 2A 2 shows six planes of material 240 and seven planes of second insulating material 245. The seventh plane of second insulating material 245 may be the uppermost layer of memory array 200-a. The number of planes of material 240 and second insulating material 245 is not limited to Figure 2A The material 240 and the second insulating material 245 may be arranged in more than six stacks or less than six stacks.

[0059] Figure 2B Shown along Figure 2A A top view of the memory array 200 - b taken along the section line AA′. Figure 2B Formation trenches 250 are shown through alternating planes of material 240 (eg, conductive material, insulating material) and second insulating material 245 of memory array 200-b. Trenches 250 can separate substrate 104 and conductive contacts 235 (previously shown in FIG. Figure 2A ) is exposed at the bottom of the trench 250. The trench 250 can be etched from top to bottom and etched into a linear shape. In some cases, the trench 250 can be formed by a combination of vertical and horizontal etching processes to form a recess in the trench 250. Figure 2C Additional details regarding the etching process and recesses are shown and described.Trench 250 may form a set of openings extending in substantially parallel directions on each plane of material 240 (eg, wordline plane, conductive layer).

[0060] Figure 2C Shown along Figure 2B2 . Memory array 200 - b is a side view of memory array 200 - b taken along line BB'. Memory array 200 - b illustrates a set of recesses 215 formed in material 240 (e.g., conductive material, insulating material) in each of the planes of memory array 200 - b. For example, a selective etching operation can be performed to isotropically form the set of recesses 215 in sidewalls 290 and 291 of trench 250. In some examples, trench 250 includes a first sidewall 290 spaced apart from a second sidewall 291, wherein a first portion 292 of first sidewall 290 formed by first insulating material 245 is spaced apart from a first portion 293 of second sidewall 291 formed by first insulating material 245 by a first distance. A second portion 294 of first sidewall 290 formed by first material 240 can be spaced apart from a second portion 294 of second sidewall 291 formed by first material 240 by a second distance that is greater than the first distance. In some examples, the portions of the sidewalls 290 and 291 of the trench 250 formed by the first material 240 are recessed relative to the portions of the sidewalls 290 and 291 of the trench 250 formed by the first insulating material 245 .

[0061] The etching operation may include one or more vertical etching processes (e.g., an anisotropic etching process or a dry etching process, or a combination thereof) or horizontal etching processes (e.g., an isotropic etching process), or a combination thereof. For example, a vertical etching process may be performed to vertically etch trench 250 to expose substrate 104-b and one or more conductive contacts 235, and a horizontal etching process may be used to form at least one recess 215 in at least one material 240. Etching parameters may be selected so that material 240 is etched faster than second insulating material 245.

[0062] Figure 2D Shown along Figure 2B 2. A side view of the memory array 200-b taken along line BB' is shown. The memory array 200-c shows the formation of a conformal material 220 (eg, a sacrificial material or layer). The conformal material 220 may be deposited into the trench 250 of the memory array 200-c. The conformal material 220 may be formed by conformally depositing the conformal material 220. Figure 2C The conformal material 220 contacts the first sidewall 290, the second sidewall 291, and the bottom wall 295 of each trench 250 (eg, contacts the substrate 104-b and the contact 235). Figure 2DConformal material 220 is shown formed on the sidewalls of trench 250 (e.g., on the surface of second insulating material 245 and material 240 in a different layer facing trench 250), but examples are not limited thereto. For example, in some cases, conformal material 220 may be confined to a collection of recesses 215 in material 240 in a different layer (e.g., conductive material, insulating material). In some cases, conformal material 220 may be referred to as a conformal layer or a sacrificial layer.

[0063] In some cases, an etching operation may be performed after forming the conformal material 220. In the etching operation, the conformal material 220 may be etched to form an opening or trench 250. The etching operation may cause a surface of the conformal material 220 (e.g., a surface facing the trench 250) to be spaced apart from a surface of the second insulating material 245 (e.g., a surface facing the trench 250). In some cases, the etching operation may cause the surface of the conformal material 220 (e.g., a surface facing the trench 250) to be substantially coplanar with a surface of the second insulating material 245 (e.g., a surface facing the trench 250), thereby forming connected sidewalls of the trench. The etching operation may further cause the substrate 104-b and the contact 235 to be exposed (e.g., by removing the conformal material 220 from the bottom wall 295 of the trench 250). The etching operations described herein may be vertical etching processes (e.g., an anisotropic etching process or a dry etching process, or a combination thereof) or horizontal etching processes (e.g., an isotropic etching process). For example, a vertical etching process may be performed to vertically etch the trench 250 , and a horizontal etching process may be used to form at least one recess in the first material 240 (eg, first conductive material 240 , sacrificial insulating material 240 ).

[0064] Figure 2E Shown along Figure 2B FIG2 shows a side view of memory array 200 - b taken along line BB'. Memory array 200 - d shows dielectric material 218 deposited in trench 250, atop conformal material 220 of memory array 200 - d. Dielectric material 218 may contact conformal material 220. Dielectric material 218 may further contact one or more contacts 235. Dielectric material 218 and conformal material 220 may cooperate to fill trench 250. In some cases, dielectric material 218 may be an example of an insulating material. In some examples, conformal material 220 may be selectively etched back to form a coplanar surface with dielectric material 218. The depth of the recess may be defined depending on the desired thickness.

[0065] Figure 2F Shown along Figure 2E A top view of an example memory array 200 - d taken along section line AA′. Figure 2FMemory array 200-d is shown after dielectric material 218 is deposited into the set of trenches 250. Each of the trenches 250 of memory array 200-d is lined with conformal material 220 and filled with dielectric material 218. The trenches 250 may extend through each of the layers of material 240 (e.g., conductive material 240, sacrificial insulating material 240), such as Figure 2E As shown in .

[0066] Figures 3A to 3I Various views of example memory arrays 200 - e , 200 - f , 200 - g , 200 - h , and 200 - i are shown during a series of steps or processes that may be performed to form a stacked memory device according to examples as disclosed herein.

[0067] Figure 3A Shown in Figure 2F 2. A top view of an example memory array 200-e during a process step subsequent to the process step shown in FIG. Figure 2F Section C-C'. Figure 3B Shown along Figure 3A FIG. 2 is a cross-sectional view of an example memory array 200 - e taken along section line BB′. Figure 3C and 3D Shown in Figure 3A and 3B 1. The example memory array 200-f during a process step subsequent to the process step shown in FIG. Figure 3C A cross-section CC' ( Figure 2F ), and Figure 3D Shown along Figure 3C FIG. 2 is a cross-sectional view of an example memory array 200 - f taken along section line BB′. Figure 3E 、 3F and 3G shows Figure 3C and 3D 1. Example memory array 200-g during process steps subsequent to the process steps shown in FIG. Figure 3E A top view of an example memory array 200-g is shown (eg, along Figure 3D The section line A-A') Figure 2F ) section CC' shown in . Figure 3F shows a top view of an example memory array 200-g, and Figure 3G Shown along Figure 3E FIG. 2 is a cross-sectional view of an example memory array 200 - g taken along section line BB′. Figure 3H Shown in Figure 3E 、 3F 3G and a top view of an example memory array 200-h during a process step subsequent to the process step shown in FIG. Figure 3FSection C-C'. Figure 3I An example memory array supporting vertical 3D memory devices with NMOS TFT selectors is shown according to examples as disclosed herein.

[0068] Figure 3A A top view of an example memory array 200-e is shown. Figure 2F The example memory array 200-e can be shown in cross section C-C'. Figure 2E and 2F During the process steps following the process steps shown in Figure 2F . The opening 360 may be formed in the trench 250 by etching away a portion of the dielectric material 218 and / or the conformal material 220. The opening 360 may be positioned above one or more of the contacts 235 such that the opening 360 exposes at least a portion of one of the contacts 235. Figure 3B Additional details regarding the relationship between openings 360 and contacts 235 are shown and described. In some cases, the example memory array 200-e may include a set of openings 360. For example, the set of openings may be formed at intervals along each of the trenches 250. Each of the openings 360 within a trench 250 may be separated from other openings in the trench 250 by dielectric material 218. The etching process used to form the openings 360 may be a vertical etching process. In some examples, the etching operation may not etch away all portions of the conformal material 320, for example, portions where the openings 360 are not formed.

[0069] Figure 3B Shown along Figure 3A A side view of the memory array 200-e taken along line BB'. Figure 3B As shown in FIG, a set of recesses 215 may be formed in the material 240 in each of the planes. The set of recesses 215 may be formed during the formation of the openings 360 (e.g., as described with reference to FIG. Figure 3A For example, a selective etching operation can be performed to form the set of recesses 215 in a fully or partially isotropic manner. The etching chemistry can be selected to selectively reach the material 240. The contacts 235 can be exposed by forming openings 360 in the trenches 250.

[0070] Figure 3C An example memory array 200-f is shown according to examples disclosed herein. Figure 2F The top view of the cross section CC' shown in FIG. Figure 3B The example memory array 200-e can be viewed from the cross-sectional line AA'. Figure 3A and 3BThe example memory array 200-f is formed after the processing steps shown in FIG. Figure 3C , storage element material 365 can be formed in opening 360. In some cases, storage element material 365 can extend to contact each sidewall of material 240. Storage element material 365 can further contact conformal material 220 and dielectric material 218. Forming storage element material 365 in opening 360 (e.g., by depositing storage element material 365 in opening 360) can reduce the size of opening 360.

[0071] The storage element material 365 can be an example of a chalcogenide material that can serve as a self-selecting storage element material (e.g., a material that can serve as both a selection device and a storage element), such as a chalcogenide alloy and / or glass. For example, the storage element material 365 can respond to an applied voltage, such as a programming pulse. For an applied voltage less than a threshold voltage, the storage element material 365 can remain in a non-conductive state (e.g., an "off" state). Alternatively, in response to an applied voltage greater than the threshold voltage, the storage element material 365 can enter a conductive state (e.g., an "on" state).

[0072] Figure 3D Shown along Figure 3C 2. Memory element material 365 may be formed in the set of recesses 215 by conformally depositing memory element material 365 into trench 250. Memory element material 365 may be deposited to contact sidewalls 290 and 291 and bottom wall 295 of trench 250 exposed by etching of conformal material 320. When memory element material 365 contacts bottom wall 295 of trench 250, memory element material 365 covers exposed contacts 235. Memory element material 365 may include a top layer 366.

[0073] Figure 3E A top view (eg, along section line AA') of an example memory array 200-g is shown. Figure 2F The cross section C-C' shown in FIG. Figure 3C and 3D, an etching operation is performed on the example memory array 200-f shown in FIG. to produce the example memory array 200-g. The etching operation may remove portions of the storage element material 365 to form storage element components (e.g., including the storage element material 365). Each of the storage element components of the storage element material 365 may be in contact with a layer of material 240 (e.g., conductive material 240). In some examples, portions of the conformal material 220 may be positioned on either side of the storage element components of the storage element material 365. The etching of the storage element material 365 may separate the storage element components of the storage element material 365 through the openings 360. The storage element components may enable the memory array 200-g (and the memory array 200 formed by processing steps subsequent to the memory array 200-g) to store data. That is, the storage element components may include the storage element material 365 and may be configured to store a logical state (e.g., a logical value of '0' or a logical value of '1').

[0074] The data storage element can be programmed to a target state by applying a pulse that satisfies a programming threshold (e.g., a programming pulse). The amplitude, shape, or other characteristics of the programming pulse can be configured to cause the storage element material 365 to assume the target state. For example, after applying the programming pulse, ions of the storage element component can be redistributed throughout the storage element, thereby changing the resistance of the memory cell detected when a read pulse is applied. In some cases, the threshold voltage of the storage element component can change based on the application of the programming pulse.

[0075] The state stored by a storage element component can be sensed, detected, or read by applying a read pulse to the storage element component. The amplitude, shape, or other characteristics of the read pulse can be configured to allow the sensing component to determine what state is stored on the storage element component. For example, in some cases, the amplitude of the read pulse is configured to be at a level at which the storage element component will be in an "on" state (e.g., current is directed through the material) for a first state, but will be in an "off" state (e.g., little or no current is directed through the material) for a second state.

[0076] In some cases, the polarity of the pulses applied to a storage element component (whether programming or reading) can affect the effectiveness of the operation being performed. For example, if a storage element component is storing a first state, a read pulse having the first polarity may cause the storage element component to assume an "on" state, while a read pulse having a second polarity may cause the storage element component to assume an "off" state. This can occur due to an asymmetric distribution of ions or other materials in the storage element component when the state is stored. Similar principles apply to programming pulses and other pulses or voltages.

[0077] Examples of chalcogenide materials that can serve as memory element components include indium (In)-antimony (Sb)-tellurium (Te) (IST) materials, such as In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, and the like, and germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) materials, such as Ge8Sb5Te8, Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge4Sb4Te7, and the like, or other chalcogenide materials, including, for example, alloys that do not change phase during operation (e.g., selenium-based chalcogenide alloys). Chalcogenide materials can also include other dopant materials at very low concentrations. Other examples of chalcogenide materials may include tellurium-arsenic (As)-germanium (OTS) materials, Ge, Sb, Te, silicon (Si), nickel (Ni), gallium (Ga), As, silver (Ag), tin (Sn), gold (Au), lead (Pb), bismuth (Bi), indium (In), selenium (Se), oxygen (O), sulfur (S), nitrogen (N), carbon (C), yttrium (Y), and scandium (Sc) materials, and combinations thereof. As used herein, hyphenated chemical composition designations indicate elements included in a particular mixture or compound and are intended to represent all stoichiometric amounts involving the indicated elements. In some examples, the chalcogenide material may be a chalcogenide glass or an amorphous chalcogenide material. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some examples, a SAG alloy may include silicon (Si), and such a chalcogenide material may be referred to as a SiSAG alloy. In some examples, chalcogenide glasses may include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form. In some examples, conductivity can be controlled through doping using various chemical species. For example, doping can include incorporating Group 3 (e.g., boron (B), gallium (Ga), indium (In), aluminum (Al), etc.) or Group 4 (tin (Sn), carbon (C), silicon (Si), etc.) elements into the composition.

[0078] Figure 3F Shown along Figure 3D FIG. 2 is a top view of an example memory array 200 - g taken along section line AA′. Figure 3F Include Figure 3E Example memory array 200-g shows a collection of trenches 250. Each of trenches 250 includes a collection of storage element components of storage element material 365. The collection of storage element components can be separated from other storage element components by openings 360 and dielectric material 218. The storage element components can be in contact with conformal material 220.

[0079] Figure 3G Shown along Figure 3FA side view of the memory array 200-g taken along line BB' may be shown. An etching operation (eg, as shown in FIG. 3 ) may be performed after forming the memory element material 365. Figure 3C and 3D 250) such that a surface of the storage element material 365 (e.g., a surface facing the trench 250) is substantially coplanar with a surface of the layer of insulating material 245 (e.g., a surface facing the trench 250). Etching of the storage element material 365 may form connected sidewalls and remove a top layer 366 of the storage element material 365, such as Figure 3D . The etching of the storage element material 365 may also expose the contacts 235 in the substrate 104-b.

[0080] The portions of storage element material 365 positioned in the recesses may correspond to storage element components. In each recess, each storage element component of storage element material 365 may contact a single conductive material 240 (e.g., a single conductive material 240 positioned adjacent to a cell of storage element material 365) and at least two dielectric layers (e.g., a top insulating material 245 positioned on top of the storage element component of storage element material 365 and a bottom insulating material 245 positioned on the bottom of the storage element component of storage element material 365). In some cases, each storage element component of storage element material 365 may contact a single material 240. Here, it may be subsequently (e.g., in Figure 3G During a process step subsequent to the process step shown in , material 240 is removed and replaced with a conductive material. Etching of storage element material 365 may expose storage element components of storage element material 365. Etching of storage element material 365 may also expose contacts 235 in substrate 104-b.

[0081] Figure 3H Shown in Figure 3E 、 3F 3G and a top view of an example memory array 200-h during a process step subsequent to the process step shown in FIG. Figure 3F As shown in the cross section C-C'. Figure 3H , a conductive material 370 is deposited into the opening 360. The conductive material 370 may be formed from a first substrate (eg, as shown in FIG. 1 ). Figure 2C The conductive support 370 is shown extending from the substrate 104-a) to the second substrate (eg, substrate 104-b). In some implementations, the conductive material 370 contacts the insulating material 245 and the conductive support 370 is shown extending from the substrate 104-a) to the second substrate (eg, substrate 104-b). Figure 3G . In some examples, the conductive material 370 is compatible with the active material. The conductive material 370 can be a uniform conductive material (e.g., a conformal conductive material) or a barrier layer with an inner material (e.g., where the barrier layer surrounds the conductive material).

[0082] In the case where the conductive material 370 includes a barrier layer and an inner material, the barrier material can be deposited into the opening 360. In some implementations, the barrier material can contact the insulating material 245 and the inner material. Figure 3G . The barrier material may be compatible with the active material. The barrier material may be a conductive material (e.g., a conformal conductive material) or a barrier layer having a conductive material. For example, the barrier material may include aluminum oxide. An inner material may be deposited in the opening 360 (e.g., to contact the barrier material) to form a conductive pillar. The inner material may be a metallic (or semi-metallic) material, or a semiconductor material such as a doped polysilicon material, among others. However, other metallic, semi-metallic, or semiconductor materials, metallic materials, or dielectric materials may be used.

[0083] Conductive material 370 may contact the first and second memory element components formed from memory element material 365. Pillars (e.g., having conductive material 370) formed in each respective one of the set of openings 360 may be arranged to extend generally perpendicular to the alternating planes of material 240 and insulating material 245. Memory element material 365 and the conductive pillars formed in each respective one of the set of openings 360 may be formed in a generally square shape. Examples of the present disclosure are not limited to exact or nearly exact square shapes. For example, memory element material 365 and the conductive pillars may be formed in any shape, including a circular or oval shape.

[0084] Figure 3I An example memory array 200-i supporting vertical 3D memory devices with NMOS TFT selectors is shown according to examples as disclosed herein. Figure 3I In the configuration of the memory device shown in FIG, pillars of conductive material 370 contact contacts 235 on the same substrate 104-b. Substrate 104-b is shown positioned below the pillars of conductive material 370, but in some other cases, contacts 235 may be formed through substrate 104-a positioned above the pillars of conductive material 370.

[0085] Contacts 235 can couple pillars formed from conductive material 370 to additional selection elements, such as select transistors. For example, contacts 235 can couple pillars (e.g., digit lines) to NMOS TFTs 305, which are formed in a pillar selection layer below substrate 104-b. In some examples (not shown), the pillar selection layer may be located above the memory layer, for example, so that the TFTs can be contacted from above the digit lines. Combinations of the two configurations are also possible; for example, some TFTs may be located below the memory layer and some above the memory layer, so that digit line selection can be partially from above and partially from below. Details of NMOS TFTs 305 will be described below. The portion located above the pillar selection layer may form a memory layer in which a vertical 3D memory array of memory cells is disposed. Transistor 305 may be a digit line selector formed as a regular matrix. Transistor 305 can be positioned to selectively couple or isolate the pillars (e.g., digit lines) at various times during access operations (e.g., read operations, write operations, refresh operations). Activating transistor 305 may initiate an access operation of one of the storage element components formed from storage element material 365. For example, activating transistor 305 and applying a voltage to material 240 (e.g., by applying a voltage to the conductive material via a word line driver) may access the storage element component formed from storage element material 365.

[0086] A peripheral circuit layer may be formed below the pillar selection layer, and in the peripheral circuit layer, for example, sense amplifiers and decoding circuitry may be arranged for word lines and bit lines.

[0087] Figure 4A and 4B Example memory arrays 200 - j and 200 - k are shown during a series of steps or processes that may be performed to form a stacked memory device according to examples as disclosed herein.

[0088] Figure 4A 2 shows a top view of an example memory array 200-j according to an example disclosed herein. Figure 3G Example memory array 200-j during a series of steps or processes performed thereafter.

[0089] Conductive material 370 may be deposited into opening 360 to form a conductive pillar. In some cases, the pillar may be partially filled with conductive material 370 and then filled with dielectric material 705. In some cases, dielectric material 705 may be the same as dielectric material 218. The pillar may extend from a first substrate (e.g., substrate 104-a) to a second substrate (e.g., substrate 104-b).

[0090] Conductive material 370 may contact the first and second memory element components formed from memory element material 365. The pillars (e.g., of conductive material 370 and dielectric material 705) formed in each respective one of the set of openings 360 may be arranged to extend generally orthogonal to the alternating planes of material 240 and insulating material 245.

[0091] Figure 4B A top view of an example memory array 200-k according to examples disclosed herein is shown. Memory array 200-k may be formed after forming a second opening and subsequently filling the second opening with insulating material 710. In some cases, dielectric material 705 and insulating material 710 are examples of the same material. The second opening may be formed in trench 250 by etching away a portion of conductive material 370. The etching process may further include etching away portions of other materials. For example, the etching process may etch away some (or all) of dielectric material 218. The etching process may include a vertical etching process occurring generally orthogonally to the alternating planes of material 240 and insulating material 245. For example, the etching process may include a single-gate vertical channel (SGVC) 3D not AND technique to create the second opening of example memory array 200-k. The second opening may extend to the bottom substrate (e.g., 104-b) to expose one or more contacts 235. The second opening can divide a pillar (e.g., including conductive material 370 and dielectric material 705) into a pair of pillars including a first pillar (e.g., a sub-pillar) and a second pillar (e.g., a sub-pillar). Each sub-pillar of the pair of pillars can correspond to a digit line. The size (e.g., cross-sectional area) of each sub-pillar of the pair of pillars may not affect the operation of memory array 200-k. That is, the height of each sub-pillar of the pair of pillars (e.g., extending from a first substrate, such as substrate 104-a, to a second substrate, such as substrate 104-b) can be relatively low (e.g., less than two microns).

[0092] In some cases, trench 250 may extend and include a set of second openings (e.g., separated by dielectric material 218), where each opening divides a pillar into a pillar pair. Insulating material 710 may be a dielectric material. In some cases, insulating material 710 may be the same material as dielectric material 218. Insulating material 710 may contact the pillars formed from conductive material 370. Insulating material 710 may be formed from a top substrate (e.g., Figure 2A The substrate 104-a shown in FIG extends to a bottom substrate (eg, Figure 2A 104 - b ), thereby isolating each sub-pillar of a pair of pillars. Insulating material 710 may further extend to contact insulating material 218. Here, the insulating material (e.g., insulating material 410 in combination with insulating material 218) may extend the length of trench 250.

[0093] The insulating material 710 can isolate pillars within a pillar pair from each other. This can reduce the effect of accessing a first storage element component located above a second storage element component when the first and second storage element components are located in the same recess. The insulating material 710 can separate the storage element material 365 on either side of the trench 250. That is, the insulating material 710 can isolate (e.g., electrically isolate) memory cells that contact a first sidewall of the trench 250 (e.g., formed by the storage element material 365) from memory cells that contact a second sidewall of the trench 250.

[0094] Figure 5 Another example memory array 200-1 supporting vertical 3D memory devices with NMOS TFT selectors according to examples disclosed herein is shown. Specifically, Figure 5 A configuration for coupling a digit line to a digit line selector is shown.

[0095] Figure 5 A cross-sectional view of the memory array 200-1 is shown. The cross-sectional view may be taken along Figure 4B Section line BB' shown in any one of . Figure 5 A configuration of a memory device is shown in which each pillar (e.g., of a pair of pillars) having a conductive material 370 contacts a contact 235 on the same substrate 104. Substrate 104-b is shown positioned below the pillars of conductive material 370, but in some other cases, contact 235 may be formed through substrate 104-a positioned above the pillars of conductive material 370.

[0096] The memory array 200-1 may include a first pillar (or first sub-pillar) formed of a conductive material 370-a that contacts a contact 235-a of the substrate 104-b. The contact 235-a may couple the pillar formed of the conductive material 370-a to an additional selection element, such as a select transistor. For example, the contact 235-a may couple the first pillar (e.g., a digit line) to an NMOS TFT 505-a formed in a pillar selection layer (e.g., a digit line) below the substrate 104-b. Figure 5 Not shown and similar to Figure 3I The details of the NMOS TFT 505-a will be described below. The portion located above the pillar selection layer may form a memory layer ( Figure 5 Not shown and similar to Figure 3I), in which a vertical 3D memory array of memory cells is disposed. Transistor 505-a may be a digit line selector formed as a regular matrix. Transistor 505-a may be positioned to selectively couple or isolate a pillar (e.g., a digit line) at various times during an access operation (e.g., a read operation, a write operation, a refresh operation). Activating transistor 505-a may initiate an access operation of one of the storage element components formed from storage element material 365. For example, activating transistor 505-a and applying a voltage to material 240-a (e.g., by applying a voltage to a conductive material via a word line driver) may access the storage element component formed from storage element material 365-a. Material 240-a may be an example of conductive material 240. In some cases, material 240-a may be deposited onto the stack (e.g., on Figure 2A In some other cases, material 240-a may be deposited onto the stack as a sacrificial insulating material. In subsequent process steps, material 240-a may be removed and replaced with conductive material 240-a.

[0097] Memory array 200-1 may further include a second pillar (or second sub-pillar) formed of conductive material 370-b that contacts substrate 104-b. The pillar formed of conductive material 370-a and the pillar formed of conductive material 370-b may form a pair of pillars. That is, the pillar formed of conductive material 370-a and the pillar formed of conductive material 370-b may be formed when the conductive pillar is divided by an etching process. Contact 235-b may couple the second pillar formed of conductive material 370-b to a transistor (e.g., an NMOS TFT), 505-b, which may be a digit line selector formed in a regular matrix. In some cases, transistor 505-b may be located at the same level as transistor 505-a (e.g., part of the same matrix). Details of NMOS TFTs 505-a and 505-b will be described below.

[0098] In some embodiments, selector TFTs 505-a and 505-b may be located on opposite sides of the memory layer and may be viewed from below (eg, Figure 5 In some cases, both TFTs may be located in a pillar selection layer (e.g., a polysilicon layer) above the memory layer. Figure 5 Not shown and similar to Figure 3I , and in the peripheral circuit layer, for example, sense amplifiers and decoding circuit systems can be arranged for word lines and bit lines.

[0099] Figure 6An example of a transistor semiconductor device according to examples as disclosed herein is shown, for example, a field-effect NMOS thin film transistor (TFT). Figure 6 A diagram depicts one embodiment of two TFT select devices 504a and 504b that can be used to select vertically oriented bitline portions or array digit lines (not shown). Each TFT select device 504a, 504b has two source / drain (S / D) regions. The source / drain regions are located on either side of a channel region. In one embodiment, the source / drain regions and the channel region are polysilicon. The TFT select devices 504a, 504b have an upper junction between the channel region and an upper portion D, and a lower junction between the channel region and a lower portion S.

[0100] Each of the TFT select devices 504a, 504b has two gates 507 and a dielectric material 505 separating each gate from the channel region and the S / D regions. This dielectric can be referred to as a gate dielectric because it separates the gates 507 from the channel region and the S / D regions. In one embodiment, the gate dielectric 505 extends along the sides of the source / drain regions and the channel region or each select device. The gate dielectric can be extended in the x-direction along the vertical sidewalls of the pillar structure including the channel region and the S / D regions.

[0101] The gate dielectric separates the gate from either the channel region or the source / drain region, as the case may be. In this example, each gate 507 extends vertically from below the lower junction to above the upper junction. That is, the gate 507 is formed to be immediately adjacent to the vertical length of the channel region and immediately adjacent to a portion of the vertical length of both the S / D regions. The upper drain can be connected to a vertically oriented bit line portion or array digit line. In some embodiments, for example, gate material can be deposited and selectively (e.g., anisotropically) removed to form the gate 507, e.g., forming a spacer-like structure of gate material adjacent to the gate dielectric along and / or around the channel region.

[0102] A gap-fill dielectric 520, such as an oxide, is formed between adjacent select devices as an insulating material. In some cases, the TFT select devices 504a and 504b may share the same gate 507 located therebetween. In other words, there may not be a gap between adjacent select devices 504a and 504b.

[0103] In some cases, TFT selection devices can be formed in a regular matrix below the memory array (specifically, below the pillars of the memory cells). In this example, the spacing of adjacent TFT selection devices in the x-direction can be consistent with the corresponding spacing of the memory cells, which will be referenced to the Figures 7A to 7C Further explanation.

[0104] Figures 7A to 7CVarious views of an example NMOS TFT selector are shown according to examples as disclosed herein.

[0105] Typically, a polysilicon-based TFT with, for example, a 48 nm pitch and a 100 nm channel length may be capable of supporting 1.5 V as a maximum drain bias and 3.5 V as a maximum gate bias, which may have a 20 uA I ON Other voltage and / or current values ​​are possible. This is a MOSFET that is always depleted with an N+S / D insert and an N-channel insert. However, in this disclosure, consistent with the significantly looser spacing of the V-3D MTX cell, a MOSFET configured with an enable voltage exceeding I is proposed. ON The selector transistor of at least one pair of parallel elongated TFTs will be increased by a factor of 10×. This 10× factor will become a factor of 5× or more due to the doubling of the channel length (from 110 to ~220 nm).

[0106] like Figures 7A to 7C As shown in FIG, stripe 710 may represent a gate terminal. There may be two gates, each with a gate oxide on one side of the channel region 720 and another gate oxide on the other side, which may be represented by rectangular boxes, and thus the width of the TFT may be doubled. Below the channel region 720, there may be a source region of the TFT, and the rectangular boxes may physically correspond to the polysilicon pillars of the transistor channel, with the drain region connected to the pillars.

[0107] In other words, a matrix of thin-film transistors (TFTs) is provided below the digit lines, with one TFT transistor for each digit line. The TFTs are formed in a polysilicon layer below the 3D memory array, while peripheral circuitry including sense amplifiers and decoding circuitry for word and bit lines is formed below the matrix.

[0108] As from these Figure 7A As can be seen, the transistor channel has been extended to 120nm, with the integration distance limited to 50nm. Therefore, the width of the transistor has been relaxed or extended, and two transistors have been arranged in parallel, so that the driving capability can be about five times (due to the larger width), so that the correct current can be fed to the memory cell.

[0109] Figure 7B An alternative configuration is schematically shown in which strips 730 of gate terminals are formed in a square configuration around a channel region 740 .

[0110] As another alternative, Figure 7C In FIG, an example is shown where a stripe 750 is multiplied between two adjacent channel regions 720 while keeping the integration distance still reduced to 55 nm.

[0111] Figures 8A to 8DVarious diagrams are shown for accessing memory cells of a vertical 3D memory device having an NMOS TFT selector according to examples as disclosed herein. Specifically, Figures 8A to 8D It is shown how to achieve selection of a single memory cell with a single NMOS TFT while deselecting all others.

[0112] As an example, these figures may show only a 3x3 matrix of pillars (P1, ..., P9, ie the pillars extending vertically towards the reader), and more particularly a small matrix of nine TFT select transistors provided at the base of these pillars, one TFT per pillar.

[0113] like Figure 8A As shown in Figure 1, for deselection, a floating-biasing strategy is safely employed for the unselected pillars that cannot be shorted to GND. The potential of the unselected pillar that remains floating will be determined by the capacitance ratio between the pillar and WL (biased at GND - all unselected, and at -3.5V with one selected), and is therefore approximately GND.

[0114] exist Figure 8A On the left side, an example 3×3 matrix of pillars (P1,…,P9) is represented. In some examples, each pillar may correspond to Figure 1 , and may include conductive material 370, as described above. In some examples, each pillar (P1, ..., P9) is coupled to a corresponding select transistor (T1, ..., T9) that may correspond to a pillar selector transistor 305, 505-a, 505-b and may be an NMOS thin film transistor (TFT). The transistors (T1, ..., T9) may be formed in a pillar select layer below the memory layer; the peripheral circuit layer may be formed below the pillar select layer. As described above, Figure 6 and 7A -7C describes the formation of selector transistors (T1, ..., T9).

[0115] like Figure 8AAs depicted in FIG, pillars (P1, ..., P9) and select transistors (T1, ..., T9) can be organized into rows and columns. For example, transistors T1, T2, and T3 can have respective terminals (e.g., source terminals) coupled to a common line L0; transistors T4, T5, and T6 can have respective terminals (e.g., source terminals) coupled to a common line L1; and transistors T7, T8, and T9 can have respective terminals (e.g., source terminals) coupled to a common line L3. Lines L0, L1, and L2 can be coupled (not shown) to a digit line driver formed in a peripheral circuit layer formed below a pillar select layer (e.g., a silicon substrate layer), such as a CMOS array below the array. Lines L0, L1, and L2 are configured to be biased to respective line voltages V_L0, V_L1, and V_L2, which can be selected digit line programming (e.g., set / reset) or read voltages or unselected digit line voltages.

[0116] In the depicted row / column organization, transistors T1, T4, and T7 may have gate terminals coupled to a common row line R2; transistors T2, T5, and T8 may have respective gate terminals coupled to a common row line R1, and transistors T3, T6, and T9 may have respective gate terminals coupled to a common row line R0. Lines R0, R1, and R2 may be coupled (not shown) to digital line driver control circuitry formed in a peripheral circuit layer. Row lines R0, R1, and R2 are configured to be biased to respective row line voltages V_R0, V_R1, and V_R2, which may be a turn-on voltage, or to an inhibit voltage, based on the operation to be performed and the cell or pillar being addressed.

[0117] exist Figure 8A , a schematic cross-section of a portion of a 3D memory array is shown. Each memory cell comprises a storage element, an intersection of a digit line (e.g., pillar Pi) and a word line, which may be a selected word line SWL or an unselected word line UWL. The memory cell can be programmed in one of at least two states by applying a programming pulse of appropriate magnitude and polarity. For example, a first polarity pulse having a magnitude greater than the threshold voltage of the memory cell can be applied to program the memory cell in a first state (the set state); the first polarity can be positive, e.g., the word line voltage is greater than the digit line voltage—see reference Figure 8B A second polarity pulse having a magnitude greater than the threshold voltage of the memory cell may be applied to program the memory cell in a second state (reset state); the second polarity may be different from (e.g., opposite to) the first polarity, and thus may be negative, e.g., the word line voltage is less than the digit line voltage—see reference Figure 8C In some embodiments, the programming polarity can be interchanged; for example, in some cases, the set state can be programmed with negative polarity and the reset state can be programmed with positive polarity. The set and reset states can correspond to logic 1 and logic 0 states, respectively; however, different rules can be used.

[0118] Memory cells in different states (e.g., set and reset, or logic 1 and 0) have different threshold voltages. Therefore, it is possible to apply a sense or read voltage across the memory cell to read the cell state. The read voltage can be positive or negative; depending on the polarity of the read voltage, different situations may occur, as explained below.

[0119] Generally speaking, after a programming pulse in a given polarity, a memory cell has a low threshold voltage when read in the same polarity, and a high threshold voltage when read in the opposite polarity. Thus, if the set state is programmed using a positive polarity pulse, as described above, then the memory cell has a low threshold voltage when read in the same (positive) polarity. Conversely, a cell programmed in the set state using a positive polarity pulse has a high threshold voltage when read in the opposite (negative) polarity. Meanwhile, if the reset state is programmed using a negative polarity pulse, as described above, then the memory cell has a high threshold voltage when read in the opposite (positive) polarity. Conversely, a cell programmed in the reset state using a negative polarity pulse has a low threshold voltage when read in the same (negative) polarity.

[0120] Independent of the read polarity, it is possible to distinguish between the set and reset states and, therefore, read the cell logic states associated therewith. In practice, it is sufficient to bias the selected digit line terminal and the selected word line SWL terminal to a read voltage (which is an intermediate voltage between the lower and upper threshold voltages of the memory cells) and detect which memory cells draw a large current or are thresholded. In the above example, a negative polarity read scheme was employed; cells programmed in the set state using a positive polarity pulse were not thresholded, while cells programmed in the reset state using a negative polarity pulse were thresholded. As mentioned, a different read scheme, such as a positive polarity read scheme, may be employed.

[0121] See again Figure 8A The cross section shown on the right shows the cross section during an access operation where the pillars are selected (e.g. Figure 8A In the case of pillars P5 in the left portion of FIG, the pillars are biased to an addressed digit line access voltage, which may be a programming voltage (e.g., a set or reset voltage), or to a read voltage, depending on the operation being performed. All cells coupled to the selected pillar have digit line terminals biased to the digit line access voltage, but only the addressed cell (the one located on the fourth plane from the bottom in the depicted example) has a word line terminal SWL biased to a word line access voltage VWL—all other cells in the selected pillar (e.g., unselected cells) have unselected word line terminals UWL biased to an unselected voltage (e.g., a ground (GND) voltage).

[0122] During an access operation, when a pillar is unselected (e.g., pillars P1, ..., P4, P6, ..., P9), the pillar is floating (or grounded) because, as will be explained in detail below, the corresponding selector transistors (T1, ..., T4, T6, ..., T9) are in a disabled state and, therefore, effectively insulated from the bias circuitry (or are passing a disabled voltage (e.g., ground voltage GND) provided by the bias circuitry). When the unselected pillar is floating, it is capacitively coupled to the word line, so the actual pillar voltage depends on the word line voltage weighted by the corresponding capacitance ratio (pillar capacitance to each WL node divided by the total capacitance, e.g., pillar capacitance to all WL nodes). Since all unaddressed or unselected word lines UWL are at ground voltage during an access operation, and only the addressed or selected word line SWL is at the access voltage, the pillar voltage remains close to ground. The deviation from ground voltage decreases as the number of word lines increases (e.g., as the number of planes or stacks in a 3D memory array increases).

[0123] although Figure 8A A small matrix of pillars (P1, ..., P9) and selector transistors (T1, ..., T9) organized into three rows and three columns is shown in FIG, but any number of rows and columns may be used. In the following description, pillar P5 will be considered the addressed or target pillar; for example, the addressed cell is coupled to a selected pillar P5 and to a selected plane or word line SWL. Based on the desired operation, the selected word line SWL is biased to an access word line voltage V_WL, which typically has an opposite polarity relative to the digit line access voltage. In a precise voltage division approach, the digit line voltage and the word line voltage are the same or approximately the same; however, different approaches, such as an amplitude ratio other than 1, may be employed. Even if not explicitly specified, the unaddressed word line UWL is typically biased to ground by corresponding word line circuitry (not shown).

[0124] To simplify the following description, a negative voltage read scheme will be employed; for example, during a read access operation, the overall voltage drop across the selected word line SWL terminal and the selected digit line terminal (pillar P5) of the memory cell is negative, i.e., V_WL-V_L1<0 volts. Furthermore, it will be assumed that the threshold voltage of a memory cell in a set state (e.g., a logic 1 state) is a negative voltage in the range of approximately -6.5V to approximately -5.5V (corresponding to a positive voltage read in the range of approximately +3.5V to approximately +4.5V), while the threshold voltage of a memory cell in a reset state (e.g., a logic 0 state) is a negative voltage in the range of approximately -4.5V to approximately -3.5V (corresponding to a positive voltage read in the range of approximately +5.5V to approximately +6.5V). This is merely an example, and different threshold voltage values ​​and ranges may be used. Thus, in the above example, during an access operation to read a memory cell, a -5.0V read voltage (e.g., the selected word line SWL voltage versus the selected digit line P5 voltage) may be applied across the addressed memory cell, as shown in FIG. Figure 8D Described in .

[0125] like Figure 8B As shown in FIG, the memory cell connected to the P5 pillar can be programmed in the set state. For this purpose, it may be necessary to apply a positive bias pulse of about +7V, since the cell can be in the reset state with a threshold voltage Vt as high as 7V (accounting for a 0.5V tolerance relative to the target reset program state threshold voltage range of 5.5 to 6.5V). This can be achieved by applying at least +3.5V to the selected word line (while the others are at GND - not shown here, see Figure 8A ) and applying at least -3.5V to bitline L1. Sector transistor T5 is enabled with a gate-on voltage of +1.0V (e.g., applied to row line R1) to pass the voltage to the digit line of the addressed cell in the array (pillar P5). The other pillars (P1, ..., P9, except P5) need to be deselected, as their cells may potentially share the same wordline and / or bitline.

[0126] As the voltage of row lines R0 and R2 and the gates coupled thereto increase to a bias above -3.5V, transistors T4 and T6 will turn on, thereby undesirably biasing the array digit lines (e.g., pillars P4 and P6) coupled to addressed bit line L1. Therefore, a -3.5V blocking or inhibiting bias can be imposed on row lines R0 and R2 to prevent T4 and T6 from turning on; this effectively results in floating array digit lines P4 and P6. Subsequently, ground voltage GND can be applied to bit lines L0 and L2.

[0127] In this configuration, all TFTs T1, ..., T9 (except T5) can be in an off state, for example, the voltage at the respective terminals coupled to bit lines L0, L1, and L2 is not passed to the respective pillars P1, ..., P9 (except P5), which can therefore be caused to float. Transistors T2 and T8 may or may not pass the GND voltage to the respective pillars P2 and P8, depending on their actual threshold voltages and the actual bias voltage of row line R1 (which can be adjusted accordingly).

[0128] The floating pillar potential will be determined by the capacitance ratio between the pillar and the WL (all unselected word lines biased at GND and the selected WL biased at +3.5 V). Therefore, the floating pillar can reach a small positive bias (e.g., +1 V) that is safe for deselection.

[0129] like Figure 8C As shown in FIG, the memory cells connected to the P5 pillar can be programmed in the reset state. For this purpose, it may be necessary to apply a negative bias pulse of about -7V, since the cells in the reset state also need to be reprogrammed and / or the cells may be in the set state with a threshold voltage Vt as high as -7V (accounting for a 0.5V tolerance relative to the target set programmed state threshold voltage range of -5.5 to -6.5V). This can be done by applying -3.5V to the selected word line (while the others are at GND - not shown here, see Figure 8A ) and applying +3.5V to bit line L1. The voltage is passed to the digit line of the addressed cell in the array (pillar P5) by enabling sector transistor T5 with a gate-on voltage of +4.5V (e.g., applied to row line R1). The other pillars (P1, ..., P9, except P5) need to be deselected, as their cells may potentially share the same word line and / or bit line.

[0130] To turn off transistors T4 and T6, and thus effectively isolate pillars P4 and P6 from bit line L1, row lines R0 and R2 and their coupled gates can be biased to +3.5V, causing the P4 and P6 pillars to float. Ground voltage GND can then be applied to bit lines L0 and L2, causing array digit line pillars P1, P2, P3, P7, P8, and P9 to be shorted to GND via respective transistors T1, T2, T3, T7, T8, and T9.

[0131] In this configuration, only pillars P4 and P6 can be left floating. The potential of the digit line P4 and P6 pillars is determined by the capacitance ratio between the pillars and WL (all unselected word lines biased at GND and one selected word line biased at -3.5V). Therefore, the floating pillars can reach a slightly negative bias (e.g., -1V) that is safe for deselection. The other unaddressed pillars are grounded, which is also a safe condition for deselection.

[0132] like Figure 8D As shown in FIG, the state of the memory cell connected to the P5 pillar can be read. For this purpose, it may be necessary to apply a negative bias pulse of about -5V. This can be done by applying at least -2.5V to the selected word line (while the others are at GND - not shown here, see Figure 8A ) and applying at least +2.5V to bit line L1. Sector transistor T5 is enabled with a gate-on voltage of +3.5V (e.g., applied to row line R1) to pass voltage to the digit line of the addressed cell in the array (pillar P5). The other pillars (P1, ..., P9, except P5) need to be deselected, as their cells may potentially share the same word line and / or bit line.

[0133] To turn off transistors T4 and T6, and thus effectively isolate pillars P4 and P6 from bit line L1, row lines R0 and R2 and the gates coupled thereto can be biased to +2.5V, causing the P4 and P6 pillars to float. Ground voltage GND can then be applied to bit lines L0 and L2, causing array digit line pillars P1, P2, P3, P7, P8, and P9 to be shorted to GND via respective transistors T1, T2, T3, T7, T8, and T9.

[0134] In this configuration, only pillars P4 and P6 can be left floating. The potential of the digit line P4 and P6 pillars is determined by the capacitance ratio between the pillars and WL (all unselected word lines biased at GND and one selected word line biased at -2.5V). Therefore, the floating pillars can reach a slightly negative bias (e.g., -0.5V) that is safe for deselection. The other unaddressed pillars are grounded, which is also a safe condition for deselection.

[0135] If a positive polarity read mechanism is employed (not shown in any figure), the memory cell can be programmed as shown in FIG. Figure 8B Similar bias conditions are applied to those described for the set state depicted in FIG, but smaller amplitudes of the wordline and bitline pulses are employed to avoid limiting all cells and instead induce snap-back only on set cells. For example, a positive wordline read voltage V_WL of +2.5V may be applied to the selected wordline SWL, a negative bitline read voltage of -2.5V may be applied to the selected bitline L1, and a pass voltage of +1.0V may be applied to the gate terminal of select transistor T5 coupled to the addressed digit line P5 via row line R1; the bias conditions described above are suitable for applying a read voltage of +5.0V to the addressed cells. Different amplitudes may be used. Additionally, unaddressed or unselected bitlines L0 and L2 may be biased to ground, and unaddressed or unselected wordlines R0 and R2 may be biased to a blocking or inhibiting voltage, such as -2.5V, causing all unaddressed or unselected digit lines to float.

[0136] The voltage values ​​used in the above description are example values ​​only and may vary while maintaining the scope of the present invention. In some cases, the ground voltage (GND) may be different from 0V; for example, the ground voltage may be a positive or negative voltage with respect to which other positive or negative voltages are evaluated. The same concepts and solutions described above may also be applied to voltages other than the reference voltage. Figures 8A to 8D The array configuration of the depicted 3D memory device configuration; for example, less adaptation of addressing similar to the reference Figures 4A to 7C 3D sub-pillars in the described memory array. In some cases, for a split-pillar architecture, a shared bit line can drive Figure 7A and 7B , wherein even / odd cells are selected at each stack or plane by even / odd word lines; alternatively, even / odd sub-bit lines may be driven independently as shown in FIG. Figure 7C Other pillar or sub-pillar decoding arrangements of the selector transistors may also be implemented (e.g., different from Figures 8A-8D ).

[0137] It should be further noted (not shown in any of the figures) that the selector transistors (eg, pillar select layers) may be formed at least partially on top of the memory layer - see Figure 3I , to better identify the layers being referred to. For example, the TFTs may be formed partially below the memory array (e.g., below the wordline conductive material layer) (e.g., coupled to even bitlines / sub-pillars) and partially above the memory array (e.g., coupled to odd bitlines / sub-pillars). Additionally or alternatively, multiple building blocks, each comprising a memory layer and a corresponding pillar selection layer, may be arranged on top of each other in a building block stack. These arrangements would allow the same basic building block (e.g., comprising a given number of memory stacks or layers and corresponding pillar selections) to be repeated several times during manufacturing to obtain 3D memory arrays with increased height (e.g., taller, with more stacks and layers) and therefore increased surface density. The bit lines for decoding different blocks and / or row lines of corresponding TFT selector transistors may be shared by all vertically stacked blocks (in which case the wordlines are decoded separately) or they may be separated for each stacked block (in which case the wordlines may be decoded collectively or individually). Connections to the bit lines, row lines, and / or word lines may extend from a peripheral circuit layer in a substrate (e.g., a silicon substrate accommodating CMOS under-array (CUA) circuitry, such as decoding and sensing circuitry) to corresponding building blocks adjacent to vertical rows of the memory array.

[0138] Figure 9A flow chart illustrating a method for accessing memory cells in a vertical 3D memory device having an NMOS TFT selector according to examples disclosed herein is shown. The operations of method 900 may be implemented by one or more controllers associated with the memory device. In some examples, the one or more controllers may execute an instruction set to control one or more functional elements of the memory device to perform the described functions. Additionally or alternatively, the one or more controllers may use dedicated hardware to perform portions of the described functions.

[0139] At 910, method 900 may include applying a first voltage to a selected word line while the other word lines are at predetermined voltages. The operations of 910 may be performed according to the methods described herein.

[0140] At 930, method 900 may include applying a second voltage to gate regions of TFTs associated with other memory cells that share the selected word line with the memory cell. The operations of 930 may be performed according to the methods described herein.

[0141] At 950, method 900 may include applying a second voltage to source regions of TFTs associated with memory cells sharing the selected word line, while source regions of other TFTs are at a predetermined voltage. The operations of 950 may be performed according to the methods described herein.

[0142] At 970, method 900 may include applying a third voltage to a gate region of a TFT associated with the memory cell. The operation of 970 may be performed according to the methods described herein.

[0143] In some cases, depending on the technology used, the first voltage may be +3.5V, the second voltage may be -3.5V, the third voltage may be +1V, and the predetermined voltage may be ground.

[0144] In some cases, depending on the technology used, the first voltage may be +2.5V, the second voltage may be -2.5V, the third voltage may be +1V, and the predetermined voltage may be ground.

[0145] In some cases, the first voltage may be -3.5V, the second voltage may be +3.5V, the third voltage may be +4.5V, and the predetermined voltage may be ground voltage.

[0146] In some cases, the first voltage may be -2.5V, the second voltage may be +2.5V, the third voltage may be +3.5V, and the predetermined voltage may be ground voltage.

[0147] It should be noted that during access using a single NMOS TFT, for the unselected pillars receiving the 3.5V, the transistor channel may be blocked and no current can pass, and therefore it may not even be necessary to place the source region at GND. The corresponding NMOS TFT can be left floating. The floating pillar of the NMOS select transistor may endanger the correct reading of the memory device. However, when programming the target cell, only the plate or plane of the selected word line is biased to 3.5V (such as Figure 8A ). Thus, even a floating pillar is at a voltage close to ground and does not affect the function of the memory device due to capacitive coupling of all other plates or planes biased to ground.

[0148] The access schemes provided in the present disclosure may further demonstrate that at least some of the pillars proximate to a selected pillar remain at a bias voltage close to ground and are unaffected by activities performed on the selected pillar.

[0149] A method for deselecting unaddressed memory cells in a 3D memory array is disclosed, wherein a plurality of word lines extend horizontally across a plurality of stacks and a plurality of array digit lines extend vertically, with each memory cell located at the intersection of a word line and an array digit line. The method includes floating an array digit line of the plurality of array digit lines that is coupled to the unaddressed memory cell.

[0150] In some embodiments, floating the array digit line includes applying an inhibit voltage to a gate of a thin film transistor (TFT) coupled between the array digit line and a bit line.

[0151] In some embodiments, the method further includes grounding unselected word lines of the plurality of word lines that are capacitively coupled to the array digit line.

[0152] In some embodiments, the method further includes deselecting a second unaddressed memory cell in the 3D memory array coupled to a second array digit line based at least in part on: applying a turn-on voltage to a second thin film transistor (TFT) coupled between the second array digit line and a second bit line; grounding the second bit line; and grounding the second array digit line.

[0153] In some embodiments, the method further includes deselecting a second unaddressed memory cell by grounding an unselected word line of the plurality of word lines.

[0154] In some embodiments, the method further includes selecting an addressed memory cell coupled to a selected digit line during deselection of the unaddressed memory cell based at least in part on: applying a word line access voltage to a selected word line of the plurality of word lines; applying a bit line access voltage to a selected bit line coupled to the selected array digit line; and applying a pass voltage to a gate of a selected TFT coupled between the selected array digit line and the selected bit line to pass the bit line access voltage to the selected array digit line.

[0155] For example, see reference Figure 8B Using the bias conditions described, memory cells can be programmed to a set state (or they can be read according to a positive voltage read scheme) by applying voltages of GND, -3.5V (-2.5V read), and GND to L0, L1, and L2, respectively, and -3.5V, +1.0V, and -3.5V to R0, R1, and R2, respectively. The addressed word lines in the 3D array can be biased to the desired word line access voltage (e.g., +3.5V set; or +2.5V read), while the unaddressed WLs can be grounded. This configuration will result in the array digit line P5 coupled to the addressed memory cells being biased to the desired digit line access voltage (-3.5V set; or -2.5V read), and thus achieving the overall desired voltage drop across the addressed memory cells. Memory cells coupled to different array digit lines (e.g., pillars P1, P2, P3, P4, P6, P7, P8, and P9) are not disturbed because the corresponding digit lines are floating and their potentials can be determined by the word line voltages weighted according to the capacitance ratio and can differ from ground by a very small amount due to all WLs being grounded except the addressed WL, which is biased at the access voltage.

[0156] In a similar manner, see reference Figure 8C

[0045] Under the bias conditions described by 8D (programmed to a reset state) and 8D (read according to a negative read scheme), memory cells can be accessed by applying voltages of GND, +3.5V (read +2.5V), and GND to L0, L1, and L2, respectively, and voltages of +3.5V, +4.5V, and +3.5V to R0, R1, and R2, respectively. The addressed word lines in the 3D array can be biased to the desired word line access voltage (e.g., set to -3.5V; or read -2.5V), while the unaddressed WLs can be grounded. This configuration will result in the array digit line P5 coupled to the addressed memory cells being biased to the desired digit line access voltage (set to +3.5V; or read to +2.5V), and thus achieving the overall desired voltage drop across the addressed memory cells. Memory cells coupled to different array digit lines are not disturbed because the respective digit lines are grounded (eg, pillars PI, P2, P3, P7, P8, and P9) or floating (eg, pillars P6, P7).

[0157] In some embodiments, unaddressed memory cells may be coupled to array digit lines (e.g., vertical pillars in a 3D memory array) that are different from the array digit lines coupled to addressed memory cells. The unaddressed memory cells may share the same word line as the addressed memory cells. By floating the digit lines coupled to the unaddressed memory cells, a safe condition is established when accessing (e.g., reading or programming, such as setting or resetting) the addressed memory cells to avoid or at least minimize disturbances to or from the unaddressed memory cells. The actual voltage of the floating digit line may depend on the voltage of the word line capacitively coupled to the floating digit line. Each word line can be affected by the voltage of the capacitively coupled floating digit line, and since all unaddressed word lines can be grounded while only the addressed word lines can be biased to the read / program access voltage, the actual voltage of the floating digit line remains close to ground. In some configurations, the portion of the digit line coupled to the unaddressed cells can be grounded, thus also providing a safe and interference-free situation. Furthermore, memory cells coupled to unaddressed word lines (e.g., word lines in a different stack or plane), including memory cells that share the same digit line as addressed memory cells, can be kept safe and undisturbed by grounding the unaddressed word lines to which they are coupled. The steps of the method described above may be performed in an order different from that described. Additional steps not yet described may be performed.

[0158] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for accessing a memory cell, comprising: applying a first voltage to a selected word line while the other word lines are at a certain voltage; applying a second voltage to a gate region of a thin film transistor TFT associated with a memory cell that shares the selected word line with the memory cell; applying the second voltage to the source regions of the TFTs associated with the memory cells sharing the selected word line, while source regions of other TFTs are at the certain voltage; and A third voltage is applied to a gate region of the TFT associated with the memory cell.

2. The method according to claim 1, wherein: The first voltage is a positive polarity programming or reading voltage, the second voltage is a negative polarity programming or reading voltage, the third voltage is a positive polarity turn-on voltage, and the certain voltage is a ground voltage.

3. The method according to claim 1, wherein: The first voltage is a negative polarity programming or reading voltage, the second voltage is a positive polarity programming or reading voltage, the third voltage is a positive polarity turn-on voltage higher than the second voltage, and the certain voltage is a ground voltage.

4. The method according to claim 1, further comprising: After applying the third voltage to the gate region of the TFT associated with the memory cell, a second memory cell among the other memory cells is deselected.

5. The method of claim 4 , wherein deselecting the second memory cell comprises: An array digit line of a plurality of array digit lines coupled to the second memory cell is floated, wherein the second memory cell is an unaddressed memory cell.

6. A method for deselecting unaddressed memory cells in a 3D memory array, comprising: Floating an array digit line coupled to the unaddressed memory cell among a plurality of array digit lines, the 3D memory array including a plurality of word lines extending in a horizontal direction and the plurality of array digit lines extending in a vertical direction across a plurality of stacks, each memory cell being located at an intersection of a word line and an array digit line. 7 . The method of claim 6 , wherein floating the array digit line comprises applying an inhibit voltage to a gate of a thin film transistor (TFT) coupled between the array digit line and a bit line.

8. The method according to claim 6, further comprising: Unselected ones of the plurality of word lines coupled to the array digit line are grounded based at least in part on floating the array digit line.

9. The method according to claim 6, further comprising: Deselecting a second unaddressed memory cell in the 3D memory array coupled to a second array digit line based at least in part on floating the array digit line based at least in part on: applying a turn-on voltage to a second thin film transistor TFT coupled between the second array digit line and the second bit line, grounding the second bit line, and The second array digit line is grounded.

10. The method according to claim 6, further comprising: The second unaddressed memory cell is deselected by grounding an unselected word line of the plurality of word lines.

11. The method according to any one of claims 6 to 10, further comprising: While deselecting the non-addressed memory cell, selecting an addressed memory cell coupled to a selected array digit line is based at least in part on: applying a word line access voltage to a selected word line of the plurality of word lines, applying a bit line access voltage to a selected bit line coupled to the selected array digit line, and A turn-on voltage is applied to the gate of a selected TFT coupled between the selected array digit line and the selected bit line to pass the bit line access voltage to the selected array digit line.

12. The method according to claim 6, further comprising: After floating the array digit line, applying a first voltage to the selected word line while the other word lines are at a certain voltage; as well as A second voltage is applied to a gate region of a TFT associated with a memory cell that shares the selected word line with the memory cell.

13. The method according to claim 12, further comprising: applying the second voltage to the source regions of the TFTs associated with the memory cells sharing the selected word line, while the source regions of the other TFTs are at the certain voltage; as well as A third voltage is applied to a gate region of the TFT associated with the memory cell.

14. A device comprising: a plurality of word lines extending horizontally above the plurality of stacks; a plurality of array digit lines extending in a vertical direction, wherein a plurality of memory cells are located at intersections of the word lines and the digit lines; as well as one or more controllers coupled to the plurality of word lines and the plurality of array digit lines, the one or more controllers being operable to cause the apparatus to: Array digit lines of the plurality of array digit lines coupled to unaddressed memory cells are floated.

15. The apparatus of claim 14, wherein to float the array digit lines, the one or more controllers are configured to cause the apparatus to: An inhibit voltage is applied to the gate of a thin film transistor TFT coupled between a digit line and a bit line of the array.

16. The apparatus of claim 14, wherein the one or more controllers are configured to cause the apparatus to: Unselected word lines of the plurality of word lines coupled to the array digit line are grounded.

17. The apparatus of claim 14, wherein the one or more controllers are configured to cause the apparatus to: Deselecting a second unaddressed memory cell coupled to a second array digit line based at least in part on: applying a pass voltage to a second thin film transistor TFT coupled between the second array digit line and the second bit line, grounding the second bit line, and The second array digit line is grounded.

18. The apparatus of claim 14, wherein the one or more controllers are configured to cause the apparatus to: The second unaddressed memory cell is deselected by grounding an unselected word line of the plurality of word lines.

19. The apparatus of any one of claims 14-18, wherein the one or more controllers are configured to cause the apparatus to: When the non-addressed memory cell is deselected, selecting an addressed memory cell coupled to a selected array digit line is based at least in part on: applying a word line access voltage to a selected word line of the plurality of word lines, applying a bit line access voltage to a selected bit line coupled to the selected array digit line, and A pass voltage is applied to the gate of a selected TFT coupled between the selected array digit line and the selected bit line to pass the bit line access voltage to the selected array digit line.

20. The apparatus of claim 14, wherein the one or more controllers are configured to cause the apparatus to: After floating the array digit lines, applying a first voltage to a selected word line while the other word lines are at a certain voltage; and A second voltage is applied to a gate region of a TFT associated with a memory cell that shares the selected word line with the memory cell.

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