Groove type epitaxial structure and preparation method thereof
By growing a combined film layer in the deep trench of the superjunction device, the problem of diffusion of doping elements at the PN interface is solved, a clearer interface and lower on-resistance are achieved, and device performance is improved.
Patent Information
- Application Number
- CN202510709451.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-09-05
AI Technical Summary
In superjunction devices, the interface between the P-type epitaxy and the N-type epitaxy is blurred due to the diffusion of doping elements, resulting in insufficient depletion, increasing the device on-resistance and reducing performance.
By sequentially growing a first intrinsic silicon layer, a carbon-doped silicon layer, and a second intrinsic silicon layer in the deep trench, a composite film layer is formed to inhibit the diffusion of P-type and N-type doped ions and keep the interface clear.
It effectively inhibits the mutual diffusion of P-type and N-type doping ions, keeps the interface clear, reduces the device on-resistance, and improves device performance.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a trench epitaxial structure and a preparation method thereof. Background Art
[0002] In a superjunction (SJ) device, deep trenches are etched into the N-type epitaxial layer (N-EPI), which is then filled with P-type epitaxial layers (P-EPI), creating a superjunction structure with alternating P-N junctions. Ideally, the interface between the P- and N-type epilayers is distinct, forming a PN junction. Specifically, during the PN junction formation process, electrons from the N-type region (e.g., phosphorus-doped) diffuse into the P-type region (e.g., boron-doped), while holes from the P-type region diffuse into the N-type region, creating an immobile space charge region of positive and negative ions on either side of the interface—the PN junction. However, during the actual growth process, thermal processes can cause the N-type dopant (e.g., phosphorus) and the P-type dopant (e.g., boron) to diffuse into each other near the interface between the P- and N-type epilayers. This phenomenon blurs the interface between the P- and N-type epilayers, affecting depletion, increasing device on-resistance, and degrading device performance. Summary of the Invention
[0003] The present application provides a trench epitaxial structure and a preparation method thereof, which can solve the problem that at the interface between the P-type epitaxial and N-type epitaxial of the traditional trench-type PN alternating super junction structure, P and N doped ions diffuse with each other, resulting in blurred interface, affecting depletion, increasing device on-resistance, and reducing device performance.
[0004] On the one hand, an embodiment of the present application provides a method for preparing a trench epitaxial structure, comprising:
[0005] Providing a substrate, on which a first epitaxial layer and a mask layer are sequentially formed, wherein deep trenches arranged in an array are formed in the mask layer and a portion of the thickness of the first epitaxial layer;
[0006] forming a first intrinsic silicon layer, wherein the first intrinsic silicon layer covers the sidewalls and bottom wall of the deep trench;
[0007] forming a carbon-doped silicon layer, wherein the carbon-doped silicon layer covers the first intrinsic silicon layer;
[0008] forming a second intrinsic silicon layer, wherein the second intrinsic silicon layer covers the carbon-doped silicon layer;
[0009] forming a second epitaxial layer, wherein the second epitaxial layer covers the second intrinsic silicon layer and fills a remaining space of the deep trench;
[0010] The mask layer on the surface of the first epitaxial layer is removed.
[0011] Optionally, in the preparation method of the trench-type epitaxial structure, the first intrinsic silicon layer is formed by an epitaxial process, wherein the silicon source gas participating in the reaction is SiH2Cl2, the process temperature is 500°C to 600°C, and the process chamber pressure is 6Torr to 20Torr.
[0012] Optionally, in the method for preparing the trench epitaxial structure, the thickness of the first intrinsic silicon layer is 200 angstroms to 300 angstroms.
[0013] Optionally, in the preparation method of the trench-type epitaxial structure, the carbon-doped silicon layer is formed by an epitaxial process, wherein the carbon source gas participating in the reaction is CH3SiH3, the process temperature is 600°C to 700°C, and the process chamber pressure is 6Torr to 20Torr.
[0014] Optionally, in the method for preparing the trench epitaxial structure, the thickness of the carbon-doped silicon layer is 350 angstroms to 500 angstroms.
[0015] Optionally, in the method for preparing the trench epitaxial structure, the doping concentration of carbon ions in the carbon-doped silicon layer is 1E19 atom / cm 3 ~4E19atom / cm 3 .
[0016] Optionally, in the preparation method of the trench-type epitaxial structure, the second intrinsic silicon layer is formed by an epitaxial process, wherein the silicon source gas participating in the reaction is SiH2Cl2, the process temperature is 500°C to 600°C, and the process chamber pressure is 6Torr to 20Torr.
[0017] Optionally, in the method for preparing the trench epitaxial structure, the thickness of the second intrinsic silicon layer is 200 angstroms to 300 angstroms.
[0018] Optionally, in the method for preparing the trench epitaxial structure, the first epitaxial layer is N-type doped; and the second epitaxial layer is P-type doped.
[0019] On the other hand, an embodiment of the present application further provides a trench epitaxial structure, comprising:
[0020] substrate;
[0021] A first epitaxial layer, the first epitaxial layer being located on the substrate, wherein deep trenches arranged in an array are formed in a portion of the thickness of the first epitaxial layer;
[0022] a first intrinsic silicon layer, wherein the first intrinsic silicon layer covers sidewalls and a bottom wall of the deep trench;
[0023] a carbon-doped silicon layer, wherein the carbon-doped silicon layer covers the first intrinsic silicon layer;
[0024] a second intrinsic silicon layer, wherein the second intrinsic silicon layer covers the carbon-doped silicon layer;
[0025] A second epitaxial layer covers the second intrinsic silicon layer and fills a remaining space of the deep trench.
[0026] The technical solution of this application has at least the following advantages:
[0027] The present application provides a trench-type epitaxial structure and a preparation method thereof. In the preparation method, a first intrinsic silicon layer, a carbon-doped silicon layer, and a second intrinsic silicon layer are sequentially grown in a deep trench in a first epitaxial layer, and then the second epitaxial layer is filled in the deep trench. A composite film layer of the first intrinsic silicon layer, the carbon-doped silicon layer, and the second intrinsic silicon layer is introduced at the interface between the first epitaxial layer and the second epitaxial layer. This can inhibit the mutual diffusion of P-type doped ions (boron ions) and N-type doped ions (phosphorus ions) during subsequent process thermal processes, thereby keeping the interface between the first epitaxial layer and the second epitaxial layer (PN interface) clear, reducing the on-resistance of the device and improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0029] Figure 1 is a flow chart of a method for preparing a trench epitaxial structure according to an embodiment of the present invention;
[0030] Figure 2-Figure 6 Schematic diagram of a semiconductor structure in each process step of preparing a trench epitaxial structure according to an embodiment of the present invention;
[0031] The description of the accompanying drawings is as follows:
[0032] 10 - substrate, 11 - deep trench, 21 - first epitaxial layer, 22 - second epitaxial layer, 30 - mask layer, 41 - first intrinsic silicon layer, 42 - carbon-doped silicon layer, 43 - second intrinsic silicon layer. DETAILED DESCRIPTION
[0033] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0034] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0035] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0036] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0037] The present invention provides a method for preparing a trench epitaxial structure. Figure 1 , Figure 1 1 is a flow chart of a method for preparing a trench epitaxial structure according to an embodiment of the present invention, wherein the method for preparing a trench epitaxial structure comprises:
[0038] First, perform step S1: refer to Figure 2 and Figure 3 , Figure 2 is a schematic diagram of a semiconductor structure after a first epitaxial layer and a mask layer are sequentially formed on a substrate according to an embodiment of the present application. Figure 3 This is a schematic diagram of the semiconductor structure after the deep trenches arranged in an array are formed in an embodiment of the present application. A substrate 10 is provided, on which a first epitaxial layer 21 and a mask layer 30 are sequentially formed, and deep trenches 11 arranged in an array are formed in the mask layer 30 and the partially thick first epitaxial layer 21.
[0039] The first epitaxial layer 21 is N-type doped.
[0040] In this embodiment, the mask layer 30 may also be a photoresist layer.
[0041] In other embodiments, the mask layer 30 may be a hard mask layer, such as a silicon nitride layer.
[0042] Then, execute step S2: refer to Figure 4 , Figure 4 Schematic diagram of the semiconductor structure after the second intrinsic silicon layer of the embodiment of the present application, forming a first intrinsic silicon layer 41 , which covers the sidewalls and bottom wall of the deep trench 11 .
[0043] Specifically, the first intrinsic silicon layer 41 is formed by an epitaxial process, wherein the silicon source gas involved in the reaction is SiH 2 Cl 2 , the process temperature is 500° C. to 600° C., and the process chamber pressure is 6 Torr to 20 Torr.
[0044] Preferably, the thickness of the first intrinsic silicon layer 41 is 200 angstroms to 300 angstroms.
[0045] Among them, the first intrinsic silicon layer 41 serves as a buffer layer of the device, which can not only prevent defects from the first epitaxial layer from continuing to subsequent growth to improve crystal quality, but also alleviate the stress caused by the lattice constant mismatch of the subsequently grown carbon-doped silicon layer 42, reduce dislocation defects, improve the overall structural stability, and improve interface characteristics.
[0046] Then, execute step S3: continue to refer to Figure 4 , forming a carbon-doped silicon layer 42 , wherein the carbon-doped silicon layer 42 covers the first intrinsic silicon layer 41 .
[0047] Specifically, the carbon-doped silicon layer 42 is formed by an epitaxial process, wherein the carbon source gas involved in the reaction is CH 3 SiH 3 , the process temperature is 600° C. to 700° C., and the process chamber pressure is 6 Torr to 20 Torr.
[0048] Preferably, the carbon-doped silicon layer 42 has a thickness of 350 angstroms to 500 angstroms.
[0049] Preferably, the carbon ion doping concentration in the carbon-doped silicon layer 42 is 1E19 atom / cm 3 ~4E19atom / cm 3 .
[0050] In the carbon-doped silicon layer 42, the mobile carbon atoms in the lattice interstices form immobile carbon atom clusters with the carbon atoms in the lattice positions. These immobile carbon atom clusters capture nearby atoms, forming larger atom clusters that hinder the diffusion of boron and phosphorus deeper into the silicon layer, thereby reducing the junction depth and improving device performance. Furthermore, since carbon atoms have the same number of valence electrons as silicon atoms, carbon doping does not generate additional holes or electrons like boron (trivalent) or phosphorus (pentavalent), maintaining overall electrical neutrality at the PN junction. This suppresses the mutual diffusion of boron and phosphorus and forms a clear interface.
[0051] Further, execute step S4: continue to refer to Figure 4 , forming a second intrinsic silicon layer 43 , wherein the second intrinsic silicon layer 43 covers the carbon-doped silicon layer 42 .
[0052] Specifically, the second intrinsic silicon layer 43 is formed by an epitaxial process, wherein the silicon source gas involved in the reaction is SiH 2 Cl 2 , the process temperature is 500° C. to 600° C., and the process chamber pressure is 6 Torr to 20 Torr.
[0053] Preferably, the second intrinsic silicon layer 43 has a thickness of 200 angstroms to 300 angstroms.
[0054] The second intrinsic silicon layer 43 may also serve as a buffer layer to relieve stress caused by lattice constant mismatch of the carbon-doped silicon layer 42 , reduce dislocation defects, enhance overall structural stability, and improve interface characteristics.
[0055] Next, execute step S5: refer to Figure 5 , Figure 5 Schematic diagram of the semiconductor structure after the second epitaxial layer of the embodiment of the present application, forming the second epitaxial layer 22 , which covers the second intrinsic silicon layer 43 and fills the remaining space of the deep trench 11 .
[0056] In this embodiment, the second epitaxial layer 22 is P-type doped.
[0057] The present application sequentially grows a first intrinsic silicon layer, a carbon-doped silicon layer, and a second intrinsic silicon layer in a deep trench in the first epitaxial layer, and then fills the deep trench with the second epitaxial layer, and introduces a combined film layer of the first intrinsic silicon layer, the carbon-doped silicon layer, and the second intrinsic silicon layer at the interface between the first epitaxial layer and the second epitaxial layer. This can inhibit the mutual diffusion of P-type doped ions (boron ions) and N-type doped ions (phosphorus ions) in the subsequent process heat process, so that the interface between the first epitaxial layer and the second epitaxial layer (PN interface) remains clear, thereby reducing the on-resistance of the device and improving the device performance.
[0058] Finally, execute step S6: reference Figure 6 , Figure 63 is a schematic diagram of the semiconductor structure after the mask layer is removed according to an embodiment of the present application, wherein the mask layer 30 on the surface of the first epitaxial layer 21 is removed.
[0059] In this embodiment, the mask layer 30 is removed by an ashing process.
[0060] Based on the same inventive concept, the present application also provides a trench epitaxial structure, referring to Figure 6 , the trench epitaxial structure includes:
[0061] substrate 10;
[0062] A first epitaxial layer 21, the first epitaxial layer 21 is located on the substrate 10, wherein deep trenches 11 arranged in an array are formed in a partial thickness of the first epitaxial layer 21;
[0063] a first intrinsic silicon layer 41 , wherein the first intrinsic silicon layer 41 covers the sidewalls and bottom wall of the deep trench 11 ;
[0064] a carbon-doped silicon layer 42 , wherein the carbon-doped silicon layer 42 covers the first intrinsic silicon layer 41 ;
[0065] a second intrinsic silicon layer 43 , wherein the second intrinsic silicon layer 43 covers the carbon-doped silicon layer 42 ;
[0066] A second epitaxial layer 22 covers the second intrinsic silicon layer 43 and fills a remaining space of the deep trench 11 .
[0067] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.
Claims
1. A method for preparing a trench epitaxial structure, characterized in that: include: Providing a substrate, on which a first epitaxial layer and a mask layer are sequentially formed, wherein deep trenches arranged in an array are formed in the mask layer and a portion of the thickness of the first epitaxial layer; forming a first intrinsic silicon layer, wherein the first intrinsic silicon layer covers the sidewalls and bottom wall of the deep trench; forming a carbon-doped silicon layer, wherein the carbon-doped silicon layer covers the first intrinsic silicon layer; forming a second intrinsic silicon layer, wherein the second intrinsic silicon layer covers the carbon-doped silicon layer; forming a second epitaxial layer, wherein the second epitaxial layer covers the second intrinsic silicon layer and fills a remaining space of the deep trench; The mask layer on the surface of the first epitaxial layer is removed.
2. The method for preparing a trench epitaxial structure according to claim 1, wherein: The first intrinsic silicon layer is formed by an epitaxial process, wherein the silicon source gas involved in the reaction is SiH2Cl2, the process temperature is 500°C to 600°C, and the process chamber pressure is 6Torr to 20Torr.
3. The method for preparing a trench epitaxial structure according to claim 1, wherein: The thickness of the first intrinsic silicon layer is 200 angstroms to 300 angstroms.
4. The method for preparing a trench epitaxial structure according to claim 1, wherein: The carbon-doped silicon layer is formed by an epitaxial process, wherein the carbon source gas involved in the reaction is CH3SiH3, the process temperature is 600°C to 700°C, and the process chamber pressure is 6Torr to 20Torr.
5. The method for preparing a trench epitaxial structure according to claim 1, wherein: The thickness of the carbon-doped silicon layer is 350 angstroms to 500 angstroms.
6. The method for preparing a trench epitaxial structure according to claim 1, wherein: The doping concentration of carbon ions in the carbon-doped silicon layer is 1E19atom / cm 3 ~4E19atom / cm 3 .
7. The method for preparing a trench epitaxial structure according to claim 1, wherein: The second intrinsic silicon layer is formed by an epitaxial process, wherein the silicon source gas involved in the reaction is SiH2Cl2, the process temperature is 500°C to 600°C, and the process chamber pressure is 6 Torr to 20 Torr.
8. The method for preparing a trench epitaxial structure according to claim 1, wherein: The thickness of the second intrinsic silicon layer is 200 angstroms to 300 angstroms.
9. The method for preparing a trench epitaxial structure according to claim 1, wherein: The first epitaxial layer is N-type doped; the second epitaxial layer is P-type doped.
10. A trench epitaxial structure, characterized in that: include: substrate; A first epitaxial layer, the first epitaxial layer being located on the substrate, wherein deep trenches arranged in an array are formed in a portion of the thickness of the first epitaxial layer; a first intrinsic silicon layer, wherein the first intrinsic silicon layer covers sidewalls and a bottom wall of the deep trench; a carbon-doped silicon layer, wherein the carbon-doped silicon layer covers the first intrinsic silicon layer; a second intrinsic silicon layer, wherein the second intrinsic silicon layer covers the carbon-doped silicon layer; A second epitaxial layer covers the second intrinsic silicon layer and fills a remaining space of the deep trench.