Trench gate MOS device and preparation method thereof

Abstract

The invention provides a trench gate MOS device and a preparation method thereof, the trench gate MOS device comprises a semiconductor structure, a body region, a source region, a first trench structure, a second trench structure, a source electrode, a gate electrode and a drain electrode, the semiconductor structure comprises a buffer layer and a drift region which are stacked; the body region is located on the upper surface of the drift region; the source region is located on the upper surface of the body region; the first groove structure comprises a first groove, a gate dielectric layer covering the bottom surface and the inner wall of the first groove, and a first conductive layer filling the first groove; the second groove structure comprises a second groove, a dielectric layer and a second conductive layer, the second groove penetrates through the first conductive layer, the gate dielectric layer and the drift region, the dielectric layer covers the inner wall and the bottom surface of the second groove, and the second conductive layer fills the second groove; the source electrode is electrically connected with the source region and the second conductive layer, the grid electrode is electrically connected with the first conductive layer, and the drain electrode is electrically connected with the buffer layer. By arranging the second groove structure, the power density of the device is improved while the on resistance of the device is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a trench gate MOS device and a preparation method thereof. Background Art

[0002] With the development of technology, the power density of SiC MOS (Silicon Carbide Metal-Oxide Semiconductor Field Effect Transistor) has been gradually improved, and the device area has been gradually reduced. At present, most of the approaches are to reduce the on-resistance of the device by increasing the channel density of SiC MOS, while increasing the power density of the device. Figure 1 and Figure 2 The figures show schematic cross-sectional structures of one trench-gate SiC MOS device and another trench-gate SiC MOS device, respectively, including a semiconductor structure 01, a substrate 011, a drift region 012, a body region 013, a source region 014, a source contact region 015, a gate protection region 017, a gate trench 02, a gate dielectric layer 021, a gate polysilicon layer 023, an interlayer dielectric layer 03, a source 04, and a drain 05. However, as the device voltage increases, the resistance of the drift region excluding the channel also increases, resulting in an increase in the on-resistance of the device.

[0003] In order to improve the withstand voltage of the device while reducing the on-resistance of the device, some researchers have proposed super junction structure SiC MOS, such as Figure 3 Figure 2 shows a schematic cross-sectional structure of a third type of trench-gate SiC MOS device, including a semiconductor structure 01, a substrate 011, a drift region 012, a body region 013, a source region 014, a P-pillar 016, a gate protection region 017, a gate trench 02, a gate dielectric layer 021, a gate polysilicon layer 022, an interlayer dielectric layer 03, a source 04, and a drain 05. However, multiple epitaxial growths and high-temperature ion implantations are required to form the P-pillars, resulting in a complex manufacturing process, large process fluctuations, high costs, and a long production cycle. Furthermore, the defect density in the device increases, which in turn reduces the device yield and increases the reliability risk. Furthermore, due to the limitations of the trench gates between the P-pillars, the size of the device cell is difficult to reduce, which is not conducive to reducing the on-resistance of the device. Some researchers have proposed increasing the density of the front conductive channel and combining it with the gate oxide layer electric field protection technology to form a trench gate SiC MOS. This method achieves a high-density channel by increasing the density of the trench gate to reduce the device on-resistance Ron. While this structure increases the trench density, it is necessary to add a P-type layer at the bottom of the trench to prevent damage from the high electric field. Due to the setting of the P-type layer, a JFET (junction field effect transistor) region is introduced into the device, which increases the conductive channel density while increasing the JFET resistance. Some researchers have also proposed using a deeper pseudo-trench gate to achieve the injection of the P-type layer, such as Figure 4Figure 1 is a schematic diagram of the cross-sectional structure of a third type of trench-gate SiC MOS device, including a semiconductor structure 01, a substrate 011, a drift region 012, a body region 013, a source region 014, a P-type implant region 018, a gate trench 02, a gate dielectric layer 021, a gate polysilicon layer 022, a dummy gate trench 023, a dummy gate polysilicon layer 024, an interlayer dielectric layer 03, a source 04, and a drain 05. However, since the real trench gate is separated by the dummy trench gate, it is difficult to significantly increase the channel density, and thus it is also difficult to significantly reduce the on-resistance Ron of the device.

[0004] Therefore, there is an urgent need to find a trench gate MOS device that can improve the power density of the device while significantly reducing the on-resistance of the device. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a trench gate MOS device and a method for manufacturing the same, so as to solve the problem in the prior art that it is difficult to significantly reduce the on-resistance of the device while improving the power density of the MOS device.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a trench gate MOS device, comprising:

[0007] A semiconductor structure comprising a first conductive type buffer layer and a first conductive type drift region stacked in sequence;

[0008] A second conductive type body region located on an upper surface layer of the drift region;

[0009] A first conductive type source region is located on the upper surface of the body region,

[0010] a first trench structure comprising a first trench, a gate dielectric layer and a first conductive layer, wherein the first trench penetrates the source region and the body region, the gate dielectric layer covers the bottom surface and inner wall of the first trench, and the first conductive layer fills the first trench;

[0011] at least one second trench structure, comprising a second trench, a dielectric layer, and a second conductive layer, wherein the second trench penetrates the first conductive layer, the gate dielectric layer, and the drift region, with the buffer layer exposed on the bottom surface, the dielectric layer covers the inner wall and bottom surface of the second trench, and the second conductive layer fills the second trench;

[0012] A source electrode, a gate electrode and a drain electrode, wherein the source electrode is electrically connected to the source region and the second conductive layer, the gate electrode is electrically connected to the first conductive layer, and the drain electrode is electrically connected to the buffer layer.

[0013] Optionally, the material of the semiconductor structure includes silicon carbide.

[0014] Optionally, the upper surface layer of the body region is further provided with a second conductive type source contact region electrically connected to the source.

[0015] Optionally, a second conductive type protection zone is further provided at the bottom of the first trench, located in the drift region and wrapping the bottom of the first trench. The protection zone is spaced a preset distance from the bottom surface of the body region, and the second trench passes through the protection zone.

[0016] Optionally, a second conductive type doped region is further provided in the drift region, and the doped region wraps a sidewall of the second trench located in the drift region.

[0017] Optionally, the thickness of the dielectric layer covering the bottom of the second trench is greater than twice the thickness of the dielectric layer covering the inner wall of the second trench.

[0018] Optionally, the first conductive layer includes first conductive type polysilicon; and the second conductive layer includes second conductive type polysilicon.

[0019] Optionally, the second conductive layer is polysilicon of the second conductive type, and the doping concentration of the second conductive layer is not greater than 1×10 17 cm -3 .

[0020] Optionally, the trench gate MOS device is further provided with an interlayer dielectric layer covering the semiconductor structure, the first trench structure and the second trench structure, and the source and the gate both penetrate the interlayer dielectric layer.

[0021] The present invention also provides a method for preparing a trench gate MOS device, comprising the following steps:

[0022] A semiconductor structure is provided, comprising a first conductive type buffer layer and a first conductive type drift region stacked in sequence, and a second conductive type body region formed on an upper surface layer of the drift region;

[0023] forming a first conductive type source region on an upper surface layer of the body region, and forming a first trench penetrating the source region and the body region;

[0024] forming a gate dielectric layer covering the inner wall and bottom surface of the first trench, and forming a first conductive layer filling the first trench;

[0025] forming at least one second trench penetrating the first conductive layer, the gate dielectric layer, and the drift region and with the buffer layer exposed at the bottom, and sequentially forming a dielectric layer covering the inner wall and bottom of the second trench and a second conductive layer filling the second trench, wherein the first trench, the remaining gate dielectric layer, and the first conductive layer constitute a first trench structure, and the second trench, the dielectric layer, and the second conductive layer constitute a second trench structure;

[0026] A source electrode electrically connected to the source region and the second conductive layer is formed, a gate electrode electrically connected to the first conductive layer is formed, and a drain electrode electrically connected to the buffer layer is formed.

[0027] Optionally, after forming the second trench and before forming the gate dielectric layer, the method further includes forming a second conductive type protection zone at the bottom of the first trench.

[0028] Optionally, after forming the second trench and before forming the dielectric layer, the method further includes forming a second conductive type doping region wrapping the sidewall of the second trench located in the drift region.

[0029] As described above, the trench-gate MOS device and its fabrication method of the present invention improve the device structure by providing a second trench structure in the device that penetrates the first conductive layer, the gate dielectric layer, and the drift region. The second conductive layer of the second conductivity type in the second trench structure is then electrically connected to the source electrode. A charge balancing structure is formed between the second conductive layer and the drift region of the device, thereby optimizing the electric field distribution in the drift region and achieving a near-uniform electric field distribution in the drift region. This significantly reduces the on-resistance of the device and improves its power density. By utilizing the uniform electric field distribution in the drift region, the structure can improve the device's withstand voltage capability by adjusting the thickness of the drift region, ensuring the device's withstand voltage capability while also enabling a smaller cell structure. Furthermore, the process for forming the second trench structure is simple, the manufacturing cost is relatively low, and the defect density in the device is not increased, thereby relatively improving the device's yield and reliability, thus having high industrial application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Shown is a schematic diagram of the cross-sectional structure of a trench gate MOS device.

[0031] Figure 2 Shown is a schematic cross-sectional structure diagram of another trench gate MOS device.

[0032] Figure 3 Shown is a schematic cross-sectional structure diagram of a third type of trench gate MOS device.

[0033] Figure 4Shown is a schematic cross-sectional structure diagram of a fourth trench gate MOS device.

[0034] Figure 5 Shown is a schematic cross-sectional structure diagram of the trench gate MOS device of the present invention.

[0035] Figure 6 Shown is another cross-sectional structural schematic diagram of the trench gate MOS device of the present invention.

[0036] Figure 7 Display as Figure 2 and Figure 5 The vertical downward electric field intensity variation curve of the AA section of the trench gate MOS device.

[0037] Figure 8 Display as Figure 3 and Figure 5 The vertical downward electric field intensity variation curve of the AA section of the trench gate MOS device.

[0038] Figure 9 Shown is a process flow chart of a method for preparing a trench gate MOS device according to the present invention.

[0039] Figure 10 It is a schematic diagram showing the cross-sectional structure of the trench gate MOS device manufacturing method after forming the body region of the present invention.

[0040] Figure 11 It is a schematic diagram showing the cross-sectional structure of the trench gate MOS device manufacturing method after forming the source region of the present invention.

[0041] Figure 12 It is a schematic diagram showing the cross-sectional structure after forming the first trench in the method for manufacturing the trench gate MOS device of the present invention.

[0042] Figure 13 It is a schematic diagram showing the cross-sectional structure of the trench gate MOS device manufacturing method after forming the protection zone according to the present invention.

[0043] Figure 14 It is a schematic diagram showing the cross-sectional structure of the trench gate MOS device manufacturing method of the present invention after the gate dielectric layer is formed.

[0044] Figure 15 It is a schematic diagram showing the cross-sectional structure of the trench gate MOS device manufacturing method of the present invention after forming the first conductive layer.

[0045] Figure 16 It is a schematic diagram showing the cross-sectional structure of the trench gate MOS device manufacturing method after forming the second trench of the present invention.

[0046] Figure 17It is a schematic diagram showing the cross-sectional structure of the trench gate MOS device manufacturing method after forming the doping region of the present invention.

[0047] Figure 18 It is a schematic diagram showing a cross-sectional structure after forming a dielectric layer in the method for preparing a trench gate MOS device of the present invention.

[0048] Figure 19 Another schematic cross-sectional structure diagram of the manufacturing method of the trench gate MOS device of the present invention after forming the dielectric layer is shown.

[0049] Figure 20 It shows a schematic cross-sectional structure diagram of the manufacturing method of the trench gate MOS device of the present invention after forming the second conductive layer.

[0050] Figure 21 Another schematic cross-sectional structure diagram of the manufacturing method of the trench gate MOS device of the present invention after forming the second conductive layer is shown.

[0051] Explanation of Figure Numbers

[0052] 01 Semiconductor Structure

[0053] 011 Substrate

[0054] 012 Drift Zone

[0055] 013 Body Area

[0056] 014 Source Area

[0057] 015 Source contact area

[0058] 016 P column

[0059] 017 Gate protection zone

[0060] 018 P-type injection region

[0061] 02 Gate Trench

[0062] 021 Gate dielectric layer

[0063] 022 Gate polysilicon layer

[0064] 023 False Gate Trench

[0065] 024 dummy gate polysilicon layer

[0066] 03 Interlayer dielectric layer

[0067] 04 Source

[0068] 05 Drain

[0069] 1 Semiconductor structure

[0070] 11 Buffer layer

[0071] 12 Drift Zone

[0072] 13 body zones

[0073] 14 Source area

[0074] 15 protected areas

[0075] 16 Doping region

[0076] 2 First trench structure

[0077] 21 First Groove

[0078] 22 Gate dielectric layer

[0079] 23 first conductive layer

[0080] 3 Second trench structure

[0081] 31 Second groove

[0082] 32 dielectric layer

[0083] 33 second conductive layer

[0084] 4 Source

[0085] 5 Drain DETAILED DESCRIPTION

[0086] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0087] See also Figures 5 to 21 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0088] Example 1

[0089] This embodiment provides a trench gate MOS device, such as Figure 5 and Figure 6As shown, there are schematic cross-sectional structures of a trench gate MOS device and another schematic cross-sectional structure of the trench gate MOS device, respectively, including a semiconductor structure 1, a second conductive type body region 13, a first conductive type source region 14, a first trench structure 2, at least one second trench structure 3, a source 4, a gate (not shown) and a drain 5, wherein the semiconductor structure 1 includes a first conductive type buffer layer 11 and a first conductive type drift region 12 stacked in sequence; the body region 13 is located on the upper surface layer of the drift region 12; the source region 14 is located on the upper surface layer of the body region 13; the first trench structure 2 includes a first trench 21, a gate dielectric layer 22 and a first conductive layer 23, the first trench 21 passes through the source region 14 and the body region 13, the gate dielectric layer 22 covers the bottom surface and inner wall of the first trench 21, and the first conductive layer 23 fills the first trench 21; the second trench structure 3 includes a second trench 31, a dielectric layer 32 and a second conductive layer 33, the second trench 31 passes through the first conductive layer 23, the gate dielectric layer 22 and the drift region 12, and the bottom surface exposes the buffer layer 11, the dielectric layer 32 covers the inner wall and bottom surface of the second trench 31, and the second conductive layer 33 fills the second trench 31; the source 4 is electrically connected to the source region 14 and the second conductive layer 33, the gate is electrically connected to the first conductive layer 23, and the drain 5 is electrically connected to the buffer layer 11.

[0090] Specifically, the first conductivity type includes one of N-type or P-type, the second conductivity type includes one of N-type or P-type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0091] Specifically, while ensuring device performance, the size, thickness, and shape of the semiconductor structure 1 can be selected based on actual conditions and are not limited here. The size, thickness, and shape of the buffer layer 11 can also be selected based on actual conditions and are not limited here. The size, thickness, and shape of the drift region 12 can also be selected based on actual conditions and are not limited here. In this embodiment, the buffer layer 11 serves as the substrate that forms the drift region 12.

[0092] As an example, the material of the semiconductor structure 1 includes silicon carbide or other suitable semiconductor materials. For example, the material of the semiconductor structure 1 can be silicon or silicon germanium. In this embodiment, the material of the semiconductor structure 1 is silicon carbide.

[0093] Specifically, the doping concentration of the drift region 12 is lower than the doping concentration of the buffer layer 11, and the electrical contact type between the buffer layer 11 and the drain 5 is ohmic contact. While ensuring the performance of the device, the doping concentration of the buffer layer 11 can be selected according to actual conditions and is no longer restricted here; the doping concentration of the drift region 12 can be selected according to actual conditions and is no longer restricted here.

[0094] Specifically, while ensuring device performance, the thickness and doping concentration of the body region 13 can be selected according to actual conditions and are not limited here.

[0095] Specifically, the electrical contact type between the source region 14 and the source electrode 4 is ohmic contact. While ensuring device performance, the size, thickness and doping concentration of the source region 14 can be selected according to actual conditions and are not limited here.

[0096] As an example, the upper surface layer of the body region 13 is further provided with a second conductive type source contact region (not shown) electrically connected to the source 4 .

[0097] Specifically, the type of electrical contact between the source contact region and the source 4 is ohmic contact. While ensuring device performance, the size, thickness and doping concentration of the source contact region can be selected according to actual conditions and are not limited here.

[0098] Specifically, the bottom surface of the first trench 21 is not lower than the bottom surface of the junction region between the body region 13 and the drift region 12. While ensuring device performance, the opening shape and opening size of the first trench 21 can be selected according to actual conditions and are no longer restricted here.

[0099] Specifically, the gate dielectric layer 22 is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0100] Specifically, while ensuring device performance, the thickness of the gate dielectric layer 22 can be selected according to actual conditions and is not limited here.

[0101] As an example, the first conductive layer 23 includes first conductive type polysilicon or other suitable conductive materials. In this embodiment, first conductive type polysilicon is used as the first conductive layer 23, that is, the first conductive layer 23 is N-type polysilicon.

[0102] Specifically, the first conductive layer 23 is polysilicon of the first conductive type, and an ohmic contact is formed between the portion of the first conductive layer 23 that contacts the gate and the gate.

[0103] Specifically, the second trench 31 is spaced a preset distance from the bottom surface of the buffer layer 11. While ensuring device performance and the second trench 31 passing through the first conductive layer 23, the gate dielectric layer 22 and the drift region 12, the opening size and opening shape of the second trench 31 can be selected according to actual conditions and are no longer restricted here; the distance between the bottom surface of the second trench 31 and the bottom surface of the buffer layer 11 can be selected according to actual conditions and is no longer restricted here.

[0104] As an example, the thickness of the dielectric layer 32 covering the bottom of the second trench 31 is greater than twice the thickness of the dielectric layer 32 covering the inner wall of the second trench 31 .

[0105] Specifically, while ensuring device performance, the thickness of the dielectric layer 32 covering the inner wall of the second trench 31 can be selected according to actual conditions and is not limited here.

[0106] Specifically, the dielectric layer 32 is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0107] As an example, the second conductive layer 33 includes second conductive type polysilicon or other suitable conductive materials. In this embodiment, the second conductive type polysilicon is used as the second conductive layer 33, that is, the second conductive layer 33 is P-type polysilicon.

[0108] As an example, the second conductive layer 33 is polysilicon of the second conductive type, and the doping concentration of the second conductive layer 23 is not greater than 1×10 17 cm -3 .

[0109] Specifically, the second conductive layer 33 is a second conductive type polysilicon, and the portion of the second conductive layer 33 in contact with the source 4 forms an ohmic contact with the source 4. When the second conductive layer 33 is a second conductive type polysilicon, the second conductive layer 33 can act as a charge provider and form a charge balance structure in the horizontal direction with the drift region 12 outside the second trench structure 3.

[0110] Specifically, the dielectric layer 32 covers the first conductive layer 23 exposed on the inner wall of the second trench 31 and also covers the exposed upper surface of the first conductive layer 23 .

[0111] Specifically, the material of the dielectric layer 32 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. In this embodiment, the gate dielectric layer 22 and the dielectric layer 32 are made of the same material.

[0112] As an example, a second conductive type protection zone 15 is provided at the bottom of the first trench 21 , which is located in the drift region 12 and wraps the bottom of the first trench 21 . The protection zone 15 is spaced a preset distance from the bottom surface of the body region 13 , and the second trench 31 passes through the protection zone 15 .

[0113] Specifically, the doping concentration of the protection zone 15 is not lower than the doping concentration of the body region 13, and the protection zone 15 is used to protect the first trench structure 2 to avoid premature breakdown at the bottom of the first trench structure 2. While ensuring device performance, the size, thickness, shape and doping concentration of the protection zone 15 can be selected according to actual conditions and are no longer restricted here.

[0114] As an example, a second conductive type doping region 16 is further provided in the drift region 12 , and the doping region 16 wraps the sidewalls of the second trench 31 in the drift region 12 .

[0115] Specifically, when the protection area 15 is provided at the bottom of the first trench structure 2 , the doping area 16 is connected to the protection area 15 .

[0116] Specifically, by setting the doping region 16 that wraps the second trench structure 3 exposed in the drift region 12 in the device, the second conductive layer 33 of the second conductive type in the second trench structure 3 and the doping region 16 together constitute a charge balance structure, so that the electric field of the device in the direction from the source 4 to the drain 5 is stabilized.

[0117] As an example, the trench gate MOS device is further provided with an interlayer dielectric layer (not shown) covering the semiconductor structure 1, the first trench structure 2 and the second trench structure 3, and the source 4 and the gate both penetrate the interlayer dielectric layer.

[0118] Specifically, the material of the interlayer dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

[0119] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer can be selected according to actual conditions and is not limited here.

[0120] Specifically, the interlayer dielectric layer is further provided with a source contact hole and a gate contact hole that penetrate the interlayer dielectric layer. The bottom surface of the gate contact hole exposes the first conductive layer 23, and the bottom surface of the source contact hole exposes at least the second conductive layer 33 and the source region 14. When the source contact region is provided in the device, the bottom surface of the source contact hole also exposes the source contact region.

[0121] Specifically, while ensuring device performance, the opening size and opening shape of the source contact hole can be selected according to actual conditions and are no longer restricted here; the opening size and opening shape of the gate contact hole can be selected according to actual conditions and are no longer restricted here.

[0122] Specifically, the source electrode 4 fills the source contact hole so that the source electrode 4 is electrically connected to the source region 14 and the second conductive layer 33, the gate fills the gate contact hole so that the gate is electrically connected to the first conductive layer 23, and the drain electrode 5 covers the bottom surface of the buffer layer 11 so that the drain electrode 5 is electrically connected to the buffer layer 11.

[0123] Specifically, the material of the source electrode 4 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum or other suitable conductive materials; the material of the gate includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum or other suitable conductive materials; the material of the drain includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum or other suitable conductive materials.

[0124] Specifically, such as Figure 7 and Figure 8 As shown, they are Figure 2 and Figure 5 The vertical downward electric field variation curve of the device in the AA section and Figure 3 and Figure 5 The electric field variation curve of the device in the vertical direction of the AA section (the depth in the figure refers to the distance from the source), compared with the device in the figure, Figure 5 The bottom surface of the second trench 31 in the second trench structure 3 of the device is flush with the bottom surface of the drift region 12. Figure 2 、 Figure 3 and Figure 5 The relevant parameters (doping concentration, size, thickness, etc.) of the same part of the device in the figure are the same. It can be seen from the figure that the longitudinal direction of the AA section refers to the direction from the source of the device to the drain of the device. Figure 3 The electric field intensity of the device in the middle shows a steep increase (large slope) and then a slow decrease (small absolute value of the slope). Figure 2 The electric field intensity in the device first increases sharply, then shows obvious fluctuations in the drift region corresponding to the P column, and then drops sharply when approaching the drain of the device. Figure 5The electric field strength of the device first increases sharply, then the electric field strength in the drift region 12 remains almost unchanged (reaching near the bottom of the second trench structure 3), and finally drops sharply near the drain (the absolute value of the slope is large), indicating that through the setting of the second trench structure 3, a charge balance structure is formed in the drift region 12 of the device, and then the electric field strength in the drift region 12 is close to an idealized uniform distribution.

[0125] Specifically, by setting the second trench structure 3 in the device, the second conductive layer 33 electrically connected to the source 4 and the drift region 12 form a charge balance structure in the lateral direction, so that the electric field of the drift region 12 is stable and close to an idealized uniform distribution, greatly reducing the on-resistance of the device. At the same time, this structure can improve the voltage resistance of the device by adjusting the thickness of the drift region 12, thereby ensuring the voltage resistance of the device.

[0126] Specifically, by setting the second trench structure 33 that passes through the first conductive layer 23, the gate dielectric layer 22 and the drift region 12, and utilizing this simple and compact structure, a smaller cellular structure can be achieved. At the same time, the reduction in the size of the cellular structure can further reduce the on-resistance of the front channel of the device, thereby improving the power density of the device.

[0127] The trench-gate MOS device of this embodiment improves the device structure by providing a second trench 31 that penetrates the first conductive layer 23, the gate dielectric layer 22, and the drift region 12. Furthermore, a dielectric layer 32 covers the inner wall and bottom of the second trench 31, and a second conductive layer 33 fills the second trench 31 and is electrically connected to the source 4. The second conductive layer 33 and the drift region 12 form a charge-balancing structure, which allows the electric field in the drift region 12 to approach an idealized uniform distribution, thereby significantly reducing the device's on-resistance and improving its power density. Due to the charge-balancing structure between the second conductive layer 33 and the drift region 12, the device's on-resistance is reduced. This structure can also improve the device's withstand voltage capability by adjusting the thickness of the drift region 12, ensuring the device's withstand voltage capability. Furthermore, the compact structure achieved by providing the second trench structure enables a smaller cell structure, further reducing the device's on-resistance and improving its power density.

[0128] Example 2

[0129] This embodiment provides a method for preparing a trench gate MOS device, such as Figure 9 FIG. 1 is a process flow chart of a method for preparing a trench gate MOS device, comprising the following steps:

[0130] S1: providing a semiconductor structure, the semiconductor structure comprising a first conductive type buffer layer and a first conductive type drift region stacked in sequence, and forming a second conductive type body region on an upper surface layer of the drift region;

[0131] S2: forming a first conductive type source region on an upper surface layer of the body region, and forming a first trench penetrating the source region and the body region;

[0132] S3: forming a gate dielectric layer covering the inner wall and bottom surface of the first trench, and forming a first conductive layer filling the first trench;

[0133] S4: forming at least one second trench penetrating the first conductive layer, the gate dielectric layer, and the drift region, with the buffer layer exposed on the bottom surface, and sequentially forming a dielectric layer covering the inner wall and bottom surface of the second trench and a second conductive layer filling the second trench, wherein the first trench, the remaining gate dielectric layer, and the first conductive layer constitute a first trench structure, and the second trench, the dielectric layer, and the second conductive layer constitute a second trench structure;

[0134] S5: forming a source electrode electrically connected to the source region and the second conductive layer, forming a gate electrode electrically connected to the first conductive layer, and forming a drain electrode electrically connected to the buffer layer.

[0135] See also Figures 10 to 15 , perform step S1, step S2 and step S3: provide a semiconductor structure 1, the semiconductor structure 1 includes a first conductive type buffer layer 11 and a first conductive type drift region 12 stacked in sequence, and form a second conductive type body region 13 on the upper surface layer of the drift region 12; form a first conductive type source region 14 on the upper surface layer of the body region 13, and form a first trench 21 passing through the source region 14 and the body region 13; form a gate dielectric layer 22 covering the inner wall and bottom surface of the first trench 21, and form a first conductive layer 23 filling the first trench 21.

[0136] Specifically, such as Figure 10 , which is a schematic diagram of the cross-sectional structure after the body region 13 is formed. The method of forming the body region 13 includes ion implantation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0137] Specifically, when the body region 13 is formed by a deposition process, the body region 13 is formed on the upper surface of the drift region 12 .

[0138] Specifically, such as Figure 11 , which is a schematic diagram of the cross-sectional structure after the source region 14 is formed. The method of forming the source region 14 includes ion implantation or other suitable methods.

[0139] Specifically, such as Figure 12 , is a schematic diagram of the cross-sectional structure after the first groove 21 is formed. The method of forming the first groove 21 includes dry etching, wet etching or other suitable methods.

[0140] As an example, after forming the second trench 21 and before forming the gate dielectric layer 22 , the method further includes forming a second conductive type protection zone 15 at the bottom of the first trench 21 .

[0141] Specifically, such as Figure 13 , which is a schematic diagram of the cross-sectional structure after the protection zone 15 is formed. The method of forming the protection zone 15 includes ion implantation or other suitable methods.

[0142] Specifically, such as Figure 14 , which is a schematic diagram of a cross-sectional structure after the gate dielectric layer 22 is formed. The method of forming the gate dielectric layer 22 includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0143] Specifically, such as Figure 15 , which is a schematic diagram of the cross-sectional structure after the first conductive layer 23 is formed. The method of forming the first conductive layer 23 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0144] Specifically, the material of the first conductive layer 23 includes first conductive type polysilicon or other suitable conductive materials.

[0145] Specifically, after forming the first conductive layer 23 and before forming the second trench 31, the step of removing the first conductive layer 23 located above the body region 13 and the source region 14 is also included, and after removing the first conductive layer 23 located above the body region 13 and the source region 14, the upper surface of the remaining first conductive layer 23 is flush with the upper surface of the body region 13.

[0146] Specifically, a method for removing the first conductive layer 23 located above the body region 13 and the source region 14 includes chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0147] See also Figures 16 to 21, perform step S4 and step S5: form at least one second trench 31 that penetrates the first conductive layer 23, the gate dielectric layer 22 and the drift region 12 and exposes the buffer layer 11 on the bottom surface, and sequentially form a dielectric layer 32 covering the inner wall and bottom surface of the second trench 31 and a second conductive layer 33 filling the second trench 31, the first trench 21 and the remaining gate dielectric layer 22 and the first conductive layer 23 constitute a first trench structure 2, and the second trench 31, the dielectric layer 32 and the second conductive layer 33 constitute a second trench structure 3; form a source electrode 4 electrically connected to the source region 14 and the second conductive layer 32, form a gate electrically connected to the first conductive layer 23, and form a drain electrode 5 electrically connected to the buffer layer 11.

[0148] Specifically, such as Figure 16 , which is a schematic diagram of the cross-sectional structure after the second trench 31 is formed. The method of forming the second trench 31 includes dry etching, wet etching or other suitable methods.

[0149] As an example, after forming the second trench 31 and before forming the dielectric layer 32 , the step of forming a second conductive type doping region 16 wrapping the sidewall of the second trench 31 in the drift region 12 is further included.

[0150] Specifically, such as Figure 17 , which is a schematic diagram of the cross-sectional structure after the doping region 16 is formed. The method of forming the second doping region 16 includes ion implantation or other suitable methods.

[0151] Specifically, such as Figure 18 and Figure 19 The figures show a schematic diagram of a cross-sectional structure after forming the dielectric layer 32 and another schematic diagram of a cross-sectional structure after forming the dielectric layer 32. The method of forming the dielectric layer 32 includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0152] Specifically, such as Figure 20 and Figure 21 The figures show a schematic diagram of a cross-sectional structure after forming the second conductive layer 33 and another schematic diagram of a cross-sectional structure after forming the second conductive layer 33. The method of forming the second conductive layer 33 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0153] Specifically, the material of the second conductive layer 33 includes second conductivity type polysilicon or other suitable conductive materials.

[0154] Specifically, after forming the second conductive layer 33 and before forming the source 4, the step of removing the second conductive layer 33 located above the body region 13, the source region 14 and the first trench structure 2 is also included, and after removing the second conductive layer 33 located above the body region 13, the source region 14 and the first trench structure 2, the upper surface of the remaining second conductive layer 33 is flush with the upper surface of the body region 13.

[0155] Specifically, a method for removing the second conductive layer 33 located above the body region 13 , the source region 14 and the first trench structure 2 includes chemical mechanical polishing, dry etching, wet etching or other suitable methods.

[0156] Specifically, after forming the second conductive layer 33 and before forming the source electrode 4 , the method further includes forming an interlayer dielectric layer covering the body region 13 , the source region 14 , the first trench structure 2 and the second trench structure 3 .

[0157] Specifically, the method of forming the interlayer dielectric layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0158] Specifically, after forming the interlayer dielectric layer and before forming the source 4, the step of forming a source contact hole and a gate contact hole is also included. The source contact hole penetrates the interlayer dielectric layer and the bottom surface exposes the source region 14 and the second conductive layer 33. The gate contact hole penetrates the interlayer dielectric layer and the bottom surface exposes the first conductive layer 23. When the source contact region is formed on the upper surface of the body region 13, the bottom surface of the source contact hole also exposes the source contact region.

[0159] Specifically, the method of forming the source contact hole includes dry etching, wet etching or other suitable methods; the method of forming the gate contact hole includes dry etching, wet etching or other suitable methods.

[0160] Specifically, the source electrode 4 fills the source contact hole, the gate electrode fills the gate contact hole, and the drain electrode 5 covers the bottom surface of the buffer layer 11 .

[0161] Specifically, the method of forming the source 4 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method of forming the gate includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method of forming the drain 5 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0162] Specifically, after forming the first conductive layer 23 and before forming the source 4, the second trench 31 is formed to penetrate the first conductive layer 23, the gate dielectric layer 22 and the drift region 12, and then the dielectric layer 32 covering the inner wall and bottom of the second trench 31 and the second conductive layer 33 filling the second trench 33 are formed. The second conductive layer 33 is electrically connected to the source 4 to form a charge balance structure between the second conductive layer 33 of the second conductive type and the drift region 12 of the first conductive type, thereby optimizing the electric field distribution in the drift region 12, reducing the on-resistance of the device, and improving the power density of the device.

[0163] Specifically, by forming the second trench structure that passes through the first conductive layer 23, the gate dielectric layer 22 and the drift region 12, the on-resistance of the device is reduced while only the steps of forming the second trench 31, the dielectric layer 32 and the second conductive layer 33 of the second conductive type that fills the second trench 31 need to be added. No complicated process steps are required, the production cost is relatively low, and the defect density in the device will not increase, thereby relatively improving the yield and reliability of the device.

[0164] The preparation method of the trench gate MOS device of this embodiment improves the manufacturing process of the device. After forming the first conductive layer 23 of the first conductive type, the second trench structure 3 is formed. A charge balance structure is formed between the second conductive layer 33 electrically connected to the source 4 in the second trench structure 3 and the drift region 12 of the first conductive type. Through a simple process, the on-resistance of the device is reduced, the power density of the device is improved, and the manufacturing cost is relatively low. It will not increase the defect density in the device, and the yield and reliability of the device are relatively improved.

[0165] In summary, the trench gate MOS device and its preparation method of the present invention improve the structure of the device, set up a second trench structure that penetrates the first conductive layer, the gate dielectric layer and the drift region, and use the second conductive layer electrically connected to the source in the second trench structure to form a charge balance structure with the drift region of the device, thereby optimizing the electric field distribution in the drift region, making the electric field in the drift region uniformly distributed, thereby reducing the on-resistance of the device and improving the power density of the device. In addition, the structure can improve the voltage resistance of the device by adjusting the thickness of the drift region, ensuring the voltage resistance of the device, and at the same time realizing a smaller cell structure. In addition, the process of forming the second trench structure is simple, the manufacturing cost is relatively low, and the defect density in the device will not increase, thereby relatively improving the yield and reliability of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0166] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A trench gate MOS device, characterized in that: include: A semiconductor structure comprising a first conductive type buffer layer and a first conductive type drift region stacked in sequence; A second conductive type body region located on an upper surface layer of the drift region; A first conductive type source region is located on the upper surface of the body region, a first trench structure comprising a first trench, a gate dielectric layer and a first conductive layer, wherein the first trench penetrates the source region and the body region, the gate dielectric layer covers the bottom surface and inner wall of the first trench, and the first conductive layer fills the first trench; At least one second trench structure, comprising a second trench, a dielectric layer and a second conductive layer, wherein the second trench penetrates the first conductive layer, the gate dielectric layer and the drift region and the bottom surface exposes the buffer layer, and the dielectric layer covers the an inner wall and a bottom surface of the second trench, wherein the second conductive layer fills the second trench; A source electrode, a gate electrode and a drain electrode, wherein the source electrode is electrically connected to the source region and the second conductive layer, the gate electrode is electrically connected to the first conductive layer, and the drain electrode is electrically connected to the buffer layer.

2. The trench gate MOS device according to claim 1, wherein: The material of the semiconductor structure includes silicon carbide.

3. The trench gate MOS device according to claim 1, wherein: The upper surface layer of the body region is further provided with a second conductive type source contact region electrically connected to the source.

4. The trench gate MOS device according to claim 1, wherein: A second conductive type protection zone is further provided at the bottom of the first trench, which is located in the drift region and wraps the bottom of the first trench. The protection zone is spaced a preset distance from the bottom surface of the body region, and the second trench passes through the protection zone.

5. The trench gate MOS device according to claim 1, wherein: A second conductive type doping region is further provided in the drift region, and the doping region wraps the sidewall of the second trench located in the drift region.

6. The trench gate MOS device according to claim 1, wherein: The thickness of the dielectric layer covering the bottom of the second trench is greater than twice the thickness of the dielectric layer covering the inner wall of the second trench.

7. The trench gate MOS device according to claim 1, wherein: The first conductive layer includes first conductive type polysilicon; the second conductive layer includes second conductive type polysilicon.

8. The trench gate MOS device according to claim 1, wherein: The second conductive layer is polysilicon of the second conductive type, and the doping concentration of the second conductive layer is not greater than 1×10 17 cm -3 .

9. The trench gate MOS device according to claim 1, wherein: The trench gate MOS device is further provided with an interlayer dielectric layer covering the semiconductor structure, the first trench structure and the second trench structure, and the source and the gate both penetrate the interlayer dielectric layer.

10. A method for preparing a trench gate MOS device, characterized in that: The following steps are involved: A semiconductor structure is provided, comprising a first conductive type buffer layer and a first conductive type drift region stacked in sequence, and a second conductive type body region formed on an upper surface layer of the drift region; forming a first conductive type source region on an upper surface layer of the body region, and forming a first trench penetrating the source region and the body region; forming a gate dielectric layer covering the inner wall and bottom surface of the first trench, and forming a first conductive layer filling the first trench; forming at least one second trench penetrating the first conductive layer, the gate dielectric layer, and the drift region and with the buffer layer exposed at the bottom, and sequentially forming a dielectric layer covering the inner wall and bottom of the second trench and a second conductive layer filling the second trench, wherein the first trench, the remaining gate dielectric layer, and the first conductive layer constitute a first trench structure, and the second trench, the dielectric layer, and the second conductive layer constitute a second trench structure; A source electrode electrically connected to the source region and the second conductive layer is formed, a gate electrode electrically connected to the first conductive layer is formed, and a drain electrode electrically connected to the buffer layer is formed.

11. The method for preparing a trench gate MOS device according to claim 1, wherein: After forming the second trench and before forming the gate dielectric layer, the method further includes forming a second conductive type protection zone at the bottom of the first trench.

12. The method for preparing a trench gate MOS device according to claim 1, wherein: After forming the second trench and before forming the dielectric layer, the method further includes forming a second conductive type doping region wrapping the sidewall of the second trench located in the drift region.

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