Semiconductor structure and preparation method of semiconductor structure

Abstract

The invention discloses a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a first chip, a second chip, a first bonding layer and a power management die. The first chip has a first 3D capacitor structure therein. The second chip has a second 3D capacitor structure therein. The first bonding layer bonds the first chip and the second chip. The power management die is bonded to the second chip. The power management die is electrically connected to the first 3D capacitor structure and the second 3D capacitor structure through an interconnect extending along a thickness of the semiconductor structure and across the first bonding layer.

Description

Technical Field

[0001] The present application relates to a semiconductor structure, and more particularly to a semiconductor structure having a power management integrated circuit stacked on a silicon capacitor layer. Background Art

[0002] In electronic devices, different components and modules often require different voltages to operate. Therefore, electronic devices need to convert input voltages, such as battery voltage or USB power supply voltage, into different voltage rails to meet the needs of various components and modules. To facilitate power management, electronic devices often use power management integrated circuits (PMICs) to perform voltage conversion and provide the multiple voltages required by the system.

[0003] The voltage conversion circuits in PMICs typically require passive components such as capacitors to store energy. The quality and quantity of these passive components significantly impact the power efficiency of the conversion process. However, due to the large area occupied by passive components, space-constrained electronic devices may face a trade-off between area and power efficiency. Traditionally, the PMIC and capacitors are typically placed on the same substrate and connected via conductive traces within the substrate. In this case, the conductive path between the PMIC and capacitor can be quite long and may cross different material interfaces, resulting in poor signal and power integrity. Therefore, improving voltage conversion efficiency remains an unresolved issue. Summary of the Invention

[0004] One aspect of the present application provides a semiconductor structure. The semiconductor structure includes a first chip, a second chip, a first bonding layer, and a power management die. The first chip has a first 3D capacitor structure, and the second chip has a second 3D capacitor structure. The first bonding layer bonds the first chip to the second chip. The power management die is bonded to the second chip. The power management die is electrically connected to the first and second 3D capacitor structures via interconnects extending along the thickness of the semiconductor structure and across the first bonding layer.

[0005] Another aspect of the present application provides a semiconductor device. The semiconductor device includes a printed circuit board (PCB), a substrate, a system-on-chip (SoC), and the aforementioned semiconductor structure. The substrate is disposed on the PCB, and the SoC is disposed on a first surface of the substrate. The semiconductor structure is coupled to the SoC.

[0006] Another aspect of the present application provides a method for fabricating a semiconductor structure. The method includes forming a bond between a first wafer having a plurality of first 3D capacitor structures and a second wafer having a plurality of second 3D capacitor structures to bond the first wafer to the second wafer; bonding a plurality of power management dies onto the second wafer; and performing a dicing process to form the semiconductor structure, which includes a first chip, a second chip, a first bonding layer, a power management die from the power management dies, a first 3D capacitor structure from the first chip, and a second 3D capacitor structure from the second chip. The power management die is electrically connected to the first and second 3D capacitor structures via interconnects extending along the thickness of the semiconductor structure and across the first bonding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] A more comprehensive understanding of the present disclosure can be obtained by referring to the embodiments and the accompanying drawings, in which like reference numerals in the drawings represent like components.

[0008] Figure 1 A semiconductor structure according to an embodiment of the present application is shown.

[0009] Figure 2 An embodiment of the present invention is shown for preparing Figure 1 A flow chart of a method for fabricating a semiconductor structure is shown.

[0010] Figures 3A to 3K An embodiment of the present invention is shown for preparing Figure 1 A cross-sectional or side view of one or more stages of a semiconductor structure is shown.

[0011] Figure 4 A semiconductor structure according to an embodiment of the present application is shown.

[0012] Figures 5A to 5H An embodiment of the present invention is shown for preparing Figure 4 A cross-sectional or side view of one or more stages of a semiconductor structure is shown.

[0013] Figure 6 A semiconductor structure according to an embodiment of the present application is shown.

[0014] Figures 7A to 7H An embodiment of the present invention is shown for preparing Figure 6 A cross-sectional or side view of one or more stages of a semiconductor structure is shown.

[0015] Figure 8 A semiconductor structure according to an embodiment of the present application is shown.

[0016] Figures 9A to 9D According to an embodiment of the present application, a method for preparing Figure 8 A cross-sectional view of one or more stages of a semiconductor structure is shown.

[0017] Figures 10A to 10E An embodiment of the present invention is shown for preparing Figure 6 A cross-sectional view of one or more stages of a semiconductor structure is shown.

[0018] Figure 11 A semiconductor structure according to an embodiment of the present application is shown.

[0019] Figures 12A to 12K An embodiment of the present invention is shown for preparing Figure 11 A cross-sectional view of one or more stages of a semiconductor structure is shown.

[0020] Figure 13 A semiconductor structure according to an embodiment of the present application is shown.

[0021] Figures 14A to 14H An embodiment of the present invention is shown for preparing Figure 13 A cross-sectional view of one or more stages of a semiconductor structure is shown.

[0022] Figures 15A to 15E An embodiment of the present invention is shown for preparing Figure 13 A cross-sectional view of one or more stages of a semiconductor structure is shown.

[0023] Figure 16 A semiconductor structure according to an embodiment of the present application is shown.

[0024] Figures 17A to 17E An embodiment of the present invention is shown for preparing Figure 16 A cross-sectional view of one or more stages of a semiconductor structure is shown.

[0025] Figures 18 to 22 FIG. 1 depicts a semiconductor device according to various embodiments of the present disclosure.

[0026] Figure 23 A cross-sectional view of a 3D capacitor structure according to some embodiments of the present disclosure is shown.

[0027] Figure 24 A cross-sectional view of a 3D capacitor structure according to some embodiments of the present disclosure is shown.

[0028] Figure 25A A top view of a rectangular array of 3D capacitor cells according to some embodiments of the present disclosure is shown.

[0029] Figure 25BA top view of a hexagonal array of 3D capacitor cells according to some embodiments of the present disclosure is shown.

[0030] Symbol Marking Description

[0031] 100, 200, 300, 400, 500, 600, 700, 900: semiconductor structures

[0032] 110,120: Chip

[0033] 110a, 120a: first surface of the chip

[0034] 110b, 120b: second surface of the chip

[0035] 112,122:Semiconductor layer

[0036] 112a: first surface of the semiconductor layer

[0037] 112b: second surface of the semiconductor layer

[0038] 114,124: Dielectric layer

[0039] 114a, 124a: Interconnection structure

[0040] 116,126:Through hole

[0041] 118,128:RDL

[0042] 117: passivation layer

[0043] 119: conductive bump

[0044] 130: Power management chip

[0045] 132: semiconductor layer

[0046] 134: Dielectric layer

[0047] 141a, 141b, 151a, 151b: bonding dielectric layer

[0048] 142a, 142b, 152a, 152b: Bonding pads

[0049] 140a, 140b, 150a, 150b: sub-bonding layer

[0050] 140,150:Joint layer

[0051] C1, C2, C3, C4: 3D capacitor structure DETAILED DESCRIPTION

[0052] The following descriptions accompanying the drawings are incorporated into and constitute a part of this specification, and they describe embodiments of the present application, but the present application is not limited to these embodiments. In addition, the following embodiments can be combined in an appropriate manner to complete another embodiment.

[0053] The phrases "one embodiment," "exemplary embodiment," "other embodiments," and "another embodiment" used herein mean that one or more embodiments of the present disclosure described herein may include a particular feature, structure, or characteristic, but not every embodiment is required to include the particular feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, although it may.

[0054] In order to make the present invention fully understood, detailed steps and structures are provided below. Obviously, the implementation of the present application does not constitute a limitation on the specific details known to those skilled in the art. In addition, known structures and steps will not be described in detail again to avoid unnecessary limitations on the present application. The preferred embodiments of the present application will be described in detail below. However, in addition to the detailed description herein, the present application can also be widely implemented in other embodiments. The scope of the present application is not limited to the embodiments herein, but is limited by the scope of the claims.

[0055] Figure 1 A semiconductor structure according to one embodiment of the present disclosure is shown. Semiconductor structure 100 includes chip 110, chip 120, a power management die 130, and a bonding layer 140. Bonding layer 140 bonds chip 110 to chip 120, and power management die 130 to chip 120. In this embodiment, semiconductor structure 100 further includes bonding layer 150, through which power management die 130 is bonded to chip 120.

[0056] In some embodiments, chip 110 and chip 120 may be capacitor chips, each including at least one 3D capacitor structure formed therein. For example, chip 110 includes at least one 3D capacitor structure C1, and chip 120 includes at least one 3D capacitor structure C2. In some embodiments, chip 110 and chip 120 may be identical or have a similar layout. Thus, 3D capacitor structure C1 may be aligned with 3D capacitor structure C2. In some embodiments, 3D capacitor structure C1 and 3D capacitor structure C2 are vertically aligned. In some embodiments, when viewed from above the semiconductor structure 100, 3D capacitor structure C1 and 3D capacitor structure C2 overlap. However, the present application is not limited thereto.

[0057] The power management die 130 may be a logic die including a power management integrated circuit (PMIC). The PMIC may be used to convert the supply voltage to different voltage rails required by various components in the system. In this embodiment, the power management die 130 may be coupled to capacitors in the chip 110 and the chip 120, such as the 3D capacitor structures C1 and C2, for voltage conversion. In this case, the power management die 130 is connected to the semiconductor structure 100 at least through the thickness direction (e.g., Figure 1 The power management die 130 is electrically connected to the 3D capacitor structure C1 and the 3D capacitor structure C2 via interconnects extending in the direction indicated by the arrows. That is, the stacked structure of chips 110, 120, and power management die 130 allows power management die 130 to be coupled to the 3D capacitor structure C1 formed in chip 110 via conductive paths spanning bonding layers 140 and 150, and to the 3D capacitor structure C2 formed in chip 120 via conductive paths spanning bonding layers 150. In this way, power management die 130 can be coupled to the capacitors provided by chips 110 and 120 using a smaller area and shorter wiring distances, thereby improving power efficiency, signal integrity, and power integrity.

[0058] like Figure 1 As shown, the chip 110 may include a semiconductor layer 112, a dielectric layer 114, at least one through-hole 116, and a redistribution layer (RDL) 118. In some embodiments, the semiconductor layer 112 may include a semiconductor material, such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the semiconductor layer 112 may be a wafer substrate. In some embodiments, the semiconductor layer 112 is a silicon substrate. In some embodiments, the semiconductor layer 112 includes a first surface 112a and a second surface 112b opposite to the first surface 112a. The first surface 112a is adjacent to the dielectric layer 114, and the second surface 112b is farther away from the dielectric layer 114. In some embodiments, the through-hole 116 extends from the first surface 112a through the semiconductor layer 112 to the second surface 112b. In some embodiments, the semiconductor layer 112 is a silicon substrate, and the through-hole 116 is a through silicon via (TSV).

[0059] A dielectric layer 114 is disposed above the semiconductor layer 112. In some embodiments, the dielectric layer 114 is disposed on the first surface 112a of the semiconductor layer 112. In some embodiments, the dielectric layer 114 comprises a dielectric material such as silicon oxide, silicon nitride, a polymer, or the like. In some embodiments, the dielectric layer 114 comprises multiple dielectric layers stacked one on top of the other. In some embodiments, the multiple dielectric layers may comprise the same material or different materials. In some embodiments, the dielectric layer 114 is an interlayer dielectric (ILD).

[0060] In some embodiments, at least one interconnect structure 114a and at least one 3D capacitor structure C1 may be formed in the dielectric layer 114. In some embodiments, the interconnect structure 114a is an electrical line in the chip 110. For example, the interconnect structure 114a may include laterally extending metal wires at different heights and vertically extending metal vias for connecting the metal wires at different heights. In some embodiments, the interconnect structure 114a may be formed in a back-end-of-line (BEOL) process.

[0061] like Figure 1 As shown, the chip 110 further includes a plurality of conductive bumps 119. The conductive bumps 119 may be solder balls or copper pillars coupled to the interconnect structure 114a formed in the dielectric layer 114, and may be used for external connection of the semiconductor structure 100. In some embodiments, the conductive bumps 119 may include a conductive material such as copper, tin, silver, lead, alloys thereof, or the like.

[0062] Chip 110 has a first surface 110a and a second surface 110b opposite to the first surface 110a. In some embodiments, the first surface 110a is adjacent to the dielectric layer 114 and is referred to as the front side of chip 110, while the second surface 110b is adjacent to the semiconductor layer 112 having the through hole 116 and is referred to as the back side of chip 110.

[0063] like Figure 1 As shown, the conductive bumps 119 are disposed on the first surface 110a. In addition, the bonding layer 140 can contact the RDL 118 located on the second surface 110b of the chip 110. In some embodiments, the bonding layer 140 can be formed by bonding a sub-bonding layer 140a and a sub-bonding layer 140b.

[0064] The sub-bonding layer 140a includes a bonding dielectric layer 141a and at least one bonding pad 142a. In some embodiments, the bonding pad 142a is surrounded by the bonding dielectric layer 141a and is at least partially exposed from the bonding dielectric layer 141a. In some embodiments, in order to connect the through hole 116 in the semiconductor layer 112 to the first bonding pad 142a in the sub-bonding layer 140a, an RDL 118 can be disposed above the semiconductor layer 112 and coupled to the through hole 116 and the bonding pad 142a. Figure 1 Only one metal layer is shown in the RDL 118, but the present application is not limited thereto. In other embodiments, the RDL 118 may include more metal layers, wherein an interlayer dielectric layer is formed to separate different metal layers.

[0065] In some embodiments, bonding pad 142a extends through bonding dielectric layer 141a to electrically connect to a metal trace in RDL 118. Thus, bonding pad 142a can be electrically connected to first 3D capacitor structure C1 through RDL 118, via 116, and interconnect structure 114a. In some embodiments, bonding pad 142a comprises a conductive material, such as copper, silver, or the like.

[0066] In some embodiments, the chip 120 may have a similar structure to the chip 110. For example, the chip 120 includes a dielectric layer 124, a semiconductor layer 122 located above the dielectric layer 124, at least one through-hole 126 extending through the semiconductor layer 122, and an RDL 128 located above the semiconductor layer 122. Figure 1 As shown, the chip 120 has a first surface 120a and a second surface 120b opposite to the first surface 120a. In some embodiments, the first surface 120a may be the front side of the chip 120, and the second surface 120b may be the back side of the chip 120. However, unlike the chip 110 having the conductive bumps 119 disposed on the first surface 110a, the sub-bonding layer 140b may be disposed on the first surface 120a of the chip 120. The sub-bonding layer 140b includes a bonding dielectric layer 141b and at least one bonding pad 142b. In some embodiments, the bonding pad 142b is surrounded by the bonding dielectric layer 141b and is at least partially exposed from the bonding dielectric layer 141b. In some embodiments, the bonding pad 142b extends through the bonding dielectric layer 141b to be electrically connected to the interconnect structure 124a formed in the dielectric layer 124.

[0067] In some embodiments, sub-bonding layer 140a and sub-bonding layer 140b can be bonded together using a hybrid bonding process to form bonding layer 140. In some embodiments, bonding pad 142a can be aligned with bonding pad 142b to facilitate the hybrid bonding process. In the hybrid bonding process, initial bonding occurs at the dielectric-to-dielectric interface at room temperature under atmospheric conditions. Annealing and metal diffusion then form a copper metal-to-metal connection.

[0068] In this manner, chip 110 can be bonded to chip 120 to form a stacked structure. Similarly, a hybrid bonding process can be performed to bond PMIC die 130 to chip 120. For example, bonding layer 150 can be formed by bonding sub-bonding layer 150a disposed on chip 120 and sub-bonding layer 150b disposed on power management die 130.

[0069] In some embodiments, a sub-bonding layer 150 a may be formed on the RDL 128 on the semiconductor layer 122 . The sub-bonding layer 150 a includes a bonding dielectric layer 151 a and at least one bonding pad 152 a . The bonding pad 152 a extends through the bonding dielectric layer 151 a to electrically connect to the metal wire in the RDL 128 .

[0070] Sub-bonding layer 150b is disposed above power management die 130 and includes a bonding dielectric layer 151b and at least one bonding pad 152b. In some embodiments, bonding pad 152b can be aligned with bonding pad 152a so that bonding pad 152b can be bonded to bonding pad 152a after a hybrid bonding process. In this way, voltage conversion circuitry (not shown) formed in semiconductor layer 132 and dielectric layer 134 in power management die 130 can be coupled to 3D capacitor structure C2 in chip 120 via bonding layer 150, RDL 128, via 126, and interconnect structure 124a. Furthermore, sub-bonding layer 150b can be coupled to 3D capacitor structure C1 in chip 110 via bonding layer 150, RDL 128, via 126, interconnect structure 124a, bonding layer 140, RDL 118, via 116, and interconnect structure 114a.

[0071] Since the power management die 130 can penetrate the semiconductor structure 100 along the thickness direction (ie, along Figure 1 Interconnects extending in the stacking direction (as indicated by the arrows) are coupled to the 3D capacitor structures C1 and C2. This shortens the wiring distance between the power management die 130 and the capacitors, thereby improving signal integrity and power integrity. Furthermore, the stacking structure of chips 110 and 120 allows more capacitors to be integrated into a smaller area, increasing capacitance density and thus improving the power efficiency of the power management die 130.

[0072] In some embodiments, the 3D capacitor structure C1 can be a 3D metal insulator metal (MIM) capacitor, and this out-of-plane dimension can be advantageously used to increase the effective MIM area and the associated capacitance density. In some embodiments, the 3D capacitor structure C1 of the present application can have a very high density, for example, greater than about 1 μF / mm 2 In some embodiments, the 3D capacitor structure may be a cylindrical capacitor.

[0073] like Figure 23 As shown, in some embodiments, each 3D capacitor structure C1 includes a metal bottom plate 908, a metal top plate 910 located above the metal bottom plate 908, and a plurality of 3D capacitor units 912 formed between the metal bottom plate 908 and the metal top plate 910. In some embodiments, a distance D1 between the metal bottom plate 908 and the metal top plate 910 is in a range from about 1 μm to about 2 μm, which is much thinner than active or passive devices formed in deep trenches.

[0074] The configuration of the 3D capacitor unit 912 may have a crown type capacitor structure or a concave type capacitor structure. Figure 23 As shown, in an embodiment where each 3D capacitor cell 912 is formed in a crown shape, the 3D capacitor cell 912 includes a first conductive film 914 and a second conductive film 916 stacked between a metal bottom plate 908 and a metal top plate 910. In some embodiments, the first conductive film 914 includes a first portion 914A connected to the metal bottom plate 908 and a second portion 914B connected to the first portion 914A and extending from the metal bottom plate 908 toward the metal top plate 910. In some embodiments, the second conductive film 916 is disposed adjacent to the first conductive film 914, connected to the metal top plate 910, and extending from the metal top plate 910 toward the metal bottom plate 908. In some embodiments, the second conductive film 916 and the second portion 914B of the first conductive film 914 are perpendicularly interlaced. For example, as shown in the cross-sectional view, the second conductive film 916 is located adjacent to the inner and outer sides of the receiving space 904. The receiving space 904 is surrounded by the first conductive film 914. In some embodiments, the second portion 914B is cylindrical, and the 3D capacitor structure C1 may be a cylindrical capacitor.

[0075] Furthermore, the 3D capacitor unit 912 further includes a first insulating film 928 for isolating the first conductive film 914 from the second conductive film 916. In other words, the MIM characteristics of the 3D capacitor structure C1 are achieved by the stacking of the first conductive film 914, the first insulating film 928, and the second conductive film 916. Figure 23As shown, in some embodiments, a second insulating film 930 may be optionally used to fill the space between the second conductive film 916 and the metal top plate 910. In some embodiments, the first insulating film 928 and the second insulating film 930 are composed of a high-k dielectric layer material. For example, the high-k dielectric layer material may include at least one of lanthanum, hafnium, and zirconium oxides.

[0076] The configuration of the 3D capacitor unit 912 may have a crown type capacitor structure or a concave type capacitor structure. Figure 23 As shown, in an embodiment where each 3D capacitor cell 912 is formed in a crown shape, the 3D capacitor cell 912 includes a first conductive film 914 and a second conductive film 916 stacked between a metal bottom plate 908 and a metal top plate 910. In some embodiments, the first conductive film 914 includes a first portion 914A connected to the metal bottom plate 908 and a second portion 914B connected to the first portion 914A and extending from the metal bottom plate 908 toward the metal top plate 910. In some embodiments, the second conductive film 916 is disposed adjacent to the first conductive film 914, connected to the metal top plate 910, and extending from the metal top plate 910 toward the metal bottom plate 908. In some embodiments, the second conductive film 916 and the second portion 914B of the first conductive film 914 are perpendicularly interlaced. For example, as shown in the cross-sectional view, the second conductive film 916 is located adjacent to the inner and outer sides of the receiving space 904. The receiving space 904 is surrounded by the first conductive film 914. In some embodiments, the second portion 914B is cylindrical, and the 3D capacitor structure C1 may be a cylindrical capacitor.

[0077] Furthermore, the 3D capacitor unit 912 further includes a first insulating film 928 for isolating the first conductive film 914 from the second conductive film 916. In other words, the MIM characteristics of the 3D capacitor structure C1 are achieved by the stacking of the first conductive film 914, the first insulating film 928, and the second conductive film 916. Figure 23 As shown, in some embodiments, a second insulating film 930 may be optionally used to fill the space between the second conductive film 916 and the metal top plate 910. In some embodiments, the first insulating film 928 and the second insulating film 930 are composed of a high-k dielectric layer material. For example, the high-k dielectric layer material may include at least one of lanthanum, hafnium, and zirconium oxides.

[0078] like Figure 24As shown, in other embodiments, the 3D capacitor unit 912 is concave, and the 3D capacitor unit 912 also includes a first conductive film 914 and a second conductive film 916 stacked between the metal bottom plate 908 and the metal top plate 910. In this embodiment, the second conductive film 916 is also formed adjacent to the first conductive film 914, connected to the metal top plate 910, and extends from the metal top plate 910 toward the metal bottom plate 908. Figure 23 In the crown-shaped capacitor unit 912 of each concave type, the second conductor film 916 is laterally surrounded by the second portion 914B of the first conductor film 914 , rather than being completely adjacent to the inner and outer sides of the accommodation space 904 enclosed by the first conductor film 914 .

[0079] Figure 25A and 25B The top view of FIG. 1 shows a plurality of 3D capacitor units 912 (concave) according to some embodiments of the present application. Figure 25A As shown, in some embodiments, when the capacitor is viewed from above, multiple metal plates (i.e., Figure 23 The 3D capacitor units 912 are arranged in a rectangular array between the metal bottom plate 908 and the metal top plate 910 as shown. Alternatively, in other embodiments, as shown in FIG. Figure 25B As shown, in the capacitor from the top view direction, these 3D capacitor units 912 can be arranged into a hexagonal array between multiple metal plates. Generally speaking, the arrangement of the hexagonal array can provide a higher density of 3D capacitor units 912. The arrangement of the 3D capacitor units 912 in the present application is not limited to the embodiment Figure 25A and Figure 25B As shown, the 3D capacitor cells 912 can be arranged into any symmetrical shape as desired.

[0080] In some embodiments, by using the 3D capacitor structures C1 and C2 of the 3D capacitor unit 912, the capacitance density of the chip 110 and the chip 120 can be greater than 1 μF / mm 2 By stacking chip 110 and chip 120, the capacitance density of semiconductor structure 100 can even be doubled. In some embodiments, in order to further improve the power efficiency of power management die 130, a larger number of capacitor chips can be stacked in semiconductor structure 100. For example, in some embodiments, when two capacitor chips are stacked, the capacitance density can reach 5μF / mm 2 , and the power efficiency can be as high as 85%. In addition, in some embodiments, when six capacitor chips are stacked, the capacitance density can reach 15μF / mm 2 , and power efficiency can be as high as 90%, and so on.

[0081] Figure 2An embodiment of the present invention is shown for preparing Figure 1 The method M1 of the semiconductor structure 100 is shown as a flow chart. The method M1 includes steps S110 to S160, but is not limited to Figure 2 The order of proceeding is shown. Figures 3A to 3K An embodiment of the present invention is shown for preparing Figure 1 A cross-sectional view of one or more stages of method M1 of semiconductor structure 100 is shown.

[0082] In steps S110 and S120, a wafer 10 and a wafer 20 are received. In some embodiments, a plurality of first chips 110 are formed on the wafer 10, and a plurality of second chips 120 are formed on the wafer 20. Figure 3A As shown, the wafer 10 includes a dielectric layer 114 and a semiconductor layer 112 located above the dielectric layer 114. The 3D capacitor structure C1 and the interconnect structure 114a are formed in the dielectric layer 114. In some embodiments, the wafer 20 and the wafer 10 may be identical to each other. However, the present application is not limited thereto. Figure 3B As shown, the wafer 20 includes a dielectric layer 124 and a semiconductor layer 122 located above the dielectric layer 124 . The 3D capacitor structure C2 and the interconnect structure 124 a are formed in the dielectric layer 124 .

[0083] In step S130, a bond is formed between wafer 10 and wafer 20. In some embodiments, a sub-bonding layer 140a (e.g., Figure 3C As shown), a sub-bonding layer 140b is formed on the wafer 20 (as shown Figure 3D As shown), the sub-bonding layer 140a and the sub-bonding layer 140b (as shown) are then bonded together. Figure 3E As shown) bonding is performed, thereby forming a bond between wafer 10 and wafer 20.

[0084] In some embodiments, as Figure 3C As shown, a via last (VL) approach can be used to form a through hole 116 in the semiconductor layer 112. In this case, the semiconductor layer 112 can be thinned before forming the sub-bonding layer 140a to form the through hole 116 extending through the semiconductor layer 112. In some embodiments, to provide support strength when forming the through hole 116, a carrier CR1 can be attached to the dielectric layer 114 in advance (i.e., before forming the through hole 116). In some embodiments, the carrier CR1 can be a glass carrier and can be attached to the dielectric layer 114 via a removable adhesive layer (not shown) (e.g., by heat or laser). After forming the through hole 116, an RDL 118 can be formed over the upper semiconductor layer 112 and the through hole 116, and then the sub-bonding layer 140a can be formed on the RDL 118.

[0085] For the wafer 20, the sub-bonding layer 140b may be formed on the dielectric layer 124, such as Figure 3D In this case, since the semiconductor layer 122 may be a part of a wafer or substrate, which can provide support strength for forming the sub-bonding layer 140 b , a carrier may not be required when forming the sub-bonding layer 140 b .

[0086] After forming the sub-bonding layer 140a and the sub-bonding layer 140b, a hybrid bonding process may be performed in step S130 to bond the sub-bonding layer 140a and the sub-bonding layer 140b to form the bonding layer 140, thereby completing the bonding of the wafer 10 and the wafer 20 (e.g., Figure 3E shown).

[0087] In step S140, the power management wafer 30 is received, such as Figure 3F In some embodiments, a plurality of power management dies 130 may be formed on the power management wafer 30. Furthermore, in step S150, the power management dies 130 are bonded onto the wafer 20 by bonding the power management wafer 30 to the wafer 20. In other words, the power management dies 130 may be stacked on the second chip 120 using a wafer-on-wafer (WoW) method.

[0088] In some embodiments, in order to bond the power management wafer 30 to the wafer 20, a sub-bonding layer 150a can be first formed above the wafer 20 and a sub-bonding layer 150b can be formed above the power management wafer 30, and then the two sub-bonding layers 150a and 150b are bonded together through a hybrid bonding process to form a bonding layer 150 for bonding the wafer 20 and the power management wafer 30.

[0089] like Figure 3G As shown, before forming the sub-bonding layer 150a, a through-hole 126 may be formed in the semiconductor layer 122, and an RDL 128 may be formed on the through-hole 126 and the semiconductor layer 122. In some embodiments, to form through-holes 126 that extend through the semiconductor layer 122 and have smaller pitches and dimensions, the semiconductor layer 122 may be thinned by grinding before forming the through-holes 126. After forming the RDL 128, the sub-bonding layer 150a may be formed on the RDL 128.

[0090] Furthermore, if Figure 3H As shown, the sub-bonding layer 150b is formed on the dielectric layer 134 of the power management wafer 30. Then, the sub-bonding layer 150a can be bonded to the sub-bonding layer 150b; in this way, the power management wafer 30 can be bonded to the top of the wafer 20, as shown in FIG. Figure 3I shown.

[0091] In addition, if Figure 3IAs shown, after the power management wafer 30 is bonded to the wafer 20, the carrier CR1 can be removed from the dielectric layer 114 of the wafer 10, and an opening 114b can be formed on the surface of the dielectric layer 114, and then a conductive bump 119 can be formed on the dielectric layer 114 and coupled to the interconnect structure 114a formed in the dielectric layer 114, as shown in FIG. Figure 3J However, the present application is not limited thereto. In some embodiments, another passivation layer may be formed on the dielectric layer 114 to facilitate the formation of the conductive bump 119 thereon.

[0092] In step S160, a dicing process may be performed to cut the stacked structure of wafer 10, wafer 20 and power management wafer 30, such as Figure 3K As shown, the semiconductor structure 100 can be singulated from the stacked wafer. In this case, the edge of the power management die 130 can be aligned with the edge of the chip 110 and the edge of the chip 120. In some embodiments, the wafer 10 can be attached to a dicing tape DP1, and the dicing blade B1 can cut the stacked structure from the surface of the power management wafer 30. However, the present application is not limited to this. In other embodiments, the back side of the power management wafer 30 can be attached to the dicing tape DP1, and the dicing blade B1 can cut the stacked structure from the surface of the wafer 10.

[0093] In the semiconductor structure 100, the chip 110 and the chip 120 are stacked with the back side of the chip 110 facing the front side of the chip 120 (i.e., in a front-to-back manner). That is, the semiconductor layer 112 of the chip 110 is adjacent to the dielectric layer 124 of the chip 120. However, the present application is not limited thereto.

[0094] Figure 4 A semiconductor structure 200 according to another embodiment of the present disclosure is shown. The semiconductor structure 200 has a similar structure to the semiconductor structure 100. However, the difference between the semiconductor structures 100 and 200 is that, in the semiconductor structure 200, the chip 110 and the chip 120 are stacked with the front side of the chip 110 facing the back side of the chip 120. That is, the dielectric layer 114 of the chip 110 is adjacent to the semiconductor layer 122 of the chip 120.

[0095] In some embodiments, the method M1 may also be used to manufacture the semiconductor structure 200. However, the order of performing steps S110 to S160 may be different. Figure 2 Different than shown. Figures 5A to 5H A cross-sectional view is shown of one or more stages of a method M1 for fabricating a semiconductor structure 200 according to one embodiment of the present disclosure.

[0096] like Figure 5A and 5BAs shown, steps S120 and S140 may be performed to receive the wafer 20 and the power management wafer 30. Step S150 may be performed to bond the power management wafer 30 to the wafer 20. In some embodiments, a sub-bonding layer 150a (e.g., Figure 5C As shown), a sub-bonding layer 150b is formed on the dielectric layer 134 of the power management wafer 30 (as shown Figure 5D As shown), the sub-bonding layer 150a and the sub-bonding layer 150b are bonded together (as shown Figure 5E As shown) to form a bonding layer 150 bonding the power management wafer 30 and the wafer 20.

[0097] Furthermore, if Figure 5E As shown, after bonding the power management wafer 30 to the wafer 20, the semiconductor layer 122 may be polished and thinned to form a through hole 126. An RDL 128 may be formed on the through hole 126 and the semiconductor layer 122, and a sub-bonding layer 140b may be formed on the RDL 128.

[0098] Perform steps S110 and S130. Figure 5F As shown, step S110 is performed to receive the wafer 10. In some embodiments, in order to form a bond between the wafer 10 and the wafer 20, a sub-bonding layer 140a may be further formed on the dielectric layer 114 of the wafer 10, as shown in FIG. Figure 5F As shown. In this way, step S130 can be performed by bonding the sub-bonding layer 140a to the sub-bonding layer 140b, as shown. Figure 5G As shown, a stack structure including wafer 10, wafer 20 and power management wafer 30 can be formed. Afterwards, semiconductor layer 112 can be polished to be thinned, through-holes 116 can be formed in semiconductor layer 112, RDL 118 can be formed on semiconductor layer 112 and through-holes 116, and conductive bumps 119 and passivation layer 117 can be formed on RDL 118, as shown. Figure 5H In step S160 , a die sawing process may be performed to cut the stacked wafers, thereby singulating the semiconductor structures 200 .

[0099] In the semiconductor structure 200, the chip 110 and the chip 120 are stacked with the front side of the chip 110 facing the back side of the chip 120. That is, the dielectric layer 114 of the first chip 110 may be adjacent to the semiconductor layer 122 of the chip 120. However, the present application is not limited thereto. In other embodiments, the chip 110 and the chip 120 may be stacked front-to-front or back-to-back.

[0100] Figure 6A semiconductor structure 300 according to another embodiment of the present disclosure is shown. The semiconductor structure 300 has a similar structure to the semiconductor structure 100. However, the difference between the semiconductor structure 100 and the semiconductor structure 300 is that in the semiconductor structure 300, the chip 110 and the chip 120 are stacked with the front side of the chip 110 facing the front side of the chip 120. That is, the dielectric layer 114 of the chip 110 is adjacent to the dielectric layer 124 of the chip 120.

[0101] In some embodiments, the semiconductor structure 300 may also be fabricated using method M1 . Figures 7A to 7H A cross-sectional view is shown illustrating one or more stages of a method M1 for fabricating a semiconductor structure 300 according to one embodiment of the present disclosure.

[0102] like Figure 7A As shown in FIG7B , steps S110 and S120 may be performed to receive wafer 11 and wafer 21 . In some embodiments, wafer 11 and wafer 21 may be similar to wafer 10 and wafer 20 . However, in wafer 11 and wafer 21 , vias 116 and 126 are formed in a via middle (VM) manner. That is, vias 116 and 126 may be formed after the front end of line (FEOL) process and before the back end of line (BEOL) process. Therefore, before the stacking process, vias 116 and 126 have already been formed in the semiconductor layers 112 and 122 of wafer 11 and wafer 21 , respectively.

[0103] Step S130 is performed to form a bond between wafer 11 and wafer 21. In some embodiments, in order to form the bonding layer 140, a sub-bonding layer 140a may be formed on the dielectric layer 114 of wafer 11 (eg, Figure 7C As shown), the sub-bonding layer 140b can be formed on the dielectric layer 124 of the wafer 21 (as shown Figure 7D ). Thereafter, a hybrid bonding process may be performed to bond the sub-bonding layer 140a and the sub-bonding layer 140b to form the bonding layer 140, as shown. Figure 7E In this case, wafer 11 and wafer 21 are stacked in a front-to-front manner, and the bonding layer 140 can contact the dielectric layer 114 and the dielectric layer 124 .

[0104] In addition, if Figure 7E As shown, after wafers 11 and 21 are bonded, semiconductor layer 122 may be polished to expose through-holes 126 formed in semiconductor layer 122 , and RDL 128 may be formed on through-holes 126 and semiconductor layer 122 . Sub-bonding layer 150 a may be formed on RDL 128 .

[0105] Step S140 is performed to receive the power management wafer 30, such as Figure 7FFurthermore, in order to facilitate the bonding between the power management wafer 30 and the wafer 21, a sub-bonding layer 150b may be further formed on the dielectric layer 134 of the power management wafer 30, as shown. Figure 7F shown.

[0106] Step S150 is performed to bond the power management wafer 30 including a plurality of power management chips 130 onto the wafer 21. Figure 7G As shown. In this way, a stack structure including wafer 11, wafer 21 and power management wafer 30 can be formed. Afterwards, the semiconductor layer 112 of wafer 11 is ground to expose the through hole 116, and RDL 118 is formed on the through hole 116 and semiconductor layer 112, and conductive bumps 119 and passivation layer 117 are formed on the RDL 118, as shown. Figure 7H In step S160 , a die sawing process may be performed to saw the stacked wafers to singulate the semiconductor structures 300 .

[0107] Although the semiconductor structures 100 , 200 , and 300 each include two capacitor chips, the present application is not limited thereto. In some embodiments, more capacitor chips may be stacked in the semiconductor structure to further improve the power efficiency of the voltage conversion performed by the PMIC.

[0108] Figure 8 A semiconductor structure 400 according to another embodiment of the present application is shown. The semiconductor structure 400 has a similar structure to the semiconductor structure 300. However, the difference between the semiconductor structure 300 and the semiconductor structure 400 is that the semiconductor structure 400 includes more stacked chips. Figure 8 As shown, in addition to the chip 110 and the chip 120 , the semiconductor structure 400 further includes chips 160 and 170 .

[0109] In some embodiments, chips 110, 120, 160, and 170 may have the same structure. For example, chip 160 includes a dielectric layer 164 and a semiconductor layer 162 located above dielectric layer 164. Furthermore, dielectric layer 164 includes at least one 3D capacitor structure C3 and at least one interconnect structure 164a. Similarly, chip 170 includes a dielectric layer 174 and a semiconductor layer 172 located above dielectric layer 174. Furthermore, dielectric layer 174 includes at least one 3D capacitor structure C4 and at least one interconnect structure 174a.

[0110] Furthermore, chip 120 can be bonded to chip 160 using a bonding layer 150 formed by bonding a sub-bonding layer 150a formed on chip 120 to a sub-bonding layer 150b formed on chip 160. Chip 160 can be bonded to chip 170 using a bonding layer 180 formed by bonding a sub-bonding layer 180a formed on chip 160 to a sub-bonding layer 180b formed on chip 170. In addition, chip 170 can be bonded to power management die 130 using a bonding layer 190 formed by bonding a sub-bonding layer 190a formed on chip 160 to a sub-bonding layer 190b formed on power management die 130. It is worth noting that in semiconductor structure 400, different chips can be stacked in a front-to-front manner or in a back-to-back manner. For example, chip 110 and chip 120 can be bonded in a front-to-front manner, and chip 120 and chip 160 can be bonded in a back-to-back manner. That is, first dielectric layer 114 of chip 110 may be adjacent to dielectric layer 124 of chip 120, and semiconductor layer 122 of chip 120 may be adjacent to semiconductor layer 162 of chip 160. In some embodiments, capacitor chips may be stacked front-to-back, front-to-front, or back-to-back as desired.

[0111] In some embodiments, the semiconductor structure 400 may be fabricated by repeating certain steps in the method M1 . 9A to 9D A cross-sectional view is shown illustrating one or more stages of a method M1 for fabricating a semiconductor structure 400 according to one embodiment of the present disclosure.

[0112] like Figure 9A As shown, steps S110 to S130 may be performed to bond the wafer 11 to the wafer 21. In some embodiments, 7A to 7D The process shown is to form Figure 9A As shown in the structure, the semiconductor layer 122 can be polished to be thinned to expose the through hole 126. The RDL 128 can be formed on the semiconductor layer 122 and the through hole 126, and the sub-bonding layer 150a can be formed on the RDL 128.

[0113] Steps S110 to S120 may be repeated again to receive the wafer 61 having the plurality of chips 160 formed therein and the wafer 71 having the plurality of chips 170 formed therein. Step S130 may also be repeated to bond the wafer 61 and the wafer 71, as shown in FIG. Figure 9BAs shown. In some embodiments, after bonding wafer 71 and wafer 61, semiconductor layer 162 may be polished to be thinned to expose through-hole 166. RDL 168 may be formed on semiconductor layer 162 and through-hole 166, and sub-bonding layer 150b may be formed on RDL 168. Then, wafer 61 may be further bonded to wafer 21 through bonding layer 150 formed by bonding sub-bonding layers 150a and 150b. In this way, four wafers 11, 21, 61, and 71 may be stacked as shown. Figure 9C shown.

[0114] After stacking the four wafers 11, 21, 61, and 71, steps S140 and S150 may be performed. For example, the power management wafer 30 may be bonded to the wafer 71 via the bonding layer 190 formed by bonding the sub-bonding layers 190a and 190b. Figure 9D Furthermore, as Figure 9D As shown, the semiconductor layer 112 of the wafer 11 may be ground to expose the through-hole 116. The RDL 118 may be formed on the semiconductor layer 112 and the through-hole 116. The conductive bump 119 and the passivation layer 117 may be formed on the RDL 118. In step S160, a die sawing process may be performed to dice the stacked wafers, thereby singulating the semiconductor structures 400.

[0115] exist Figures 3A to 3H as well as Figures 5A to 5H In the process shown, wafer 10 and wafer 20 may have the same structure, and when they are received, no through-holes are formed in the semiconductor layer, that is, the through-holes are formed during the wafer stacking process (i.e., the through-holes are formed last). 7A to 7H as well as Figures 9A to 9C In the process shown, wafers 11, 21, 61, and 71 may have the same structure, and upon receipt, vias are already formed in the semiconductor layer (i.e., in the middle of the vias). However, the present application is not limited thereto. In some embodiments, semiconductor structures 100 to 400 may be fabricated using wafers having different structures.

[0116] Figures 10A to 10E 1 is a cross-sectional view illustrating one or more stages of a method M1 for fabricating a semiconductor structure 100 according to one embodiment of the present disclosure.

[0117] In step S110, a wafer 11 is received, wherein a through hole 116 is formed in the semiconductor layer 112. Figure 10A As shown, in step S120, a wafer 20 is received, wherein no through hole is formed in the semiconductor layer 122, as shown in FIG. Figure 10B Furthermore, as Figure 10A and 10BAs shown, the sub-bonding layer 140a is formed on the dielectric layer 114, and the sub-bonding layer 140b is formed on the second dielectric layer 124. In this case, step S130 can be performed to bond the sub-bonding layer 140a and the sub-bonding layer 140b through a hybrid bonding process to form a bonding layer 140. In this way, the wafer 11 and the wafer 20 can be bonded, as shown in FIG. Figure 10C shown.

[0118] Furthermore, if Figure 10C As shown, the semiconductor layer 122 is polished and the through hole 126 is formed, and the RDL 128 can be formed on the semiconductor layer 122 and the through hole 126. In addition, a sub-bonding layer 150a is further formed on the RDL 128. In this case, when the power management wafer 30 is received in step S140, the sub-bonding layer 150b can be formed on the power management wafer 30, so that in step S150, the power management wafer 30 can be bonded to the wafer 20 through the bonding layer 150 formed by bonding the sub-bonding layer 150a and the sub-bonding layer 150b. Figure 10D shown.

[0119] After forming the stack structure of wafer 11, wafer 20 and power management wafer 30, the semiconductor layer 112 of wafer 11 is ground to expose the through hole 116, and RDL 118 is formed on the semiconductor layer 112 and the through hole 116, and the conductive bump 119 and the passivation layer 117 are formed on the RDL 118. Figure 10E In step S160 , a dicing process may be performed to dice the stacked wafers, thereby singulating the semiconductor structures 300 .

[0120] In some embodiments, in the semiconductor structure 100 , 200 , 300 or 400 , the power management die 130 is bonded to the capacitor chip in a wafer-on-wafer (WoW) manner, however, the present application is not limited thereto. Figure 11 A semiconductor structure 500 according to an embodiment of the present disclosure is shown.

[0121] Semiconductor structure 500 has a similar structure to semiconductor structure 100. However, semiconductor structure 500 includes three capacitor chips 110, 120, and 160, and a power management die 130, which is bonded to capacitor chip 160 via conductive bumps 539 and bump pads 569. In other words, power management die 130 is stacked on capacitor chip 160 in a chip-on-wafer (CoW) configuration.

[0122] like Figure 11As shown, semiconductor structure 500 includes chips 110, 120, and 160, and power management die 130. Chip 110 can be bonded to chip 120 via bonding layer 140, and chip 120 can be bonded to chip 160 via bonding layer 150. Furthermore, semiconductor structure 500 includes a plurality of bump pads 569 formed on RDL 168 of chip 160, and a plurality of conductive bumps 539 formed on dielectric layer 134 of power management die 130. In some embodiments, conductive bumps 539 can be microbumps aligned with bump pads 569, so that power management die 130 can be bonded to chip 160 by bonding conductive bumps 539 to bump pads 569. Furthermore, semiconductor structure 500 includes an underfill 580 surrounding conductive bumps 539 and disposed above chip 160 to protect the bond between conductive bumps 539 and bump pads 569. In some embodiments, to further protect the semiconductor structure 500, a molding layer 590 may be disposed on the chip 160 and surround the power management die 130, the underfill 580, and the conductive bumps 539. However, the present application is not limited thereto. In other embodiments, a molded underfill (MUF) layer capable of simultaneously filling the gaps between the conductive bumps 539 and the molded power management die 130 may be used in place of the underfill 580 and the molding layer 590.

[0123] Figures 12A to 12K FIG. 5 shows a cross-sectional view of one or more stages of fabricating a semiconductor structure 500 according to an embodiment of the present application. Figure 12A and Figure 12B As shown, wafer 10 and wafer 20 are received. In some embodiments, multiple chips 110 are formed in wafer 10, and multiple chips 120 are formed in wafer 20. In some embodiments, wafer 10 and wafer 20 may have the same structure and may be replicas of each other.

[0124] Furthermore, to facilitate bonding between wafer 10 and wafer 20, a sub-bonding layer 140a and a sub-bonding layer 140b may be formed on wafers 10 and 20, respectively. In some embodiments, carrier CR1 may be temporarily attached to dielectric layer 114 of wafer 10, so that through-holes 116 can be formed in semiconductor layer 112 with sufficient support strength. RDL 118 may be formed on through-holes 116 and semiconductor layer 112, and sub-bonding layer 140a may be formed on RDL 118, as shown in FIG. Figure 12C In addition, Figure 12D As shown, the sub-bonding layer 140 b can be formed on the dielectric layer 124 of the wafer 20 without using a carrier.

[0125] In this way, the sub-bonding layer 140a and the sub-bonding layer 140b can be bonded through a hybrid bonding process, so that the wafer 10 can be bonded to the wafer 20, such as Figure 12E In addition, Figure 12E As shown, after wafer 20 is bonded to wafer 10 , a through hole 126 may be formed in the semiconductor layer 122 of wafer 20 , an RDL 128 may be formed on the through hole 126 and the semiconductor layer 122 , and a sub-bonding layer 150 a may be formed on the RDL 128 to facilitate bonding with the next chip.

[0126] exist Figure 12F In the embodiment, another wafer 61 including a plurality of chips 160 is received. Furthermore, in order to bond the wafer 61 to the wafer 20, a sub-bonding layer 150b is formed on the dielectric layer 164 of the wafer 61. In this way, the sub-bonding layer 150a and the sub-bonding layer 150b can be bonded by a hybrid bonding process, so that the wafer 61 can be bonded to the wafer 20, as shown in FIG. Figure 12G shown.

[0127] After wafer 61 is bonded to wafer 20, carrier CR1 may be removed and openings may be formed on the surface of dielectric layer 114 so that conductive bumps 119 may be formed on dielectric layer 114 and coupled to interconnect structures 114a of dielectric layer 114, as shown in FIG. Figure 12H As shown. An adhesive layer AD1 can be applied to wafer 10 to protect conductive bumps 119 and bond carrier CR2 to the stacked structure. In this case, carrier CR2 provides support strength during subsequent processes, including polishing semiconductor layer 162 to expose vias 166 therein, forming RDL 168 on semiconductor layer 162 and vias 166, and forming bump pads 569 on RDL 168. In some embodiments, carrier CR2 can be a glass substrate.

[0128] In addition, a plurality of power management dies 130 may be received, and the conductive bumps 539 may be formed on the dielectric layer 134 of the power management dies 130. The power management dies 130 may be bonded to the wafer 61 by bonding the conductive bumps 539 to the bump pads 569 formed on the wafer 61, as shown in FIG. Figure 12J Furthermore, in some embodiments, after the power management die 130 is bonded to the wafer 61, an underfill 580 may be applied to protect the connection between the conductive bumps 539 and the bump pads 569, and a molding process may be performed to mold the power management die 130 on the wafer 61 using a molding layer 590. The carrier CR2 may be removed, and a die sawing process may be performed to singulate the semiconductor structure 500 from the CoW structure, as shown. Figure 12KAs shown. In some embodiments, wafer 10 may be attached to dicing tape DP1, and dicing blade B1 may cut the stacked structure from the mold layer 590 surrounding the power management die 130. However, the present application is not limited thereto. In other embodiments, the mold layer 590 and the backside of the power management die 130 may be attached to dicing tape DP1, and dicing blade B1 may cut the stacked structure from the surface of wafer 10.

[0129] Figure 13 A semiconductor structure 600 according to an embodiment of the present disclosure is shown. Semiconductor structure 600 has a similar structure to semiconductor structure 500. However, whereas chips 110, 120, and 160 are stacked in a front-to-back arrangement in semiconductor structure 500, chips 110, 120, and 160 in semiconductor structure 600 may be stacked differently. For example, chip 120 may be stacked front-to-front on chip 110, while chip 160 may be stacked front-to-back on chip 120.

[0130] 14A to 14H FIG. 6 is a cross-sectional view of one or more stages of fabricating a semiconductor structure 600 according to an embodiment of the present application. Figure 14A and Figure 14B As shown, wafers 11 and 20 are received. In some embodiments, the difference between wafer 11 and wafer 20 is that through-holes are formed in semiconductor layer 112 of wafer 11 while wafer 20 does not.

[0131] Furthermore, in order to facilitate the bonding between wafer 11 and wafer 20, a sub-bonding layer 140a and a sub-bonding layer 140b can be formed on the dielectric layers 114 and 124 of wafers 11 and 20 respectively. In this way, the sub-bonding layer 140a and the sub-bonding layer 140b can be bonded through a hybrid bonding process, thereby bonding wafer 11 to wafer 20, such as Figure 14C In addition, Figure 14C As shown, after wafer 20 is bonded to wafer 11 , through-holes 126 may be formed in the semiconductor layer 122 of wafer 20 , and RDL 128 may be formed on the through-holes 126 and the semiconductor layer 122 . A sub-bonding layer 150 a may be formed on the RDL 128 to facilitate bonding of the next chip.

[0132] exist Figure 14D In order to bond the wafer 60 to the wafer 20, a sub-bonding layer 150b may be formed on the dielectric layer 164 of the wafer 60. In this way, the sub-bonding layer 150a and the sub-bonding layer 150b may be bonded by a hybrid bonding process, so that the wafer 60 may be bonded to the wafer 20, as shown in FIG. Figure 14E shown.

[0133] After wafer 60 is bonded to wafer 20, semiconductor layer 162 may be ground to be thinned to form vias 166 in semiconductor layer 162. RDL 168 may be formed on semiconductor layer 162 and vias 166, and then a passivation layer 117 having openings may be formed on RDL 168 to subsequently receive conductive bumps 119.

[0134] like Figure 14F As shown, after forming the conductive bumps 119, an adhesive layer AD1 may be applied to the wafer 60 to protect the conductive bumps 119 and to bond the carrier CR2 to the wafer stack structure. In this case, the carrier CR2 can provide support strength during subsequent processes, wherein the subsequent processes include polishing the semiconductor layer 112 to expose the through-holes 116 therein, forming the RDL 118 on the semiconductor layer 112 and the through-holes 116, and forming the bump pads 569 on the RDL 118. Figure 14G shown.

[0135] A plurality of power management dies 130 may be received, and the conductive bumps 539 may be formed on the dielectric layer 134 of each power management die 130. In this case, the power management die 130 may be bonded to the wafer 11 by bonding the conductive bumps 539 to the bump pads 569 formed on the wafer 11, as shown in FIG. Figure 14H Furthermore, in some embodiments, after the power management die 130 is bonded to the wafer 11, an underfill 580 may be applied to protect the connections between the conductive bumps 539 and the bump pads 569, and a molding process may be performed to mold the power management die 130 on the wafer 11 using a molding layer 590. The carrier CR2 may be removed, and a die sawing process may be performed to singulate the semiconductor structure 600 from the CoW structure.

[0136] exist 14A to 14H In the illustrated process, semiconductor structure 600 can be manufactured using wafers having different structures, for example, wafer 11 having an intermediate through-hole structure and wafer 20 having a final through-hole structure. However, the present application is not limited thereto. In some embodiments, semiconductor structure 600 can be manufactured using wafers having the same structure.

[0137] Figures 15A to 15E FIG. 6 is a cross-sectional view of one or more stages of fabricating a semiconductor structure 600 according to another embodiment of the present invention. Figure 15A As shown in FIG15B , a wafer 11 having a plurality of chips 110 formed therein and a wafer 21 having a plurality of chips 120 formed therein can be received. In some embodiments, wafers 11 and 21 can have the same structure, each having a through-hole 116 formed in semiconductor layer 112 and a through-hole 126 formed in semiconductor layer 122 before BEOL processing.

[0138] Furthermore, in order to facilitate the bonding between wafer 11 and wafer 21, a sub-bonding layer 140a and a sub-bonding layer 140b are formed on the dielectric layers 114 and 124 of wafers 11 and 21 respectively. In this way, the sub-bonding layer 140a and the sub-bonding layer 140b can be bonded through a hybrid bonding process, so that wafer 11 can be bonded to wafer 21, as shown in FIG. Figure 15C In addition, Figure 15C As shown, after wafer 21 is bonded to wafer 11 , the semiconductor layer 122 of wafer 21 may be ground to expose the through hole 126 , an RDL 128 may be formed on the through hole 126 and the semiconductor layer 122 , and a sub-bonding layer 150 a may be formed on the RDL 128 to facilitate bonding of the next chip.

[0139] exist Figure 15D In the embodiment, a wafer 61 having a plurality of chips 160 formed therein is received. In some embodiments, the wafer 61 may have the same structure as the wafers 11 and 21. Furthermore, in order to bond the wafer 61 to the wafer 21, a sub-bonding layer 150b may be formed on the dielectric layer 164 of the wafer 61. In this way, the sub-bonding layer 150a and the sub-bonding layer 150b may be bonded through a hybrid bonding process, so that the wafer 61 may be bonded to the wafer 21, as shown in FIG. Figure 15E shown.

[0140] After wafer 61 is bonded to wafer 21, semiconductor layer 162 may be ground to be thinned to expose through-holes 166 formed in semiconductor layer 162. RDL 168 may be formed on semiconductor layer 162 and through-holes 166, and then a passivation layer 117 having openings may be formed on RDL 168 to receive conductive bumps 119. Figure 15E The structure shown can be transformed into Figure 14E The structure shown is the same. Therefore, the subsequent process can also refer to Figures 14F to 14H For the sake of simplicity, the relevant diagrams will not be repeated here. Figure 14H After the CoW structure including the plurality of semiconductor structures 600 is formed, a sawing process may be performed to singulate the semiconductor structures 600 .

[0141] In some embodiments, the semiconductor structure may include more capacitor chips to improve the power efficiency of voltage conversion. Figure 16 FIG. 7 shows a semiconductor structure 700 according to an embodiment of the present application. Figure 16 As shown, the semiconductor structure 700 includes chips 110 , 120 , 160 , 170 and a power management die 130 .

[0142] In some embodiments, the semiconductor structure 700 may be fabricated by repeating certain steps in method M1 . 17A to 17EA cross-sectional view is shown illustrating one or more stages of a method M1 for fabricating a semiconductor structure 700 according to one embodiment of the present disclosure.

[0143] like Figure 17A As shown, steps S110 to S130 may be performed to allow wafer 11 and wafer 21 to be bonded. In some embodiments, 7A to 7D The process shown is to form Figure 17A The structure shown.

[0144] Steps S110 to S120 may be repeated to receive wafer 61 and wafer 71. After wafer 71 and wafer 61 are bonded, a sub-bonding layer 150a may be formed on wafer 21, and a sub-bonding layer 150b may be formed on wafer 61. Then, wafer 61 may be further bonded to wafer 21 through a bonding layer 150 formed by bonding sub-bonding layers 150a and 150b. In this way, four wafers 11, 21, 61, and 71 may be stacked as shown in FIG. Figure 17B shown.

[0145] After stacking the four wafers 11, 21, 61, and 71, the semiconductor layer 172 may be polished to expose the through-holes 176, and the RDL 178 may be formed on the semiconductor layer 172 and the through-holes 176. A passivation layer 117 having openings may be formed on the RDL 178 to subsequently receive the conductive bumps 119, as shown in FIG. Figure 17B shown.

[0146] After the conductive bumps 119 are formed on the passivation layer 117 and coupled to the RDL 178, an adhesive layer AD1 is applied to the wafer 71 to protect the conductive bumps 119 and to attach the carrier CR2 to the wafer stack. Figure 17C In this case, the carrier CR2 can provide support strength in subsequent processes, including polishing the semiconductor layer 112 to expose the through hole 116 therein, forming the RDL 118 on the semiconductor layer 112 and the through hole 116, and forming the bump pad 569 on the RDL 118. Figure 17D shown.

[0147] In steps S140 and S150, a plurality of power management dies 130 may be received, and the conductive bumps 539 may be formed on the dielectric layer 134 of the power management dies 130. In this case, the power management dies 130 may be bonded to the wafer 11 by bonding the conductive bumps 539 to the bump pads 569 on the wafer 11, as shown in FIG. Figure 17EFurthermore, in some embodiments, after the power management die 130 is bonded to the wafer 11, an underfill 580 may be applied to protect the connections between the conductive bumps 539 and the bump pads 569, and a molding process may be performed to mold the power management die 130 on the wafer 11 using a molding layer 590. Finally, the carrier CR2 may be removed, and a dicing process may be performed to singulate the semiconductor structure 700 from the CoW structure.

[0148] Because semiconductor structures 100, 200, 300, 400, 500, 600, and 700 allow the power management die to be coupled to capacitors in the capacitor die via interconnects extending along the stacking direction, the wiring distance between the power management die and the capacitors can be shortened, thereby improving signal integrity and power integrity. Furthermore, the stacked structure of the capacitor die allows more capacitors to be integrated into a smaller area, thereby improving the energy efficiency of the power management die.

[0149] In some embodiments, semiconductor structures 100, 200, 300, 400, 500, 600, and 700 can be used to provide voltage for a system-on-chip (SoC). For example, each power management die 130 in semiconductor structures 100, 200, 300, 400, 500, 600, and 700 can include fully integrated voltage regulators (FIVRs) for the SoC. In some embodiments, semiconductor structures 100, 200, 300, 400, 500, 600, or 700 and the SoC are provided in the same package.

[0150] Figure 18 A semiconductor device 80 according to an embodiment of the present disclosure is shown. Semiconductor device 80 includes a printed circuit board (PCB) 801, a substrate 802, a SoC 803, and a semiconductor structure 900. In some embodiments, semiconductor structure 900 may be any of semiconductor structures 100, 200, 300, 400, 500, 600, and 700, or similar structures thereof. In some embodiments, substrate 802 may be a packaging substrate, and SoC 803 may be disposed on a first surface 802a of substrate 802. Furthermore, semiconductor structure 900 is embedded in substrate 802, and has a plurality of conductive bumps 919 exposed from first surface 802a of substrate 802 and coupled to SoC 803. In other words, semiconductor structure 900 is embedded in substrate 802 and may be packaged together with SoC 803 in the same package on substrate 802. In some embodiments, the substrate 802 further includes a plurality of solder balls 8021 disposed on the second surface 802 b to facilitate soldering the substrate 802 to the PCB 801 .

[0151] Figure 19 A semiconductor device 81 according to one embodiment of the present disclosure is shown. Semiconductor device 81 is similar to semiconductor device 80. However, the difference between semiconductor device 80 and semiconductor device 81 is that semiconductor structure 900 is disposed on second surface 802b of substrate 802 in semiconductor device 81. That is, semiconductor structure 900 is disposed on the bottom surface of substrate 802 in semiconductor device 81.

[0152] Figure 20 A semiconductor device 82 according to an embodiment of the present disclosure is shown. Semiconductor device 82 is similar to semiconductor device 81. However, semiconductor device 82 differs from semiconductor device 80 in that substrate 802 is disposed on first surface 801a of PCB 801, while semiconductor structure 900 in semiconductor device 82 may be disposed on second surface 801b of PCB 801. In other words, semiconductor structure 900 is disposed on the bottom surface of PCB 801 in semiconductor device 82.

[0153] Figure 21 A semiconductor device 83 according to an embodiment of the present disclosure is shown. Semiconductor device 83 is similar to semiconductor device 80. However, in semiconductor device 83, a fan-out frame 804, including copper pillars 8042, a molding 8041, RDLs 8043, and solder balls 8044, is disposed on PCB 801. Furthermore, a semiconductor structure 900 is embedded in molding 8041 and coupled to SoC 803 via portions of copper pillars 8042 and RDLs 8043.

[0154] Figure 22 A semiconductor device 84 according to one embodiment of the present disclosure is shown. Semiconductor device 84 is similar to semiconductor device 81. However, semiconductor device 84 differs from semiconductor device 81 in that semiconductor device 84 further includes an interposer 805 disposed on a substrate 802 and a SoC 803 disposed on a first surface 805a of interposer 805. Furthermore, interposer 805 includes a plurality of solder balls 8051 on a second surface 805b for soldering to substrate 802. In this case, semiconductor structure 900 may also be disposed on second surface 805b of interposer 805. That is, in semiconductor device 84, semiconductor structure 900 is disposed on the bottom surface of interposer 805. In some embodiments, semiconductor devices 80, 81, 82, 83, and 84 may also be considered semiconductor structures including semiconductor structure 900.

[0155] In summary, the semiconductor devices and methods for fabricating the same, as provided by various embodiments of the present application, enable coupling the power management die to the capacitors in the capacitor die via interconnects extending along the stacking direction, thereby shortening the wiring distance between the power management die and the capacitors. This improves both signal integrity and power integrity. Furthermore, utilizing the stacked capacitor die structure allows for the integration of more transistors within a smaller area, thereby improving the energy efficiency of the power management die.

[0156] Although the present application and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present application as defined by the appended claims. For example, many of the processes discussed above may be implemented in different ways and replaced by other processes or combinations thereof.

[0157] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, articles, compositions of matter, means, methods, and steps described in the specification. As will be readily understood by one of ordinary skill in the art from this disclosure, processes, machines, articles, compositions of matter, means, methods, or steps now existing or later developed that perform substantially the same functions or achieve substantially the same functions may be applied in accordance with this disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, articles, compositions of matter, means, methods, and steps.

Claims

1. A semiconductor structure, characterized in that Include: a first chip having a first 3D capacitor structure; a second chip having a second 3D capacitor structure; a first bonding layer for bonding the first chip to the second chip; as well as a power management die bonded to the second chip; The power management die is electrically connected to the first 3D capacitor structure and the second 3D capacitor structure through interconnects extending along a thickness of the semiconductor structure and across the first bonding layer. 2 . The semiconductor structure of claim 1 , wherein the power management die is bonded to the second chip via a second bonding layer, and edges of the power management die are aligned with edges of the first chip and edges of the second chip when viewed from above.

3. The semiconductor structure of claim 1 , wherein the first chip comprises a first dielectric layer, a first semiconductor layer above the first dielectric layer, a first through-hole extending through the first semiconductor layer, a first RDL above the first semiconductor layer and the first through-hole, and the first 3D capacitor structure is located in the first dielectric layer.

4. The semiconductor structure of claim 3 , wherein the first dielectric layer of the first chip is adjacent to a second dielectric layer of the second chip, the first semiconductor layer of the first chip is adjacent to the second dielectric layer of the second chip, or the first semiconductor layer of the first chip is adjacent to a second semiconductor layer of the second chip; and The first bonding layer contacts the first RDL or contacts the first dielectric layer.

5. The semiconductor structure of claim 1 , wherein the power management die is bonded to the second chip via a plurality of first conductive bumps, and the semiconductor structure further comprises: A bottom filling paste is disposed above the second chip and surrounds the first conductive bumps; and A molding layer is disposed on the second chip and surrounds the power management die, the bottom filling glue and the first conductive bumps.

6. The semiconductor structure as claimed in claim 1, wherein the first chip has a first surface and a second surface opposite to the first surface, the first chip further includes a plurality of second conductive bumps on the first surface of the first chip, and the second surface of the first chip contacts the first bonding layer.

7. The semiconductor structure according to claim 1, wherein a capacitance density of the first chip and a capacitance density of the second chip are both greater than 1 μF / mm 2 .

8. The semiconductor structure of claim 1 , wherein the first 3D capacitor structure comprises: a metal roof; a metal bottom plate located above the metal top plate; and A plurality of 3D capacitor units are formed between the metal top plate and the metal bottom plate.

9. The semiconductor structure of claim 8, wherein each of the 3D capacitor units comprises: a first conductive film comprising: a first portion connected to the metal base plate; and a second portion connected to the first portion and extending from the metal bottom plate toward the metal top plate; as well as a second conductor film adjacent to the first conductor film and connected to the metal top plate and extending from the metal top plate toward the metal bottom plate; The second conductor film and the second portion of the first conductor film are vertically interlaced.

10. The semiconductor structure of claim 1, wherein the first 3D capacitor structure is a cylindrical capacitor.

11. The semiconductor structure of claim 1 , further comprising: a printed circuit board; a substrate disposed on the printed circuit board; and A system single chip is disposed on a first surface of the substrate and is coupled to the first chip, the second chip and the power management die.

12. The semiconductor structure of claim 11, wherein: The first chip, the second chip, and the power management die are embedded in the substrate, and a plurality of conductive bumps are exposed from the first surface of the substrate; or The first chip, the second chip and the power management die are arranged on a second surface of the substrate.

13. A method for manufacturing a semiconductor structure, characterized in that: Include: forming a bond between a first wafer having a plurality of first 3D capacitor structures therein and a second wafer having a plurality of second 3D capacitor structures therein to bond the first wafer to the second wafer; bonding a plurality of power management dies onto the second wafer; as well as performing a dicing process to form the semiconductor structure, which includes a first chip, a second chip, a first bonding layer, a power management die among the power management dies, a first 3D capacitor structure among the first 3D capacitor structures in the first chip, and a second 3D capacitor structure among the second 3D capacitor structures in the second chip; The power management die is electrically connected to the first 3D capacitor structure and the second 3D capacitor structure through interconnects extending along a thickness of the semiconductor structure and across the first bonding layer.

14. The method of claim 13, wherein the step of forming the bond between the first wafer and the second wafer comprises forming a first sub-bonding layer above the first wafer, forming a second sub-bonding layer above the second wafer, and bonding the first sub-bonding layer and the second sub-bonding layer.

15. The method of claim 14, further comprising: receiving the first wafer comprising a first dielectric layer, a first semiconductor layer over the first dielectric layer, a first via extending through the first semiconductor layer, and the first 3D capacitor structures in the first dielectric layer; attaching a carrier to the first dielectric layer of the first wafer; grinding the first semiconductor layer of the first wafer to expose the first through hole; as well as forming a first RDL on the first semiconductor layer and the first through hole of the first wafer; The first sub-bonding layer is formed on the first RDL.

16. The method of claim 14, further comprising: receiving the first wafer comprising a first dielectric layer, a first semiconductor layer over the first dielectric layer, and the first 3D capacitor structures in the first dielectric layer; attaching a carrier to the first dielectric layer of the first wafer; forming a first through hole in the first semiconductor layer; and forming a first RDL on the first semiconductor layer and the first through hole of the first wafer; The first sub-bonding layer is formed on the first RDL.

17. The method of claim 14, further comprising: receiving the first wafer comprising a first dielectric layer, a first semiconductor layer over the first dielectric layer, and the first 3D capacitor structures in the first dielectric layer, The first sub-bonding layer is formed on the first dielectric layer.

18. The method of claim 13, further comprising: receiving a power management wafer comprising the power management dies; The step of bonding the power management chips onto the second wafer includes: forming a third sub-bonding layer above the second wafer; forming a fourth sub-bonding layer above the power management wafer; and The third sub-bonding layer and the fourth sub-bonding layer are bonded. 19 . The method of claim 13 , wherein each of the first 3D capacitor structures comprises a metal top plate, a metal bottom plate, and a plurality of 3D capacitor cells formed between the metal top plate and the metal bottom plate. 20 . The method of claim 19 , further comprising arranging the 3D capacitor units in a rectangular array or a hexagonal array.

Images