Semiconductor device and application thereof

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and application thereof.The semiconductor device comprises a first semiconductor layer, a second semiconductor layer, a first electrode and a second electrode, the second semiconductor layer is arranged on the first semiconductor layer, and the doping types of the first semiconductor layer and the second semiconductor layer are different; the first electrode is connected with the first semiconductor layer, the second electrode is connected with the second semiconductor layer, the first electrode surrounds the second electrode in a plan view, the first electrode is of a non-closed annular structure, the non-closed annular structure comprises a first side area, the non-closed annular structure is provided with an opening in the first side area, and the size of the opening accounts for 5%-95% of the length of the first side area. Through the arrangement, the semiconductor device can effectively reduce the on-resistance of the diode, thereby improving the ESD capability of the diode, and improving the ESD protection performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device, a radio frequency amplifier including the semiconductor device, and a communication device including the radio frequency amplifier. Background Art

[0002] Nowadays, Internet of Things (IoT) devices, smartphones, and other mobile devices are ubiquitous. With the frequent plugging and unplugging of USB, Lightning interfaces, and other cables, these electronic devices are easily susceptible to ESD shocks. Therefore, providing effective ESD protection is very important. Currently, ESD protection diodes are mainly used as a solution for electrostatic protection. For example, in microwave integrated circuits (MMICs), PN diodes are widely used as ESD protection circuits. However, the existing ESD protection performance is still poor. Therefore, how to provide effective ESD protection has become one of the technical problems that technicians in this field urgently need to solve.

[0003] It should be noted that the information disclosed in this background technology section is only intended to increase understanding of the overall background of the present invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0004] The present invention provides a semiconductor device comprising a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The second semiconductor layer is disposed on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer having different doping types, the first electrode connected to the first semiconductor layer, and the second electrode connected to the second semiconductor layer. When viewed from above, the first electrode surrounds the second electrode, and the first electrode is a non-closed ring structure including a first side region. The non-closed ring structure has an opening at the first side region, and the size of the opening accounts for 5% to 95% of the length of the first side region.

[0005] The present invention also provides a radio frequency amplifier and a communication device. The radio frequency amplifier includes the aforementioned semiconductor device. The communication device includes the aforementioned radio frequency amplifier.

[0006] The present invention provides a semiconductor device and its application. By adjusting the morphology of a first electrode and a second electrode, the first electrode at least surrounds the second electrode, and the first electrode has a non-closed ring structure, and an opening is provided on one side of the second electrode, thereby increasing the junction area of ​​the diode, reducing the on-resistance of the diode, greatly improving the ESD capability of the diode, and enhancing the ESD protection performance of the semiconductor device.

[0007] Other features and beneficial effects of the present invention will be described in the following description, and some of the technical features and beneficial effects can be obviously derived from the description or understood by practicing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, some of the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 This is a schematic diagram of the layout structure of a diode made using the traditional HBT process; Figure 2 is a schematic top view of the structure of a semiconductor device provided by a first embodiment of the present invention; Figure 3 yes Figure 2 Compared to Figure 1 Schematic diagram of increased junction area; Figure 4 yes Figure 2 Schematic diagram of the cross-section structure; Figure 5 yes Figure 2 A schematic structural diagram of a semiconductor device having a heterojunction bipolar transistor; Figure 6 This is a schematic diagram of the layout structure of a diode made using a traditional HEMT process; Figure 7 is a schematic top view of the structure of a semiconductor device provided by a second embodiment of the present invention; Figure 8 yes Figure 7 Schematic diagram of the cross-section structure; Figure 9 is a schematic structural diagram of interconnection of multiple semiconductor devices provided by the first embodiment; Figure 10 FIG. 1 is a schematic diagram of the interconnection structure of multiple semiconductor devices provided by the second embodiment.

[0010] Reference numerals: 11-first semiconductor layer; 12-second semiconductor layer; 21-first electrode; 22-second electrode; 32-isolation region; 34-passivation layer; 36-metal connection layer; 38-cap layer; 41-first side region; 42-second side region; 43-third side region; 44-fourth side region; 51-first long side; 52-first short side; 53-second long side; 54-second short side; 60-opening; 62-opening; 70-interconnection metal layer; S1-size; S2-length of the first side region. DETAILED DESCRIPTION

[0011] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments; the technical features designed in different implementation modes of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0012] In the description of the present invention, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variations thereof all mean "at least including".

[0013] See also Figure 2 and Figure 3 , Figure 2 is a schematic top view of the structure of a semiconductor device provided by a first embodiment of the present invention; Figure 3 yes Figure 2 Compared to Figure 1 Schematic diagram of increased junction area; Figure 4 yes Figure 2 Schematic diagram of the cross-section structure. Figure 4 It is along Figure 2 FF is a cross-sectional view taken along the cutting line FF. To achieve at least one of the aforementioned advantages or other advantages, a first embodiment of the present invention provides a semiconductor device. As shown in the figure, the semiconductor device may include a first semiconductor layer 11, a second semiconductor layer 12, a first electrode 21, and a second electrode 22. In this embodiment, the semiconductor device is a protection diode fabricated using an HBT semiconductor device process.

[0014] The first semiconductor layer 11 and the second semiconductor layer 12 have different doping types. For example, the first semiconductor layer 11 may be an N-type semiconductor layer with N-type doping, and the second semiconductor layer 12 may be a P-type semiconductor layer with P-type doping. The second semiconductor layer 12 is disposed on the first semiconductor layer 11 .

[0015] The first electrode 21 is connected to the first semiconductor layer 11, and the second electrode 22 is connected to the second semiconductor layer 12. The materials of the first electrode 21 and the second electrode 22 include metal materials, such as platinum-titanium-platinum-gold alloy. Figure 2 As shown, the first electrode 21 surrounds the second electrode 22, and the first electrode 21 is a non-closed ring structure. That is to say, the first electrode 21 will form a gap on the basis of the complete ring structure, thereby becoming a non-closed ring structure, and the non-closed ring structure is arranged around the second electrode 22. Specifically, the non-closed ring structure includes a first side area 41, and the non-closed ring structure has an opening 60 at the first side area 41. Since the first electrode 21 is a non-closed ring structure, it must have a gap, that is, forming an opening 60, and the first side area 41 refers to the side area where the opening 60 is located. The size S1 of the opening 60 accounts for 5% to 95% of the length S2 of the first side area 41 ( Figure 2 The regions of the first electrode 21 and the second electrode 22 are indicated by different shades, and the length S2 may refer to the outer length of the non-closed ring structure, and in some cases may also refer to the inner length of the non-closed ring structure). This increases the junction area of ​​the diode, reduces the on-resistance of the diode, and greatly improves the ESD capability of the diode, thereby enhancing the ESD protection performance of the semiconductor device.

[0016] refer to Figure 1 The layout structure of the diode made by the traditional HBT process shown in the figure has an N-type electrode that surrounds three sides of the P-type electrode, and the remaining side is used for metal connection. Due to process limitations, its ESD capability often does not meet the expected indicators and cannot meet the ESD protection performance requirements of existing products. In comparison, this embodiment adjusts the morphology of the first electrode 21 and the second electrode 22 so that the first electrode 21 extends to surround the last side of the second electrode 22, and forms an opening 60 to reserve some space for the metal connection of the second electrode 22. In this way, the junction area of ​​the diode is increased (refer to Figure 3The shaded area in the figure represents the newly added junction area. This reduces the diode's on-resistance, significantly improving the diode's ESD capability and, consequently, the semiconductor device's ESD protection performance. Because the diode's anode and cathode are connected to the corresponding P-type and N-type semiconductor layers via corresponding metal electrodes, the dimensions of the metal electrodes (i.e., the dimensions of first electrode 21 and second electrode 22) define the diode's effective P-type and N-type semiconductor areas, while the area between the two metal electrodes defines the diode's junction area.

[0017] It has been verified by experiments. Figure 1 Shown with Figure 2 The diodes shown in the figure have the same size. Figure 2 The ESD protection performance of the protection diode is improved by about 50%, which greatly improves the ESD protection performance of the semiconductor device.

[0018] In some embodiments, the dimension S1 of the opening 60 accounts for 5% to 20% of the length S2 of the first side region 41. The smaller the dimension S1 of the opening 60, the greater the increase in junction area, thereby enhancing the ESD resistance of the diode. Furthermore, if the dimension S1 of the opening 60 is less than 5%, there is a risk of device damage due to actual process factors.

[0019] In some embodiments, the first electrode 21 surrounds at least 80% of the circumference of the second electrode 22. In this way, the junction area of ​​the diode is further increased, the on-resistance of the diode is reduced, the ESD capability of the diode is greatly improved, and the ESD protection performance of the semiconductor device is enhanced.

[0020] In some embodiments, when viewed from above, the second electrode 22 is rectangular, having a first long side 51, a first short side 52, a second long side 53, and a second short side 54 connected in sequence. In this case, the perimeter of the second electrode 22 is formed by the first long side 51, the first short side 52, the second long side 53, and the second short side 54. The first electrode 21 is a square, non-closed ring structure, further comprising a second side region 42, a third side region 43, and a fourth side region 44. The third side region 43 is disposed opposite the first side region 41, and the second side region 42 is disposed opposite the fourth side region 44. The two ends of the second side region 42 are connected to the first side region 41 and the third side region 43, respectively. The two ends of the fourth side region 44 are connected to the first side region 41 and the third side region 43, respectively. Since the first side region 41 has an opening 60, it is composed of two parts. The first side area 41 corresponds to the first long side 51, the second side area 42 corresponds to the first short side 52, the third side area 43 corresponds to the second long side 53, and the fourth side area 44 corresponds to the second short side 54. The first long side 51, the first short side 52, the second long side 53, and the second short side 54 are located within the pattern formed by the first side area 41, the second side area 42, the third side area 43, and the fourth side area 44. In other words, the first pattern formed by the first side area 41, the second side area 42, the third side area 43, and the fourth side area 44 surrounds the second pattern formed by the first long side 51, the first short side 52, the second long side 53, and the second short side 54, and the first pattern surrounds at least 80% of the perimeter of the second pattern. For example, if the first side area 41 exists in the vertical area outward from the first long side 51, then that portion of the first side area 41 surrounds the first long side 51. Optionally, the length S2 of the first side region 41 is greater than the lengths of the second side region 42 and the fourth side region 44, and the opening 60 is positioned closer to the first long side 51 to increase the junction area and enhance the ESD resistance of the diode. However, the present invention is not limited thereto; in other embodiments, the opening 60 may also be positioned at the short side.

[0021] In some embodiments, when viewed from above, the ratio of the area of ​​the second electrode 22 to the area of ​​the first electrode 21 is greater than 0.5, that is, M2:M1>0.5, where M2 is the area of ​​the second electrode 22 and M1 is the area of ​​the first electrode 21, which can increase the on-state current and enhance the ESD capability of the device.

[0022] In some embodiments, the second electrode 22 may be in a square, polygonal, etc. The first electrode 21 may be in a circular non-closed ring structure or a polygonal non-closed ring structure.

[0023] In some embodiments, when viewed from above, between the first electrode 21 and the second electrode 22, the first electrode 21 surrounds the second electrode 22, and an opening 60 is formed only on one side of the first electrode 21, so as to increase the junction area of ​​the diode, reduce the on-resistance of the diode, and greatly improve the ESD capability of the diode.

[0024] In some embodiments, as Figure 5 As shown, a heterojunction bipolar transistor (HBT) is provided on the semiconductor device. The first semiconductor layer 11 and the HBT subcollector layer can be fabricated together in the same process and have the same material system. The second semiconductor layer 12 and the HBT base layer can be fabricated together in the same process and have the same material system. A collector layer is provided between the first semiconductor layer 11 and the second semiconductor layer 12. An isolation region 32 is provided outside the first electrode 21.

[0025] The sub-collector layer can be made of a highly doped N-type layer, such as N+GaAs, to reduce on-resistance and nonlinear capacitance. The base layer can be made of a combination of materials such as GaAs and InGaAs, which are heavily P-type doped, which helps to form a heterojunction barrier and reduce the collector carrier injection effect. At the same time, the thinner thickness can reduce the carrier transit time. The collector layer mainly uses GaAs material, which is low-doped N-type to increase the device breakdown voltage and collect carriers. The isolation region 32 can be formed by ion implantation and has the function of isolating the conductor.

[0026] In some embodiments, as Figure 4 As shown, the semiconductor device may further include a passivation layer 34 and a metal connection layer 36. The passivation layer 34 and the metal connection layer 36 are formed on the substrate. Figure 2 (not shown in the figure). The passivation layer 34 covers the isolation region 32, the first electrode 21, the second electrode 22, the first semiconductor layer 11, and the second semiconductor layer 12. The passivation layer 34 has openings 62 and provides insulation and protection. The metal connection layer 36 is disposed on the passivation layer 34 and connects the first electrode 21 and the second electrode 22 through the openings 62, serving as the positive and negative electrodes of the diode.

[0027] In some embodiments, the first electrode 21 is an N-type electrode and the second electrode 22 is a P-type electrode, with the N-type electrode surrounding the P-type electrode. In other embodiments, the first electrode 21 can be a P-type electrode and the second electrode 22 can be an N-type electrode, i.e., the P-type electrode surrounds the N-type electrode. However, if the P-type electrode occupies the same area, the layout area of ​​the P-type electrode surrounding the N-type electrode will be larger, affecting the size of the device.

[0028] See also Figure 7 and Figure 8 , Figure 7is a schematic top view of the structure of a semiconductor device provided by a second embodiment of the present invention; Figure 8 yes Figure 7 Schematic diagram of the cross-section structure, Figure 8 It is along Figure 7 Schematic diagram of the cross section taken along the interception line FF. Figure 2 As for the semiconductor device shown, the semiconductor device of this embodiment is a protection diode manufactured based on the HEMT semiconductor device process, used for ESD protection. The diode is usually arranged on the cap layer 38, that is, the first electrode 21 is arranged on the cap layer 38.

[0029] refer to Figure 6 The diodes made with the conventional HEMT process shown above have N-type and P-type electrodes that are independently arranged in blocks. Due to process limitations, their ESD resistance often falls short of expectations and cannot meet the ESD protection requirements of existing products. In contrast, this embodiment adjusts the morphology of the first electrode 21 and the second electrode 22 so that the first electrode 21 extends to surround most of the second electrode 22 (the first electrode 21 surrounds at least 80% of the circumference of the second electrode 22). Figure 7 The regions of the first electrode 21 and the second electrode 22 are indicated by different shades in the figure, and an opening 60 is formed to reserve space for a metal connection to the second electrode 22. This increases the junction area of ​​the diode, reduces the on-resistance of the diode, and significantly improves the ESD capability of the diode, thereby enhancing the ESD protection performance of the semiconductor device.

[0030] For the extended use of the first electrode 21 and the second electrode 22, reference may be made to the corresponding description of the first electrode 21 and the second electrode 22 in the first embodiment. The junction area in this embodiment is also the semiconductor layer region between the first electrode 21 and the second electrode 22.

[0031] In some embodiments, the semiconductor device fabricated based on the HEMT semiconductor device process further includes a high electron mobility transistor.

[0032] A barrier layer, channel layer, and other structures can be disposed beneath the cap layer 38, using conventional arrangements in the prior art. For example, an insertion layer, such as an AlN layer, can be disposed between the channel layer and the barrier layer. Therefore, this embodiment will not be described in detail here. Furthermore, the diode of the semiconductor device provided in this embodiment can also be applied to HEMT structures made of other material systems.

[0033] In some embodiments, an intrinsic layer is disposed between the first semiconductor layer 11 and the second semiconductor layer 12. The intrinsic layer refers to an undoped semiconductor material and serves as a high resistance region in the device to improve the ESD capability of the device.

[0034] See also Figure 9 , Figure 9 The figure is a schematic diagram of the interconnected structure of multiple semiconductor devices provided by the first embodiment. In this embodiment, the forward ESD circuit includes 12 semiconductor devices (protection diodes), which are connected via an interconnect metal layer 70 (illustrated by hatching in the figure). The primary function of the ESD circuit is to provide electrostatic protection at each power port. When static electricity passes through, it is first discharged through this circuit. Due to its strong anti-static capability, this circuit provides effective ESD protection. In some embodiments, a reverse protection diode may also be connected to further enhance ESD protection. Given that static electricity can flow in both positive and negative directions, power ports require ESD circuits that protect against both positive and negative charges. Diodes generally have stronger negative ESD protection, so the number of diodes is relatively small. Diodes also have a certain voltage drop. Too few diodes can cause the chip power port to prematurely turn on and ground, while too many can cause static electricity to disrupt internal chip components first. Therefore, the number of diodes can be adjusted based on the application voltage range.

[0035] See also Figure 10 , Figure 10 The figure is a schematic diagram of the interconnected structure of multiple semiconductor devices provided by the second embodiment. In this embodiment, the forward ESD circuit includes seven semiconductor devices (protection diodes), which are connected via an interconnect metal layer 70 (illustrated by hatching in the figure). The primary function of the ESD circuit is to provide electrostatic protection at each power port. When static electricity passes through, it is first discharged through this circuit. Due to its strong anti-static capability, this circuit provides effective ESD protection. In some embodiments, multiple reverse protection diodes can be connected to further enhance ESD protection. Given that static electricity can flow in both positive and negative directions, power ports require ESD circuits that protect against both positive and negative charges. Generally, diodes have stronger negative ESD protection, so the number of diodes is relatively small. Diodes also have a certain voltage drop. Too few diodes can cause the chip power port to prematurely turn on and ground, while too many can cause static electricity to disrupt internal chip components first. Therefore, the number of diodes can be adjusted based on the application voltage range.

[0036] Accordingly, an embodiment of the present invention further provides a radio frequency amplifier, comprising the semiconductor device of any of the aforementioned embodiments. An embodiment of the present invention further provides a communication device, which can be applied to communication devices such as microwave systems, radars, wireless communication modules, and network devices.

[0037] In summary, the present invention provides a semiconductor device and its application, which adjusts the morphology of the first electrode 21 and the second electrode 22 so that the first electrode 21 surrounds at least 80% of the circumference of the second electrode 22, thereby increasing the junction area of ​​the diode, reducing the on-resistance of the diode, and greatly improving the ESD capability of the diode, thereby enhancing the ESD protection performance of the semiconductor device.

[0038] In addition, those skilled in the art should understand that, although there are many problems in the prior art, each embodiment or technical solution of the present invention may be improved in only one or several aspects, without having to simultaneously solve all the technical problems listed in the prior art or background art. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as limiting the claim.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: a first semiconductor layer; a second semiconductor layer, the second semiconductor layer being disposed on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer having different doping types; a first electrode connected to the first semiconductor layer; a second electrode connected to the second semiconductor layer; From a top view, the first electrode surrounds the second electrode, and the first electrode is a non-closed ring structure. The non-closed ring structure includes a first side area. The non-closed ring structure has an opening at the first side area, and the size of the opening accounts for 5% to 95% of the length of the first side area.

2. The semiconductor device according to claim 1, wherein: In a top view, the size of the opening accounts for 5% to 20% of the length of the first side area.

3. The semiconductor device according to claim 1, wherein: The first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer.

4. The semiconductor device according to claim 1, wherein: In a top view, a ratio of an area of ​​the second electrode to an area of ​​the first electrode is greater than 0.

5.

5. The semiconductor device according to claim 1, wherein: When viewed from above, the second electrode is rectangular, and the second electrode has a first long side, a first short side, a second long side and a second short side connected in sequence. The first electrode includes a second side area, a third side area and a fourth side area. The third side area is arranged opposite to the first side area, and the second side area is arranged opposite to the fourth side area. The two ends of the second side area are respectively connected to the first side area and the third side area, and the two ends of the fourth side area are respectively connected to the first side area and the third side area, and the first long side, the first short side, the second long side and the second short side are located in a figure formed by the first side area, the second side area, the third side area and the fourth side area.

6. The semiconductor device according to claim 5, wherein: The length of the first side region is greater than the lengths of the second side region and the fourth side region.

7. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a heterojunction bipolar transistor.

8. The semiconductor device according to claim 7, wherein: The first semiconductor layer is a sub-collector layer, the second semiconductor layer is a base layer, a collector layer is provided between the first semiconductor layer and the second semiconductor layer, and an isolation region is provided outside the first electrode.

9. The semiconductor device according to claim 1, wherein: The semiconductor device is further provided with a high electron mobility transistor.

10. The semiconductor device according to claim 9, wherein: The first semiconductor layer is disposed on the cap layer.

11. The semiconductor device according to claim 9, wherein: An intrinsic layer is disposed between the first semiconductor layer and the second semiconductor layer.

12. The semiconductor device according to claim 1, wherein: The first electrode surrounds at least 80% of the circumference of the second electrode.

13. A radio frequency amplifier, characterized in that: The radio frequency amplifier includes the semiconductor device according to any one of claims 1 to 12.

14. A communication device, characterized in that: The communication device comprises the radio frequency amplifier according to claim 13.

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