Solar cell, photovoltaic module and manufacturing method of solar cell

Abstract

The invention discloses a solar cell, a photovoltaic module and a manufacturing method of the solar cell, relates to the technical field of solar cells, and aims to solve the problem of how to enable the photoelectric efficiency of the solar cell to reach a relatively high level. The solar cell comprises a semiconductor substrate, a first doped layer and a second doped layer. The semiconductor substrate comprises a first surface and a second surface which are opposite, and the first surface comprises a first electrode region and a first non-electrode region. The surface of the first electrode area is provided with a first texture structure, the first non-electrode area is provided with a second texture structure and a third texture structure, the second texture structure is located in the middle area of the semiconductor substrate, the third texture structure is located in the edge area of the semiconductor substrate, and the width of the edge area is smaller than or equal to 3 mm; the fluctuation degree of the third texture structure is smaller than that of the second texture structure. The first doped layer is arranged in the first electrode area, the second doped layer is arranged in the first non-electrode area, and the doping concentration of the first doped layer is larger than that of the second doped layer.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell, a photovoltaic module and a method for manufacturing a solar cell. Background Art

[0002] A solar cell is a device that utilizes solar energy and directly converts light energy into electrical energy through the photoelectric effect or photochemical effect.

[0003] Current solar cells mainly include IBC cells (Interdigitated Back Contact), TOPCON (Tunnel Oxide Passivated Contact), PERC cells (Passivated emitter and real cell), heterojunction cells and bifacial solar cells.

[0004] Currently, there are many improvements in battery structure. However, how to achieve a high level of photovoltaic efficiency of solar cells remains a technical problem that needs to be solved urgently in the industry. Summary of the Invention

[0005] The object of the present invention is to provide a solar cell, a photovoltaic module and a method for manufacturing a solar cell, so as to improve the efficiency of the solar cell.

[0006] In order to achieve the above-mentioned objectives, in a first aspect, the present invention provides a solar cell. The solar cell comprises: a semiconductor substrate, a first doped layer, and a second doped layer. The semiconductor substrate comprises a first surface and a second surface relative to each other, the first surface comprising a first electrode region and a first non-electrode region. The surface of the first electrode region has a first texture structure, the first non-electrode region has a second texture structure and a third texture structure, the second texture structure is located in the middle region of the semiconductor substrate, the third texture structure is located in the edge region of the semiconductor substrate, the width of the edge region is less than or equal to 3 mm, and the undulation of the third texture structure is less than the undulation of the second texture structure. The first doped layer is arranged in the first electrode region, the second doped layer is arranged in the first non-electrode region, and the doping concentration of the first doped layer is greater than the doping concentration of the second doped layer.

[0007] In the solar cell provided by the present invention, the doping concentration of the first doping layer arranged in the first electrode area is greater than the doping concentration of the second doping layer arranged in the first non-electrode area. By reducing the doping concentration of the first non-electrode area, the high-concentration area on the front of the solar cell is reduced, the compounding problem caused by the high doping concentration on the surface of the semiconductor substrate is reduced, and the open circuit voltage of the battery is increased; at the same time, the first doping layer of the first electrode area is retained to ensure that there is a small contact resistance between the electrode and the first doping layer, reduce the battery series resistance, improve the fill factor, and thus improve the efficiency of the solar cell. Since the first non-electrode area is not blocked by the grid line, the first non-electrode area focuses on the light trapping effect and passivation performance of the front of the battery cell, while the first electrode area focuses on the contact performance and passivation performance. Based on the functional difference between the first electrode area and the first non-electrode area mentioned above, the first non-electrode area needs to take into account both the light trapping effect and the passivation performance of the passivation layer coating. In the present application, the first non-electrode area has a second texture structure located in the middle area of ​​the semiconductor substrate and a third texture structure located in the edge area of ​​the semiconductor substrate. The undulation degree of the third texture structure is less than that of the second texture structure. That is, in the present application, the first non-electrode area extending to the edge area of ​​the semiconductor substrate has a third texture structure with relatively gentle undulations. The third texture structure can provide a good surface for the subsequent coverage of the passivation layer. At the same time, the undulation is small, indicating that the specific surface area of ​​the semiconductor substrate located in the edge area is smaller. In the same coating process, a thicker passivation layer can be formed to meet the passivation performance of the edge of the solar cell and ensure the efficiency of the solar cell.

[0008] In one implementation, the third texture structure includes one or more of a tower-base structure, a prismatic structure, an inverted pyramid structure, a prism structure, or a pyramid-type structure.

[0009] In one implementation, the first texture structure and / or the second texture structure is a pyramid structure.

[0010] When the technical solution is adopted, it is beneficial to increase the surface area of ​​the semiconductor substrate, improve the light trapping effect of the semiconductor substrate, and help more light to be refracted into the semiconductor substrate through the area where the first texture structure and / or the second texture structure are located and be utilized by the semiconductor substrate, so that the solar cell has a higher photoelectric conversion efficiency.

[0011] In one implementation, the reflectivity of the first electrode region where the first texture structure is located is greater than the reflectivity of the first non-electrode region where the second texture structure is located.

[0012] When the technical solution is adopted, the surface of the first non-electrode area where the second texture structure is located is not blocked by grid lines and the velvet structure with low reflectivity can better utilize the incident light, improve the light absorption utilization rate, and thus improve the photoelectric conversion rate of the solar cell.

[0013] In one implementation, part of the edge area has a tunneling layer and / or a doped conductive layer; the tunneling layer and the doped conductive layer are arranged on the first doped layer and / or the second doped layer; the first doped layer and the second doped layer have the same doping type, and the doping conductive layer and the first doped layer and the second doped layer have opposite doping types.

[0014] When this technical solution is adopted, the chemical passivation of the tunneling layer and the field passivation of the doped conductive layer can significantly reduce the degree of recombination on the surface of the semiconductor substrate. The tunneling layer and the doped conductive layer can further passivate the edges of the cell, reducing recombination at the cell edges. In addition, the provision of the tunneling layer and / or the doped conductive layer in some edge regions can reduce damage to the central portion of the first surface during the process of removing the side tunneling layer and / or the doped conductive layer, reducing the probability of damage to the first and second texture structures, and improving the light trapping effect on the front side.

[0015] In one implementation, the semiconductor substrate further includes a plurality of side surfaces between the first surface and the second surface; a groove is provided on at least some of the side surfaces, the bottom of the groove is lower than the surface of the side surface, and the height difference between the bottom of the groove and the surface of the side surface is greater than or equal to 0.5 μm and less than or equal to 7 μm.

[0016] When the technical solution is adopted, when forming the doped conductive layer on the second surface, the doped conductive layer will also be formed by plating on the side surface of the semiconductor substrate and the first electrode area of ​​the first surface. The doped conductive layer on the first surface and the second surface is isolated by grooves provided on at least part of the side surface, thereby avoiding short circuits and edge leakage in the solar cell. The grooves can also increase the distance between the first surface and the second surface, increasing the difficulty of overlapping the doped conductive layers on the first and second surfaces at the side. In addition, during the preparation process, the semiconductor substrate on the side of the battery is partially etched to remove the inner expansion layer formed in the semiconductor substrate during the formation of the doped conductive layer, thereby reducing the possibility of short circuits caused by contact between doped conductive layers of opposite polarities.

[0017] If the height difference between the bottom of the groove and the surface of the side where it is located is less than 0.5μm, the depth of the groove is shallow. At this time, the groove set on the side cannot effectively isolate the doped conductive layer on the first surface and the second surface, and cannot ensure the complete removal of the inner expansion layer on the side of the battery, resulting in an increased probability of short circuit and edge leakage in the solar cell. If the height difference between the surface of the groove and the surface of the side where it is located is greater than 7μm, the depth of the groove is deep. At this time, more of the side of the semiconductor substrate is removed, which will reduce the overall mechanical strength of the cell. In addition, the solar cell uses light to separate electrons and holes on the semiconductor substrate to generate electricity. If the semiconductor substrate is removed too much, the light absorption rate of the semiconductor substrate is reduced, resulting in a decrease in the number of photogenerated carriers, i.e., holes and electrons, generated by the irradiation on the semiconductor substrate, which will lead to a decrease in the photoelectric conversion rate of the solar cell. Combining the above two aspects, the present application sets the height difference between the surface of the groove and the surface of the side where it is located within a reasonable range. While avoiding short circuit and edge leakage in the solar cell, it ensures that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the solar cell will not be reduced, and it also ensures that the cell has sufficient mechanical strength.

[0018] In one implementation, the surface of the side includes a surface close to the first surface and a surface close to the second surface, and the distance between the bottom of the groove and the surface close to the first surface of the side surface is greater than the distance between the bottom of the groove and the surface close to the second surface of the side surface.

[0019] In one implementation, along the thickness direction of the semiconductor substrate, the first electrode region is higher than the first non-electrode region; and the distance between the first electrode region and the first non-electrode region is greater than or equal to 2 μm and less than or equal to 7 μm.

[0020] When the technical solution is adopted, the first non-electrode area is recessed relative to the first electrode area, so that light can be reflected and absorbed in the groove to reduce the reflectivity of the second texture structure and the third texture structure.

[0021] In one implementation, the second surface includes a second electrode region and a second non-electrode region; the second electrode region and the second non-electrode region are alternately arranged on the second surface; the tunneling layer is arranged on the surface of the second electrode region; the doped conductive layer is arranged in the second electrode region and is located on the side of the tunneling layer away from the semiconductor substrate; along the thickness direction of the semiconductor substrate, the second electrode region is higher than the second non-electrode region; the distance between the second electrode region and the second non-electrode region is greater than or equal to 2 μm and less than or equal to 6 μm.

[0022] When the technical solution is adopted, if the distance between the second electrode region and the second non-electrode region along the thickness direction of the semiconductor substrate is greater than 6μm, the depth of the second non-electrode region is deep, and the second surface of the semiconductor substrate is removed more, the overall mechanical strength of the cell is reduced; and the solar cell uses light to separate electrons and holes on the semiconductor substrate to generate electricity. If the semiconductor substrate is removed too much, the transmission path of light in the semiconductor substrate will be reduced, and the light absorption rate of the semiconductor substrate will be reduced, resulting in the number of photogenerated carriers, i.e., holes and electrons, generated by irradiation on the semiconductor substrate. This will reduce the photoelectric conversion rate of the solar cell. The present application sets the distance between the second electrode region and the second non-electrode region along the thickness direction of the semiconductor substrate within the above-mentioned value range, ensuring that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the solar cell will not be reduced, and also ensuring that the cell has sufficient mechanical strength.

[0023] In one implementation, along the thickness direction of the semiconductor substrate, a projection of the first non-electrode region on the first surface at least partially overlaps with a projection of the second non-electrode region on the first surface.

[0024] In the case of adopting the technical solution, when the second non-electrode area and the first non-electrode area are both recessed into the interior of the semiconductor substrate, if the second non-electrode area and the first non-electrode area completely correspond to each other along the thickness direction of the semiconductor substrate, then the thickness of the semiconductor substrate located in the second non-electrode area and the first non-electrode area is smaller than the thickness of the semiconductor substrate located in the second electrode area and the first electrode area. That is, the thickness of the semiconductor substrate in the non-electrode area is smaller than the thickness of the semiconductor substrate in the electrode area, which leads to a significant reduction in the mechanical strength of the semiconductor substrate in the non-electrode area. In the present application, the second non-electrode area and the first non-electrode area are staggered along the thickness direction of the semiconductor substrate, which can meet the mechanical strength requirements of the semiconductor substrate and reduce or eliminate the probability of the semiconductor substrate breaking.

[0025] In one implementation, the second non-electrode region has a fourth texture structure, and the size consistency of the fourth texture structure is lower than the size consistency of the first texture structure.

[0026] When adopting the technical solution, the fourth texture structure includes a pyramid structure and a tower base structure. Compared with the second non-electrode area without a texture structure, the reflectivity of the second non-electrode area is significantly reduced. Combined with the optimization of the passivation process, the battery efficiency is not affected, further improving the battery bifaciality.

[0027] In a second aspect, the present invention further provides a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string includes a plurality of interconnecting members and a plurality of solar cells as described in the above technical solution. The interconnecting members are used to connect the plurality of solar cells in series to form a cell string, and the encapsulation layer is used to cover the surface of the cell string.

[0028] The beneficial effects of the photovoltaic module provided by the present invention are the same as the beneficial effects of the solar cell described in the above technical solution, and will not be described in detail here.

[0029] In a third aspect, the present invention further provides a method for manufacturing a solar cell. The method for manufacturing a solar cell comprises: First, a semiconductor substrate is provided; the semiconductor substrate has a first surface and a second surface opposite to each other; the first surface and the second surface are subjected to a texturing process to form a first texture structure; the first surface includes a first electrode region and a first non-electrode region; Next, a diffusion process is performed on the first surface of the semiconductor substrate to form a first doped layer and a first doped oxide layer formed on the first doped layer; Next, removing the first doped oxide layer located on the first non-electrode region; Next, etching the first doped layer in the first non-electrode region to form a second doped layer, so that the doping concentration of the second doped layer is lower than the doping concentration of the first doped layer; Next, a tunneling layer and a doped conductive layer are deposited on the edge region of the first surface and the second surface, and portions of the tunneling layer and the doped conductive layer located on the edge region of the first surface are removed; Next, after removing a portion of the tunneling layer and the doped conductive layer located on the edge region of the first surface, a secondary texturing process is performed to form a texture structure on the first non-electrode region.

[0030] The beneficial effects of the method for manufacturing a solar cell provided by the present invention are the same as the beneficial effects of the solar cell described in the above technical solution, and will not be repeated here. Furthermore, the chemical passivation of the tunneling layer and the field passivation effect of the doped conductive layer can significantly reduce the degree of recombination on the surface of the semiconductor substrate. At the same time, the tunneling layer can also ensure the effective tunneling of majority carriers, and the doped conductive layer can significantly improve the conductivity of photogenerated carriers, thereby improving the open circuit voltage and fill factor of the solar cell. When the tunneling layer and the doped conductive layer are stacked on the edge area of ​​the first surface and the second surface at the same time, the tunneling layer and the doped conductive layer form a passivation contact structure. The tunneling layer allows the majority electrons to tunnel into the doped conductive layer while blocking the hole recombination of the minority carriers, thereby allowing the electrons to be transported laterally in the doped conductive layer and collected by the metal, greatly reducing the metal contact recombination current, improving the open circuit voltage and short circuit current of the battery, and thus improving the battery efficiency.

[0031] In one implementation, the second surface includes a second electrode region and a second non-electrode region; after depositing the tunneling layer and the doped conductive layer on the edge region of the first surface and the second surface, and before removing a portion of the tunneling layer and the doped conductive layer located on the edge region of the first surface, the method for manufacturing a solar cell further includes: irradiating the tunneling layer and the doped conductive layer on the second non-electrode region with a second laser to etch the tunneling layer and the doped conductive layer located on the second non-electrode region; In the secondary texturing step, a fourth texture structure is further formed in the second non-electrode area.

[0032] Compared with the polished surface of the second non-electrode area, the reflectivity of the second non-electrode area is significantly reduced. Combined with the optimization of the passivation process, the battery efficiency is not affected, and the battery bifaciality is improved.

[0033] In one implementation, the semiconductor substrate includes a plurality of side surfaces between a first surface and a second surface; before depositing the tunneling layer and the doped conductive layer in the edge region of the first surface and the second surface, the method for manufacturing a solar cell further includes: removing the first doped oxide layer and the first doped layer from the second surface and the side surface close to the second surface, thereby forming a recessed region on at least a portion of the side surface, wherein the bottom surface of the recessed region is lower than the surface of the side surface; While removing a portion of the tunneling layer and the doped conductive layer located on the edge region of the first surface, the method for manufacturing a solar cell further includes: etching a portion of the bottom surface of the recessed area to form a groove; The surface of the side includes a surface close to the first surface and a surface close to the second surface, and the distance between the bottom of the groove and the surface close to the first surface of the side surface is greater than the distance between the bottom of the groove and the surface close to the second surface of the side surface.

[0034] The grooves described above isolate the doped conductive layers on the first and second surfaces, preventing short circuits and edge leakage in the solar cell. The grooves also increase the distance between the first and second surfaces, making it easier for the doped conductive layers on the first and second surfaces to overlap. During the manufacturing process, the semiconductor substrate on the side of the cell is etched to remove the inner expansion layer formed in the semiconductor substrate during the formation of the doped conductive layer, reducing the possibility of short circuits caused by contact between doped conductive layers of opposite polarity.

[0035] In one implementation, after the secondary texturing process, the method for manufacturing a solar cell further includes: forming a passivation layer on the doped conductive layer and on the first and second surfaces of the semiconductor substrate; Electrodes are formed on the passivation layer, and the electrodes are respectively located in the first electrode region and the second electrode region.

[0036] The passivation layer can passivate the surface of the semiconductor substrate, reduce surface recombination, and improve the open circuit voltage and fill factor. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 is a cross-sectional view of a first solar cell according to an embodiment of the present invention; Figure 2 is a cross-sectional view of a second solar cell according to an embodiment of the present invention; Figure 3 This is an enlarged schematic diagram of a portion of the structure on the first side of a solar cell according to an embodiment of the present invention. Figure 1 ; Figure 4 This is an enlarged schematic diagram of a portion of the structure on the first side of a solar cell according to an embodiment of the present invention. Figure 2 ; Figure 5 It is a schematic diagram of an enlarged portion of the structure of the second surface of a solar cell according to an embodiment of the present invention.

[0038] Reference numerals: 1-semiconductor substrate, 10-first surface, 100-first electrode region, 101-first non-electrode region, 102-first texture structure, 103-second texture structure; 11-second surface, 110-second electrode region, 111-second non-electrode region, 112-fourth texture structure; 12-side surface, 120-groove; 3-tunneling layer, 4-doped conductive layer, 5-passivation layer, 50-aluminum oxide passivation layer, 51-silicon nitride passivation layer; 6-first electrode, 7-second electrode. DETAILED DESCRIPTION

[0039] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0040] It should be noted that when an element is referred to as being "fixed on" or "set on" another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or indirectly connected to the other element. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0041] In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0042] In a first aspect, an embodiment of the present invention provides a solar cell. Figure 1 The solar cell comprises: a semiconductor substrate 1, a first doped layer and a second doped layer. The semiconductor substrate 1 comprises a first surface 10 and a second surface 11 opposite to each other. The first surface 10 comprises a first electrode region 100 and a first non-electrode region 101. The surface of the first electrode region 100 has a first texture structure 102, and the first non-electrode region 101 has a second texture structure 103 and a third texture structure ( Figure 1), the second texture structure 103 is located in the middle area of ​​the semiconductor substrate 1, and the third texture structure is located in the edge area of ​​the semiconductor substrate 1. The width of the edge area is less than or equal to 3 mm, and the undulation of the third texture structure is less than that of the second texture structure 103. The first doped layer is arranged in the first electrode area 100, and the second doped layer is arranged in the first non-electrode area 101. The doping concentration of the first doped layer is greater than the doping concentration of the second doped layer. The above-mentioned edge area refers to the area close to the four edges of the semiconductor substrate 1. The edge area surrounds the middle area. The width of the edge area refers to the distance from the side of the edge area away from the edge of the semiconductor substrate 1 to the edge of the semiconductor substrate 1.

[0043] In terms of shape, the first and second surfaces of the semiconductor substrate 1 may be the same or different. In an embodiment of the present invention, the first and second surfaces are the same. For example, the first surface 10 or the second surface 11 may be square, rectangular, square with rounded corners, circular, or the like.

[0044] In terms of materials, the semiconductor substrate 1 can be a substrate made of any semiconductor material, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a gallium arsenide substrate.

[0045] In terms of conductivity type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an N-type conductive substrate, or a P-type conductive substrate. Preferably, the semiconductor substrate 1 is a P-type conductive substrate or an N-type conductive substrate. Compared with the intrinsic conductive substrate, the P-type conductive substrate or the N-type conductive substrate has better conductivity, so that the final solar cell has a lower bulk resistivity, thereby improving the efficiency of the solar cell. Exemplarily, the semiconductor substrate 1 is an N-type silicon substrate. Compared with the P-type conductive substrate, the N-type silicon substrate has the advantages of a long minority carrier lifetime, no light decay, and good weak light performance.

[0046] From the perspective of light reception, when the first surface 10 is a light-facing surface, the second surface 11 is a backlight surface.

[0047] See also Figure 1 In the solar cell provided by the embodiment of the present invention, the doping concentration of the first doping layer arranged in the first electrode area 100 is greater than the doping concentration of the second doping layer arranged in the first non-electrode area 101. By reducing the doping concentration of the first non-electrode area 101, the high-concentration area on the front of the solar cell is reduced, the recombination problem caused by the high doping concentration on the surface of the semiconductor substrate 1 is reduced, and the open-circuit voltage of the battery is increased; at the same time, the first doping layer of the first electrode area 100 is retained to ensure that there is a small contact resistance between the electrode and the first doping layer, reduce the series resistance of the battery, and improve the fill factor, thereby improving the efficiency of the solar cell.

[0048] See also Figure 1Because the first non-electrode region 101 is not obstructed by the grid lines, it focuses on light trapping and passivation performance on the front side of the cell, while the first electrode region 100 focuses on contact performance and passivation performance. Based on the functional differences between the first electrode region 100 and the first non-electrode region 101, the first non-electrode region 101 needs to balance light trapping and the passivation performance of the passivation layer coating. In this application, the first non-electrode region 101 has a second texture structure 103 located in the middle region of the semiconductor substrate 1 and a third texture structure located in the edge region of the semiconductor substrate 1. The third texture structure has a less undulating texture than the second texture structure 103. That is, in this application, the first non-electrode region 101 extending to the edge region of the semiconductor substrate 1 has a relatively gently undulating third texture structure. The third texture structure provides a good surface for subsequent passivation layer coating. The low undulation indicates that the specific surface area of ​​the semiconductor substrate 1 in the edge region is smaller. In the same coating process, a thicker passivation layer can be formed to meet the passivation performance requirements at the edge of the solar cell, ensuring the efficiency of the solar cell.

[0049] As a possible implementation manner, regarding “the doping concentration of the first doping layer is greater than the doping concentration of the second doping layer”, the doping concentration of the second doping layer is greater than or equal to zero.

[0050] See also Figure 1 When the doping concentration of the second doped layer is zero, a PN junction is formed between the semiconductor substrate 1 and the first doped layer within the first electrode region 100, while no PN junction exists in the first non-electrode region 101 of the semiconductor substrate 1. In other words, the first side 10 of the solar cell comprises both heavily doped and undoped regions. This effectively reduces the recombination level in the first non-electrode region 101 of the first side 10, increasing the cell's open-circuit voltage. Furthermore, high doping can be performed in the first electrode region 100, improving the contact resistance between the electrode and the first doped layer, reducing the cell's series resistance, and increasing the fill factor, thereby improving the efficiency of the solar cell.

[0051] Furthermore, the above “doping concentration of the first doping layer” may refer to the doping concentration on the surface of the first doping layer, or refer to the average concentration of the first doping layer at different positions along the thickness direction.

[0052] Similarly, the “doping concentration of the second doping layer” may refer to the doping concentration on the surface of the second doping layer, or refer to the average concentration of the second doping layer at different positions along the thickness direction.

[0053] “The doping concentration of the first doping layer is greater than the doping concentration of the second doping layer” may mean that the doping concentration at the surface of the first doping layer is greater than the doping concentration at the surface of the second doping layer. Alternatively, the average concentration of the first doping layer at different locations along the thickness direction is greater than the average concentration of the second doping layer at different locations along the thickness direction.

[0054] In some embodiments, see Figure 1 The above-mentioned first doped layer can be an additional film layer formed on the semiconductor substrate 1; or, the first doped layer is formed by performing a diffusion treatment on the first surface 10 of the semiconductor substrate 1, and at this time, the top surface of the first doped layer is coplanar with the first surface 10 of the semiconductor substrate 1.

[0055] In some embodiments, see Figure 1 The above-mentioned second doped layer can be an additional film layer formed on the semiconductor substrate 1; or, the second doped layer is formed by diffusion processing the first surface 10 of the semiconductor substrate 1, and the top surface of the second doped layer is coplanar with the first surface 10 of the semiconductor substrate.

[0056] As a possible implementation, see Figures 1 to 4 The semiconductor substrate 1 is an N-type silicon substrate, the first doped layer is a P-type doped layer, and the second doped layer is a P-type doped layer. The first doped layer and the second doped layer are diffusion layers on the surface of the semiconductor substrate 1. In this case, the surface of the first doped layer and the second doped layer is a single crystal silicon surface. The doping concentration of the second doped layer is set to be lower than the doping concentration of the first doped layer. This improves the passivation of the subsequent passivation layer on the surface of the semiconductor substrate 1, which is more important than the battery structure that provides additional doping layers.

[0057] As a possible implementation, the third texture structure includes one or more of a tower-base structure, a prismatic structure, an inverted pyramid structure, a prism structure, or a pyramid-shaped structure. This increases the shape selectivity of the third texture structure and broadens the application scenarios of the solar cell.

[0058] As a possible implementation, see Figure 1 The first texture structure 102 and / or the second texture structure 103 are pyramid-shaped structures. This helps increase the surface area of ​​the semiconductor substrate 1, improves the light trapping effect of the semiconductor substrate 1, and helps more light be refracted into the semiconductor substrate 1 through the areas where the first texture structure 102 and / or the second texture structure 103 are located and utilized by the semiconductor substrate 1, thereby achieving higher photoelectric conversion efficiency for the solar cell.

[0059] In an alternative approach, see Figure 1When the first texture structure 102 is a pyramid-shaped structure, the tower height of the first texture structure 102 is greater than or equal to 1 μm and less than or equal to 4 μm; the base size of the first texture structure 102 is greater than or equal to 1 μm and less than or equal to 5 μm. The base of the first texture structure 102 is square, rhombus, rectangle, parallelogram, approximately rhombus, or approximately rectangle. The base size of the first texture structure 102 can be the longest side, short side, diagonal, or the longest distance between the two endpoints of the base shape. The tower height and base size of the first texture structure 102 can be the tower height or base size of a single texture structure, or can be the average tower height or base size of the first texture structure 102 within a certain area. For example, in the range of 1 μm×1 μm, the tower height of the first texture structure 102 can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm, etc. The bottom surface size of the first texture structure 102 may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm.

[0060] In an alternative approach, see Figure 1 When the second texture structure 103 is a pyramid structure, the tower height of the second texture structure 103 is greater than or equal to 1 μm and less than or equal to 4 μm; the bottom surface size of the second texture structure 103 is greater than or equal to 1 μm and less than or equal to 5 μm. The bottom surface of the second texture structure 103 is square, rhombus, rectangle, parallelogram, approximately rhombus or approximately rectangle. The bottom surface size of the second texture structure 103 can be the long side, short side, diagonal or the longest distance between the two end points of the bottom surface shape. The tower height and bottom surface size of the second texture structure 103 can be the tower height or bottom surface size of a single texture structure, or the average value of the tower height or bottom surface size of the second texture structure 103 within a certain area. For example, in the range of 1 μm×1 μm, the tower height of the second texture structure 103 can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm or 4 μm, etc. The bottom surface size of the second texture structure 103 may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm.

[0061] See also Figure 1 The tower heights or bottom dimensions of the first texture structure 102 and the second texture structure 103 may be equal or unequal.

[0062] As a possible implementation, see Figures 1 to 5 , part of the edge area has a tunneling layer 3 and / or a doped conductive layer 4; the tunneling layer 3 and the doped conductive layer 4 are arranged on the first doping layer and / or the second doping layer; the first doping layer and the second doping layer have the same doping type, and the doping conductive layer 4 has an opposite doping type to the first doping layer and the second doping layer.

[0063] See also Figures 1 to 5 The chemical passivation of the tunneling layer 3 and the field passivation of the doped conductive layer 4 can significantly reduce the degree of recombination on the surface of the semiconductor substrate 1. The tunneling layer 3 and the doped conductive layer 4 can further passivate the edges of the cell, reducing recombination at the edges of the cell. In addition, since the tunneling layer 3 and / or the doped conductive layer 4 are provided in some edge areas, damage to the middle portion of the surface on the first surface 10 can be reduced during the process step of removing the tunneling layer 3 and / or the doped conductive layer 4 on the side surface 12, reducing the probability of damaging the first texture structure 102 and the second texture structure 103, and improving the light trapping effect on the front side.

[0064] See also Figures 1 to 5 As for the material and thickness of the tunneling layer 3, they can be set according to actual conditions and are not specifically limited here. For example, the material of the tunneling layer 3 may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbide. The thickness of the tunneling layer 3 is greater than or equal to 1 nm and less than or equal to 2 nm. For example, the thickness of the tunneling layer 3 may be 1 nm, 1.2 nm, 1.5 nm, 1.7 nm, 1.8 nm or 2 nm. Furthermore, the doped conductive layer 4 may be a doped polysilicon layer, and the doped polysilicon layer may be a phosphorus-doped polysilicon layer. Of course, it may also be doped with other substances and is not specifically limited here.

[0065] As a possible implementation, see Figure 2 The semiconductor substrate 1 further includes a plurality of side surfaces 12 located between the first surface 10 and the second surface 11 ; grooves 120 are provided on at least some of the side surfaces 12 , and the bottoms of the grooves 120 are lower than the surfaces of the side surfaces 12 .

[0066] See also Figure 2 When forming the doped conductive layer 4 on the second surface, the doped conductive layer 4 will also be formed by plating on the side surface 12 of the semiconductor substrate 1 and the first electrode region 100 of the first surface 10. The groove 120 provided on at least a portion of the side surface 12 is used to isolate the doped conductive layer 4 on the first surface 10 and the second surface, thereby preventing short circuits and edge leakage in the solar cell. The groove 120 can also increase the distance between the first surface 10 and the second surface, making it more difficult for the doped conductive layers 4 on the first surface 10 and the second surface to overlap at the side surface 12. In addition, during the preparation process, the semiconductor substrate 1 on the side of the battery is partially etched to remove the inner expansion layer formed in the semiconductor substrate 1 during the formation of the doped conductive layer 4, thereby reducing the possibility of short circuits caused by contact between doped conductive layers 4 of opposite polarities.

[0067] In some embodiments, see Figure 2When the solar cell is a whole solar cell, the grooves 120 may be provided on all four side surfaces 12 of the semiconductor substrate 1 , or the grooves 120 may be provided on at least one side surface 12 .

[0068] See also Figure 2 When the solar cell is a split solar cell, grooves 120 may be provided on three of the four side surfaces 12 of the semiconductor substrate 1 except the split side surface, or a groove 120 may be provided on at least one side surface 12 except the split side surface.

[0069] In some embodiments, participating Figure 2 , the height difference between the bottom of the groove 120 and the surface of the side surface 12 ( Figure 2 The height difference may be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, or 7 μm.

[0070] In some embodiments, see 1 to Figure 5 Along the thickness direction of the semiconductor substrate 1, the width of the groove 120 accounts for 50% to 95% of the width of the side surface 12. The width of the groove 120 ranges from 60 μm to 130 μm. For example, the width can be 50%, 55%, 60%, 65%, 70%, 75%, 80%, 86%, 90%, or 95%. Along the thickness direction of the semiconductor substrate 1, the width of the side surface 12 is 140 μm, and the width of the groove 120 can be 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 120 μm, or 130 μm. Providing the groove 120 within the aforementioned width range can reduce the probability of overlap of the doped layers (i.e., the first doped layer and / or the second doped layer) or the doped conductive layer 4 by increasing the area of ​​the side surface 12, thereby reducing the risk of leakage in the solar cell caused by overlap of the doped layers or the doped conductive layer 4 on the side surface 12.

[0071] In some embodiments, see 1 to Figure 5 The boundary between the sidewall of the groove 120 and the side surface 12 is wavy, so the ratio of the width of the groove 120 to the width of the side surface 12 is not equal everywhere on the solar cell, showing a random distribution feature.

[0072] Combined with the above description, see Figure 1 The above-mentioned first doped layer can be an additional film layer formed on the semiconductor substrate 1; or, the first doped layer is formed by performing a diffusion treatment on the first surface 10 of the semiconductor substrate 1, and at this time, the top surface of the first doped layer is coplanar with the first surface 10 of the semiconductor substrate 1.

[0073] The following describes how to obtain or calculate the height difference between the bottom of the groove and the surface of the side surface where the groove is located, taking three possible cases as examples. It should be noted that the following description is for understanding only and is not intended to be a specific limitation.

[0074] The first one: See Figure 1 and Figure 2 When the first doped layer is an additional film layer formed on the semiconductor substrate 1, the first distance between the bottom of the groove 120 and the outer side surface of the first doped layer and the thickness of the first doped layer formed on the side surface 12 where the groove 120 is located are obtained; then, the difference between the first distance and the thickness of the first doped layer is calculated, and the difference is the height difference between the bottom of the groove 120 and the surface of the side surface 12 where the groove 120 is located.

[0075] Second: See Figure 1 and Figure 2 When the first doped layer is an additional film layer formed on the semiconductor substrate 1, the height difference between the bottom of the groove 120 and the surface of the side surface 12 thereof is directly measured, and the side surface 12 is the interface between the semiconductor substrate 1 and the first doped layer.

[0076] The third method: when the first doping layer is formed by performing a diffusion process on the first surface 10 of the semiconductor substrate 1 , the height difference between the bottom of the groove 120 and the surface of the side surface 12 thereof is directly measured and obtained.

[0077] See also Figure 2 If the height difference between the bottom of the groove 120 and the surface of the side surface 12 is less than 0.5 μm, the depth of the groove 120 is relatively shallow. In this case, the groove 120 set on the side surface 12 cannot effectively isolate the doped conductive layer 4 on the first surface 10 and the second surface, and cannot ensure the complete removal of the inner expansion layer on the side surface 12 of the battery, resulting in an increased probability of short circuit and edge leakage in the solar cell. If the height difference between the bottom of the groove 120 and the surface of the side surface 12 is greater than 7 μm, the depth of the groove 120 is relatively deep. In this case, more of the side surface 12 of the semiconductor substrate 1 is removed, which will reduce the overall mechanical strength of the battery cell. In addition, solar cells use light to separate electrons and holes on the semiconductor substrate 1 to generate electricity. If the semiconductor substrate 1 is removed too much, the light absorption rate of the semiconductor substrate 1 is reduced, resulting in a decrease in the number of photogenerated carriers, i.e., holes and electrons, generated by the irradiation on the semiconductor substrate 1, and thus a decrease in the photoelectric conversion rate of the solar cell. Combining the above two aspects, the present application sets the height difference between the surface of the groove 120 and the surface of the side surface 12 thereof within a reasonable range. While avoiding short circuit and edge leakage of the solar cell, it ensures that the light absorption rate of the semiconductor substrate 1 is high, the photoelectric conversion rate of the solar cell will not be reduced, and it also ensures that the cell has sufficient mechanical strength.

[0078] In some embodiments, see Figure 2 The surface of the side surface 12 includes a surface close to the first surface 10 and a surface close to the second surface. The distance H1 between the bottom of the groove 120 and the surface of the side surface 12 close to the first surface 10 is greater than the distance H2 between the bottom of the groove 120 and the surface of the side surface 12 close to the second surface. Because H1 and H2 are not formed in the same process step, H2 is set to be smaller than H1 to reduce the etching depth of the side surface 12 of the solar cell and ensure the mechanical strength of the solar cell.

[0079] As a possible implementation, see Figures 1 to 5 Along the thickness direction A of the semiconductor substrate 1, the first electrode region 100 is higher than the first non-electrode region 101. Along the thickness direction of the semiconductor substrate 1, the distance L1 between the first electrode region 100 and the first non-electrode region 101 is greater than or equal to 2 μm and less than or equal to 7 μm. In this case, the first non-electrode region 101 is recessed relative to the first electrode region 100, allowing light to be reflected and absorbed within the groove 120, thereby reducing the reflectivity of the second texture structure 103 and the third texture structure.

[0080] See also Figures 2 to 4 The distance L1 between the first electrode region 100 and the first non-electrode region 101 may be the distance between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the top surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101. Exemplarily, the distance L1 between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101 may be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, or 7 μm, etc.

[0081] It is worth noting that see Figures 2 to 4 The top surface of the first electrode region 100 is formed by the vertices of multiple first texture structures 102. Due to the different sizes of different first texture structures 102, the top surface here is the plane formed by the vertices of the majority of the first texture structures 102 on the first electrode region 100. The proportion of the majority of the first texture structures 102 in the first electrode region 100 can be flexibly selected according to actual conditions. Similarly, the top surface of the first non-electrode region 101 is formed by the vertices of multiple second texture structures 103.

[0082] As a possible implementation, see Figures 1 to 5The reflectivity of the first electrode region 100 where the first texture structure 102 is located is greater than the reflectivity of the first non-electrode region 101 where the second texture structure 103 is located. The absence of grid lines on the surface of the first non-electrode region 101 where the second texture structure 103 is located, combined with the suede structure with lower reflectivity, allows for better utilization of incident light, improving light absorption and utilization, thereby increasing the photoelectric conversion efficiency of the solar cell.

[0083] As a possible implementation, see Figure 1 and Figure 2 The second surface 11 includes a second electrode region 110 and a second non-electrode region 111. The second electrode region 110 and the second non-electrode region 111 are alternately arranged on the second surface. The tunneling layer 3 is provided on the surface of the second electrode region 110, and the doped conductive layer 4 is provided in the second electrode region 110 and is located on the side of the tunneling layer 3 away from the semiconductor substrate 1. The surface of the second electrode region 110 includes a tower base structure, the undulation of the tower base structure is smaller than that of the pyramid structure, and the reflectivity of the surface in the area where the tower base structure is located is greater than the reflectivity of the surface in the area where the pyramid structure is located.

[0084] See also Figure 1 and Figure 2 , a second electrode region 110 and a second non-electrode region 111 are provided on the second surface 11. The second non-electrode region 111 is not provided with a tunneling layer 3 and a doped conductive layer 4. This can reduce the area of ​​the doped conductive layer 4 on the second surface 11, reduce parasitic absorption on the second surface 11, and improve the utilization rate of the incident light on the second surface 11 of the solar cell. During the preparation of the tunneling layer 3 and the doped conductive layer 4, the tunneling layer 3 and the doped conductive layer 4 are usually first deposited as a whole layer on the second surface 11. The tunneling layer 3 and the doped conductive layer 4 on the second non-electrode region 111 are then removed using laser, wet etching, or other methods. Therefore, arranging the second electrode region 110 higher than the second non-electrode region 111 ensures that while the tunneling layer 3 and the doped conductive layer 4 in the second non-electrode region 111 are removed, the inner expansion layer on the surface of the semiconductor substrate 1 in the second non-electrode region 111 is also removed. This reduces Auger recombination in the second non-electrode region 111 caused by the doping elements, reduces the probability of carrier recombination in the second non-electrode region 111, and improves the cell efficiency.

[0085] In some embodiments, see Figure 2 and Figure 5, along the thickness direction A of the semiconductor substrate, the second electrode region 110 is higher than the second non-electrode region 111. The distance L2 between the second electrode region 110 and the second non-electrode region 111 is greater than or equal to 2μm and less than or equal to 6μm. The distance L2 between the second electrode region 110 and the second non-electrode region 111 can be the distance between the top surface of the second electrode region 110 and the top surface of the second non-electrode region 111, or the distance between the bottom surface of the second electrode region 110 and the top surface of the second non-electrode region 111, or the distance between the bottom surface of the second electrode region 110 and the top surface of the second non-electrode region 111. Exemplarily, the distance L2 between the second electrode region 110 and the second non-electrode region 111 can be 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm or 6μm, etc.

[0086] See also Figures 1 to 5 If the distance between the second electrode region 110 and the second non-electrode region 111 along the thickness direction A of the semiconductor substrate is greater than 6μm, and the depth of the second non-electrode region 111 is deeper, then more of the second surface 11 of the semiconductor substrate 1 is removed, which will reduce the overall mechanical strength of the cell. Moreover, solar cells use light to separate electrons and holes on the semiconductor substrate 1 to generate electricity. If too much of the semiconductor substrate 1 is removed, the transmission path of light in the semiconductor substrate 1 will be reduced, and the light absorption rate of the semiconductor substrate 1 will be reduced, resulting in a decrease in the number of photogenerated carriers, i.e., holes and electrons, generated by irradiation on the semiconductor substrate 1, which will in turn reduce the photoelectric conversion rate of the solar cell. In this application, the distance between the surface of the second electrode region 110 and the surface of the second non-electrode region 111 along the thickness direction of the semiconductor substrate 1 is set within the above-mentioned value range, ensuring that the light absorption rate of the semiconductor substrate 1 is high, the photoelectric conversion rate of the solar cell will not be reduced, and also ensuring that the cell has sufficient mechanical strength.

[0087] In some embodiments, see Figures 1 to 5 In the process of texturing the second non-electrode area 111 of the second surface 11 to form the fourth texture structure 112, a portion of the semiconductor substrate 1 located in the second non-electrode area 111 is corroded and removed, so that along the thickness direction A of the semiconductor substrate, the surface of the second non-electrode area 111 is higher than the surface of the second electrode area 110.

[0088] See also Figures 1 to 5At this time, the surface of the second non-electrode area 111 is composed of the vertices of multiple fourth texture structures 112. Based on the different sizes of different fourth texture structures 112, the surface of the second non-electrode area 111 here is a plane formed by the vertices of most of the fourth texture structures 112 on the second non-electrode area 111. The proportion of most of the fourth texture structures 112 in the second non-electrode area 111 can be flexibly selected according to actual conditions.

[0089] In some embodiments, see Figures 1 to 5 Along the thickness direction A of the semiconductor substrate 1 , a projection of the first non-electrode region 101 on the first surface 10 at least partially overlaps with a projection of the second non-electrode region 111 on the first surface 10 .

[0090] See also Figures 1 to 5 In the actual production of solar cells, the second non-electrode region 111 is the laser active area. When the laser acts on the second surface 11 of the semiconductor substrate 1, it affects the first surface 10 of the semiconductor substrate 1, causing changes in the surface of the first surface 10 corresponding to the laser active area. Based on this, when the second non-electrode region 111 and the first non-electrode region 101 are overlapped along the thickness direction of the semiconductor substrate 1, the laser-affected area (i.e., the first non-electrode region 101) on the other side affected by the laser active area (i.e., the second non-electrode region 111) can be etched away during the process, reducing the area affected by the laser on the first and second surfaces 10, 11 of the semiconductor substrate 1, providing a good surface foundation for subsequent coating and electrode printing. When the second non-electrode region 111 and the first non-electrode region 101 are both recessed into the interior of the semiconductor substrate 1, if the second non-electrode region 111 and the first non-electrode region 101 completely correspond to each other along the thickness direction of the semiconductor substrate 1, then the thickness of the semiconductor substrate 1 located in the second non-electrode region 111 and the first non-electrode region 101 is smaller than the thickness of the semiconductor substrate 1 located in the second electrode region 110 and the first electrode region 100. That is, the thickness of the semiconductor substrate 1 in the non-electrode region is smaller than the thickness of the semiconductor substrate 1 in the electrode region, resulting in a significant reduction in the mechanical strength of the semiconductor substrate 1 in the non-electrode region. In the present application, the second non-electrode region 111 and the first non-electrode region 101 are staggered along the thickness direction of the semiconductor substrate 1, which can meet the mechanical strength requirements of the semiconductor substrate 1 and reduce or eliminate the probability of the semiconductor substrate 1 breaking.

[0091] In an alternative approach, see Figure 1 and Figure 2 The second non-electrode region 111 has a fourth texture structure 112. The fourth texture structure 112 includes a pyramid structure and a tower base structure. Compared with the second non-electrode region 111 without a texture structure, the reflectivity of the second non-electrode region 111 is significantly reduced. Combined with the optimization of the passivation process, the cell efficiency is not affected, further improving the cell bifaciality.

[0092] In an alternative approach, see Figure 1 and Figure 2 The second non-electrode region 111 has a fourth texture structure 112, and the size consistency of the fourth texture structure 112 is lower than the size consistency of the first texture structure 102. Exemplarily, the fourth texture structure 112 and the first texture structure 102 are pyramid structures.

[0093] See also Figure 1 and Figure 2 , size consistency refers to the consistency of the one-dimensional size and / or height of the bottom surface of the pyramid structure. Size consistency is the difference between the size of the pyramid structure in a certain area and the average value of the size of the pyramid structure in the area. For example, the one-dimensional size of the bottom surface of the pyramid structure in the unit area of ​​the first non-electrode area 101 and the one-dimensional size of the bottom surface of the pyramid structure of the second non-electrode area 111 can be statistically analyzed respectively, and the variance or range of the sizes of the pyramid structures of the first non-electrode area 101 and the second non-electrode area 111 can be calculated respectively. The variance or range of the pyramid structures of the first non-electrode area 101 and the second non-electrode area 111 are used as a reference for consistency. Different pyramid structures can compare the size of the variance or range to compare the quality of consistency. The smaller the variance or range, the better the size consistency.

[0094] As a possible implementation, see Figure 1 and Figure 2 The second non-electrode region 111 has a fourth texture structure 112 , the middle area of ​​the first non-electrode region 101 has a second texture structure 103 , and the size consistency of the second texture structure 103 is greater than the size consistency of the fourth texture structure 112 .

[0095] See also Figure 1 and Figure 2The first non-electrode area 101 is located on the light-receiving surface of the bifacial cell. Compared with the second non-electrode area 111, most of the incident light enters from the light-receiving surface. Therefore, better light trapping effect and passivation performance are required to ensure that the incident light enters the semiconductor substrate 1 from the light-receiving surface instead of being reflected or incident on the surface of the light-receiving surface and recombined by the recombination center on the light-receiving surface, thereby increasing the possibility of the incident light being transmitted to the laser photogenerated carriers in the semiconductor substrate 1, thereby increasing the utilization rate of the solar cell for the incident light. The second texture structure 103 located on the light-receiving surface has a higher dimensional consistency than the fourth texture structure 112 located on the backlight surface, which can ensure that different positions in the middle area of ​​the first non-electrode area 101 have a good light trapping effect, reducing the probability of incident light being reflected outside the solar cell. At the same time, the better dimensional consistency of the second texture structure 103 can provide a surface with relatively regular undulations, which is more beneficial to the thickness uniformity of the subsequent passivation layer 5, thereby improving the passivation performance of the surface of the first non-electrode area 101, reducing the possibility of incident light being recombined on the surface of the first non-electrode area 101, and ensuring that the incident light has a greater probability of being incident on the semiconductor substrate 1 at different positions of the first non-electrode area 101 and is not recombined by surface defects. The dimensional consistency of the second texture structure 103 is designed to be greater than the dimensional consistency of the fourth texture structure 112. The prepared second texture structure 103 and fourth texture structure 112 can respectively meet the light trapping and passivation requirements of the light-receiving surface of the solar cell, and the requirements for improving the light trapping performance of the backlight surface. Combined with the preparation process, the differentiated size settings of the second texture structure 103 and the fourth texture structure 112 can reduce the degree of etching of the second non-electrode area 111 of the solar cell while meeting the battery performance requirements, reduce the loss in the thickness direction of the semiconductor substrate 1, ensure the thickness of the battery cell, increase the utilization of the absorbed incident light, and ensure the mechanical strength of the battery cell.

[0096] See also Figure 1 and Figure 2The fourth texture structure 112 of the second non-electrode area 111 has better size consistency, which can improve the light trapping effect on the surface of the second non-electrode area 111. It can not only improve the light trapping effect of the back of the solar cell on the incident light, but also reduce the probability of light transmitted from the inside of the solar cell to the back being reflected out of the solar cell. At the same time, the first texture structure 102 in the first electrode area 100 and the second texture structure 103 in the first non-electrode area 101 have better size consistency. While enhancing the reflection of the front of the solar cell and improving the light trapping effect of the front of the solar cell, it also enhances the uniformity of the thickness of the passivation layer 5 at different positions when coating the passivation layer 5 on the front of the solar cell, improves the passivation performance of the front of the solar cell, and reduces the probability of incident light being recombined on the light-receiving surface. By matching the structures of the electrode area and the non-electrode area on the light-receiving surface and the backlight surface and the texture structures in different areas, the light utilization rate is improved from the two aspects of improving the light trapping effect and reducing the probability of incident light being recombined, thereby improving the efficiency of the solar cell.

[0097] As a possible implementation, see Figure 1 and Figure 2 The first electrode region 100 and / or the second electrode region 110 includes a collector electrode region and a bus electrode region. The extension direction of the collector electrode region intersects the extension direction or arrangement direction of the bus electrode region. The bus electrode region is wider than the collector electrode region. The bus electrode region includes continuously arranged bus electrodes or intermittently arranged bus electrodes, as well as a terminal line structure provided at the edge of the cell, which is used for welding interconnects such as solder ribbons in the module.

[0098] See also Figure 1 and Figure 2 Because the bus electrode has lower contact performance with the solar cell than the collector electrode, or because the bus electrode needs to be welded to interconnects such as welding ribbons, the bus electrode width is usually increased to increase the contact area with the solar cell surface or interconnects to improve the contact and welding performance of the bus electrode. Therefore, the width of the bus electrode area in the first electrode region 100 and the second electrode region 110 is set to be larger than the width of the collector electrode area. This ensures the contact and welding performance of the bus electrode with the solar cell while reducing the area of ​​the first electrode region 100 and the second electrode region 110.

[0099] In a second aspect, embodiments of the present invention further provide a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string includes a plurality of interconnects and a plurality of solar cells as described in the above technical solution. The interconnects are used to connect the plurality of solar cells in series to form a cell string, and the encapsulation layer is used to cover the surface of the cell string.

[0100] The beneficial effects of the photovoltaic module provided by the embodiment of the present invention are the same as the beneficial effects of the solar cell described in the above technical solution, and will not be described in detail here.

[0101] In a third aspect, the present invention also provides a method for manufacturing a solar cell. Figure 1 and Figure 2 , the manufacturing method of the solar cell includes: First, a semiconductor substrate 1 is provided; the semiconductor substrate 1 has a first surface 10 and a second surface 11 opposite to each other, and a plurality of side surfaces 12 located between the first surface 10 and the second surface 11. The first surface 10 and the second surface 11 are subjected to a texturing process to form a first texture structure 102; the first surface 10 includes a first electrode region 100 and a first non-electrode region 101; The first texture structure 102 can trap light, reduce the reflection of sunlight by the solar cell, and thus improve the performance of the solar cell.

[0102] For example, the semiconductor substrate 1 is cleaned, and then the first surface 10 and the second surface are textured using an alkaline texturing solution. Specific cleaning steps and texturing methods can be found in the prior art and are not specifically limited here. The shape, material, conductivity type, and light-receiving characteristics of the semiconductor substrate 1 are described above and are not further elaborated here.

[0103] Next, the first surface 10 of the semiconductor substrate 1 is diffused to form a first doped layer and a first doped oxide layer formed on the first doped layer; wherein the semiconductor substrate 1 and the first doped layer located in the first electrode region 100 have opposite conductivity types. At this time, the semiconductor substrate 1 and the first doped layer located in the first electrode region 100 form a PN junction.

[0104] Exemplarily, the doping source used in the diffusion process includes a Group III source. For example, the Group III source may be a boron source, a gallium source, an indium source, or the like.

[0105] In an optional embodiment, the Group III source is a boron source and the first doped oxide layer is a borosilicate glass layer. The borosilicate glass layer can protect the solar cell during subsequent processing, reducing the risk of etching the first electrode region 100 and ensuring the quality of the solar cell.

[0106] In some embodiments, a diffusion process is performed on the first surface 10 of the semiconductor substrate 1 to form a first doped layer and a first doped oxide layer formed thereon. The semiconductor substrate 1 is placed in a tubular diffusion furnace and a boron source, BCl₃ or BBr₃, is diffused in a nitrogen and oxygen atmosphere. The diffusion time and temperature can be set as needed. At this point, a first doped layer (e.g., a doped P+ layer) and a first doped oxide layer (e.g., a borosilicate glass layer) are formed.

[0107] Next, the first doped oxide layer located on the first non-electrode region 101 is removed; The following describes the removal of the first doped oxide layer located on the first non-electrode region 101 by taking two possible methods as examples. It should be understood that the following description is only for understanding and is not intended to be a specific limitation.

[0108] The first method: using a first laser to irradiate the first doped oxide layer located on the first non-electrode area 101; Specifically, a first laser process is used to irradiate the first doped oxide layer located within the first non-electrode region 101 to remove the first doped oxide layer located on the first non-electrode region 101. Exemplarily, the first laser irradiation damages the borosilicate glass layer located within the first non-electrode region 101, thereby reducing the protective effect of the borosilicate glass layer on the first non-electrode region 101. The first laser can be any of red, green, or violet light. The high-energy laser beam of a specific wavelength emitted by the laser acts on the borosilicate glass layer. The borosilicate glass layer absorbs the high-energy laser, causing atoms within the borosilicate glass layer to gain energy and generate vibrations, migration, and other movements, breaking the chemical bonds between the atoms, thereby disrupting the internal structure of the borosilicate glass layer and making it loose. Alternatively, at very high laser energy, the borosilicate glass layer will melt and vaporize within a short period of time, ultimately volatilizing and removing it. Regardless of whether the borosilicate glass layer is removed or loosened, its protective effect on the first non-electrode region 101 is significantly reduced. During subsequent alkaline cleaning, the insufficient protection of the borosilicate glass layer allows the alkali to corrode the semiconductor substrate 1.

[0109] It should be noted that after the first doped oxide layer is loosened by the first laser irradiation treatment, it can be immediately cleaned with a cleaning solution to remove the first doped oxide layer located on the first non-electrode region 101. Alternatively, after the first doped oxide layer is loosened by the first laser irradiation treatment, it can be left untreated and the loosened first doped oxide layer can be removed together with the cleaning of other film layers on the semiconductor substrate later.

[0110] Illustratively, the first laser wavelength in the first laser process is greater than or equal to 300 nm and less than or equal to 1200 nm. For example, the first laser wavelength can be 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm or 1200 nm, etc.

[0111] The second method is to pattern the first doped oxide layer to remove the first doped oxide layer located on the first non-electrode area 101. For example, a mask layer is formed on the first doped oxide layer located in the first electrode area 100. The mask layer is resistant to acid corrosion but can be easily removed by cleaning in an alkaline solution. Then, a first cleaning solution is used to remove the first doped oxide layer located in the first non-electrode area 101 that is not protected by the mask layer. For example, HF pickling is used. The borosilicate glass layer located in the first electrode area 100 is not affected due to the protection of the mask layer, while the borosilicate glass layer located in the first non-electrode area 101 is removed by HF corrosion. At this time, during the subsequent alkaline cleaning, the first non-electrode area 101 loses the protection of the borosilicate glass layer, allowing the alkali to corrode the semiconductor substrate 1. Then, a second cleaning solution is used to remove the mask layer. For example, an alkaline solution is used to clean and remove the mask layer.

[0112] As a possible implementation, the width W1 of the first non-electrode region 101 is greater than or equal to 200 μm and less than or equal to 800 μm. For example, the width W1 of the first non-electrode region 101 can be 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm, or 800 μm.

[0113] Next, the first doped layer in the first non-electrode region 101 is etched to form a second doped layer, so that the doping concentration of the second doped layer is lower than the doping concentration of the first doped layer; The doping concentration of the first doping layer located in the first electrode area 100 is greater than the doping concentration of the second doping layer located in the first non-electrode area 101. By reducing the doping concentration of the first non-electrode area 101, the high-concentration area on the front of the solar cell is reduced, the recombination problem caused by the high doping concentration on the surface of the semiconductor substrate 1 is reduced, and the open-circuit voltage of the battery is increased; at the same time, the first doping layer of the first electrode area 100 is retained to ensure that there is a smaller contact resistance between the electrode and the first doping layer, reduce the series resistance of the battery, and improve the fill factor, thereby improving the efficiency of the solar cell.

[0114] Exemplarily, a portion of the first doped layer located in the first non-electrode region 101 is etched away, and the remaining portion of the first doped layer is the second doped layer, in which case the doping concentration of the second doped layer is less than the doping concentration of the first doped layer. Alternatively, the first doped layer located in the first non-electrode region 101 is completely etched away, in which case the doping concentration of the second doped layer in the first non-electrode region 101 is zero. That is, the PN junction in the first non-electrode region 101 is removed, which effectively reduces the recombination level of the first non-electrode region 101 in the first surface 10, thereby increasing the open circuit voltage of the battery. At the same time, high doping can be performed in the first electrode region 100, thereby improving the contact resistance between the electrode and the first doped layer in the first electrode region 100, reducing the series resistance of the battery, and increasing the fill factor, thereby increasing the efficiency of the solar cell.

[0115] In some embodiments, the first non-electrode region 101 is etched to a depth greater than or equal to 1 μm and less than or equal to 5 μm. For example, the depth may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, or 5 μm.

[0116] As a possible implementation, the above-mentioned solar cell manufacturing method further includes the following steps: removing the first doped layer formed on the second surface 11 and the side surface 12 to remove the PN junction on the second surface 11 and the side surface 12. It should be noted that when the first surface 10 of the semiconductor substrate 1 is subjected to the diffusion process, a first doped layer and a first doped oxide layer are inevitably formed on at least a portion of the side surface 12 and the second surface 11. The at least a portion of the second surface 11 can be understood as: an edge region of the second surface 11 close to the side surface 12, or the entire second surface 11.

[0117] Exemplarily, a chain machine and a slot machine are used to polish the second surface 11 (backlight surface) and side surface 12, where the first doped layer is formed, to remove the PN junction on the second surface 11 and side surface 12 of the semiconductor substrate 1, thereby eliminating leakage caused by the PN junction on side surface 12. The specific processing process and the chemicals used can refer to the existing technology and are not specifically limited here. Furthermore, while cleaning the PN junction on the second surface 11 and side surface 12, the remaining borosilicate glass layer in the first non-electrode area 101 of the first surface 10 is also cleaned to facilitate the subsequent secondary texturing process.

[0118] Next, the first doped oxide layer and the first doped layer are removed from the second surface 11 and the portion of the side surface 12 adjacent to the second surface, thereby forming a recessed region on at least a portion of the side surface 12. The bottom surface of the recessed region is lower than the surface of the side surface 12. The removal method is not specifically limited herein, as long as it meets the requirements.

[0119] Next, see Figure 1 and Figure 2A tunneling layer 3 and a doped conductive layer 4 are deposited on the edge region of the first surface 10 and the second surface 11. The semiconductor substrate 1 and the doped conductive layer 4 located within the first electrode region 100 have the same conductivity type. For the first surface 10 of the semiconductor substrate 1, the tunneling layer 3 and the doped conductive layer 4 are disposed on the first doped layer or the second doped layer located in the edge region.

[0120] For example, a tunneling layer 3 and a doped conductive layer 4 are sequentially grown on the polished second surface 11, and the tunneling layer 3 and the doped conductive layer 4 are plated around the edge region of the first surface 10. Alternatively, a tunneling layer 3 and a doped conductive layer 4 are sequentially grown on the edge region of the first surface 10 and on the polished second surface 11. Simultaneously, a second doped oxide layer is grown on the doped conductive layer 4. During subsequent processing of the solar cell, the second doped oxide layer can provide protection, reducing the risk of etching the second electrode region 110, thereby ensuring the quality of the solar cell.

[0121] As a possible implementation, there are three possible methods for depositing the doped conductive layer 4: double-sided deposition using LPCVD (Low Pressure Chemical Vapor Deposition), single-sided deposition using LPCVD, and plasma-enhanced deposition using PECVD. LPCVD double-sided deposition and PECVD deposition of the doped conductive layer 4 ensure consistency between the doped conductive layer 4 formed on the first surface 10 and the second surface 11, enabling a uniform textured structure to be formed in the first non-electrode region 101 and the second non-electrode region 111 during subsequent texturing. When depositing the doped conductive layer on the second surface 11 using LPCVD, wrap-around plating may occur on the first surface 10, resulting in wrap-around and non-wrapped regions on the first surface 10. This, in turn, leads to inconsistent reaction times for subsequent secondary texturing in the wrap-around and non-wrapped regions of the first surface 10. By optimizing additives and formulations, it is possible to ensure that both the wrap-around and non-wrapped regions form a good textured structure, achieving the desired light trapping and passivation effects.

[0122] As for the material and thickness of the tunneling layer 3, they can be set according to actual conditions and are not specifically limited here. For example, the material of the tunneling layer 3 can include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbide. The doped conductive layer 4 can be a doped polysilicon layer, and the doped polysilicon layer can be a phosphorus-doped polysilicon layer. Of course, other substances can also be doped, and are not specifically limited here. The second doped oxide layer is a phosphosilicate glass layer.

[0123] At this time, the above-mentioned solar cell manufacturing method can be used to manufacture a tunneling oxide layer passivation contact cell to meet actual needs. Furthermore, the chemical passivation of the tunneling layer 3 and the field passivation of the doped conductive layer 4 can significantly reduce the degree of recombination on the surface of the semiconductor substrate 1. At the same time, the tunneling layer 3 can also ensure the effective tunneling of the majority carriers, and the doped conductive layer 4 can significantly improve the conductivity of the photogenerated carriers, thereby improving the open circuit voltage and fill factor of the solar cell. When the second surface 11 is stacked with the tunneling layer 3 and the doped conductive layer 4, the tunneling layer 3 and the doped conductive layer 4 form a passivation contact structure. The tunneling layer 3 allows the majority carriers to tunnel into the doped conductive layer 4 while blocking the recombination of the minority carriers, thereby allowing the majority carriers to be transported laterally in the doped conductive layer 4 and collected by the metal, greatly reducing the metal contact recombination current, improving the open circuit voltage and short circuit current of the battery, and thus improving the battery efficiency. When the tunneling layer 3 and the doped conductive layer 4 are stacked on the edge region of the first surface 10 , the tunneling layer 3 and the doped conductive layer 4 can further passivate the edge region of the first surface 10 , thereby improving the passivation performance of the cell edge.

[0124] As a possible implementation, after depositing the tunneling layer 3 and the doped conductive layer 4 on the edge region of the first surface 10 and the second surface 11, the above-mentioned method for manufacturing a solar cell further includes the following steps: irradiating the tunneling layer 3 and the doped conductive layer 4 on the second non-electrode region 111 with a second laser to etch the tunneling layer 3 and the doped conductive layer 4 on the second non-electrode region 111; Exemplarily, a second laser process is used to irradiate the second doped oxide layer within the second non-electrode region 111, i.e., the second doped oxide layer is laser patterned. The second laser irradiation area is the second non-electrode region 111. High-energy laser irradiation acts on the phosphosilicate glass layer in a short period of time, causing the phosphosilicate glass layer to be modified, loosened, or vaporized, reducing the protective capability of the phosphosilicate glass layer within the second non-electrode region 111. This ensures that a reaction rate gradient is formed during the subsequent alkaline etching process, allowing the second non-electrode region 111 to be etched as required, while the second electrode region 110 is unaffected due to the protection of the phosphosilicate glass layer. During the subsequent etching process, the doped conductive layer within the second electrode region 110 is protected by the phosphosilicate glass layer and is not corroded by the alkaline agent. However, due to the destruction of the phosphosilicate glass layer within the second non-electrode region 111, the doped conductive layer within the second non-electrode region 111 is corroded by the alkaline agent, and the alkaline agent further corrodes the tunneling layer 3 and the semiconductor substrate 1 downward. At this point, the tunneling layer 3 and doped conductive layer 4 located in the second electrode region 110 form a conductive contact layer, which corresponds one-to-one with the electrodes. The doped conductive layer 4 located in the second non-electrode region 111 on the second surface 11 is removed, effectively reducing parasitic absorption and increasing the battery current. The doped conductive layer 4 in the second electrode region 110 is retained, preventing corrosion of the semiconductor substrate 1 by the slurry during metallization and improving the battery's fill factor.

[0125] Exemplarily, the wavelength of the second laser in the second laser process is greater than or equal to 300 nm and less than or equal to 1200 nm. For example, the second laser wavelength may be 300 nm, 350 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, or 1200 nm. The width W2 of the second non-electrode region 111 is greater than or equal to 250 μm and less than or equal to 800 μm. For example, the width W2 of the second non-electrode region 111 may be 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm, or 800 μm.

[0126] It should be noted that if the second surface 11 of the solar cell does not need to form the above-mentioned conductive contact layer corresponding one-to-one with the electrode, the second doped oxide layer does not need to be laser patterned. In this case, the entire second surface is a tunneling layer and a doped conductive layer.

[0127] Next, a portion of the tunneling layer 3 and the doped conductive layer 4 located on the edge region of the first surface 10 is removed; For example, a chained single-side cleaning device is first used to remove the phosphosilicate glass layer (i.e., the second doped oxide layer) coated on the first side 10 (light-receiving side) of the semiconductor substrate 1, as well as the phosphosilicate glass layer coated on the side 12 of the semiconductor substrate 1. For example, the chained pickling process uses an HF aqueous solution at room temperature to remove the phosphosilicate glass layer, with the HF to water ratio being greater than or equal to 1:15 and less than or equal to 1:3. For example, the HF to water ratio can be 1:3, 2:15, 1:5, 4:15, or 1:15. Furthermore, an alkaline solution is used to remove the tunneling layer 3 and doped conductive layer 4 on the edge region of the first side, as well as the tunneling layer 3 and doped conductive layer 4 on the side 12. In this step, the alkaline solution further etches the side 12 of the semiconductor substrate 1 to form a recess 120. Specifically, the alkaline solution etches the bottom surface of a portion of the recessed region to form recess 120. It should be noted that whether the semiconductor substrate 1 corresponding to the edge region of the first side is further etched downward is not specifically defined and can be determined based on actual conditions.

[0128] See also Figure 1 and Figure 2 , a secondary texturing treatment is performed to form a texture structure (i.e., a second texture structure 103 and a third texture structure) on the first non-electrode area 101. Exemplarily, a mixed solution of sodium hydroxide solution and a texturing additive is used to form a texture structure on the first non-electrode area 101. The second texture structure 103 is located in the middle area of ​​the semiconductor substrate 1, and the third texture structure is located in the edge area of ​​the semiconductor substrate 1; the undulation of the third texture structure is less than that of the second texture structure 103. The above-mentioned first surface 10 includes a middle area and an edge area, and the above-mentioned edge area refers to the area close to the four edges of the semiconductor substrate 1, and the edge area surrounds the middle area. In some embodiments, the width range of the edge area is less than or equal to 3 mm, and the width of the edge area refers to the distance from the side of the edge area away from the edge of the semiconductor substrate 1 to the edge of the semiconductor substrate 1.

[0129] As a possible implementation method, if the alkaline solution only removes part of the doped conductive layer 4 formed on the first surface 10 of the semiconductor substrate 1, the tunneling layer 3 and the doped conductive layer 4 are arranged on the first doped layer or the second doped layer located in the edge area.

[0130] It's worth noting that after using a chained single-sided cleaning device to remove the phosphosilicate glass layer coated on the first surface 10 (light-receiving surface) of the semiconductor substrate 1 and the phosphosilicate glass layer coated on the side surface 12 of the semiconductor substrate 1, some or no phosphosilicate glass layer may remain on the first surface 10. Therefore, during the subsequent secondary texturing step, the morphology of the third texture structure near the edge of the semiconductor substrate 1 can vary. In some embodiments, the third texture structure includes one or more of a tower-shaped structure, a prismatic structure, an inverted pyramid structure, a truncated pyramid structure, or a pyramid-shaped structure.

[0131] As a possible implementation, combined with the above description, see Figure 1 and Figure 2 Since the phosphosilicate glass layer located in the second non-electrode area 111 is destroyed, the doped conductive layer 4 located in the second non-electrode area 111 is corroded by the alkaline solution, and the alkaline solution further corrodes the tunneling layer 3 and the semiconductor substrate 1 downward.

[0132] During the secondary texturing step, a fourth texture structure 112 is also formed in the second non-electrode region 111. Compared to a polished second non-electrode region 111, the reflectivity of the second non-electrode region 111 is significantly reduced. Combined with the optimized passivation process, the cell efficiency is not affected, thereby improving the cell bifaciality.

[0133] It is understandable that a texturing additive can be directly added to the alkaline solution for removing the tunneling layer 3 and the doped conductive layer 4 on the edge area of ​​the first surface 10, as well as the tunneling layer 3 and the doped conductive layer 4 on the side surface 12, so as to form a texture structure on the first non-electrode area 101, or a separate texturing alkaline solution can be directly used to etch the first non-electrode area 101 to form a texture structure.

[0134] Combined with the above description, see Figure 1 and Figure 2 In the present application, the bottom surface of a portion of the recessed area is etched to form a groove 120. When the doped conductive layer 4 is formed on the second surface 11, the doped conductive layer 4 will also be formed by plating on the side surface 12 of the semiconductor substrate 1 and the first electrode region 100 of the first surface 10. The groove 120 provided on at least part of the side surface 12 is used to isolate the doped conductive layer 4 on the first surface 10 and the second surface 11 to avoid short circuits and edge leakage in the solar cell; the groove 120 can also increase the distance between the first surface 10 and the second surface 11, and increase the difficulty of overlapping the doped conductive layers 4 on the first surface 10 and the second surface 11 at the side surface 12. In addition, during the preparation process, part of the semiconductor substrate 1 on the side surface 12 of the battery is etched to remove the inner expansion layer formed in the semiconductor substrate 1 during the formation of the doped conductive layer 4, thereby reducing the possibility of short circuits caused by contact between doped conductive layers 4 of opposite polarities.

[0135] In some embodiments, see Figures 1 to 5 When the solar cell is a whole solar cell, the grooves 120 may be provided on all four side surfaces 12 of the semiconductor substrate 1 , or the grooves 120 may be provided on at least one side surface 12 .

[0136] See also Figures 1 to 5 When the solar cell is a split solar cell, grooves 120 may be provided on three of the four side surfaces 12 of the semiconductor substrate 1 except the split side surface, or a groove 120 may be provided on at least one side surface 12 except the split side surface.

[0137] In some embodiments, see Figure 1 and Figure 2 The surface of the side surface 12 includes a surface close to the first surface 10 and a surface close to the second surface 11. The bottom of the groove 120 is lower than the surface of the side surface 12. The height difference between the bottom of the groove 120 and the surface of the side surface 12 is ( Figure 2 The height difference (H1 and H2 in FIG) is greater than or equal to 0.5 μm and less than or equal to 7 μm. Along the thickness direction of the semiconductor substrate 1, the width of the groove 120 is greater than or equal to 0.5 μm and less than or equal to 7 μm. For example, the height difference can be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, or 7 μm.

[0138] See also Figure 2If the height difference between the bottom of the groove 120 and the surface of the side surface 12 is less than 0.5 μm, the depth of the groove 120 is relatively shallow. In this case, the groove 120 set on the side surface 12 cannot effectively isolate the doped conductive layer 4 on the first surface 10 and the second surface 11, nor can it ensure the complete removal of the inner expansion layer on the side of the battery, resulting in an increased probability of short circuit and edge leakage in the solar cell. If the height difference between the bottom of the groove 120 and the surface of the side surface 12 is greater than 7 μm, the depth of the groove 120 is relatively deep. In this case, more of the side surface 12 of the semiconductor substrate 1 is removed, which will reduce the overall mechanical strength of the battery cell. In addition, solar cells use light to separate electrons and holes on the semiconductor substrate 1 to generate electricity. If the semiconductor substrate 1 is removed too much, the light absorption rate of the semiconductor substrate 1 is reduced, resulting in a decrease in the number of photogenerated carriers, i.e., holes and electrons, generated by the irradiation on the semiconductor substrate 1, and thus a decrease in the photoelectric conversion rate of the solar cell. Combining the above two aspects, the present application sets the height difference between the surface of the groove 120 and the surface of the side surface 12 thereof within a reasonable range. While avoiding short circuit and edge leakage of the solar cell, it ensures that the light absorption rate of the semiconductor substrate 1 is high, the photoelectric conversion rate of the solar cell will not be reduced, and it also ensures that the cell has sufficient mechanical strength.

[0139] In some embodiments, see Figure 1 and Figure 2 The surface of the side surface 12 includes a surface close to the first surface 10 and a surface close to the second surface 11. The distance H1 between the bottom of the groove 120 and the surface of the side surface 12 close to the first surface 10 is greater than the distance H2 between the bottom of the groove 120 and the surface of the side surface 12 close to the second surface 11. Because H1 and H2 are not formed in the same process step, H2 is set to be smaller than H1 to reduce the etching depth of the side surface 12 of the solar cell and ensure the mechanical strength of the solar cell.

[0140] See also Figure 1 and Figure 2The second texture structure 103 and the third texture structure located on the first surface 10 are beneficial to increasing the surface area of ​​the semiconductor substrate 1 and improving the light trapping effect of the semiconductor substrate 1, which is beneficial for more light to be refracted into the semiconductor substrate 1 through the area where the second texture structure 103 and the third texture structure are located and utilized by the semiconductor substrate 1, so that the solar cell has a higher photoelectric conversion efficiency. Since the first non-electrode area 101 is not blocked by the grid lines, the first non-electrode area 101 focuses on the light trapping effect and passivation performance of the front side of the cell, while the first electrode area 100 focuses on the contact performance and passivation performance. Based on the functional difference between the first electrode area 100 and the first non-electrode area 101, the first non-electrode area 101 needs to take into account both the light trapping effect and the passivation performance of the passivation layer coating. In the present application, the first non-electrode area 101 has a second texture structure 103 located in the middle area of ​​the semiconductor substrate 1 and a third texture structure located in the edge area of ​​the semiconductor substrate 1. The undulation of the third texture structure is less than that of the second texture structure 103. That is, in the present application, the first non-electrode region 101 extending to the edge region of the semiconductor substrate 1 has a third texture structure with relatively gentle undulations. The third texture structure can provide a good surface for the subsequent passivation layer to cover. At the same time, the undulations are small, indicating that the specific surface area of ​​the semiconductor substrate 1 located in the edge region is smaller. In the same coating process, a thicker passivation layer can be formed to meet the passivation performance of the edge of the solar cell and ensure the efficiency of the solar cell.

[0141] Combined with the above description, see Figure 1 and Figure 2 Since the alkaline solution corrodes downward the semiconductor substrate 1 located in the second non-electrode area 111, a portion of the semiconductor substrate 1 located in the second non-electrode area 111 is corroded and removed. At this time, along the thickness direction A of the semiconductor substrate 1, the surface of the second non-electrode area 111 is higher than the surface of the second electrode area 110.

[0142] In some embodiments, a distance L2 between the top surface of the second electrode region 110 and the top surface of the second non-electrode region 111 is greater than or equal to 2 μm and less than or equal to 6 μm along the thickness direction A of the semiconductor substrate 1. For example, the distance L2 between the top surface of the second electrode region 110 and the top surface of the second non-electrode region 111 may be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, or 6 μm, etc.

[0143] It should be noted that the top surface of the second non-electrode area 111 is composed of the vertices of multiple fourth texture structures 112. Based on the different sizes of different fourth texture structures 112, the top surface of the second non-electrode area 111 here is a plane formed by the vertices of most of the fourth texture structures 112 on the second non-electrode area 111. The proportion of most of the fourth texture structures 112 in the second non-electrode area 111 can be flexibly selected according to actual conditions.

[0144] As a possible implementation method, during the secondary texturing treatment, the volume ratio of alkali to additive in the alkali texturing tank is greater than or equal to 2:1 and less than or equal to 8:1, the temperature of the alkali tank is greater than or equal to 60°C and less than or equal to 85°C, and the time is greater than or equal to 2 min and less than or equal to 8 min. For example, the volume ratio of alkali to additive in the alkali texturing tank can be 2:1, 3:1, 4:1, 5:1, 6:1, 7:1 or 8:1, etc. The temperature of the alkali tank can be 60°C, 65°C, 70°C, 75°C, 80°C, 82°C or 85°C, etc. The time can be 2 min, 3 min, 3.5 min, 4 min, 4.5 min, 5 min, 5.5 min, 6 min, 6.5 min, 7 min, 7.5 min or 8 min, etc. It should be noted that in the secondary texturing treatment, the relevant parameters when forming the texture structure on the first non-electrode area 101 and the relevant parameters when forming the fourth texture structure 112 on the second non-electrode area 111 can be the same or different, as long as the above ranges are met.

[0145] As a possible implementation, see Figure 1 and Figure 2 , the first texture structure 102 and / or the second texture structure 103 is a pyramid structure.

[0146] In an alternative approach, see Figure 1When the first texture structure 102 (and / or the second texture structure 103) is a pyramidal structure, the pyramid height of the first texture structure 102 (and / or the second texture structure 103) is greater than or equal to 1 μm and less than or equal to 4 μm; the base size of the first texture structure 102 (and / or the second texture structure 103) is greater than or equal to 1 μm and less than or equal to 5 μm. The base of the first texture structure 102 may be a square, rhombus, rectangle, parallelogram, approximately rhombus, or approximately rectangular. The base size of the first texture structure 102 may be the longest side, short side, diagonal, or the longest distance between the two endpoints of the base shape. The pyramid height and base size of the first texture structure 102 may be the pyramid height or base size of a single texture structure, or the average of the pyramid height or base size of the first texture structures 102 within a certain area. The same applies to the second texture structure 103. For example, within a range of 1 μm×1 μm, the tower height may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm, etc. The bottom surface size may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, or 5 μm, etc. The tower heights or bottom surface sizes of the first texture structure 102 and the second texture structure 103 may be equal or unequal.

[0147] As a possible implementation, see Figure 1 and Figure 2 When forming the second texture structure 103 , the alkaline texturing formula etches downwardly the semiconductor substrate 1 in the middle area. At this time, along the thickness direction A of the semiconductor substrate 1 , the first electrode region 100 is higher than the first non-electrode region 101 .

[0148] In some embodiments, see Figure 1 and Figure 2 , along the thickness direction of the semiconductor substrate 1, the distance L1 between the first electrode region 100 and the first non-electrode region 101 is greater than or equal to 2 μm and less than or equal to 7 μm. Figure 2 and Figure 3 The distance L1 between the first electrode region 100 and the first non-electrode region 101 may be the distance between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the top surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101. Exemplarily, the distance L1 between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101 may be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, or 7 μm, etc.

[0149] It is worth noting that see Figure 1 and Figure 2 The top surface of the first electrode region 100 is formed by the vertices of multiple first texture structures 102. Due to the different sizes of different first texture structures 102, the top surface here is the plane formed by the vertices of the majority of the first texture structures 102 on the first electrode region 100. The proportion of the majority of the first texture structures 102 in the first electrode region 100 can be flexibly selected according to actual conditions. Similarly, the top surface of the first non-electrode region 101 is formed by the vertices of multiple second texture structures 103.

[0150] Next, see Figure 1 and Figure 2 A passivation layer 5 is formed on the doped conductive layer 4 and the first surface 10 and the second surface 11 of the semiconductor substrate 1 .

[0151] The material and thickness of the passivation layer 5 can be set according to actual conditions and are not specifically limited here. For example, the material of the passivation layer can include one or more of silicon nitride, hydrogenated silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, zinc oxide, and hafnium dioxide.

[0152] As a possible implementation, see Figure 1 and Figure 2 The passivation layer 5 can be a single-layer film, such as a single silicon nitride layer; it can also be a stack of multiple films, such as a stack of aluminum oxide layers and silicon nitride layers, or only a silicon nitride stacked structure.

[0153] In some embodiments, see Figure 1 and Figure 2 An aluminum oxide passivation layer 50 is grown on the doped conductive layer 4 and on the first surface 10 and the second surface 11 of the semiconductor substrate 1 by atomic layer deposition, and then a silicon nitride passivation layer 51 is deposited on the aluminum oxide passivation layer 50 located on the doped conductive layer 4 and the first surface 10 and the second surface 11 by plasma enhanced chemical vapor deposition (PECVD) equipment.

[0154] The passivation layer 5 can passivate the surface of the semiconductor substrate 1, reduce surface recombination, and improve the open circuit voltage and fill factor. At the same time, the silicon nitride passivation layer 51 can protect the semiconductor substrate 1 and reduce pollution and mechanical damage.

[0155] Next, see Figure 1 and Figure 2Electrodes are formed on the passivation layer 5, with the electrodes being located in the first electrode region 100 and the second electrode region 110, respectively. Specifically, the first electrode 6 is formed on the first electrode region 100 of the first surface 10 of the semiconductor substrate 1, and the second electrode 7 is formed on the second electrode region 110 of the second surface 11 of the semiconductor substrate 1, using a printing device.

[0156] For example, see Figure 1 and Figure 2 The semiconductor substrate 1 is metallized, and electrodes are formed using methods such as screen printing or electroplating. The paste used to make the first electrode 6 and the second electrode 7 can be made of silver alloy, silver-copper alloy, copper alloy, nickel alloy, etc. The paste is solidified through a low-temperature sintering process, and then light injection is used to enhance the hydrogen passivation effect. Finally, laser-assisted contact formation (LECO) is used to form a good ohmic contact, completing the production of the solar cell.

[0157] In summary, see Figure 1 and Figure 2 The solar cell manufacturing method provided in this application, after performing a diffusion treatment on the first and second surfaces 10 and 11 of the semiconductor substrate 1, uses a first laser process or patterning process to remove the first doped oxide layer located on the first non-electrode region 101. A secondary texturing process is then performed to form a second texture structure 103 and a third texture structure on the first non-electrode region 101, and a fourth texture structure 112 on the second non-electrode region 111. Compared to existing technologies, the solar cell manufacturing method provided in this application achieves the same results with a shorter process flow, improving the feasibility of mass production.

[0158] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any appropriate manner in any one or more embodiments or examples. The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate comprising a first side and a second side facing each other; The first surface includes a first electrode area and a first non-electrode area; The surface of the first electrode region has a first texture structure; the first non-electrode region has a second texture structure and a third texture structure, the second texture structure is located in a middle region of the semiconductor substrate, the third texture structure is located in an edge region of the semiconductor substrate, and the width of the edge region is less than or equal to 3 mm; the undulation of the third texture structure is less than that of the second texture structure; a first doping layer, disposed in the first electrode region; The second doping layer is arranged in the first non-electrode area; the doping concentration of the first doping layer is greater than the doping concentration of the second doping layer.

2. The solar cell according to claim 1, wherein The third texture structure includes one or more of a tower base structure, a prismatic structure, an inverted pyramid structure, a prism structure or a pyramid structure.

3. The solar cell according to claim 1, wherein The first texture structure and / or the second texture structure is a pyramid structure.

4. The solar cell according to claim 1 or 3, characterized in that The reflectivity of the first electrode region where the first texture structure is located is greater than the reflectivity of the first non-electrode region where the second texture structure is located.

5. The solar cell according to claim 1, wherein Part of the edge region has a tunneling layer and / or a doped conductive layer; The tunneling layer and the doped conductive layer are arranged on the first doped layer and / or the second doped layer; The first doping layer and the second doping layer have the same doping type, and the doping type of the doped conductive layer is opposite to that of the first doping layer and the second doping layer.

6. The solar cell according to claim 1 or 5, characterized in that The semiconductor substrate further includes a plurality of side surfaces located between the first surface and the second surface; At least part of the side surfaces are provided with grooves, the bottoms of the grooves being lower than the surfaces of the side surfaces; and the height difference between the bottoms of the grooves and the surfaces of the side surfaces being greater than or equal to 0.5 μm and less than or equal to 7 μm.

7. The solar cell according to claim 6, characterized in that The surface of the side surface includes a surface close to the first surface and a surface close to the second surface; A distance between a bottom of the groove and a surface of the side surface close to the first surface is greater than a distance between the bottom of the groove and a surface of the side surface close to the second surface.

8. The solar cell according to claim 1, wherein Along the thickness direction of the semiconductor substrate, the first electrode region is higher than the first non-electrode region; The distance between the first electrode area and the first non-electrode area is greater than or equal to 2 μm and less than or equal to 7 μm.

9. The solar cell according to claim 1, wherein The second surface includes a second electrode area and a second non-electrode area; the second electrode area and the second non-electrode area are alternately arranged on the second surface; a tunneling layer, the tunneling layer being disposed on a surface of the second electrode region; a doped conductive layer, the doped conductive layer being disposed in the second electrode region and located on a side of the tunneling layer away from the semiconductor substrate; Along the thickness direction of the semiconductor substrate, the second electrode region is higher than the second non-electrode region; a distance between the second electrode region and the second non-electrode region is greater than or equal to 2 μm and less than or equal to 6 μm; Alternatively, along the thickness direction of the semiconductor substrate, a projection of the first non-electrode area on the first surface and a projection of the second non-electrode area on the first surface at least partially overlap; Alternatively, the second non-electrode region has a fourth texture structure, and the size consistency of the fourth texture structure is lower than the size consistency of the first texture structure.

10. A photovoltaic module, characterized in that: The photovoltaic module comprises: A battery string, comprising a plurality of interconnecting members and a plurality of solar cells according to any one of claims 1 to 9; the interconnecting members are used to connect the plurality of solar cells in series to form the battery string; The encapsulation layer is used to cover the surface of the battery string.

11. A method for manufacturing a solar cell, characterized in that: include: providing a semiconductor substrate; The semiconductor substrate has a first surface and a second surface opposite to each other; the first surface and the second surface are subjected to a texturing process to form a first texture structure; the first surface includes a first electrode area and a first non-electrode area; Performing a diffusion process on the first surface of the semiconductor substrate to form a first doped layer and a first doped oxide layer formed on the first doped layer; removing the first doped oxide layer located on the first non-electrode region; etching the first doped layer in the first non-electrode region to form a second doped layer, so that the doping concentration of the second doped layer is less than the doping concentration of the first doped layer; depositing a tunneling layer and a doped conductive layer on an edge region of the first surface and the second surface, and removing portions of the tunneling layer and the doped conductive layer located on the edge region of the first surface; After partially removing the tunneling layer and the doped conductive layer located on the edge region of the first surface, a secondary texturing process is performed to form a texture structure on the first non-electrode region.

12. The method for manufacturing a solar cell according to claim 11, wherein: The second surface includes a second electrode area and a second non-electrode area; After depositing a tunneling layer and a doped conductive layer on the edge region of the first surface and the second surface, and before removing a portion of the tunneling layer and the doped conductive layer located on the edge region of the first surface, the method for manufacturing a solar cell further comprises: irradiating the tunneling layer and the doped conductive layer on the second non-electrode region with a second laser to etch the tunneling layer and the doped conductive layer located on the second non-electrode region; In the secondary texturing step, a fourth texture structure is further formed in the second non-electrode area.

13. The method for manufacturing a solar cell according to claim 11 or 12, characterized in that: The semiconductor substrate includes a plurality of side surfaces located between the first surface and the second surface; Before depositing the tunneling layer and the doped conductive layer on the edge region of the first surface and the second surface, the method for manufacturing the solar cell further includes: removing the first doped oxide layer and the first doped layer from the second surface and a portion of the side surface close to the second surface, thereby forming a recessed area on at least a portion of the side surface, wherein a bottom surface of the recessed area is lower than a surface of the side surface; While removing a portion of the tunneling layer and the doped conductive layer located on an edge region of the first surface, the method for manufacturing a solar cell further includes: etching a portion of the bottom surface of the recessed area to form a groove; The surface of the side surface includes a surface close to the first surface and a surface close to the second surface, and the distance between the bottom of the groove and the surface close to the first surface among the surfaces of the side surface is greater than the distance between the bottom of the groove and the surface close to the second surface among the surfaces of the side surface.

14. The method for manufacturing a solar cell according to claim 12, wherein: After the secondary texturing process, the solar cell manufacturing method further includes: forming a passivation layer on the doped conductive layer and on the first and second surfaces of the semiconductor substrate; Electrodes are formed on the passivation layer, and the electrodes are respectively located in the first electrode region and the second electrode region.

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