Solar cell, manufacturing method and photovoltaic module

Abstract

The invention discloses a solar cell, a manufacturing method and a photovoltaic module, and relates to the technical field of photovoltaics. The solar cell comprises a semiconductor substrate, at least a partial area of a first surface is a suede area, and a plurality of similar pyramids are formed on the suede area; the first semiconductor layer at least covers the suede area of the first surface, at least part of the first semiconductor layer on the side face of the pyramid-like structure comprises a first crystallization area, and the first crystallization area extends in the circumferential direction of the pyramid-like structure; and the crystallization degree of the first crystallization region is greater than that of the rest region, covered on the pyramid-like side surface, of the first semiconductor layer. In the manufacturing process, the first semiconductor layer can be rapidly grown firstly, and then the crystallization degree in the first crystallization region of the first semiconductor layer is increased through laser irradiation, so that the contact resistance of the first semiconductor layer is reduced, and the contact resistance and transmission loss are reduced while the production efficiency is ensured.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell, a manufacturing method, and a photovoltaic module. Background Art

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight strikes the pn junction of the solar cell's semiconductor, forming new hole-electron pairs. Under the influence of the built-in electric field within the pn junction, photogenerated holes flow to the p region, and photogenerated electrons flow to the n region. Once the circuit is connected, current is generated. For a grown film of the same thickness, amorphous silicon layers grow faster than crystals (microcrystals or nanocrystals). However, amorphous silicon lacks the high electrical conductivity of crystalline silicon, resulting in higher contact resistance and transmission losses, which are detrimental to the electrical contact of the solar cell. Summary of the Invention

[0003] The purpose of this application is to provide a solar cell and a manufacturing method thereof, and a photovoltaic module to ensure production efficiency while reducing contact resistance and transmission loss.

[0004] In order to achieve the above objectives, this application provides the following technical solutions:

[0005] A solar cell comprising:

[0006] A semiconductor substrate having a first surface and a second surface opposite to each other, wherein at least a portion of the first surface is a velvet surface, and a plurality of pyramid-like structures are formed on the velvet surface;

[0007] The first semiconductor layer at least covers the velvet surface of the first surface, and the first semiconductor layer on at least a portion of the pyramid-like side includes a first crystallized region, and the first crystallized region extends along the circumference of the pyramid-like; the degree of crystallization of the first crystallized region is greater than the degree of crystallization of the remaining area of ​​the first semiconductor layer covering the pyramid-like side.

[0008] In the solar cell provided by the present application, a first crystallized region is formed locally in the first semiconductor layer covering the side of the pyramid-like structure. The first crystallized region extends along the circumference of the pyramid-like structure to form an overall ring or an open ring. The grains in the first crystallized region are enlarged, the number of grains is increased, and the grain interface is reduced, thereby reducing the contact resistance of the first crystallized region of the first semiconductor layer, thereby reducing the contact resistance between the first crystallized region and other conductive components, thereby reducing the transmission loss of carriers collected in the first semiconductor layer. In this way, in the actual manufacturing process, the first semiconductor layer containing amorphous silicon can be quickly grown first, and then the degree of crystallization in the first crystallized region of the first semiconductor layer can be increased by laser irradiation, thereby reducing the contact resistance of the first semiconductor layer, so as to ensure production efficiency while reducing contact resistance and transmission loss.

[0009] A method for manufacturing a solar cell, comprising:

[0010] A semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, at least a portion of the first surface is a velvet surface, and a plurality of pyramid-like structures are formed on the velvet surface;

[0011] forming a first semiconductor layer on the first surface, wherein the first semiconductor layer at least covers the velvet surface of the first surface; the first semiconductor layer includes at least one processed area;

[0012] At least a portion of the processing area is irradiated with laser light, so that the crystallization degree of at least a local area of ​​the first semiconductor layer irradiated by the laser covering the side of the pyramid is increased to form a first crystallized area, which extends along the circumference of the pyramid.

[0013] The laser can irradiate part or all of the processing area to increase the degree of crystallization of at least a local area of ​​the first semiconductor layer covering the side of the pyramid-like layer to form a first crystallized region. The first crystallized region can extend along the circumference of the pyramid-like layer to form a full ring or an open ring, thereby helping to reduce the contact resistance of the first crystallized region of the first semiconductor layer, and further reducing the contact resistance between the first crystallized region and other conductive components, thereby helping to reduce the transmission loss of carriers collected in the first semiconductor layer.

[0014] A photovoltaic module comprises a plurality of solar cells as described in any one of the above or solar cells formed by any one of the above manufacturing methods and at least one interconnector, wherein the interconnector connects two adjacent solar cells in series or in parallel. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 A top-view SEM image of a solar cell provided in an embodiment of the present application;

[0017] Figure 2 for Figure 1 Enlarged view of the middle dashed box area;

[0018] Figure 3 A schematic top view of a first semiconductor layer covering a pyramid-like structure of a solar cell provided in an embodiment of the present application;

[0019] Figure 4 An image characterizing the contact resistance of a solar cell provided in an embodiment of the present application obtained by testing it using a conductive atomic force microscope (C-AFM);

[0020] Figure 5 A partial cross-sectional SEM image of a solar cell provided in an embodiment of the present application;

[0021] Figure 6 A partial cross-sectional SEM image of a solar cell provided in another embodiment of the present application;

[0022] Figure 7 A local SEM image of the first semiconductor layer covering the side of the pyramid-like structure of the solar cell provided by an embodiment of the present application;

[0023] Figure 8 A local SEM image of the first semiconductor layer covering the side of the pyramid-like structure of a solar cell provided by another embodiment of the present application;

[0024] Figure 9 A local SEM image of the first semiconductor layer covering the side of the pyramid-like structure of a solar cell provided by another embodiment of the present application;

[0025] Figure 10 A top-view SEM image of a solar cell provided in another embodiment of the present application;

[0026] Figure 11 for Figure 10 A magnified view of a local area;

[0027] Figure 12 A cross-sectional TEM image of a solar cell provided in another embodiment of the present application;

[0028] Figure 13 TEM image of the pyramid-like structure provided in the embodiment of the present application;

[0029] Figure 14 A top-view TEM image of a pyramid-like structure provided in an embodiment of the present application;

[0030] Figure 15 A top view of a solar cell provided in another embodiment of the present application;

[0031] Figure 16 A schematic diagram of a method for manufacturing a solar cell according to an embodiment of the present application Figure 1 ;

[0032] Figure 17 A schematic diagram of a method for manufacturing a solar cell according to an embodiment of the present application Figure 2 ;

[0033] Figure 18 A schematic diagram of a method for manufacturing a solar cell according to an embodiment of the present application Figure 3 ;

[0034] Figure 19 A schematic diagram of a method for manufacturing a solar cell according to another embodiment of the present invention Figure 1 ;

[0035] Figure 20 A schematic diagram of a method for manufacturing a solar cell according to another embodiment of the present invention Figure 2 ;

[0036] Figure 21 A schematic diagram of a method for manufacturing a solar cell according to another embodiment of the present invention Figure 3 ;

[0037] Figure 22 A top view of a solar cell provided in one embodiment of the present application;

[0038] Figure 23 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0039] Figure 24 A top view of a solar cell provided in accordance with another embodiment of the present application.

[0040] Reference numerals:

[0041] 2a-first crystallized region, 2b-second crystallized region;

[0042] 10-semiconductor substrate, 11-intrinsic semiconductor layer, 12-first semiconductor layer, 13-processing area, 13a-laser irradiation area, 14-interface layer, 15-second semiconductor layer, 16-functional layer, 17-transparent conductive layer, 18-first electrode, 19-second electrode, A-first region, B-second region, C-overlapping region. DETAILED DESCRIPTION

[0043] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0044] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0046] In the description of this application, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on this application.

[0047] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0048] During the manufacturing process of solar cells, the applicant discovered that, for amorphous silicon films of the same thickness, they grow faster than crystalline (microcrystal or nanocrystal) films. However, amorphous silicon lacks the high electrical conductivity of crystalline silicon, resulting in higher contact resistance and transmission losses, which are detrimental to the electrical contact of solar cells.

[0049] In view of the above situation, the present application provides a solar cell to reduce contact resistance and transmission loss while ensuring production efficiency, thereby improving the photoelectric conversion efficiency of the solar cell.

[0050] See also Figure 1-Figure 2 The solar cell provided in the embodiment of the present application includes a semiconductor substrate 10 and a first semiconductor layer 12. The semiconductor substrate 10 has a first surface and a second surface opposite to each other, i.e., two surfaces opposite to each other along the thickness direction of the semiconductor substrate 10 are the first surface and the second surface, respectively. The first surface may correspond to the backlight side of the solar cell, and the second surface may correspond to the light-facing side of the solar cell; alternatively, the first surface may correspond to the light-facing side of the solar cell, and the second surface may correspond to the backlight side of the solar cell.

[0051] The first semiconductor layer 12 is disposed on the first surface. The first semiconductor layer 12 may be formed entirely or partially on the first surface. When the first semiconductor layer 12 is partially formed on the first surface, the first semiconductor layer 12 may be distributed in a plurality of stripes or in a plurality of "F"-like shapes. The first semiconductor layer 12 may be additionally formed on the first surface of the semiconductor substrate 10 using a deposition technique, or may be formed within the semiconductor substrate 10 by diffusion, ion implantation, or other methods.

[0052] At least a portion of the first surface is a velvet surface, on which a plurality of pyramid-like structures are formed. The first semiconductor layer 12 covers at least the velvet surface of the first surface. Thus, the first semiconductor layer 12 is disposed on the velvet surface, and the side of the first semiconductor layer 12 facing away from the semiconductor substrate 10 has an undulating morphology substantially similar to that of the velvet surface. In this case, the first semiconductor layer 12 has a larger specific surface area, which can increase the contact area between the first semiconductor layer 12 and other conductive components, further reducing carrier transmission losses.

[0053] The material of the first semiconductor layer 12 includes amorphous silicon and / or nanocrystalline silicon. The amorphous silicon and / or nanocrystalline silicon material contains more hydrogen, so that the first semiconductor layer 12 contains more hydrogen, which is beneficial to hydrogenating the dangling bonds on the surface of the semiconductor substrate 10 and reducing surface defects, thereby having a higher passivation effect on the semiconductor substrate 10.

[0054] The first semiconductor layer 12 on at least a portion of the pyramid-like side surface includes a first crystallized region 2a, and the first crystallized region 2a extends along the circumference of the pyramid-like surface. Specifically, a straight line passing through the top of the pyramid-like surface and perpendicular to the semiconductor substrate 10 is the vertical centerline of the pyramid-like surface, and the circumference of the pyramid-like surface refers to the direction surrounding the vertical centerline. The first crystallized region 2a extends along the side surface of the pyramid-like surface and around the vertical centerline of the pyramid-like surface. Specifically, the first crystallized region 2a can extend along the circumference of the pyramid-like surface to form a full ring or an open ring, wherein the open ring can be a half ring, a 1 / 4 ring, a 2 / 3 ring, etc.

[0055] The degree of crystallization of the first crystallized region 2a is greater than the degree of crystallization of the remaining areas of the first semiconductor layer 12 covering the pyramid-like side surfaces. That is, the degree of crystallization of the first crystallized region 2a, which is an entire ring or an open ring, is greater than that of the remaining areas of the first semiconductor layer 12 covering the pyramid-like side surfaces. In this application, a greater degree of crystallization may refer to an increased crystallization rate, a larger grain size, and / or a larger number of grains. The first crystallized region 2a includes nanocrystalline silicon and / or microcrystalline silicon.

[0056] It is understandable that, with other factors being equal, the smaller the degree of crystallization of the semiconductor layer, the smaller the grains in the semiconductor layer. The first semiconductor layer 12 comprises amorphous silicon, whose atomic arrangement is disordered, and the grains in the first semiconductor layer 12 are small and have more grain interfaces, resulting in a higher resistance of the first semiconductor layer 12. The first semiconductor layer 12 comprises nanocrystalline silicon, whose atomic arrangement is also mostly disordered, and the grains in the first semiconductor layer 12 are small and have more grain interfaces, resulting in a higher resistance of the first semiconductor layer 12 relative to microcrystalline silicon and nanocrystalline silicon with larger nanocrystalline grains or a larger proportion of nanocrystalline grains. In the solar cell provided in the present application, a first crystallized region 2a is formed locally in the first semiconductor layer 12 covering the side of the pyramid-like structure. The first crystallized region 2a extends along the circumference of the pyramid-like structure to form an entire ring or an open ring. The grain size, the number of grains, and the number of grain interfaces within the first crystallized region 2a are increased, thereby reducing the contact resistance of the first crystallized region 2a of the first semiconductor layer 12, thereby reducing the contact resistance between the first crystallized region 2a and other conductive components, thereby reducing the transmission loss of carriers collected in the first semiconductor layer 12. In this way, in an actual manufacturing process, the first semiconductor layer 12 containing amorphous silicon can be rapidly grown first, and then the degree of crystallization within the first crystallized region 2a of the first semiconductor layer 12 can be increased by laser irradiation, thereby forming nanocrystalline silicon or even microcrystalline silicon in the laser irradiated area (generally, the number of microcrystalline silicon particles formed is small or even no, because the formation of microcrystalline silicon particles requires a large amount of laser energy or exposure time, and its damage is large; nanocrystalline silicon should account for the majority), thereby reducing the contact resistance of the first semiconductor layer 12, thereby ensuring production efficiency while reducing contact resistance and transmission loss.

[0057] Generally, the first semiconductor layer 12 includes a processed area irradiated by the laser and a non-processed area not irradiated by the laser. The position of the processed area irradiated by the laser will produce a first crystallized area on its pyramid-like structure, and the position where the crystallized area is produced will reduce the final contact resistance. The testing method is as follows: Figure 4 As shown, Figure 4The image characterizing the contact resistance of the solar cell provided by the embodiment of the present application is obtained by testing it with a conductive atomic force microscope (C-AFM). As can be seen from the figure, in the current image collected by scanning the probe at different positions under the same given voltage difference, the left part is the laser crystallized processing area, and the position with multiple bright spots has a strong current signal due to the small contact resistance. This is caused by the increase in the degree of crystallization of the first crystallized area 2a. The right side is the non-processed area of ​​the first semiconductor layer 12 that has not been irradiated by the laser. Because of its large contact resistance, the current signal is weak. The strong current area of ​​the laser processed area presents multiple discrete point-shaped or block-shaped areas, which means that the area with low contact resistance presents multiple discrete point-shaped or block-shaped areas, among which the block-shaped area can be formed by partially connecting the point-shaped area; other areas with weak current are basically connected as a whole. This setting can take into account both reducing contact resistance and ensuring the passivation effect. It can be seen that the contact resistance at multiple bright spot positions on the left is smaller than that at other positions. The positions on the left with a large number of bright spots are the laser processed areas, which present multiple discrete bright spots, indicating that discrete crystallization areas will be formed at multiple pyramid positions. In the non-laser processed area, there are basically no bright spots, the degree of crystallization is low, and the contact resistance is relatively large.

[0058] Moreover, when the first crystallized region 2a extends along the circumference of the pyramid to form an integral ring or an open ring, it is beneficial to make the contact resistance between the first crystallized region 2a of the first semiconductor layer 12 and other conductive components more balanced, preventing large current differences at different positions of the first crystallized region 2a, thereby avoiding local overheating caused by current differences.

[0059] It should be noted that, in the present application, a greater degree of crystallization means that the grain size of the first crystallized region 2a is relatively larger, and / or the number of grains is relatively larger, and / or the crystallization rate is relatively higher, compared to other areas of the first semiconductor layer 12 covering the side of the pyramid-like structure. For example, when the first semiconductor layer 12 is amorphous silicon, nanocrystalline grains will be generated in the first crystallized region 2a (i.e., the grain size becomes larger, and a small number of microcrystalline particles may also be generated at the same time). At the same time, the amorphous silicon material that originally had basically no grains will also produce nanocrystalline grains in the first crystallized region 2a (i.e., the number of grains increases), which will also increase the final crystallization rate. Of course, these three may appear alone or in combination. If the first semiconductor layer 12 is nanocrystalline silicon (meaning that the first semiconductor layer 12 is mainly nanocrystalline grains, which may also include part of amorphous silicon and microcrystalline silicon), it will also produce nanocrystalline grain growth in the first crystallization region 2a (that is, the grain size becomes larger, which may be larger nanocrystalline grains or even microcrystalline grains), and it may also regenerate nanocrystalline grains internally (that is, the number of grains increases), which will also improve the final crystallization rate. Of course, these three may appear alone or in combination. Figure 6-Figure 9As shown, the first semiconductor layer 12 is an amorphous silicon layer. The portion within the dotted box covering the side of the pyramid-like structure has a significantly increased degree of crystallization. That is, each first crystallized region 2a may include multiple discrete regions with orderly lattices, which can be considered as grains with a nanometer size, i.e., nanocrystalline silicon. Generally, the grain size of nanocrystalline silicon in the narrow sense is between 1-100nm, while the grain size of microcrystalline silicon in the narrow sense is generally between 100-1000nm. It should be noted that in some terms, the broad term microcrystalline silicon can include nanocrystalline silicon, i.e., microcrystalline silicon can be a more general concept.

[0060] In some embodiments, the first crystallization region 2a is discontinuously arranged along the circumference of the pyramid, that is, the first crystallization region 2a is intermittently arranged. In this way, during the process of laser irradiation to form the first crystallization region 2a, the laser energy and irradiation time used can be appropriately reduced to reduce the damage of the laser to the semiconductor substrate 10 and ensure the passivation effect.

[0061] In some embodiments, as Figure 3 As shown, the first crystallized region 2a is continuously and uninterruptedly arranged along the circumference of the pyramid, so that the area with increased crystallization degree is larger and the transmission resistance is lower, while ensuring that the passivation is not damaged, thereby reducing the transmission loss of the carriers collected in the first semiconductor layer 12.

[0062] In some embodiments, as Figure 1-Figure 3 as well as Figure 5 As shown, there are multiple first crystallized regions 2a, and the multiple first crystallized regions 2a are spaced apart along the height direction of the pyramid. That is, the portion of the first semiconductor layer 12 covering the side of the pyramid includes multiple first crystallized regions 2a, and the multiple first crystallized regions 2a are spaced apart in sequence from the bottom to the top of the pyramid, with a gap between adjacent first crystallized regions 2a. Using this technical solution, during the process of laser irradiation to form multiple first crystallized regions 2a, the laser irradiated areas do not overlap, that is, the laser irradiating the multiple first crystallized regions 2a does not repeat. As a result, the laser irradiated areas are less affected by the laser thermal radiation, thereby increasing the degree of crystallization of the laser-irradiated portion of the first semiconductor layer 12 to form the first crystallized regions 2a while preventing damage to the laser-irradiated areas due to the action of the laser. This reduces contact resistance and transmission loss while ensuring the power generation performance of the solar cell.

[0063] In some embodiments, the spacing between the multiple first crystallized regions 2a is substantially uniform (less than 10 nm) along the extension direction of the pyramid-like side edges. Here, the side edges refer to the ridges of the side of the pyramid extending obliquely from the bottom to the top. Using this technical solution, during the process of forming the multiple first crystallized regions 2a by laser irradiation, the spacing between the laser-irradiated areas is uniform. This simplifies the setting of laser parameters during processing, reduces processing difficulty, and improves the processing efficiency of the multiple first crystallized regions 2a.

[0064] In some embodiments, the spacing between the plurality of first crystallized regions 2a gradually decreases along the direction in which the side edges of the pyramid extend. Specifically, the spacing between the plurality of first crystallized regions 2a can be gradually reduced from the bottom to the top of the pyramid. This arrangement allows the portion of the first semiconductor layer 12 covering the pyramid-like side surface near the top to have a larger area with an increased degree of crystallization, which helps reduce the contact resistance of the first semiconductor layer 12 covering the pyramid-like side surface near the top, thereby reducing the current transmission loss of the aforementioned portion. At the same time, the portion of the first semiconductor layer 12 covering the pyramid-like side surface near the bottom to have a lower degree of crystallization is larger, ensuring that the portion of the first semiconductor layer 12 covering the pyramid-like side surface near the bottom still has a high passivation effect on the velvet surface, reducing the number of defects on the velvet surface and improving the operating efficiency of the solar cell. As can be seen from the above, using this technical solution, the portion of the first semiconductor layer 12 covering the pyramid-like side surface near the bottom can still maintain a good passivation effect, while the portion of the first semiconductor layer 12 covering the pyramid-like side surface near the top to have a lower contact resistance, thus achieving a balance between contact resistance and passivation effect.

[0065] In some embodiments, the width of the first crystallized region 2a refers to the distance the first crystallized region 2a extends in a direction parallel to the side of the pyramid-like structure. If the width of the first crystallized region 2a is too large, the laser irradiation area will be larger, and the first semiconductor layer 12 may be easily damaged during the laser irradiation process. Furthermore, if the width of the first crystallized region 2a is too large, the spacing between adjacent first crystallized regions 2a will be reduced. During the laser irradiation process, adjacent first crystallized regions 2a may thermally affect each other and damage the first semiconductor layer 12. Therefore, in this technical solution, the width of the first crystallized region 2a is set to be less than or equal to 100 nm to reduce laser damage to the first semiconductor layer 12.

[0066] Considering that if the width of the first crystallized region 2a is too small, the purpose of reducing the transmission resistance cannot be achieved, in this technical solution, in order to take into account both the transmission resistance of the first crystallized region 2a and the damage to the first semiconductor layer 12, the width of the first crystallized region 2a is set within a reasonable range of 10nm to 50nm, so as to reduce the transmission resistance while reducing the damage of the laser to the first semiconductor layer 12.

[0067] For example, the width of the first crystallized region 2 a may be 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, 10 nm, or 5 nm.

[0068] On the one hand, if the spacing between adjacent first crystallized regions 2a is too large, the area of ​​the first crystallized regions 2a will be reduced, which will fail to achieve the purpose of reducing the transmission resistance. On the other hand, if the spacing between adjacent first crystallized regions 2a is too small, the laser irradiating the two adjacent first crystallized regions 2a may damage the first semiconductor layer 12 during the irradiation process, thereby reducing the power generation efficiency of the solar cell. In this technical solution, in order to take into account the above two aspects, the spacing between any adjacent first crystallized regions 2a ranges from 50nm to 500nm, so as to reduce the transmission resistance while reducing the damage of the laser to the first semiconductor layer 12. For example, the spacing between any adjacent first crystallized regions 2a can be 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm or 500nm.

[0069] In some embodiments, the surface of the first semiconductor layer 12 generally has tiny protrusions and depressions, and the roughness can refer to the degree of unevenness caused by the micro-protrusions / micro-depressions on the surface. The roughness of the first crystallized region 2a is greater than the roughness of the remaining areas of the first semiconductor layer 12 covering the pyramid-like side. That is, per unit area, the number of protrusions and / or depressions on the surface of the first crystallized region 2a is greater than the number of protrusions and / or depressions in the remaining areas of the first semiconductor layer 12 covering the pyramid-like side; and / or the average height of the multiple protrusions on the surface of the first crystallized region 2a is greater than the average height of the multiple protrusions in the remaining areas of the first semiconductor layer 12 covering the pyramid-like side; and / or the arrangement of the protrusions and / or depressions on the surface of the first crystallized region 2a is more disordered than the arrangement of the protrusions and / or depressions in the remaining areas of the first semiconductor layer 12 covering the pyramid-like side. By adopting this technical solution, the roughness of the first crystallized region 2a is greater, thereby increasing the surface area of ​​the first crystallized region 2a, reducing the contact resistance between the first crystallized region 2a and other conductive components, and further reducing the transmission loss; at the same time, it is beneficial to increase the adhesion between the first crystallized region 2a and other conductive components, preventing the first crystallized region 2a from detaching from other conductive components.

[0070] In some embodiments, as Figure 10-12As shown, the portion of the first semiconductor layer 12 covering the top of the pyramid-like structure includes a second crystallized region 2b. The degree of crystallization of the second crystallized region 2b is greater than the degree of crystallization of the first semiconductor layer 12 in the area outside the first crystallized region 2a covering the side of the pyramid-like structure. In this technical solution, the degree of crystallization of the second crystallized region 2b is relatively large, that is, the grain size of the second crystallized region 2b is relatively large, and / or the number of grains is relatively large, and / or the crystallization rate is relatively high. The second crystallized region 2b includes nanocrystalline silicon and / or microcrystalline silicon. The specific situation of the degree of crystallization of the second crystallized region 2b can be referred to the description of the degree of crystallization of the first crystallized region 2a above, and will not be repeated here.

[0071] By adopting the above technical solution, the degree of crystallization of the part of the first semiconductor layer 12 covering the top of the pyramid-like layer is increased to form a second crystallized region 2b. The grains in the second crystallized region 2b are enlarged, the number of grains is increased, and the grain interface is reduced, which is conducive to further reducing the contact resistance of the first semiconductor layer 12, and further helping to reduce the transmission loss of the carriers collected in the first semiconductor layer 12.

[0072] In some embodiments, as Figure 12 As shown, the second crystallization region 2b includes bubbles, so that the light irradiated to the bubbles can be scattered back into the semiconductor substrate 10 through the inner wall of the bubbles, thereby improving the light absorption and utilization rate. The shape of the bubbles can be any shape such as round, spherical, ellipsoidal, linear, etc. Among them, the bubbles can be in a closed form. The interior of the bubbles is generally hollow, and a small amount of semiconductor material can also exist. The bubbles can also be in an open form, and the inner diameter of the bubbles is larger than the diameter at the opening of the bubbles. For example, a part of the bubbles formed inside the first semiconductor layer 12 is in a closed form, and another part of the bubbles formed on the surface of the first semiconductor layer 12 away from the semiconductor substrate 10 is in an open form. The maximum size of the open-form bubbles is larger than the size of the opening on the surface of the first semiconductor layer 12 away from the semiconductor substrate 10, that is, the opening size of the open-form bubbles is relatively small.

[0073] In some embodiments, the orthographic projection of the second crystallized region 2b on the semiconductor substrate 10 is circular, elliptical, square or irregular, that is, the orthographic projection of the second crystallized region 2b on the semiconductor substrate 10 can be any shape and is not limited here.

[0074] In some embodiments, the equivalent radius of the orthographic projection of the second crystallized region 2b on the semiconductor substrate 10 is 50 nm to 600 nm. This keeps the area of ​​the second crystallized region 2b of the first semiconductor layer 12 within a reasonable range, thereby reducing the laser energy used and reducing laser damage to the semiconductor substrate 10; while also ensuring that the second crystallized region 2b has a low transmission resistance. Exemplarily, the equivalent radius of the orthographic projection of the second crystallized region 2b on the semiconductor substrate 10 is 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, or 600 nm.

[0075] In some embodiments, along the thickness direction of the semiconductor substrate 10, the first crystallized region 2a extends from the side of the first semiconductor layer 12 facing away from the semiconductor substrate 10 toward the semiconductor substrate 10; the thickness of the first crystallized region 2a is less than or equal to the thickness of the first semiconductor layer 12. Specifically, when the thickness of the first crystallized region 2a is less than the thickness of the first semiconductor layer 12, the first crystallized region 2a is formed only in the region of the first semiconductor layer 12 near the surface facing away from the semiconductor substrate 10. With this technical solution, the degree of crystallization is increased at least in the region near the surface of the first semiconductor layer 12 facing away from the semiconductor substrate 10, thereby reducing the transmission resistance and transmission loss between the first semiconductor layer 12 and other conductive components while reducing the processing difficulty of the first crystallized region 2a.

[0076] In other embodiments, the thickness of the first crystallized region 2a is less than or equal to 2 / 3 of the thickness of the first semiconductor layer 12. This configuration allows the first crystallized region 2a to be formed within 2 / 3 of the thickness of the first semiconductor layer 12 near the surface facing away from the semiconductor substrate 10. This reduces the transmission resistance and transmission loss between the first semiconductor layer 12 and other conductive components while preventing excessive laser energy from reaching the semiconductor substrate 10 and damaging it. For example, the thickness of the first crystallized region 2a can be 2 / 3, 1 / 3, 1 / 2, 3 / 5, etc., of the thickness of the first semiconductor layer 12.

[0077] In some embodiments, the quasi-pyramid can be a pyramid with a sharp top angle; alternatively, the quasi-pyramid can be a quasi-pyramid with rounded chamfers; or alternatively, the quasi-pyramid can be a quasi-pyramid with a flattened top angle. In this case, the quasi-pyramid can have at least the three aforementioned examples, which helps improve the applicability of the solar cell provided by the embodiment of the present invention in different application scenarios. In addition, there is no need to strictly control the manufacturing precision to obtain a quasi-pyramid with a single morphology, which reduces the process difficulty and helps improve the yield of the solar cell.

[0078] In some embodiments, as Figure 13 and Figure 14As shown, the side of the pyramid-like surface includes irregular jagged protrusions or depressions. With this arrangement, the side shape of the pyramid-like surface is more irregular, so that the velvet structure has a larger specific surface area, lower reflectivity, and better light trapping effect, which can increase the short-circuit current and ultimately improve the photoelectric conversion efficiency of the solar cell. During the manufacturing process, the pyramid-like velvet surface of the cleaned semiconductor substrate 10 is auxiliary polished and velvet-etched again using polishing and velvet-making solutions. The etching rate of the solution on each crystal direction of crystalline silicon is adjusted using additives. Irregular etching is performed on the sidewalls of the pyramid-like velvet surface, and the pyramid-like surface is further etched inward, so that the width of the pyramid-like surface is gradually reduced, and the angle between the side surface and the base surface is gradually increased, forming a tower-like velvet structure on the silicon surface with lower reflectivity; finally, irregular jagged protrusions or depressions are formed on the side of the pyramid-like surface.

[0079] In some embodiments, as Figure 13 As shown, the pyramid-like side includes a first sub-cone surface ( Figure 13 The part between L3 and L4), the third sub-cone near the top ( Figure 13 The part between L1-L2) and the second sub-cone surface between the first sub-cone surface and the third sub-cone surface ( Figure 13 The portion between L2-L3 in the middle). The plane perpendicular to the thickness direction of the semiconductor substrate 10 is the first plane, and the angle between the first sub-cone surface and the first plane is 50°-55°; and / or, the angle between the second sub-cone surface and the first plane is 55°-85°; and / or, the angle between the third sub-cone surface and the first plane is 55°-80°. In this technical solution, from the bottom to the top of the pyramid-like structure, the inclination angle of the side surface of the pyramid-like structure (that is, the angle with the first plane) changes, so that the side surface of the pyramid-like structure forms a serrated protrusion or depression, thereby making the velvet structure have a larger specific surface area, lower reflectivity, better light trapping effect, and improve the photoelectric conversion efficiency of the solar cell. Among them, the inclination angle of the first sub-cone surface is smaller than the inclination angle of the second sub-cone surface, and the inclination angle of the second sub-cone surface is larger than the inclination angle of the third sub-cone surface. As a result, the connection between the first sub-cone surface and the second sub-cone surface forms a protrusion extending along the circumferential direction, and the connection between the second sub-cone surface and the third sub-cone surface forms a depression extending along the circumferential direction.

[0080] For example, the angle between the first sub-conical surface and the first plane is 50°, 51°, 52°, 53°, 54°, or 55°, etc. The angle between the second sub-conical surface and the first plane is 55°, 58°, 60°, 62°, 65°, 68°, 70°, 72°, 75°, 78°, 80°, 82°, or 85°, etc. The angle between the third sub-conical surface and the first plane is 55°, 58°, 60°, 62°, 65°, 68°, 70°, 72°, 75°, 78°, or 80°, etc.

[0081] In some embodiments, along the thickness direction of the semiconductor substrate 10, the height of the first sub-cone surface accounts for 20% to 30% of the overall height of the pyramid-like structure; the height of the second sub-cone surface accounts for 40% to 60% of the overall height of the pyramid-like structure; and the height of the third sub-cone surface accounts for 20% to 30% of the overall height of the pyramid-like structure. For example, the height of the first sub-cone surface accounts for 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, or 30% of the overall height of the pyramid-like structure. The height of the second sub-cone surface accounts for 40%, 42%, 45%, 48%, 50%, 52%, 55%, 58%, or 60% of the overall height of the pyramid-like structure. The height of the third sub-cone surface accounts for 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, or 30% of the overall height of the pyramid-like structure. Alternatively, the height of the first sub-cone surface accounts for 25% of the overall height of the pyramid-like structure, the height of the second sub-cone surface accounts for 50% of the overall height of the pyramid-like structure, and the height of the third sub-cone surface accounts for 25% of the overall height of the pyramid-like structure. In some other embodiments, the first sub-cone surface and the second sub-cone surface may be included, or the second sub-cone surface and the third sub-cone surface may be included, or more sub-cone surfaces with different inclination angles may be included, and the junctions of adjacent sub-cone surfaces may form protrusions or depressions extending along the circumferential direction.

[0082] Corresponding to this type of pyramid morphology is that at least part of the first crystallized region 2a is arranged corresponding to the protrusion or depression, that is, the first crystallized region 2a extends along the protrusion or depression, and the degree of crystallization at the protrusion or depression is greater than the degree of crystallization of the first semiconductor layer 12 on both sides of the protrusion or depression. This arrangement makes it easier to form the first crystallized region 2a under conditions of less laser energy or laser action time, while taking into account the passivation effect. Of course, under this type of pyramid morphology, part of the first crystallized region 2a may still be formed at a non-protruding or concave position, thereby increasing the crystallized area and reducing the contact resistance.

[0083] In some embodiments, the solar cell further includes a second semiconductor layer 15. The second semiconductor layer 15 has a conductivity type opposite to that of the first semiconductor layer 12, so as to collect and conduct electrons and holes, respectively, thereby facilitating the formation of photocurrent. Specifically, the second semiconductor layer 15 can be formed additionally on the semiconductor substrate 10 through a deposition technique, or can be formed within the semiconductor substrate 10 through diffusion, ion implantation, or other methods. The second semiconductor layer can be polycrystalline silicon, single crystal silicon, amorphous silicon, microcrystalline silicon, or nanocrystalline silicon.

[0084] The solar cell can be a double-sided contact cell, with the second semiconductor layer 15 provided on the second surface. In this technical solution, at least a portion of the second surface is a velvet surface, on which a plurality of pyramid-like structures are formed, and the second semiconductor layer 15 at least covers the velvet surface of the second surface. The second semiconductor layer 15 may include amorphous silicon and / or nanocrystalline silicon, and the portion of the second semiconductor layer 15 covering the side of the pyramid-like structure includes a third crystallized region, which extends along the circumference of the pyramid-like structure to form a full ring or an open ring to reduce the contact resistance between the third crystallized region and other conductive components, thereby facilitating the reduction of the transmission loss of the carriers collected in the second semiconductor layer 15. Of course, in some other embodiments, when the second semiconductor layer 15 may include single crystal silicon, polycrystalline silicon and / or microcrystalline silicon, the entire layer does not need to be crystallized, and the second semiconductor layer 15 as a whole has the same degree of crystallization. In some other embodiments, the second surface may be a polished surface.

[0085] The solar cell can also be a back contact cell, in which the second semiconductor layer 15 is provided on the first surface, and the first semiconductor layer 12 and the second semiconductor layer 15 are alternately distributed. The first semiconductor layer 12 and the second semiconductor layer 15 can be alternately distributed in strips on the first surface, or can be alternately distributed in interdigitated shapes. In this technical solution, the second semiconductor layer 15 can also be covered on the velvet surface of the first surface, and the second semiconductor layer 15 includes amorphous silicon and / or nanocrystalline silicon. The portion of the second semiconductor layer 15 covering the side of the pyramid-like layer includes a third crystallization region, and the third crystallization region extends along the circumference of the pyramid-like layer to form a full ring or an open ring. Of course, in some other embodiments, when the second semiconductor layer 15 can include single crystal silicon, polycrystalline silicon and / or microcrystalline silicon, it does not need to be crystallized as a whole, and the second semiconductor layer 15 as a whole has the same degree of crystallization.

[0086] When the solar cell is a back-contact cell, the width of the first semiconductor layer 12 can be 300um to 1000um. For example, the width of the first semiconductor layer 12 is 300um, 400um, 500um, 600um, 700um, 800um, 900um, or 1000um. Alternatively, the width of the first semiconductor layer 12 can be 450um to 600um. The width of the second semiconductor layer 15 can be 100um to 400um. For example, the width of the second semiconductor layer 15 is 100um, 150um, 200um, 250um, 300um, 350um, or 400um. Alternatively, the width of the first semiconductor layer 12 can be 100um to 350um. An isolation region is defined between the first semiconductor layer 12 and the second semiconductor layer 15 . The width of the isolation region is 20 um to 200 um, for example, 20 um, 30 um, 50 um, 80 um, 100 um, 120 um, 150 um, 180 um or 200 um.

[0087] When the second semiconductor layer 15 is amorphous silicon or nanocrystalline silicon, the characteristics and parameters of the second semiconductor layer 15 and its third crystallized region may refer to those of the first semiconductor layer 12 and are not described in detail here.

[0088] In some embodiments, the solar cell provided herein further includes a first electrode 18 formed on a side of the first semiconductor layer 12 facing away from the semiconductor substrate 10. The orthographic projection of the first electrode 18 on the semiconductor substrate 10 at least partially overlaps with the orthographic projection of the first crystallized region 2a on the semiconductor substrate 10. This technical solution facilitates the timely removal of carriers collected by the first semiconductor layer 12 through the first crystallized region 2a and the first electrode 18, thereby improving current collection efficiency.

[0089] The first electrode 18 may be made of silver, copper, aluminum, or alloys thereof. Specifically, the first electrode 18 may be formed by screen printing, electroplating, sputtering, or evaporation.

[0090] In some embodiments, the solar cell provided herein further includes a transparent conductive layer 17. The transparent conductive layer 17 is formed at least on the side of the first semiconductor layer 12 facing away from the semiconductor substrate 10. The first electrode 18 is formed on the side of the transparent conductive layer 17 facing away from the semiconductor substrate 10. The transparent conductive layer 17 has a high electrical conductivity and can promptly conduct collected carriers, thereby reducing the carrier recombination rate. Specifically, the transparent conductive layer 17 can be formed by deposition or other methods. The material of the transparent conductive layer 17 can include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. The transparent conductive layer 17 can be a single-layer thin film or a laminated thin film.

[0091] In some embodiments, the solar cell provided in the present application also includes an intrinsic semiconductor layer 11 formed between the first semiconductor layer 12 and the semiconductor substrate 10, and the intrinsic semiconductor layer 11 includes intrinsic amorphous silicon and / or intrinsic nanocrystalline silicon. Using this technical solution, the intrinsic semiconductor layer 11 and the first semiconductor layer 12 can form a selective contact structure, which has an excellent interface passivation effect, and can achieve selective collection of carriers, reduce the carrier recombination rate in the area of ​​the semiconductor substrate 10 where the first semiconductor layer 12 is formed, and further improve the photoelectric conversion efficiency of the solar cell.

[0092] In terms of thickness, along the thickness direction of the semiconductor substrate 10, the intrinsic semiconductor layer 11 has a thickness of 2 nm to 15 nm. For example, the thickness of the intrinsic semiconductor layer 11 can be 2 nm, 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, etc. The thickness of the first semiconductor layer 12 is 10 nm to 60 nm. For example, the thickness of the first semiconductor layer 12 is 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, or 60 nm. The thickness of the transparent conductive layer 17 is 10 nm to 60 nm. For example, the thickness of the transparent conductive layer 17 is 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, or 60 nm.

[0093] In some embodiments, the solar cell provided in the present application further includes an interface layer 14 formed between the first semiconductor layer 12 and the semiconductor substrate 10. The interface layer 14 and the second semiconductor layer 15 form a passivation contact structure, which has an excellent interface passivation effect and can achieve selective collection of carriers, reduce the carrier recombination rate in the area where the semiconductor substrate 10 forms the second semiconductor layer 15, and further improve the photoelectric conversion efficiency of the solar cell. The material of the above-mentioned interface layer 14 can be determined based on the material of the second semiconductor layer 15. For example: when the second semiconductor layer 15 includes a doped polycrystalline silicon layer, the interface layer 14 is a tunneling oxide layer; for another example: when the second semiconductor layer 15 includes a doped amorphous silicon layer, the interface layer 14 includes an intrinsic amorphous silicon layer. The embodiment of the present invention does not specifically limit the material of the interface layer 14.

[0094] In actual applications, the embodiments of the present invention do not specifically limit the material and conductivity type of the semiconductor substrate 10. For example, the semiconductor substrate 10 may be a silicon substrate. Alternatively, the semiconductor substrate 10 may be a substrate made of any semiconductor material, such as a silicon germanium substrate, a germanium substrate, or a gallium arsenide substrate. The conductivity type of the semiconductor substrate 10 may be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate 10.

[0095] Regarding the first semiconductor layer 12 and the second semiconductor layer 15, in terms of doping type, the doping type of the first semiconductor layer 12 can be N-type, in which case the doping type of the second semiconductor layer 15 is P-type; alternatively, the doping type of the first semiconductor layer 12 can also be P-type, in which case the doping type of the second semiconductor layer 15 is N-type. The embodiment of the present invention does not specifically limit the doping type of the first semiconductor layer 12 and the second semiconductor layer 15, as long as the doping types of the two are opposite. When the doping type is P-type, it is generally doped with Group III elements. When the doping type is N-type, it is generally doped with Group V elements or Group VI elements.

[0096] The present application also provides a method for manufacturing a solar cell, which can be used to manufacture the solar cell described in any of the above embodiments. The method for manufacturing a solar cell comprises the following steps:

[0097] S100: providing a semiconductor substrate 10, wherein the semiconductor substrate 10 has a first surface and a second surface opposite to each other, wherein at least a portion of the first surface is a velvet surface, and a plurality of pyramid-like structures are formed on the velvet surface.

[0098] Before this step, in some embodiments, the semiconductor substrate 10 may be placed in a polishing and cleaning machine to remove the cut damage layer of the semiconductor substrate 10 using a polishing liquid.

[0099] S200 : forming a first semiconductor layer 12 on the first surface, wherein the first semiconductor layer 12 includes amorphous silicon and / or nanocrystalline silicon and at least covers the velvet surface of the first surface; the first semiconductor layer 12 includes at least one processed area 13 .

[0100] In the above steps, the first semiconductor layer 12 can be additionally formed on the first surface of the semiconductor substrate 10 by deposition technology, or formed in the semiconductor substrate 10 by diffusion, ion implantation, etc. In addition, the first semiconductor layer 12 can be formed on the first surface as a whole layer or locally.

[0101] like Figure 15 As shown, the number of the treatment zones 13 can be one or more. When there are multiple treatment zones 13, the multiple treatment zones 13 can be spaced apart and distributed in a direction perpendicular to the length of the first semiconductor layer 12. In the case where the solar cell being manufactured is a back-contact cell, the treatment zone 13 can be the entire first surface, or the width of the treatment zone 13 can be 5% to 120% of the width of the textured area. For example, the width of the treatment zone 13 can be 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, 110% or 120% of the width of the textured area.

[0102] S300: Using laser to irradiate at least a portion of the processing area 13, the degree of crystallization of at least a local area of ​​the first semiconductor layer 12 irradiated by the laser covering the side of the pyramid-like structure is increased to form a first crystallized region 2a, and the first crystallized region 2a extends along the circumference of the pyramid-like structure.

[0103] Specifically, the laser can irradiate part or all of the processing area 13 to increase the degree of crystallization of at least a partial area of ​​the first semiconductor layer 12 covering the side of the pyramid-like structure, forming a first crystallized region 2a. The first crystallized region 2a can extend along the circumference of the pyramid-like structure to form a full ring or an open ring, thereby facilitating the reduction of the contact resistance of the first crystallized region 2a of the first semiconductor layer 12, thereby reducing the contact resistance between the first crystallized region 2a and other conductive components, and thereby reducing the transmission loss of carriers collected in the first semiconductor layer 12. In an actual manufacturing process, the first semiconductor layer 12 comprising amorphous silicon can be rapidly grown first, and then laser irradiation can be used to increase the degree of crystallization within the first crystallized region 2a of the first semiconductor layer 12, thereby reducing the contact resistance of the first semiconductor layer 12, thereby ensuring production efficiency while reducing contact resistance and transmission loss. The overall degree of crystallization of the first semiconductor layer 12 in the processing area 13 is greater than the degree of crystallization of the first semiconductor layer 12 outside the processing area 13.

[0104] In some embodiments, before or after laser irradiating at least a portion of the processed region 13 to increase the degree of crystallization of at least a portion of the first semiconductor layer 12 covering the pyramid-like side surfaces by the laser irradiation, forming the first crystallized region 2a, the manufacturing method further includes: S301 irradiating at least a portion of the processed region 13 to increase the degree of crystallization of the portion of the first semiconductor layer 12 covering the pyramid-like top by the laser irradiation, forming the second crystallized region 2b. Specifically, laser irradiating at least a portion of the processed region 13 to form the second crystallized region 2b can be performed before or after forming the first crystallized region 2a. The degree of crystallization of the second crystallized region 2b is greater than the degree of crystallization of the first semiconductor layer 12 covering the pyramid-like side surfaces outside the first crystallized region 2a, further reducing the contact resistance of the first semiconductor layer 12, thereby facilitating reduced transmission loss of carriers collected within the first semiconductor layer 12.

[0105] In some embodiments, parameters such as the processing wavelength, pulse width, laser energy density, and processing time of the laser irradiation process can be determined based on requirements for the degree of crystallization and extension range of the first crystallized region 2a and the second crystallized region 2b of the first semiconductor layer 12 in actual application scenarios, and are not specifically limited herein. It is understood that when the processing wavelength of the laser irradiation process is smaller, the pulse width is larger, the laser energy density is higher, and the processing time is longer, when the laser irradiation process is used to treat the first semiconductor layer 12, the temperature of the first semiconductor layer 12 is increased to a greater extent, which is more conducive to forming a crystallized region with a greater crystallization depth and a longer extension length.

[0106] In some embodiments, the laser used in step S300 is a first laser, and the energy density of the first laser is in the range of 10 mJ / cm 2~3000mJ / cm 2 The pulse width of the first laser is in the order of picoseconds. The first laser can be irradiated by a picosecond laser. For example, the energy density of the first laser is 10 mJ / cm 2 , 50mJ / cm 2 、100mJ / cm 2 、140mJ / cm 2 、180mJ / cm 2 , 200mJ / cm 2 , 240mJ / cm 2 、280mJ / cm 2 、300mJ / cm 2 , 400mJ / cm 2 , 500mJ / cm 2 、1000mJ / cm 2 , 2000mJ / cm 2 or 3000mJ / cm 2 wait.

[0107] The laser used in step S301 is the second laser, and the energy density of the second laser is greater than or equal to 200mJ / cm 2 ~6000mJ / cm 2 The pulse width of the second laser is in the nanosecond range. The second laser can be irradiated by a nano laser. For example, the energy density of the second laser is 200 mJ / cm 2 , 240mJ / cm 2 、280mJ / cm 2 、300mJ / cm 2 , 400mJ / cm 2 , 500mJ / cm 2 、1000mJ / cm 2 , 2000mJ / cm 2 、3000mJ / cm 2 , 4000mJ / cm 2 , 5000mJ / cm 2 or 6000mJ / cm 2 wait.

[0108] In some embodiments, at least a portion of the processing area 13 is irradiated with a laser, comprising: irradiating a portion of the processing area 13 along multiple paths with a laser, and the areas irradiated by the laser along the multiple paths do not overlap, that is, multiple laser irradiation areas 13a do not overlap. The area irradiated by the laser along one path forms a first crystallization area 2a, and the area irradiated by the laser along multiple paths forms multiple first crystallization areas 2a. In this technical solution, during the laser irradiation process, the areas irradiated by the laser along multiple paths do not repeat, that is, it is impossible for any position in the processing area 13 to be repeatedly irradiated by the laser. In this way, the area irradiated by the laser in the processing area 13 is less affected by the laser thermal radiation, thereby increasing the degree of crystallization of the first semiconductor layer 12 in the laser irradiated portion to form the first crystallization area 2a, while avoiding damage to the area irradiated by the laser in the processing area 13 due to the action of the laser, thereby reducing the contact resistance and transmission loss while ensuring the power generation performance of the solar cell.

[0109] In some embodiments, the width of a single laser path is 20um to 500um, for example, the width of a single laser path is 20um, 50um, 100um, 150um, 200um, 250um, 300um, 350um, 400um, 450um or 500um.

[0110] like Figure 16-Figure 18 As shown, in the case where the manufactured solar cell is a double-sided contact cell, a first semiconductor layer 12 is formed on the first surface of the semiconductor substrate 10, and a second semiconductor layer 15 is formed on the second surface. Figure 17 As shown, laser is used to irradiate at least a portion of the processing area 13 of the first semiconductor layer 12, so that the degree of crystallization of at least a local area of ​​the first semiconductor layer 12 irradiated by the laser covering the side of the pyramid-like layer is increased to form a first crystallized region 2a, and the first crystallized region 2a extends along the circumference of the pyramid-like layer.

[0111] Next, if Figure 18As shown, a transparent conductive layer 17 is formed on the first surface, and a first electrode 18 is formed on the first surface. The first electrode 18 is formed on the side of the transparent conductive layer 17 facing away from the semiconductor substrate 10. A functional layer 16 is formed on the second surface. This functional layer 16 can be a transparent conductive layer 17 or a passivation layer. The second semiconductor layer 15 can be at least one of single-crystal silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon, or nanocrystalline silicon. Specifically, when the second semiconductor layer 15 comprises doped polycrystalline silicon, the functional layer 16 can be a passivation layer. The passivation layer protects the cell surface and prevents water vapor and oxygen from penetrating into the cell interior, thereby preventing cell performance degradation due to oxidation or hydrolysis. Furthermore, the provision of the passivation layer can reduce the surface recombination rate of the cell, thereby improving the photoelectric conversion efficiency of the cell. The passivation layer can be a single layer structure or a multilayer structure. Specifically, the passivation layer is at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer, or a composite film formed by stacking these layers. When the second semiconductor layer 15 comprises doped microcrystalline silicon, doped nanocrystalline silicon, and / or doped amorphous silicon, the functional layer 16 may be a transparent conductive layer 17 to promptly conduct carriers collected by the second semiconductor layer 15 and reduce the carrier recombination rate. A second electrode 19 is formed on the second surface. The second electrode 19 is formed on the side of the functional layer 16 facing away from the semiconductor substrate 10. When the functional layer 16 is a passivation layer, the second electrode 19 is electrically connected to the second semiconductor layer 15 through the passivation layer. When the functional layer 16 is a transparent conductive layer, the second electrode 19 contacts the surface of the transparent conductive layer facing away from the semiconductor substrate 10.

[0112] In the case where the solar cell being manufactured is a back contact cell, as Figures 19-22 As shown, the method for manufacturing a solar cell further includes: forming a second semiconductor layer 15 at least in a local area of ​​the first surface, the second semiconductor layer 15 and the first semiconductor layer 12 having opposite conductivity types, and the second semiconductor layer 15 can be patterned to achieve alternating distribution of the second semiconductor layer 15 and the first semiconductor layer 12, and the patterning can be performed before or after the laser irradiation treatment area 13. The second semiconductor layer 15 can be at least one of single crystal silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon or nanocrystalline silicon. It should be noted that when the second semiconductor layer 15 includes a polycrystalline silicon layer, the first semiconductor layer 12 is formed after the second semiconductor layer 15 is formed on the first surface. When the second semiconductor layer 15 includes amorphous silicon and / or nanocrystalline silicon, the first semiconductor layer 12 can be formed after the second semiconductor layer 15 is formed on the first surface, or the second semiconductor layer 15 can be formed after the first semiconductor layer 12 is formed on the first surface.

[0113] like Figure 20As shown, next, laser is used to irradiate at least a portion of the processing area 13 of the first semiconductor layer 12, so that the degree of crystallization of at least a local area of ​​the first semiconductor layer 12 irradiated by the laser covering the side of the pyramid-like layer is increased to form a first crystallized region 2a, and the first crystallized region 2a extends along the circumference of the pyramid-like layer.

[0114] Next, if Figure 21 As shown, a functional layer 16 is formed on the first surface. In this embodiment, the functional layer 16 is a transparent conductive layer. The transparent conductive layer covers the side of the first semiconductor layer 12 and the second semiconductor layer 15 facing away from the semiconductor substrate 10. A first electrode 18 is formed on the side of the transparent conductive layer facing away from the first semiconductor layer 12, and a second electrode 19 is formed on the side of the transparent conductive layer facing away from the second semiconductor layer 15.

[0115] like Figure 21 and Figure 22 As shown, the first surface has a first area A, a second area B and an overlapping area C. A first semiconductor layer 12 is formed in the first area A, and a second semiconductor layer 15 is formed in the second area B. The first semiconductor layer 12 and the second semiconductor layer 15 can be stacked in the overlapping area C. In the overlapping area C, the transparent conductive layer covers the side of the first semiconductor layer and the second semiconductor layer 15 facing away from the semiconductor substrate 10, and the transparent conductive layer has an opening running through its thickness to prevent a short circuit.

[0116] In some embodiments, as Figure 21 and Figure 22 As shown, along the direction perpendicular to the first electrode 18, the width of the processing area 13 can be less than or equal to the width of the first region A. The orthographic projection of the processing area 13 on the first surface is located inside the orthographic projection of the first region A on the first surface, or the orthographic projection of the processing area 13 on the first surface completely overlaps with the orthographic projection of the first region A on the first surface. With this arrangement, the width of the processing area 13 is narrower, which helps to reduce processing difficulty and improve processing efficiency. Specifically, the width of the processing area 13 can be 5% to 100% of the width of the first region A. For example, the width of the processing area 13 is 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90% or 100% of the width of the first region A, etc.

[0117] In other embodiments, Figure 23 and Figure 24As shown, along a direction perpendicular to the first electrode 18, the width of the processed region 13 can be greater than the width of the first region A. The processed region 13 extends from the first region A to the overlapping region C. With this configuration, at least a portion of the amorphous silicon in contact with the second semiconductor layer 15 at the overlapping region C or the side steps of the first semiconductor layer 12 is crystallized, resulting in increased conductivity and leakage rate at that location, and lower reverse breakdown voltage, thereby reducing the risk of hot spots in the solar cell and the vulnerability of the solar cell to burning due to localized heat concentration. It is understood that within the overlapping region C, the amorphous silicon may not form grains, and even if grains are formed there, they are fewer than those formed in the first region.

[0118] In terms of length, Figure 21 and Figure 22 As shown, along a direction parallel to the first electrode 18, the length of the processed area 13 is less than the length of the first region A, and the distance between the edge of the processed area 13 and the edge of the first region A is greater than 0. Since the edge of the first semiconductor layer 12 is relatively thin, it is easily blackened and damaged after laser irradiation, which affects the carrier collection efficiency. In this technical solution, the laser irradiation area is at a certain distance from the edge of the first region A, which can reduce the damage of the laser to the thinner edge area of ​​the first semiconductor layer 12, thereby improving the carrier collection efficiency of the first semiconductor layer 12.

[0119] In addition, the present application also provides a photovoltaic component, which includes a plurality of solar cells provided in any of the above embodiments and at least one interconnecting member, wherein the interconnecting member connects two adjacent solar cells in series or in parallel. When the solar cell is a double-sided contact cell, the interconnecting member includes a first interconnecting member and a second interconnecting member, and the two adjacent solar cells are the first solar cell and the second solar cell respectively. The first interconnecting member connects the electrode on the first surface of the first solar cell and extends to connect to the electrode on the second surface of the second solar cell. Similarly, the second interconnecting member is analogous to form an interconnection. When the solar cell is a back-contact solar cell, the interconnecting members are all connected to the electrodes on the first surface of the solar cell to form an interconnection. In addition, when the first electrode 18 and the second electrode 19 are both fine grids, a main grid can be provided at the corresponding position of the interconnecting member, and the current is transmitted through the semiconductor layer, the fine grid, the main grid and the interconnecting member. Of course, the main grid can also be not provided at the corresponding position of the interconnecting member or only a terminal line close to the edge of the cell can be provided, and the current is transmitted through the semiconductor layer, the fine grid and the interconnecting member.

[0120] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell and the method for manufacturing the solar cell, and are not described in detail here.

[0121] In some embodiments, the projection of the interconnection on the semiconductor substrate 10 at least partially overlaps with the projection of the first crystallized region 2a on the semiconductor substrate 10. This configuration reduces transmission losses between the crystallized regions, electrodes, and interconnection, and improves power generation efficiency.

[0122] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0123] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other, wherein at least a portion of the first surface is a suede area, and a plurality of pyramid-like structures are formed on the suede area; A first semiconductor layer covers at least the velvet surface of the first surface, and the first semiconductor layer on at least a portion of the pyramid-like side includes a first crystallized region, and the first crystallized region extends along the circumference of the pyramid-like; the degree of crystallization of the first crystallized region is greater than the degree of crystallization of the remaining area of ​​the first semiconductor layer covering the pyramid-like side.

2. The solar cell according to claim 1, wherein The material of the first semiconductor layer includes an amorphous layer and / or nanocrystalline silicon, and the first crystallized region includes nanocrystalline silicon and / or microcrystalline silicon.

3. The solar cell according to claim 1, wherein The first semiconductor layer includes adjacent processed areas and unprocessed areas, wherein a first crystallized area is formed in the processed area, and areas of the processed area with low contact resistance present a plurality of discrete point-shaped or block-shaped areas.

4. The solar cell according to claim 1, wherein The first crystallized region is discontinuously arranged along the circumference of the pyramid-like shape.

5. The solar cell according to claim 1, wherein There are a plurality of first crystallized regions, and the plurality of first crystallized regions are arranged at intervals along a height direction of the pyramid-like region.

6. The solar cell according to claim 5, characterized in that Along the extension direction of the side edges of the pyramid-like structure, the spacing between multiple first crystallized regions is the same; and / or the width of the first crystallized regions is less than or equal to 100 nm; and / or the spacing between any adjacent first crystallized regions is in the range of 50 nm to 500 nm.

7. The solar cell according to claim 1, wherein The roughness of the first crystallized region is greater than the roughness of the remaining region of the first semiconductor layer covering the side surfaces of the pyramid-like layer.

8. The solar cell according to claim 1, wherein The portion of the first semiconductor layer covering the top of the pyramid-like layer includes a second crystallized region.

9. The solar cell according to claim 8, characterized in that The orthographic projection of the second crystallized region on the semiconductor substrate is circular, elliptical, square or irregular; and / or the equivalent radius of the orthographic projection of the second crystallized region on the semiconductor substrate is 50 nm to 600 nm.

10. The solar cell according to claim 1, wherein Along the thickness direction of the semiconductor substrate, the first crystallized region extends from a side of the first semiconductor layer away from the semiconductor substrate toward a direction close to the semiconductor substrate; the thickness of the first crystallized region is less than or equal to 2 / 3 of the thickness of the first semiconductor layer.

11. The solar cell according to claim 1, wherein At least one side surface of the pyramid-like structure includes a first sub-conical surface and a second sub-conical surface adjacent to each other along the thickness direction of the semiconductor substrate, and the first sub-conical surface and the second sub-conical surface have different inclination angles, and a connection between the first sub-conical surface and the second sub-conical surface forms a protrusion or a depression extending along the circumference of the pyramid-like structure.

12. The solar cell according to claim 11, characterized in that At least a portion of the first crystallized region is disposed corresponding to the protrusion or the depression.

13. The solar cell according to claim 1, wherein The solar cell further comprises a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer; The second semiconductor layer is provided on the first surface, and the first semiconductor layer and the second semiconductor layer are alternately distributed; Alternatively, the second semiconductor layer is provided on the second surface.

14. The solar cell according to claim 1, wherein The solar cell further includes a first electrode formed on a side of the first semiconductor layer facing away from the semiconductor substrate, wherein an orthographic projection of the first electrode on the semiconductor substrate at least partially overlaps with an orthographic projection of the first crystallized region on the semiconductor substrate.

15. A method for manufacturing a solar cell, characterized in that: include: A semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, at least a portion of the first surface is a velvet surface, and a plurality of pyramid-like structures are formed on the velvet surface; forming a first semiconductor layer on the first surface, wherein the first semiconductor layer at least covers the velvet surface of the first surface; the first semiconductor layer includes at least one processed area; Laser is used to irradiate at least a portion of the processing area, so that the degree of crystallization of at least a local area of ​​the first semiconductor layer irradiated by the laser covering the side of the pyramid-like structure is increased to form a first crystallized region, which extends along the circumference of the pyramid-like structure.

16. The method for manufacturing a solar cell according to claim 15, wherein: Before or after irradiating at least a portion of the processing area with a laser to increase the degree of crystallization of at least a partial area of ​​the first semiconductor layer irradiated by the laser and covering the side of the pyramid-like layer to form a first crystallized area, the manufacturing method further includes: At least a portion of the processing area is irradiated with laser light, so that the crystallization degree of the portion of the first semiconductor layer irradiated by the laser and covering the top of the pyramid-like layer is increased to form a second crystallized area.

17. The method for manufacturing a solar cell according to claim 16, wherein: In the step of irradiating at least a portion of the processing area with a laser so as to increase the degree of crystallization of at least a local area of ​​the first semiconductor layer irradiated by the laser and covering the side of the pyramid-like layer to form a first crystallized area, a first laser is used, and the energy density of the first laser is in the range of 10 mJ / cm 2 ~3000mJ / cm 2 , the pulse width of the first laser is in the order of picoseconds; and / or, in the step of irradiating at least a portion of the processing area with a laser to increase the degree of crystallization of the portion of the first semiconductor layer irradiated by the laser and covering the top of the pyramid-like layer to form a second crystallized area, a second laser is used, and the energy density of the second laser is greater than or equal to 200 mJ / cm 2 ~6000mJ / cm 2 , the pulse width of the second laser is in the nanosecond order.

18. The method for manufacturing a solar cell according to claim 15 or 16, wherein: Irradiating at least a portion of the processing area with a laser comprises: irradiating a portion of the processing area with the laser along a plurality of paths, wherein the areas irradiated by the laser along the plurality of paths do not overlap.

19. A photovoltaic module, characterized in that: The invention comprises a plurality of solar cells according to any one of claims 1 to 14 or a plurality of solar cells formed by the manufacturing method according to any one of claims 15 to 18, and at least one interconnector, wherein the interconnector connects two adjacent solar cells in series or in parallel.

20. The photovoltaic module according to claim 19, characterized in that A projection of the interconnection on the semiconductor substrate at least partially overlaps with a projection of the first crystallized region on the semiconductor substrate.

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