Silicon wafer with back laminated SE structure, TOPCon solar cell and preparation method of TOPCon solar cell

Abstract

The invention provides a silicon wafer with a back laminated SE structure. The back of the silicon wafer is provided with a tunneling oxide layer and an intrinsic polysilicon layer which are laminated. The invention also provides a TOPCon solar cell and a preparation method of the TOPCon solar cell. The preparation method comprises the following steps: a step of primary deposition of the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer, a step of engraving a pattern in a non-printing area of the silk screen by using high-energy laser, a step of removing the intrinsic polysilicon layer in a laser area by primary alkali washing, and a step of secondary deposition of the tunneling oxide layer and the intrinsic polysilicon layer. According to the silicon wafer, the thickness of the doped polysilicon layer in the printing area is reserved, the passivation requirement of the non-printing area is met, the thickness of the doped polysilicon layer in the non-printing area is reduced, and parasitic absorption is reduced while current is increased.

Description

Technical Field

[0001] The present disclosure relates to the technical field of solar cells, and in particular to a silicon wafer with a back-stacked SE structure, a TOPCon solar cell, and a preparation method thereof. Background Art

[0002] TOPCon solar cells utilize tunnel oxide passivated contact technology based on the principle of selective carriers. They utilize an N-type silicon substrate. The ultra-thin silicon oxide layer and doped polysilicon layer on the back of the cell together form a passivated contact structure, effectively reducing surface recombination and metal contact recombination. Simulations show that the n-type current is approximately 0.03 mA / cm per 10 nanometers. 2 The short-circuit current density loss is due to the increase in free carrier concentration in the doped polysilicon layer, which leads to more light being absorbed by free carriers. This highlights the importance of solving and reducing parasitic absorption to improve the overall efficiency of solar cells.

[0003] In the prior art, this problem is usually improved through two approaches. One approach is to reduce the thickness of the doped polysilicon layer, which can effectively reduce parasitic absorption losses and achieve the purpose of increasing current. However, an overly thin doped polysilicon layer will cause passivation damage due to corrosion by the slurry, thereby affecting the opening voltage; the other approach is to increase the phosphorus doping concentration in the doped polysilicon layer, which can enhance the passivation effect and improve the contact ability. However, too high a doping concentration will cause phosphorus atoms to diffuse, weakening the passivation effect and resulting in a decrease in passivation quality. Summary of the Invention

[0004] In order to solve the above problems, the present disclosure provides a silicon wafer with a back-side stacked SE structure, wherein the back side of the silicon wafer has a stacked tunneling oxide layer and an intrinsic polysilicon layer.

[0005] In the silicon wafer with a back-side stacked SE structure described in the present disclosure, the stacked tunneling oxide layer and intrinsic polysilicon layer include a first tunneling oxide layer, a first intrinsic polysilicon layer, a second tunneling oxide layer, and a second intrinsic polysilicon layer deposited sequentially.

[0006] The thickness of the first tunneling oxide layer is 0.2-1 nm, the thickness of the first intrinsic polysilicon layer is 50-150 nm, the thickness of the second tunneling oxide layer is 0.5-1.5 nm, and the thickness of the second intrinsic polysilicon layer is 30-50 nm.

[0007] The present disclosure also provides a TOPCon solar cell, which includes the silicon wafer with the back-side stacked SE structure.

[0008] The present disclosure also provides a method for preparing a TOPCon solar cell, the method comprising the following steps:

[0009] The step of depositing a tunneling oxide layer, an intrinsic polysilicon layer, and an oxide layer at one time;

[0010] Steps for engraving non-printing area graphics on the screen using a high-energy laser;

[0011] A step of removing the intrinsic polysilicon layer in the laser area by a single alkali wash; and

[0012] The step of depositing a tunneling oxide layer and an intrinsic polysilicon layer twice.

[0013] According to the method for preparing a TOPCon solar cell disclosed in the present invention, in the step of depositing the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer at one time, in the range of 500-800°C, oxygen is used as the process gas to deposit a first tunneling oxide layer; SiH4 is used as the process gas to deposit a first intrinsic polysilicon layer; and oxygen is used as the process gas to deposit an oxide layer.

[0014] In the step of depositing the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer at one time, the thickness of the first tunneling oxide layer is 0.2-1 nm, and the thickness of the first intrinsic polysilicon layer is 50-150 nm.

[0015] According to the method for preparing TOPCon solar cells disclosed herein, in the step of using a high-energy laser to engrave the pattern of the non-printing area of ​​the screen, the laser power is 5-10KW, the engraving speed is 1000-3000mm / s, and the protective effect of the outer oxide layer is destroyed by irradiation with infrared light.

[0016] According to the method for preparing TOPCon solar cells disclosed herein, in the step of removing the intrinsic polysilicon layer in the laser area by one alkali washing, the silicon wafer is immersed in a KOH solution at a temperature range of 20-50° C. for 50-200 seconds.

[0017] According to the preparation method of TOPCon solar cells disclosed in the present invention, in the step of secondary deposition of the tunneling oxide layer and the intrinsic polysilicon layer, the second tunneling oxide layer is deposited using oxygen as the process gas in the range of 500-800°C; and the second intrinsic polysilicon layer is deposited using SiH4 as the process gas.

[0018] In the step of depositing the tunneling oxide layer and the intrinsic polysilicon layer for the second time, the thickness of the second tunneling oxide layer is 0.5-1.5 nm, and the thickness of the second intrinsic polysilicon layer is 30-50 nm.

[0019] According to the preparation method of TOPCon solar cells disclosed in the present invention, before the step of depositing the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer at one time, the steps of cleaning and texturing the N-type silicon wafer, diffusing P-type impurities on the N-type silicon wafer to form a PN junction, removing BSG and polishing the back side are also included.

[0020] According to the method for preparing TOPCon solar cells disclosed in the present invention, after the step of using a high-energy laser to engrave the pattern of the non-printing area of ​​the screen and before the step of removing the intrinsic polysilicon layer in the laser area by a single alkali wash, the method further includes the step of removing the oxide layer on the front side of the silicon wafer.

[0021] According to the method for preparing a TOPCon solar cell disclosed in the present invention, before the step of secondary depositing the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer, the step of removing the oxide layer on the back side of the silicon wafer is further included.

[0022] According to the preparation method of TOPCon solar cells disclosed in the present invention, after the steps of secondary deposition of the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer, the steps further include phosphorus doping of the silicon wafer, removal of PSG, secondary alkali washing and acid washing, deposition of an aluminum oxide passivation layer, deposition of front and back silicon nitride layers, and metallization to form ohmic contacts.

[0023] According to the silicon wafer with a back-side stacked SE structure disclosed in the present invention, the thickness of the doped polysilicon layer in the printed area is retained. While ensuring the passivation requirements of the non-printed area, the thickness of the doped polysilicon layer in the non-printed area is reduced, thereby reducing parasitic absorption while increasing the current; in addition, by adding an ultra-thin tunneling oxide layer, the degree of internal expansion of phosphorus atoms is reduced, the battery surface is passivated more effectively, carrier recombination is reduced, and the conversion efficiency and stability of the battery are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic flow chart of a method for preparing a TOPCon solar cell according to one embodiment of the present disclosure.

[0025] Figures 2 to 16 Schematic diagram of the structural changes of a silicon wafer during processing in each step in a method for preparing a TOPCon solar cell according to one embodiment of the present disclosure.

[0026] Figure Number:

[0027] 1-silicon wafer, 2-BSG, 3-P+, 4-first intrinsic polysilicon layer, 5-first tunneling oxide layer, 6-oxide layer,

[0028] 7-laser, 8-second tunneling oxide layer, 9-second intrinsic polysilicon layer, 10-doped phosphorus, 11-PSG,

[0029] 12-ALD passivation layer, 13-SiN layer, 14,15-positive and negative electrodes DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the technical solution of the present disclosure is described in detail below with reference to the accompanying drawings.

[0031] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.

[0032] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0033] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] The terms used herein are used only to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof is not excluded.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0036] Unless otherwise specified, the term "concentration" herein refers to mass concentration. The concentration of each substance in a mixed solution refers to the mass concentration of each substance based on the total amount of the mixed solution.

[0037] The present disclosure provides a silicon wafer with a back-side stacked SE (Selective Emitter) structure, wherein the back side of the silicon wafer has a stacked tunneling oxide layer and an intrinsic polysilicon layer.

[0038] In the silicon wafer with a back-side stacked SE structure described in the present disclosure, the stacked tunneling oxide layer and intrinsic polysilicon layer include a first tunneling oxide layer, a first intrinsic polysilicon layer, a second tunneling oxide layer, and a second intrinsic polysilicon layer deposited sequentially.

[0039] The thickness of the first tunneling oxide layer is 0.2-1 nm, the thickness of the first intrinsic polysilicon layer is 50-150 nm, the thickness of the second tunneling oxide layer is 0.5-1.5 nm, and the thickness of the second intrinsic polysilicon layer is 30-50 nm.

[0040] The present disclosure also provides a TOPCon solar cell, which includes the silicon wafer with the back-side stacked SE structure.

[0041] The present disclosure also provides a method for preparing a TOPCon solar cell, such as Figure 1 As shown, the preparation method comprises the following steps:

[0042] S1-a step of depositing a tunneling oxide layer, an intrinsic polysilicon layer, and an oxide layer at one time;

[0043] S2-Step of using high energy laser to engrave the graphics in the non-printing area of ​​the screen;

[0044] S3-a step of removing the intrinsic polysilicon layer in the laser area by alkali washing once; and

[0045] S4-a step of secondary deposition of a tunneling oxide layer and an intrinsic polysilicon layer.

[0046] According to the preparation method of TOPCon solar cells disclosed in the present invention, in the steps of depositing a tunneling oxide layer, an intrinsic polysilicon layer and an oxide layer at one time, oxygen is first used as a process gas to deposit a first tunneling oxide layer in the range of 500-800°C; then SiH4 is used as a process gas to deposit a first intrinsic polysilicon layer; and finally, oxygen is again used as a process gas to deposit an oxide layer.

[0047] In the step of depositing the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer at one time, the thickness of the first tunneling oxide layer is 0.2-1 nm, and the thickness of the first intrinsic polysilicon layer is 50-150 nm.

[0048] According to the method for preparing TOPCon solar cells disclosed herein, in the step of using a high-energy laser to engrave the pattern of the non-printing area of ​​the screen, the laser power is 5-10KW, the engraving speed is 1000-3000mm / s, and the protective effect of the outer oxide layer is destroyed by irradiation with infrared light.

[0049] According to the method for preparing TOPCon solar cells disclosed herein, in the step of removing the intrinsic polysilicon layer in the laser area by alkali washing, the silicon wafer is immersed in a KOH solution at a temperature range of 20-50° C. for 50-200 seconds.

[0050] According to the preparation method of TOPCon solar cells disclosed in the present invention, in the step of secondary deposition of the tunneling oxide layer and the intrinsic polysilicon layer, in the range of 500-800°C, oxygen is first used as the process gas to deposit a second tunneling oxide layer; then SiH4 is used as the process gas to deposit a second intrinsic polysilicon layer.

[0051] In the step of depositing the tunneling oxide layer and the intrinsic polysilicon layer for the second time, the thickness of the second tunneling oxide layer is 0.5-1.5 nm, and the thickness of the second intrinsic polysilicon layer is 30-50 nm.

[0052] According to the preparation method of TOPCon solar cells disclosed in the present invention, before the step of depositing the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer at one time, it also includes the steps of cleaning and texturing the N-type silicon wafer, diffusing P-type impurities on the N-type silicon wafer to form a PN junction, removing BSG and polishing the back side.

[0053] According to the method for preparing TOPCon solar cells disclosed in the present invention, after the step of using a high-energy laser to engrave the pattern of the non-printing area of ​​the screen and before the step of removing the intrinsic polysilicon layer in the laser area by one alkali wash, the method further includes the step of removing the oxide layer on the front side of the silicon wafer.

[0054] According to the method for preparing a TOPCon solar cell disclosed in the present invention, before the step of secondary deposition of the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer, the step of removing the oxide layer on the back side of the silicon wafer is also included.

[0055] According to the preparation method of TOPCon solar cells disclosed in the present invention, after the steps of secondary deposition of the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer, the steps also include phosphorus diffusion doping of the silicon wafer, removal of PSG, secondary alkali washing and acid washing, deposition of an aluminum oxide passivation layer, deposition of front and back silicon nitride layers, and metallization to form ohmic contacts.

[0056] According to one embodiment of the present disclosure, Figures 1 to 16 As shown, the preparation method of the TOPCon solar cell includes:

[0057] S11- Cleaning and texturing of N-type silicon wafers

[0058] N-type silicon wafers are textured in an alkaline solution with a concentration of 2-8wt% at a temperature range of 25-50°C for 120-300s. The alkaline solution can be a NaOH solution or a KOH solution. The alkaline solution is used to remove organic dirt and metal impurities on the surface of the silicon wafer. By utilizing the anisotropic corrosion characteristics of silicon in low-concentration alkaline solution, Si reacts chemically with the alkaline solution to form a pyramid texture on the surface of the silicon wafer. The reaction equation is: 2NaOH+Si+H2O=Na2SiO3+2H2. At this time, the silicon wafer is Figure 2 As shown in .

[0059] S12-Diffusion of P-type impurities on N-type silicon wafer to form PN junction

[0060] The silicon wafer is placed in a furnace at 800-1100℃, and the impurity source BCl3 is used to react with oxygen to produce B2O3. The reaction equation is: 4BCl3+3O2→2B2O3+6CL2↑.

[0061] The generated B2O3 reacts with silicon, and the reaction equation is: 2B2O3+3Si→3SiO2+4B. Through high temperature advancement, the appropriate doping concentration ρ / square resistance R is gradually reached.

[0062] After this step, the silicon wafer is Figure 3 As shown in .

[0063] S13- BSG removal and backside polishing

[0064] Use chain equipment to remove BSG, then place the silicon wafer in a tank with appropriate amount of NaOH solution and polishing additive (NaOH solution concentration is 1-3wt%, polishing agent concentration is 0.5-1.5wt%) for polishing, the operating temperature is 60-70℃. After alkaline polishing, it is rinsed with pure water. The reaction equation is: Si + 2NaOH + H2O = Na2SiO3 + 2H2↑. The silicon wafer obtained at this time is as follows Figure 4 As shown in .

[0065] S14-Single deposition of tunneling oxide layer, intrinsic polysilicon layer and oxide layer

[0066] Using a tubular LPCVD device, with a chamber temperature in the range of 500-800°C, O2 is introduced to react with Si to form SiOx, depositing a first tunneling oxide layer with a thickness of 0.2-1nm. The reaction equation is: O2+Si→SiOx. At the same temperature, SiH4 is introduced. SiH4 decomposes under thermal decomposition to form Si and H2, depositing a second intrinsic polysilicon layer with a thickness of 50-150nm. The reaction equation is: SiH4(gas)=Si(solid)+H2. Finally, oxygen is introduced to form a 1-8nm oxide protection layer. The silicon wafer obtained at this time is as follows: Figure 5 As shown in .

[0067] S15 - Use high-powered laser to engrave non-printing areas of the screen

[0068] Use a laser machine to carve out the non-printing area of ​​the screen. The laser power is 5-10KW and the engraving speed is 1000-3000mm / s. Place the silicon wafer under the laser. The interaction between the infrared beam and the silicon surface destroys the protective effect of the outer silicon oxide, making it easier to remove the polysilicon layer in the non-printing area by alkali washing. The silicon wafer obtained at this time is as follows: Figure 6 As shown in .

[0069] S16-Remove the oxide layer on the front of the silicon wafer

[0070] Using a chain device, remove the oxide layer on the front side of the silicon wafer using a 3-8 wt% HF solution. Figure 7 As shown in .

[0071] S17-One alkali wash to remove the intrinsic polysilicon layer in the laser area

[0072] Soak the silicon wafer in KOH solution at a temperature range of 20-50°C for 50-200 seconds to remove the polysilicon layer on the front side and the polysilicon layer on the back side of the laser area. The ratio of water to KOH solution in the tank is 2:1 to 8:1, preferably 5:1. The silicon wafer obtained at this time is as follows: Figure 8 As shown in .

[0073] S18-Removal of oxide layer on the back of silicon wafer

[0074] Use chain equipment to remove the oxide layer on the back of the silicon wafer using HF solution with a concentration of 3-8wt%. Figure 9 As shown in .

[0075] S19-Secondary deposition tunneling oxide layer, intrinsic polysilicon layer and oxide layer

[0076] Using a tubular LPCVD device, with a chamber temperature in the range of 500-800°C, O2 is introduced to react with Si to form SiOx, depositing a second tunnel oxide layer with a thickness of 0.5-1.5nm. The reaction equation is: O2+Si→SiOx. At the same temperature, SiH4 is introduced. SiH4 decomposes thermally to form Si and H2, depositing a second intrinsic polysilicon layer with a thickness of 30-50nm. The reaction equation is: SiH4(gas)=Si(solid)+H2. The silicon wafer obtained at this time is as follows Figure 10 As shown in .

[0077] S20-Phosphorus doping of silicon wafers

[0078] In the presence of oxygen, POCl3 decomposes at high temperatures to form phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5). The reaction equation is: POCl3 + O2 → 2P2O5 + 6Cl2↑. The resulting P2O5 reacts with silicon at the diffusion temperature to form silicon dioxide (SiO2) and phosphorus atoms. The reaction equation is: 2P2O5 + 5Si → 5SiO2 + 4P↓. At the end of phosphorus diffusion, the phosphorus doping concentration reaches approximately 4E20, for example, 2E20 to 7E20.

[0079] The silicon wafer obtained at this time is Figure 11 As shown in .

[0080] S21-Removal of PSG

[0081] Using chain equipment, PSG is removed using HF solution with a concentration of 3-8 wt%. Figure 12 As shown in .

[0082] S22- Secondary alkaline and acid washing to remove the front polysilicon layer and the front and back oxide layers

[0083] Soak the silicon wafer in KOH solution at a temperature range of 20-50°C for 50-200 seconds to remove the front polysilicon layer. The ratio of water to KOH solution in the tank is 2:1 to 8:1, preferably 5:1.

[0084] After alkaline washing and water washing to remove impurities, the silicon wafer is then placed in a tank containing HF solution to remove the front and back oxide layers. The ratio of H2O to HF solution in the tank is 10:1 to 15:1, preferably 12:1.

[0085] The silicon wafer obtained at this time is Figure 13 As shown in .

[0086] S23-Deposition of front aluminum oxide passivation layer

[0087] By alternately introducing gaseous precursors TMA and H2O into the reaction chamber, a deposition film of AL2O3 is formed on the silicon wafer through chemical adsorption reaction. Figure 14 As shown in .

[0088] S24-Deposition of front and back silicon nitride layers

[0089] The silicon nitride passivation layer is deposited by PECVD. SiH4 and NH3 are introduced into the graphite boat, the temperature inside the tube is raised to 400-600°C, 8-12KW of RF power is connected, the pressure is set to 1500-2500mTorr, and the deposition duration is 500-800s. The silicon wafer obtained at this time is as follows Figure 15 As shown in .

[0090] S25-Metalization to form ohmic contact

[0091] Print metal paste on the front and back of the silicon wafer, and sinter it at high temperature through the screen to form an ohmic contact between the silicon wafer and the metal electrode. Figure 16 The solar electrode sheet shown in .

[0092] According to the silicon wafer with a back-side stacked SE structure disclosed in the present invention, the thickness of the doped polysilicon layer in the printed area is retained. While ensuring the passivation requirements of the non-printed area, the thickness of the doped polysilicon layer in the non-printed area is reduced, thereby reducing parasitic absorption while increasing the current; in addition, by adding an ultra-thin tunneling oxide layer, the degree of internal expansion of phosphorus atoms is reduced, the battery surface is passivated more effectively, carrier recombination is reduced, and the conversion efficiency and stability of the battery are improved.

[0093] In order to enable those skilled in the art to more clearly understand the technical solution of the present disclosure, the technical solution of the present disclosure is described in detail below through specific embodiments.

[0094] Example 1

[0095] The N-type silicon wafer was textured in a NaOH solution with a concentration of 4.8 wt % at 32° C. for 200 s.

[0096] The silicon wafer is placed in a furnace at 1000℃, and the impurity source BCl3 is used to react with oxygen to generate B2O3. The generated B2O3 reacts with silicon, and the doping concentration ρ of 2E19 is achieved through high temperature advancement.

[0097] The BSG was removed using a chain-type device, and then the wafer was polished in a tank containing a mixture of 1.6 wt% NaOH and 0.97 wt% polishing additive at 65°C. Alkaline polishing was followed by a pure water rinse.

[0098] Using a tubular LPCVD device, with a chamber temperature in the 600°C range, O2 is introduced to react with Si to form SiOx, depositing a 0.6nm thick first tunneling oxide layer. At the same temperature, SiH4 is introduced, where it thermally decomposes to form Si and H2, depositing a 100nm thick first intrinsic polysilicon layer. Finally, oxygen is introduced to form a 3nm thick protective oxide layer.

[0099] A laser machine is used to engrave the non-printing area of ​​the screen. The laser power is 7KW and the engraving speed is 2000mm / s. The silicon wafer is placed under the laser. The interaction between the infrared beam and the silicon surface destroys the protective effect of the outer silicon oxide, making it easier to remove the polysilicon layer in the non-printing area by alkaline washing.

[0100] The oxide layer on the front side of the silicon wafer was removed using a chain device with a 5 wt% HF solution.

[0101] The silicon wafer was placed in a tank containing a water and KOH solution in a ratio of 5:1, heated to 35°C, and soaked for 100 seconds to remove the polysilicon layer on the front side and the polysilicon layer on the back side of the laser area.

[0102] The oxide layer on the back of the silicon wafer was removed using a chain device with a 5 wt% HF solution.

[0103] Using a tubular LPCVD device, with a chamber temperature in the range of 600°C, O2 is introduced to react with Si to form SiOx, depositing a 1nm thick second tunnel oxide layer. At the same temperature, SiH4 is introduced, where it thermally decomposes to form Si and H2, depositing a 40nm thick second intrinsic polysilicon layer.

[0104] In the presence of oxygen, POCl3 decomposes at high temperature to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5). The generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms.

[0105] PSG was removed using a chain device with a 5 wt% HF solution.

[0106] The silicon wafer was placed in a tank containing a 5:1 ratio of water and KOH solution, heated to 35°C, and soaked for 100 seconds to remove the front polysilicon layer.

[0107] After alkaline cleaning, water washing is used to remove impurities. The silicon wafer is then placed in a tank containing HF solution to remove the front and back oxide layers. The ratio of H2O to HF solution in the tank is 12:1.

[0108] The gaseous precursors TMA and H2O are pulsed alternately into the reaction chamber, and a deposited film AL2O3 is generated on the front side of the silicon wafer through a chemical adsorption reaction.

[0109] A silicon nitride passivation layer was deposited on the front and back sides of the silicon wafer using PECVD. SiH4 and NH3 were introduced into a graphite boat, the temperature inside the boat was raised to 500°C, 10 kW of RF power was applied, the pressure was set to 2000 mTorr, and the deposition duration was 600 seconds.

[0110] Metal paste is printed on the front and back of the silicon wafer and sintered at high temperature through a screen to form an ohmic contact between the silicon wafer and the metal electrode.

[0111] Example 2

[0112] The N-type silicon wafer was textured in a NaOH solution with a concentration of 8 wt % at 20° C. for 300 s.

[0113] The silicon wafer is placed in an 800°C furnace, and the impurity source BCl3 is used to react with oxygen to generate B2O3. The generated B2O3 reacts with silicon, and the doping concentration ρ of 2E19 is achieved through high temperature advancement.

[0114] The BSG was removed using a chain-type device, and then the wafer was polished in a tank containing a mixture of 1 wt% NaOH and 0.5 wt% polishing additive at 60°C. Alkaline polishing was followed by a pure water rinse.

[0115] Using a tubular LPCVD device, with a chamber temperature in the 500°C range, O2 is introduced to react with Si to form SiOx, depositing a 0.2nm thick first tunneling oxide layer. At the same temperature, SiH4 is introduced, where it thermally decomposes to form Si and H2, depositing a 50nm thick first intrinsic polysilicon layer. Finally, oxygen is introduced to form a 1nm protective oxide layer.

[0116] A laser machine is used to engrave the non-printing area of ​​the screen. The laser power is 5KW and the engraving speed is 1000mm / s. The silicon wafer is placed under the laser. The interaction between the infrared beam and the silicon surface destroys the protective effect of the outer silicon oxide, making it easier to remove the polysilicon layer in the non-printing area by alkaline washing.

[0117] The oxide layer on the front side of the silicon wafer was removed using a chain device with a 3 wt% HF solution.

[0118] The silicon wafer was placed in a tank containing a water and KOH solution in a ratio of 2:1, heated to 20°C, and immersed for 200 seconds to remove the polysilicon layer on the front side and the polysilicon layer on the back side of the laser area.

[0119] The oxide layer on the back of the silicon wafer was removed using a chain device with a 3 wt% HF solution.

[0120] Using a tubular LPCVD device, with a chamber temperature in the 500°C range, O2 is introduced to react with Si to form SiOx, depositing a 0.5nm thick second tunnel oxide layer. At the same temperature, SiH4 is introduced, where it thermally decomposes to form Si and H2, depositing a 30nm thick second intrinsic polysilicon layer.

[0121] In the presence of oxygen, POCl3 decomposes at high temperature to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5). The generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms.

[0122] PSG was removed using a chain device with a 3 wt% HF solution.

[0123] Place the silicon wafer in a tank containing a 2:1 ratio of water and KOH solution, heat it to 20°C, and soak the silicon wafer for 50 seconds to remove the front polysilicon layer.

[0124] After alkaline cleaning, water washing is used to remove impurities. The silicon wafer is then placed in a tank containing HF solution to remove the front and back oxide layers. The ratio of H2O to HF solution in the tank is 10:1.

[0125] The gaseous precursors TMA and H2O are pulsed alternately into the reaction chamber, and a deposited film AL2O3 is generated on the front side of the silicon wafer through a chemical adsorption reaction.

[0126] A silicon nitride passivation layer was deposited on the front and back sides of the silicon wafer using PECVD. SiH4 and NH3 were introduced into a graphite boat, the temperature inside the boat was raised to 400°C, 8 kW of RF power was applied, the pressure was set to 2500 mTorr, and the deposition duration was 800 seconds.

[0127] Metal paste is printed on the front and back of the silicon wafer and sintered at high temperature through a screen to form an ohmic contact between the silicon wafer and the metal electrode.

[0128] Example 3

[0129] The N-type silicon wafer was textured in a NaOH solution with a concentration of 8 wt % at 50° C. for 120 seconds.

[0130] The silicon wafer is placed in a furnace at 1100℃, and the impurity source BCl3 is used to react with oxygen to generate B2O3. The generated B2O3 reacts with silicon, and the doping concentration ρ of 2E19 is achieved through high temperature advancement.

[0131] The BSG was removed using a chain-type device, and the wafers were then polished in a bath containing a mixture of 3 wt% NaOH and 1.5 wt% polishing additive at 70°C. Alkaline polishing was followed by a pure water rinse.

[0132] Using a tubular LPCVD device, with a chamber temperature in the 800°C range, O2 is introduced to react with Si to form SiOx, depositing a 1nm thick first tunneling oxide layer. At the same temperature, SiH4 is introduced, where it thermally decomposes to form Si and H2, depositing a 150nm thick first intrinsic polysilicon layer. Finally, oxygen is introduced to form an 8nm thick protective oxide layer.

[0133] A laser machine is used to engrave the non-printing area of ​​the screen. The laser power is 10KW and the engraving speed is 3000mm / s. The silicon wafer is placed under the laser. The interaction between the infrared beam and the silicon surface destroys the protective effect of the outer silicon oxide, making it easier to remove the polysilicon layer in the non-printing area by alkaline washing.

[0134] The oxide layer on the front side of the silicon wafer was removed using a chain device with an 8 wt% HF solution.

[0135] The silicon wafer was placed in a tank containing a water and KOH solution in a ratio of 8:1, heated to 50°C, and immersed for 200 seconds to remove the polysilicon layer on the front side and the polysilicon layer on the back side of the laser area.

[0136] The oxide layer on the back of the silicon wafer was removed using a chain device with an 8 wt% HF solution.

[0137] Using a tubular LPCVD device, with a chamber temperature in the 800°C range, O2 is introduced to react with Si to form SiOx, depositing a 1.5nm thick second tunnel oxide layer. At the same temperature, SiH4 is introduced, where it thermally decomposes to form Si and H2, depositing a 50nm thick second intrinsic polysilicon layer.

[0138] In the presence of oxygen, POCl3 decomposes at high temperature to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5). The generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms.

[0139] PSG was removed using a chain device with an 8 wt% HF solution.

[0140] The silicon wafer was placed in a tank containing a water and KOH solution in a ratio of 8:1, heated to 50°C, and soaked for 200 seconds to remove the front polysilicon layer.

[0141] After alkaline cleaning, water washing is used to remove impurities. The wafers are then placed in a tank containing HF solution to remove the front and back oxide layers. The ratio of H2O to HF solution in the tank is 15:1.

[0142] The gaseous precursors TMA and H2O are pulsed alternately into the reaction chamber, and a deposited film AL2O3 is generated on the front side of the silicon wafer through a chemical adsorption reaction.

[0143] A silicon nitride passivation layer was deposited on the front and back sides of the silicon wafer using PECVD. SiH4 and NH3 were introduced into a graphite boat, the temperature inside the boat was raised to 600°C, 12kW of RF power was applied, the pressure was set to 2500mTorr, and the deposition duration was 500s.

[0144] Metal paste is printed on the front and back of the silicon wafer and sintered at high temperature through a screen to form an ohmic contact between the silicon wafer and the metal electrode.

[0145] Comparative Example 1

[0146] The N-type silicon wafer was textured in a NaOH solution with a concentration of 4.8 wt % at 32° C. for 200 s.

[0147] The silicon wafer is placed in a furnace at 1000℃, and the impurity source BCl3 is used to react with oxygen to generate B2O3. The generated B2O3 reacts with silicon, and the doping concentration ρ / square resistance R of 2E19 is achieved through high temperature advancement.

[0148] The BSG was removed using a chain-type device, and then the wafer was polished in a tank containing a mixture of 1.6 wt% NaOH and 0.97 wt% polishing additive at 65°C. Alkaline polishing was followed by a pure water rinse.

[0149] Using a tubular LPCVD device, with a chamber temperature in the 600°C range, O2 is introduced to react with Si to form SiOx, depositing a 0.8nm thick tunnel oxide layer. At the same temperature, SiH4 is introduced, where it thermally decomposes to form Si and H2, depositing a 100nm thick polysilicon layer. Finally, oxygen is introduced to form a 3nm thick oxide protective layer.

[0150] The oxide layer on the front side of the silicon wafer was removed using a chain device with a 5 wt% HF solution.

[0151] The silicon wafer was placed in a tank containing a 5:1 ratio of water and KOH solution, heated to 35°C, and soaked for 100 seconds to remove the front polysilicon layer.

[0152] The oxide layer on the back of the silicon wafer was removed using a chain device with a 5 wt% HF solution.

[0153] In the presence of oxygen, POCl3 decomposes at high temperature to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5). The generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms.

[0154] PSG was removed using a chain device with a 5 wt% HF solution.

[0155] The silicon wafer was placed in a tank containing a 5:1 ratio of water and KOH solution, heated to 35°C, and soaked for 100 seconds to remove the front polysilicon layer.

[0156] After alkaline cleaning, water washing is used to remove impurities. The silicon wafer is then placed in a tank containing HF solution to remove the front and back oxide layers. The ratio of H2O to HF solution in the tank is 12:1.

[0157] The gaseous precursors TMA and H2O are pulsed alternately into the reaction chamber, and a deposited film AL2O3 is generated on the front side of the silicon wafer through a chemical adsorption reaction.

[0158] A silicon nitride passivation layer was deposited on the front and back sides of the silicon wafer using PECVD. SiH4 and NH3 were introduced into a graphite boat, the temperature inside the boat was raised to 500°C, 10 kW of RF power was applied, the pressure was set to 2000 mTorr, and the deposition duration was 600 seconds.

[0159] Metal paste is printed on the front and back of the silicon wafer and sintered at high temperature through a screen to form an ohmic contact between the silicon wafer and the metal electrode.

[0160] The performance of the battery prepared in the above embodiment was tested, and the results are shown in Table 1 below.

[0161] Table 1 - Battery performance test results

[0162] Voc(mV) Isc(A) Rs(mΩ) Rsh(Ω) FF(%) IRev2(A) Eff(%) Example 1 741.1 13.921 0.88 374 85.51 0.04216 26.359 Example 2 741.5 13.925 0.89 377 85.50 0.04220 26.361 Example 3 741.3 13.928 0.90 375 85.50 0.04218 26.363 Comparative Example 1 739.5 13.848 0.77 721 85.73 0.02192 26.232

[0163] As shown in Table 1, compared to Comparative Example 1, Example 1 shows an increase in Voc by 1.6 mV, an increase in Isc by 0.073 A, an increase in Rs by 0.11 mΩ, a decrease in Rsh by 347 Ω, a decrease in FF by 0.22%, an increase in Irev2 by 0.02024 A, and an increase in Eff by 0.127%. Therefore, the battery prepared according to the embodiments of the present disclosure exhibits superior performance, such as higher voltage and current, and lower parasitic absorption.

[0164] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some embodiments, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A silicon wafer having a back-side stacked SE structure, characterized in that: The back side of the silicon wafer has a tunneling oxide layer and an intrinsic polysilicon layer stacked on top of each other.

2. The silicon wafer with a back-side stacked SE structure according to claim 1, wherein: The stacked tunneling oxide layer and intrinsic polysilicon layer include a first tunneling oxide layer, a first intrinsic polysilicon layer, a second tunneling oxide layer and a second intrinsic polysilicon layer which are deposited in sequence.

3. The silicon wafer with a back-side stacked SE structure according to claim 2, wherein: The thickness of the first tunneling oxide layer is 0.2-1 nm, the thickness of the first intrinsic polysilicon layer is 50-150 nm, the thickness of the second tunneling oxide layer is 0.5-1.5 nm, and the thickness of the second intrinsic polysilicon layer is 30-50 nm.

4. A TOPCon solar cell, characterized in that: The TOPCon solar cell comprises a silicon wafer having a back-side stacked SE structure according to any one of claims 1 to 3.

5. A method for preparing a TOPCon solar cell, characterized in that: The preparation method comprises the following steps: The step of depositing a tunneling oxide layer, an intrinsic polysilicon layer, and an oxide layer at one time; Steps for engraving non-printing area graphics on the screen using a high-energy laser; A step of removing the intrinsic polysilicon layer in the laser area by a single alkali wash; and The step of depositing a tunneling oxide layer and an intrinsic polysilicon layer twice.

6. The method for preparing a TOPCon solar cell according to claim 5, characterized in that: In the step of depositing the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer at one time, in the range of 500-800°C, oxygen is used as the process gas to deposit and form the first tunneling oxide layer; SiH4 is used as the process gas to deposit and form the first intrinsic polysilicon layer; and oxygen is used as the process gas to deposit and form the oxide layer.

7. The method for preparing a TOPCon solar cell according to claim 6, characterized in that: The thickness of the first tunneling oxide layer is 0.2-1 nm, and the thickness of the first intrinsic polysilicon layer is 50-150 nm.

8. The method for preparing a TOPCon solar cell according to claim 5, wherein: In the step of using a high-energy laser to engrave the pattern of the non-printing area of ​​the screen, the laser power is 5-10KW and the engraving speed is 1000-3000mm / s.

9. The method for preparing a TOPCon solar cell according to claim 5, wherein: In the step of removing the intrinsic polysilicon layer in the laser area by one alkali washing, the silicon wafer is immersed in a KOH solution at a temperature range of 20-50° C. for 50-200 seconds.

10. The method for preparing a TOPCon solar cell according to claim 5, wherein: In the step of depositing the tunneling oxide layer and the intrinsic polysilicon layer twice, the second tunneling oxide layer is deposited by using oxygen as a process gas in the range of 500-800° C.; and the second intrinsic polysilicon layer is deposited by using SiH 4 as a process gas.

11. The method for preparing a TOPCon solar cell according to claim 10, characterized in that: The thickness of the second tunneling oxide layer is 0.5-1.5 nm, and the thickness of the second intrinsic polysilicon layer is 30-50 nm.

12. The method for preparing a TOPCon solar cell according to claim 5, characterized in that: Before the step of depositing the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer at one time, the method further includes the steps of cleaning and texturing the N-type silicon wafer, diffusing P-type impurities on the N-type silicon wafer to form a PN junction, removing BSG and polishing the back side.

13. The method for preparing a TOPCon solar cell according to claim 5, wherein: After the step of engraving the non-printing area pattern of the screen with a high-energy laser and before the step of removing the intrinsic polysilicon layer in the laser area by one alkali wash, the method further includes the step of removing the oxide layer on the front side of the silicon wafer.

14. The method for preparing a TOPCon solar cell according to claim 5, characterized in that: Before the step of secondary depositing the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer, the method further includes a step of removing the oxide layer on the back side of the silicon wafer.

15. The method for preparing a TOPCon solar cell according to claim 5, characterized in that: After the steps of secondary deposition of the tunneling oxide layer, the intrinsic polysilicon layer and the oxide layer, the method further includes the steps of phosphorus doping the silicon wafer, removing PSG, secondary alkali washing and acid washing, depositing an aluminum oxide passivation layer, depositing front and back silicon nitride layers, and metallizing to form ohmic contacts.

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