Display panel for improving wiring fracture and packaging method thereof

Abstract

The invention provides a display panel for improving wiring breakage and a packaging method thereof, and belongs to the technical field of photoelectron manufacturing. The display panel comprises a bearing substrate, a driving chip, a light-emitting device and at least one wiring layer, the driving chip and the light-emitting device are both located on the same side of the bearing substrate, the at least one wiring layer is stacked on the surface of the bearing substrate, the wiring layer comprises a planarization layer and a metal wire, the metal wire is located on one surface of the planarization layer and extends to the other surface of the planarization layer through a via hole, and the metal wires of every two adjacent wiring layers are connected; the planarization layer closest to the wiring layer of the bearing substrate is located on the surface of the bearing substrate and covers the light-emitting device, and the metal wire of the wiring layer closest to the bearing substrate is connected with an electrode of the light-emitting device through a via hole; and the metal wires farthest from the wiring layer of the bearing substrate are connected with the pins of the driving chip. The problem that wiring metal is prone to breakage can be solved.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a display panel capable of improving wiring breakage and a packaging method thereof. Background Art

[0002] In the emerging display industry, Mini / Micro LEDs are continuously expanding the application boundaries of display screens. MIP (MicroLED in package) is a technology that packages three-color LED chips on a single substrate. AMIP (AMIC & Micro LED in Package) integrates an active driver IC and three-color Micro LEDs into a single package, achieving a unified lamp and driver.

[0003] The AMIP display panel in the related art usually arranges the driver IC and the three-color Micro LED on a substrate, and the pins of the driver IC are connected to the pads of the three-color Micro LED through wiring metal.

[0004] However, the thickness of the driver IC is in the hundreds of microns, while the thickness of the Micro LED chip is within 10μm. The difference in thickness between the two is huge. There is a huge gap during packaging after integration, which makes the wiring metal easily break and causes abnormal electrical connections. Summary of the Invention

[0005] The present disclosure provides a display panel and packaging method for improving wiring breakage, which can improve the problem of easy breakage of wiring metal due to the large difference in thickness between the driver IC and Micro LED core when packaging them. The technical solution is as follows:

[0006] An embodiment of the present disclosure provides a display panel, which includes: a carrier substrate, a driver chip, a light-emitting device and at least one wiring layer; the driver chip and the light-emitting device are located on the same side of the carrier substrate, and at least one wiring layer is stacked on the surface of the carrier substrate. The wiring layer includes a planarization layer and metal traces, and the surface of the planarization layer has a via hole penetrating the planarization layer. The metal traces are located on one surface of the planarization layer and extend to the other surface of the planarization layer through the via hole, and the metal traces of two adjacent wiring layers are connected; the planarization layer closest to the carrier substrate is located on the surface of the carrier substrate and covers the light-emitting device, and the metal traces closest to the carrier substrate are connected to the electrodes of the light-emitting device through the via hole; the metal traces farthest from the carrier substrate are connected to the pins of the driver chip.

[0007] In another implementation of the embodiment of the present disclosure, the thickness of the wiring layer is less than or equal to 10 μm.

[0008] In another implementation of the embodiment of the present disclosure, the display panel includes multiple layers of wiring layers stacked in sequence on the carrier substrate; in two adjacent wiring layers, the orthographic projection of the via hole in the planarization layer away from the carrier substrate on the surface of the carrier substrate is located within the orthographic projection of the metal trace close to the carrier substrate on the surface of the carrier substrate.

[0009] In another implementation of the embodiment of the present disclosure, the metal traces of the multiple wiring layers are connected in a step-like manner.

[0010] In another implementation of the embodiment of the present disclosure, the surface of the carrier substrate has a concave hole, the driving chip is located in the concave hole, and at least a portion of the driving chip is located outside the concave hole.

[0011] In another implementation of the embodiment of the present disclosure, the display panel also includes a protective layer, which is located on the surface of the carrier substrate away from the driver chip; the surface of the carrier substrate close to the driver chip has a groove exposing the protective layer, and the groove at least passes through the carrier substrate, the driver chip is located in the groove, and at least part of the driver chip is located outside the groove.

[0012] In another implementation of the embodiment of the present disclosure, the thickness of the carrier substrate is 0.3 mm to 0.7 mm.

[0013] In another implementation of the embodiment of the present disclosure, the planarization layer includes at least one of a silicon oxide layer, an aluminum oxide layer, and a titanium oxide layer.

[0014] An embodiment of the present disclosure provides a packaging method for a display panel, the packaging method comprising: bonding a driver chip and a light-emitting device on the same side of a carrier substrate; forming at least one wiring layer on the surface of the carrier substrate, the wiring layer comprising a planarization layer and metal traces, the surface of the planarization layer having vias penetrating the planarization layer, the metal traces being located on one surface of the planarization layer and extending to the other surface of the planarization layer through the vias, the metal traces of two adjacent wiring layers being connected; the planarization layer of the wiring layer closest to the carrier substrate being located on the surface of the carrier substrate and covering the light-emitting device, the metal traces of the wiring layer closest to the carrier substrate being connected to the electrodes of the light-emitting device through vias; the metal traces of the wiring layer farthest from the carrier substrate being connected to the pins of the driver chip.

[0015] In another implementation of the embodiment of the present disclosure, forming at least one wiring layer on the surface of the carrier substrate includes: controlling the thickness of the wiring layer to be less than or equal to 10 μm.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0017] The display panel provided by the embodiment of the present disclosure is provided with at least one wiring layer on a carrier substrate, wherein the wiring layer includes a planarization layer and metal traces, the surface of the planarization layer has vias penetrating the planarization layer, the metal traces are located on one surface of the planarization layer and extend to the other surface of the planarization layer through the vias, and the metal traces of two adjacent wiring layers are connected. In this way, when multiple wiring layers are stacked, the metal traces of the topmost wiring layer and the bottommost wiring layer can also be electrically connected through the metal traces of the middle wiring layer. The metal traces of the bottommost wiring layer are electrically connected to the light-emitting device, and the metal traces of the topmost wiring layer are connected to the pins of the driver chip. Therefore, the wiring layer can be used to achieve electrical connection between the driver chip and the light-emitting device. In this way, even if the thickness of the driver chip and the thickness of the light-emitting device differ too much, forming a large gap, multiple wiring layers can be stacked to fill the thickness difference between the driver chip and the light-emitting device. In this way, the total climbing height of the metal trace is reduced to multiple climbing heights of small distances by using the wiring layer, which can effectively avoid the problem of the metal trace breaking due to excessive single climbing height, thereby improving the reliability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0020] Figure 2 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0021] Figure 3 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0022] Figure 4 is a flow chart of a display panel packaging method provided by an embodiment of the present disclosure;

[0023] Figure 5 is a packaging state diagram of a display panel provided by an embodiment of the present disclosure;

[0024] Figure 6 is a packaging state diagram of a display panel provided by an embodiment of the present disclosure;

[0025] Figure 7 This is a packaging state diagram of a display panel provided by an embodiment of the present disclosure.

[0026] The descriptions of the marks in the figure are as follows:

[0027] 10. Carrying substrate; 11. Concave hole; 12. Groove;

[0028] 20. Driver chip;

[0029] 30. Light-emitting devices;

[0030] 40. Wiring layer; 41. Planarization layer; 42. Metal traces;

[0031] 50. Protective layer. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0033] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] Figure 1 Schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 1 As shown, the display panel includes: a carrier substrate 10 , a driving chip 20 , a light emitting device 30 and at least one wiring layer 40 .

[0035] like Figure 1As shown, the driving chip 20 and the light-emitting device 30 are both located on the same side of the carrier substrate 10, at least one wiring layer 40 is stacked on the surface of the carrier substrate 10, the wiring layer 40 includes a planarization layer 41 and a metal trace 42, the surface of the planarization layer 41 has a via hole passing through the planarization layer 41, the metal trace 42 is located on one surface of the planarization layer 41, and the metal trace 42 extends to the other surface of the planarization layer 41 through the via hole, and the metal traces 42 of two adjacent wiring layers 40 are connected.

[0036] like Figure 1 As shown, the planarization layer 41 of the wiring layer 40 closest to the carrier substrate 10 is located on the surface of the carrier substrate 10 and covers the light-emitting device 30, and the metal traces 42 of the wiring layer 40 closest to the carrier substrate 10 are connected to the electrodes of the light-emitting device 30 through vias.

[0037] like Figure 1 As shown, the metal trace 42 of the wiring layer 40 farthest from the carrier substrate 10 is connected to the pin of the driver chip 20 .

[0038] The display panel provided by the embodiment of the present disclosure is provided with at least one wiring layer 40 on the carrier substrate 10, wherein the wiring layer 40 includes a planarization layer 41 and metal traces 42, the surface of the planarization layer 41 has vias penetrating the planarization layer 41, the metal traces 42 are located on one surface of the planarization layer 41, and extend to the other surface of the planarization layer 41 through the vias, and the metal traces 42 of two adjacent wiring layers 40 are connected. In this way, when multiple wiring layers 40 are stacked, the metal traces 42 of the topmost wiring layer 40 and the bottommost wiring layer 40 can also be electrically connected through the metal traces 42 of the middle wiring layer 40. The metal traces 42 of the bottommost wiring layer 40 are electrically connected to the light-emitting device 30, and the metal traces 42 of the topmost wiring layer 40 are connected to the pins of the driver chip 20. Therefore, the wiring layer 40 can be used to achieve electrical connection between the driver chip 20 and the light-emitting device 30. Even if the thickness difference between the driver chip 20 and the light-emitting device 30 is too great, resulting in a large step, multiple wiring layers 40 can be stacked to fill the gap. Using the wiring layers 40, the total slope of the metal traces 42 is reduced to multiple smaller slopes, effectively preventing the metal traces 42 from breaking due to excessive single slopes, thereby improving the reliability of the display panel.

[0039] Exemplarily, the driver chip 20 includes a driver integrated circuit (IC).

[0040] Optionally, the carrier substrate 10 may be a glass substrate.

[0041] The glass substrate's surface is extremely flat, providing a precise physical foundation for arranging the light-emitting devices 30 and etching the circuits. Furthermore, the glass substrate's light transmittance exceeds 90%, minimizing light scattering and absorption, ensuring color reproduction and brightness uniformity.

[0042] Optionally, the thickness of the carrier substrate 10 is 0.3 mm to 0.7 mm. Exemplarily, the thickness of the carrier substrate 10 is 0.5 mm.

[0043] By setting the thickness of the carrier substrate 10 within the above range, the weight of the display panel can be significantly reduced, improving portability. Furthermore, a carrier substrate 10 of this thickness offers good impact resistance, reducing the risk of damage to the display panel from drops. Furthermore, an ultra-thin carrier substrate 10 can provide a clearer display, supporting the demand for high-resolution screens.

[0044] Optionally, the light emitting device 30 includes: a carrier, electrodes, and a plurality of pixel chips, wherein the plurality of pixel chips are arranged on a surface of the carrier at intervals. The electrodes are located on the surface of the pixel chips and are electrically connected to the pixel chips.

[0045] Optionally, the light emitting device 30 further includes a light shielding layer, which is located on the surface of the carrier and in the gaps between the pixel chips. The light shielding layer is used to connect the side walls of the pixel chips, thereby more reliably fixing the pixel chips on the carrier.

[0046] For example, the light shielding layer includes a silicon oxide layer and a black coating on the surface of the silicon oxide layer. The light shielding layer is black so that most of the light entering the light shielding layer is absorbed, preventing the light from being emitted laterally to other pixel chips and causing light crosstalk.

[0047] For example, the light shielding layer may be a distributed Bragg reflector (DBR) layer, which can reflect light, thereby effectively blocking the light from being emitted laterally, avoiding the problem of light crosstalk and improving the brightness of the light emitting device 30 .

[0048] The DBR layer includes a plurality of SiO2 layers and TiO2 layers that are periodically and alternately stacked. The number of periods in the DBR layer can be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0049] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0050] Optionally, the light-emitting device 30 may further include a passivation layer, which is located on a surface of the light-shielding layer away from the carrier and covers each pixel chip. The passivation layer also has through holes that expose each pixel chip. Electrodes are located on a surface of the passivation layer away from the carrier and are electrically connected to the pixel chips through the through holes.

[0051] By forming a passivation layer on the surface of the light-shielding layer, not only can the pixel chip be protected, but the passivation layer can also make the surface of the light-emitting device 30 smoother, which is beneficial for the subsequent formation of electrodes and prevents the electrodes from breaking.

[0052] For example, the passivation layer may be a silicon oxide layer, which can stably fix the pixel chip on the carrier.

[0053] Optionally, the plurality of pixel chips include: a first pixel chip, a second pixel chip and a third pixel chip, and the first pixel chip, the second pixel chip and the third pixel chip all emit light of different colors.

[0054] In the embodiment of the present disclosure, the plurality of pixel chips include a first pixel chip that emits red light, a second pixel chip that emits green light, and a third pixel chip that emits blue light.

[0055] The difference between the first pixel chip, the second pixel chip and the third pixel chip lies in the different luminescent colors of the epitaxial layers.

[0056] For the first pixel chip, the epitaxial layer is a red epitaxial layer. For the second pixel chip, the epitaxial layer is a green epitaxial layer. For the third pixel chip, the epitaxial layer is a blue epitaxial layer.

[0057] The red epitaxial layer includes a first p-type layer, a first light-emitting layer and a first n-type layer stacked in sequence.

[0058] In the red epitaxial layer, the first p-type layer includes a p-type AlInP layer.

[0059] The first light-emitting layer includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The first light-emitting layer may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0060] The first n-type layer includes an n-type AlGaInP current spreading layer.

[0061] In the embodiment of the present disclosure, the green epitaxial layer includes a second p-type layer, a second light-emitting layer, and a second n-type layer stacked in sequence.

[0062] In the green epitaxial layer, the second p-type layer includes a p-type GaN layer.

[0063] The second light-emitting layer includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The second light-emitting layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0064] The second n-type layer includes an n-type GaN layer.

[0065] In the embodiment of the present disclosure, the blue epitaxial layer includes a third p-type layer, a third light-emitting layer, and a third n-type layer stacked in sequence.

[0066] In the blue epitaxial layer, the third p-type layer includes a p-type GaN layer.

[0067] The third light-emitting layer may include alternately grown InGaN quantum well layers and GaN quantum barrier layers. The third light-emitting layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0068] The third n-type layer includes an n-type GaN layer.

[0069] Optionally, the pixel chip has a thickness of 2 μm to 10 μm.

[0070] Exemplarily, the thickness of the red epitaxial layer is 5 μm, the thickness of the green epitaxial layer is 8 μm, and the thickness of the blue epitaxial layer is 6 μm.

[0071] Illustratively, the carrier may be a sapphire substrate or a glass substrate.

[0072] Optionally, the thickness of the wiring layer 40 is less than or equal to 10 μm.

[0073] Illustratively, the thickness of the wiring layer 40 may be 3 μm to 10 μm.

[0074] In the embodiment of the present disclosure, controlling the thickness of the wiring layer 40 within the above-mentioned range can avoid the thickness of the wiring layer 40 being set too large, which would cause the climbing height of the metal trace 42 to be too large, causing the metal trace 42 to break; it can also avoid the thickness of the wiring layer 40 being too small, which would fail to isolate and protect the metal trace 42.

[0075] Optionally, the display panel includes multiple wiring layers 40 sequentially stacked on the carrier substrate 10 .

[0076] For example, Figure 1 As shown, the display panel includes four sequentially stacked wiring layers 40. The total thickness of the four stacked wiring layers 40 does not exceed the thickness of the display panel.

[0077] like Figure 1As shown, in two adjacent wiring layers 40 , the orthographic projection of the via hole in the planarization layer 41 away from the carrier substrate 10 on the surface of the carrier substrate 10 is located within the orthographic projection of the metal trace 42 close to the carrier substrate 10 on the surface of the carrier substrate 10 .

[0078] In two adjacent wiring layers 40, the vias of the upper planarization layer 41 expose the metal traces 42 on the lower planarization layer 41, so that the metal traces 42 on the upper planarization layer 41 can be directly extended to the metal traces 42 of the lower planarization layer 41 through the vias, which is conducive to achieving electrical connection between the upper and lower metal traces 42.

[0079] Optionally, the metal traces 42 of the multi-layer wiring layer 40 are connected in a stair-like manner.

[0080] For example, Figure 1 As shown, four wiring layers 40 are stacked sequentially on the carrier substrate 10, with the light-emitting device 30 as the center. The metal traces 42 in each wiring layer 40 are offset horizontally away from the light-emitting device 30, so that the metal traces 42 on the four wiring layers 40 are connected together to form four steps. In this way, the four wiring layers 40 are stacked to fill the thickness difference between the driver chip 20 and the light-emitting device 30. The wiring layers 40 reduce the total climbing height of the metal traces 42 to the climbing height of the four planarization layers 41, effectively avoiding the problem of metal traces 42 breaking due to excessive single climbing height.

[0081] Figure 2 Schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 2 As shown, a surface of the carrier substrate 10 has a concave hole 11 , the driving chip 20 is located in the concave hole 11 , and at least a portion of the driving chip 20 is located outside the concave hole 11 .

[0082] In the above implementation, by drilling holes in the surface of the carrier substrate 10, the driver chip 20 can be sunken into the recessed hole 11, thereby reducing the height difference between the driver chip 20 and the light-emitting device 30. Only a flattening layer 41 needs to be provided on the upper surface of the carrier substrate 10 to realize the metal traces 42 connecting the pins of the driver chip 20 to the electrodes of the light-emitting device 30.

[0083] Among them, such as Figure 2 As shown, if the thickness of the driver chip 20 is smaller than that of the carrier substrate 10, the hole drilled in the carrier substrate 10 is a blind hole, that is, the recessed hole 11 does not penetrate the carrier substrate 10. This allows a portion of the driver chip 20 to be embedded in the carrier substrate 10, while the other portion that needs to be electrically connected to the metal trace 42 protrudes from the upper surface of the carrier substrate 10.

[0084] For example, the thickness of the portion of the driver chip 20 protruding from the upper surface of the carrier substrate 10 may be less than or equal to 10 μm, which will not cause the metal trace 42 to have an excessively large climbing height, thereby preventing the metal trace 42 from breaking.

[0085] Figure 3 Schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 3 As shown, the display panel further includes a protection layer 50 , which is located on a surface of the carrier substrate 10 away from the driving chip 20 .

[0086] like Figure 3 As shown, a groove 12 exposing the protective layer 50 is formed on the surface of the carrier substrate 10 near the driver chip 20 . The groove 12 at least passes through the carrier substrate 10 . The driver chip 20 is located in the groove 12 , and at least part of the driver chip 20 is located outside the groove 12 .

[0087] In the above implementation, holes are drilled in the surface of the carrier substrate 10 to allow the driver chip 20 to be sunken into the groove 12, thereby reducing the height difference between the driver chip 20 and the light-emitting device 30. Only a flattening layer 41 needs to be provided on the upper surface of the carrier substrate 10 to allow metal traces 42 to connect the pins of the driver chip 20 to the electrodes of the light-emitting device 30.

[0088] Among them, such as Figure 3 As shown, if the thickness of the driver chip 20 is greater than the thickness of the carrier substrate 10, and the hole punched on the carrier substrate 10 is a through hole, a protective layer 50 needs to be provided on the lower surface of the carrier substrate 10 to wrap and protect the portion of the driver chip 20 protruding from the lower surface of the carrier substrate 10, and to ensure the flatness of the overall appearance of the display panel for the subsequent use of the entire screen.

[0089] For example, the thickness of the portion of the driver chip 20 protruding from the upper surface of the carrier substrate 10 may be less than or equal to 10 μm, which will not cause the metal trace 42 to have an excessively large climbing height, thereby preventing the metal trace 42 from breaking.

[0090] Optionally, the planarization layer 41 includes at least one of a silicon oxide layer, an aluminum oxide layer, and a titanium oxide layer.

[0091] For example, the planarization layer 41 may include a plurality of periodically alternately stacked SiO2 layers and TiO2 layers, that is, the planarization layer 41 is a DBR layer, which allows the planarization layer 41 to also reflect light, thereby improving the brightness of the light-emitting device 30.

[0092] Figure 4 FIG. 1 is a flow chart of a method for packaging a display panel provided by an embodiment of the present disclosure. Figure 4 As shown, the packaging method includes:

[0093] Step 101 : Bond the driver chip 20 and the light-emitting device 30 on the same side of the carrier substrate 10 .

[0094] Exemplarily, the driver chip 20 includes a driver integrated circuit.

[0095] For example, the carrier substrate 10 may be a glass substrate.

[0096] Optionally, the thickness of the carrier substrate 10 is 0.3 mm to 0.7 mm. Exemplarily, the thickness of the carrier substrate 10 is 0.5 mm.

[0097] Optionally, the light emitting device 30 includes: a carrier, electrodes, and a plurality of pixel chips, wherein the plurality of pixel chips are arranged on a surface of the carrier at intervals. The electrodes are located on the surface of the pixel chips and are electrically connected to the pixel chips.

[0098] Optionally, the plurality of pixel chips include: a first pixel chip, a second pixel chip and a third pixel chip, and the first pixel chip, the second pixel chip and the third pixel chip all emit light of different colors.

[0099] In the embodiment of the present disclosure, the plurality of pixel chips include a first pixel chip that emits red light, a second pixel chip that emits green light, and a third pixel chip that emits blue light.

[0100] The difference between the first pixel chip, the second pixel chip and the third pixel chip lies in the different luminescent colors of the epitaxial layers.

[0101] Step 102 : forming at least one wiring layer 40 on the surface of the carrier substrate 10 .

[0102] Among them, the wiring layer 40 includes a planarization layer 41 and a metal trace 42. The surface of the planarization layer 41 has a via that penetrates the planarization layer 41. The metal trace 42 is located on one surface of the planarization layer 41 and extends to the other surface of the planarization layer 41 through the via. The metal traces 42 of two adjacent wiring layers 40 are connected; the planarization layer 41 of the wiring layer 40 closest to the carrier substrate 10 is located on the surface of the carrier substrate 10 and covers the light-emitting device 30. The metal trace 42 of the wiring layer 40 closest to the carrier substrate 10 is connected to the electrode of the light-emitting device 30 through the via; the metal trace 42 of the wiring layer 40 farthest from the carrier substrate 10 is connected to the pin of the driving chip 20.

[0103] The display panel packaged by the packaging method provided by the embodiment of the present disclosure is provided with at least one wiring layer 40 on the carrier substrate 10, wherein the wiring layer 40 includes a planarization layer 41 and a metal trace 42, the surface of the planarization layer 41 has a via hole penetrating the planarization layer 41, the metal trace 42 is located on one surface of the planarization layer 41, and extends to the other surface of the planarization layer 41 through the via hole, and the metal traces 42 of two adjacent wiring layers 40 are connected. In this way, when multiple wiring layers 40 are stacked, the metal traces 42 of the topmost wiring layer 40 and the bottommost wiring layer 40 can also be electrically connected through the metal traces 42 of the middle wiring layer 40. The metal traces 42 of the bottommost wiring layer 40 are electrically connected to the light-emitting device 30, and the metal traces 42 of the topmost wiring layer 40 are connected to the pins of the driver chip 20. Therefore, the wiring layer 40 can be used to achieve electrical connection between the driver chip 20 and the light-emitting device 30. Even if the thickness difference between the driver chip 20 and the light-emitting device 30 is too great, resulting in a large step, multiple wiring layers 40 can be stacked to fill the gap. Using the wiring layers 40, the total slope of the metal traces 42 is reduced to multiple smaller slopes, effectively preventing the metal traces 42 from breaking due to excessive single slopes, thereby improving the reliability of the display panel.

[0104] Step 101 may include the following steps:

[0105] like Figure 5 As shown, the driving chip 20 and the light emitting device 30 are bonded to the upper surface of the carrier substrate 10 on a carrier substrate 10 with a thickness of 0.5 mm.

[0106] Step 102 may include the following steps:

[0107] First, if Figure 6 As shown, a first layer of planarization glue is applied, and then holes are opened in the light emitting device 30 corresponding to the electrode positions by means of coating, exposure, development, and etching.

[0108] Then, if Figure 6 As shown, the first metal trace 42 is connected to the electrode of the light-emitting device 30 through the via hole of the first planarization layer 41 by evaporation, and the metal trace 42 is led out from the upper surface of the first planarization layer 41.

[0109] Then, if Figure 7 As shown, a second layer of planarization glue is applied, and then vias corresponding to the first layer of metal traces 42 are opened through methods of coating, exposure, development, and etching.

[0110] Then, if Figure 7As shown, the second layer of metal traces 42 are connected to the first layer of metal traces 42 through the openings of the second layer of planarization glue by evaporation, and the metal traces 42 are led out from the upper surface of the second layer of planarization layer 41.

[0111] Then, the four-layer wiring layer 40 is prepared in the above manner. Figure 1 As shown, after the fourth layer of planarization glue is opened, the fourth layer of metal traces 42 are connected to the third layer of metal traces 42 through the openings, and are also connected to the pins corresponding to the driver chip 20 on the upper surface of the fourth layer of planarization layer 41 .

[0112] In the embodiment of the present disclosure, forming at least one wiring layer 40 on the surface of the carrier substrate 10 includes: controlling the thickness of the wiring layer 40 to be less than or equal to 10 μm.

[0113] Illustratively, the thickness of the wiring layer 40 may be 3 μm to 10 μm.

[0114] In the embodiment of the present disclosure, controlling the thickness of the wiring layer 40 within the above-mentioned range can avoid the thickness of the wiring layer 40 being set too large, which would cause the climbing height of the metal trace 42 to be too large, causing the metal trace 42 to break; it can also avoid the thickness of the wiring layer 40 being too small, which would fail to isolate and protect the metal trace 42.

[0115] The above does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not intended to limit the present disclosure. Any technician familiar with the profession can make slight changes or modifications to equivalent embodiments with equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel comprises: a carrier substrate (10), a driving chip (20), a light-emitting device (30) and at least one wiring layer (40); The driving chip (20) and the light-emitting device (30) are both located on the same side of the carrier substrate (10); at least one wiring layer (40) is stacked on the surface of the carrier substrate (10); the wiring layer (40) comprises a planarization layer (41) and a metal trace (42); the surface of the planarization layer (41) has a via hole penetrating the planarization layer (41); the metal trace (42) is located on one surface of the planarization layer (41) and extends to the other surface of the planarization layer (41) through the via hole; the metal traces (42) of two adjacent wiring layers (40) are connected; The planarization layer (41) closest to the carrier substrate (10) is located on the surface of the carrier substrate (10) and covers the light-emitting device (30), and the metal trace (42) closest to the carrier substrate (10) is connected to the electrode of the light-emitting device (30) through a via hole; The metal trace (42) farthest from the carrier substrate (10) is connected to the pin of the driver chip (20).

2. The display panel according to claim 1, wherein: The thickness of the wiring layer (40) is less than or equal to 10 μm.

3. The display panel according to claim 1 or 2, wherein: The display panel comprises a plurality of wiring layers (40) sequentially stacked on the carrier substrate (10); In two adjacent wiring layers (40), the orthographic projection of the via hole of the planarization layer (41) far away from the carrier substrate (10) on the surface of the carrier substrate (10) is located within the orthographic projection of the metal trace (42) close to the carrier substrate (10) on the surface of the carrier substrate (10).

4. The display panel according to claim 3, wherein: The metal wirings (42) of the multiple wiring layers (40) are connected in a step-like manner.

5. The display panel according to claim 1 or 2, wherein: The surface of the carrier substrate (10) has a concave hole (11), the driving chip (20) is located in the concave hole (11), and at least a portion of the driving chip (20) is located outside the concave hole (11).

6. The display panel according to claim 1 or 2, characterized in that: The display panel further comprises a protective layer (50), wherein the protective layer (50) is located on a surface of the carrier substrate (10) away from the driving chip (20); A groove (12) exposing the protective layer (50) is provided on a surface of the carrier substrate (10) close to the driver chip (20); the groove (12) at least passes through the carrier substrate (10); the driver chip (20) is located in the groove (12), and at least a portion of the driver chip (20) is located outside the groove (12).

7. The display panel according to claim 1 or 2, characterized in that: The thickness of the carrier substrate (10) is 0.3 mm to 0.7 mm.

8. The display panel according to claim 1 or 2, wherein: The planarization layer (41) includes at least one of a silicon oxide layer, an aluminum oxide layer, and a titanium oxide layer.

9. A method for packaging a display panel, characterized in that: The packaging method comprises: Bonding the driver chip and the light-emitting device on the same side of the carrier substrate; At least one wiring layer is formed on the surface of the carrier substrate, and the wiring layer includes a planarization layer and metal routing. The surface of the planarization layer has a via hole penetrating the planarization layer. The metal routing is located on one surface of the planarization layer and extends to the other surface of the planarization layer through the via hole. The metal routings of two adjacent wiring layers are connected. The planarization layer of the wiring layer closest to the carrier substrate is located on the surface of the carrier substrate and covers the light-emitting device. The metal routing of the wiring layer closest to the carrier substrate is connected to the electrode of the light-emitting device through the via hole. The metal routing of the wiring layer farthest from the carrier substrate is connected to the pin of the driver chip.

10. The packaging method according to claim 9, wherein: Forming at least one wiring layer on the surface of the carrier substrate includes: controlling the thickness of the wiring layer to be less than or equal to 10 μm.

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