Display panel and method of manufacturing the same

Abstract

A display panel and a method of manufacturing the same are disclosed. The display panel includes: a base layer; a pixel defining film disposed on the base layer and defining a light emitting opening therein; an auxiliary electrode disposed on the pixel defining film and including a conductive material; a light emitting element including an anode, a light emitting pattern disposed on the pixel defining film and the auxiliary electrode, and a cathode disposed on the auxiliary electrode and the light emitting pattern; and a lower encapsulation inorganic pattern covering the light emitting element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from and all benefits arising from Korean Patent Application No. 10-2024-0030960, filed on March 4, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to a display panel and a method of manufacturing the display panel, and more particularly, to a display panel having improved display quality. Background Art

[0004] Display devices that provide images to users, such as televisions, monitors, smartphones, and tablet personal computers ("PCs"), include display panels that display images. Various display panels, such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels, have been developed as display panels.

[0005] The organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. The light emitting pattern may be separate for each of a plurality of light emitting regions, and the cathode may provide a common voltage to each of the plurality of light emitting regions. Summary of the Invention

[0006] Embodiments of the present disclosure provide a display panel in which a light emitting element is formed without using a metal mask and has improved display quality, and a method of manufacturing the display panel.

[0007] According to an embodiment, a display panel includes: a base layer; a pixel defining film, which is arranged on the base layer and defines a light-emitting opening in the pixel defining film; an auxiliary electrode, which is arranged on the pixel defining film and includes a conductive material; a light-emitting element, including an anode, a light-emitting pattern arranged on the pixel defining film and the auxiliary electrode, and a cathode arranged on the auxiliary electrode and the light-emitting pattern; and a lower encapsulation inorganic pattern, covering the light-emitting element.

[0008] The end of the cathode may be in direct contact with the upper surface of the auxiliary electrode.

[0009] The lower encapsulation inorganic pattern may cover the cathode and may be in direct contact with an upper surface of the auxiliary electrode.

[0010] The auxiliary electrode may define an auxiliary opening therein, and the auxiliary opening may overlap the light emitting opening in a thickness direction of the base layer.

[0011] The light emitting pattern may be provided inside the light emitting opening and the auxiliary opening.

[0012] The auxiliary electrode may include titanium (Ti).

[0013] An end of the lower encapsulation inorganic pattern may extend in a thickness direction of the base layer.

[0014] The light emitting element and the lower encapsulation inorganic pattern may each be provided in plural, and the plurality of light emitting elements may be spaced apart from each other, and the plurality of lower encapsulation inorganic patterns may be spaced apart from each other while respectively covering the plurality of light emitting elements.

[0015] The display panel may further include: a common inorganic film having an integral shape while covering the plurality of lower encapsulation inorganic patterns; an encapsulation organic film disposed on the common inorganic film; and an upper encapsulation inorganic film disposed on the encapsulation organic film.

[0016] A plurality of outer surfaces of the plurality of lower encapsulation inorganic patterns may define a gap region, and a common inorganic film may cover the plurality of outer surfaces of the plurality of lower encapsulation inorganic patterns and an upper surface of the auxiliary electrode.

[0017] According to an embodiment, a display panel includes: a base layer; a pixel defining film, which is arranged on the base layer and defines a first light-emitting opening and a second light-emitting opening in the pixel defining film; an auxiliary electrode, which is arranged on the pixel defining film; a first light-emitting element, including a first anode, a first light-emitting pattern and a first cathode arranged sequentially in the thickness direction of the base layer; a second light-emitting element, including a second anode, a second light-emitting pattern and a second cathode arranged sequentially in the thickness direction of the base layer; a first lower encapsulation inorganic pattern, which is arranged on the first light-emitting element and the auxiliary electrode, and covers the first light-emitting element; a second lower encapsulation inorganic pattern, which is arranged on the second light-emitting element and the auxiliary electrode, covers the second light-emitting element, and is separated from the first lower encapsulation inorganic pattern; and a common inorganic film, which covers the upper surface and outer surface of the first lower encapsulation inorganic pattern, the upper surface and outer surface of the second lower encapsulation inorganic pattern, and the upper surface of the auxiliary electrode.

[0018] According to an embodiment, a method for manufacturing a display panel includes: providing a preliminary display panel including a base layer and a pixel defining film disposed on the base layer; forming a preliminary partition wall including a first preliminary partition wall layer, a second preliminary partition wall layer, and a third preliminary partition wall layer and disposed on the preliminary display panel; forming a partition wall from the preliminary partition wall defining a plurality of partition wall openings therein and including a first partition wall layer, a second partition wall layer, and a third partition wall layer; forming a plurality of light-emitting openings overlapping with the plurality of partition wall openings by etching the pixel defining film; forming a plurality of light-emitting elements disposed on the pixel defining film and the first partition wall layer; forming a plurality of lower encapsulation inorganic patterns disposed on the plurality of light-emitting elements and the first partition wall layer and covering the plurality of light-emitting elements; and forming an auxiliary electrode by removing the second preliminary partition wall layer and the third preliminary partition wall layer.

[0019] The forming of the partition wall may include dry etching the first to third preliminary partition wall layers; and wet etching the second preliminary partition wall layer, wherein the second partition wall layer may be recessed inwardly compared to the first and third partition wall layers.

[0020] The forming of the plurality of light emitting elements may include: forming a light emitting pattern disposed on the pixel defining film and the first partition wall layer; and forming a cathode disposed on the light emitting pattern such that an end of the cathode contacts an upper surface of the first partition wall layer.

[0021] The forming of the plurality of lower encapsulation inorganic patterns may include depositing a lower encapsulation inorganic layer such that the lower encapsulation inorganic layer covers the cathode and is in direct contact with an upper surface of the first partition wall layer.

[0022] The forming of the plurality of lower encapsulation inorganic patterns may include depositing a lower encapsulation inorganic layer such that the lower encapsulation inorganic layer contacts an upper surface of the first partition wall layer and a side surface of the second partition wall layer.

[0023] The forming of the auxiliary electrode may include forming a gap region between a plurality of outer surfaces of the plurality of lower encapsulation inorganic patterns.

[0024] The method may further include forming a common inorganic film having an integral shape and covering the plurality of outer surfaces of the plurality of lower encapsulation inorganic patterns.

[0025] The method may further include forming a common inorganic film contacting an upper surface of the auxiliary electrode and covering the plurality of lower encapsulation inorganic patterns.

[0026] The forming of the preliminary partition wall may include: depositing a first preliminary partition wall layer including titanium (Ti); depositing a second preliminary partition wall layer including aluminum (Al); and depositing a third preliminary partition wall layer including titanium (Ti). BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0028] Figure 1A is a perspective view of a display device according to an embodiment of the present disclosure.

[0029] Figure 1B is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0030] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0031] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure.

[0032] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to an embodiment of the present disclosure.

[0033] Figure 5 It is along Figure 3 sectional view of the display panel taken along line II'.

[0034] Figure 6 It is along Figure 4 sectional view of the display panel taken along line II-II'.

[0035] Figures 7A to 7L are cross-sectional views illustrating some operations of a method of manufacturing a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In this specification, the expression that a first component (or region, layer, portion, part, etc.) is "disposed on" a second component, "connected with" a second component, or "coupled to" a second component means that the first component is directly disposed on the second component / directly connected with the second component / directly coupled to the second component, or means that a third component is interposed between the first component and the second component.

[0037] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportions, and sizes of the components are exaggerated for the purpose of effectively describing the technical content. The expression "and / or" includes one or more combinations that can be defined for the relevant components.

[0038] Although the terms "first," "second," and the like may be used to describe various components, the components should not be limited by the terms. The terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the proper scope of the present disclosure. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0039] In addition, the terms "under," "beneath," "on," "over," etc. are used to describe the relationship between components shown in the drawings. Conceptually relative terms are described based on the directions shown in the drawings.

[0040] It will be understood that the terms "include", "comprising", "having", etc. indicate the presence of the features, quantities, steps, operations, elements or components or combinations thereof described in this specification, and do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements or components or combinations thereof.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used in the specification have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless expressly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with that in the context of the relevant technology and should not be interpreted in an overly idealized or overly formalized sense.

[0042] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0043] Figure 1A is a perspective view of a display device DD according to an embodiment of the present disclosure, and Figure 1B is an exploded perspective view of a display device DD according to an embodiment of the present disclosure.

[0044] In an embodiment, the display device DD may be a large electronic device such as a television, a monitor, or an external billboard. Furthermore, the display device DD may be a small or medium-sized electronic device such as a personal computer (PC), a laptop computer, a personal digital assistant, an in-car navigation unit, a game console, a smartphone, a tablet PC, or a camera. However, this is illustrative, and other display devices may be employed as long as the display device does not deviate from the concept of the present disclosure. Figure 1A and Figure 1B It is illustratively shown in FIG that the display device DD is a smartphone.

[0045] refer to Figure 1A and Figure 1B , the display device DD can display an image IM in a third direction DR3 on a display surface FS that is parallel to the first direction DR1 and the second direction DR2. The image IM may include a static image and a dynamic image. Figure 1A , a clock window and an icon are shown as examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0046] In an embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each component are defined relative to the direction in which the image IM is displayed. The front surface and the rear surface may face each other in a third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. At the same time, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be changed to other directions. In the specification, the phrase "on a plane" may mean a state when viewed in the third direction DR3 (i.e., in a plan view).

[0047] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to constitute an external appearance of the display device DD.

[0048] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmissive area TA and a bezel area BZA. The transmissive area TA may be an optically transparent area. For example, the transmissive area TA may have a visible light transmittance of approximately 90% or greater.

[0049] The bezel region BZA may be a region having a relatively lower light transmittance than the transmissive region TA. The bezel region BZA may define the shape of the transmissive region TA. The bezel region BZA may be adjacent to and surround the transmissive region TA. However, this is illustrative, and the bezel region BZA of the window WP may be omitted. The window WP may include at least one functional layer selected from an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited to the embodiment.

[0050] The display module DM may be disposed under the window WP. The display module DM may be a component that substantially generates an image IM. The image IM generated by the display module DM is displayed on the display surface IS of the display module DM and is visually recognized by the user from the outside through the transmissive area TA.

[0051] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area activated by an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA is an area covered by the bezel area BZA and may not be visually recognized from the outside.

[0052] The housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide a predetermined inner space. The display module DM may be accommodated in the inner space.

[0053] The housing HAU may be made of a relatively rigid material. For example, the housing HAU may include multiple frames and / or panels made of glass, plastic, metal, or a combination thereof. The housing HAU can stably protect the components of the display device DD housed within the interior space from external impacts.

[0054] Figure 2 is a cross-sectional view of a display module DM according to an embodiment of the present disclosure.

[0055] refer to Figure 2, the display module DM may include a display panel DP and an input sensor INS. Although not shown separately, the display device DD according to an embodiment of the present disclosure (see Figure 1A ) may further include a protection member provided on a lower surface of the display panel DP or an anti-reflection member and / or a window member provided on an upper surface of the input sensor INS.

[0056] The display panel DP may be a light-emitting display panel. However, this is illustrative, and the present disclosure is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro light-emitting diodes ("LEDs"). Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0057] The display panel DP may include a base layer BL, and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE arranged on the base layer BL. The input sensor INS may be directly disposed on the thin film encapsulation layer TFE. In the specification, the phrase "component A is directly disposed on component B" means that no adhesive layer is disposed between components A and B.

[0058] The base layer BL may include at least one plastic film. The base layer BL is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. Figure 1B The display area DA and the non-display area NDA described in may be equally defined on the base layer BL.

[0059] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer may include at least one inorganic layer and at least one organic layer. The circuit elements may include signal lines and pixel driving circuits, etc.

[0060] The display element layer DP-OLED may include partition walls and a light-emitting element. The light-emitting element may include an anode, an intermediate layer, and a cathode.

[0061] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be arranged to improve optical efficiency, and some of which may be arranged to protect the organic light emitting diode.

[0062] The input sensor INS acquires coordinate information of an external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single conductive layer or multiple conductive layers. Furthermore, the input sensor INS may include a single insulating layer or multiple insulating layers. The input sensor INS may sense external input capacitively. However, this is illustrative, and the present disclosure is not limited thereto. For another example, in an embodiment, the input sensor INS may sense external input using electromagnetic induction or pressure sensing. In another embodiment of the present disclosure, the input sensor INS may be omitted.

[0063] Figure 3 is a plan view of the display panel DP according to an embodiment of the present disclosure. As used herein, a “plan view” is a view of the base layer BL (see FIG. Figure 5 ) in the thickness direction (ie, the third direction DR3).

[0064] refer to Figure 3 A display area DA and a non-display area NDA surrounding the display area DA may be defined by a display panel DP. The display panel DP may include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP may also include a drive circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA may be distinguished from each other depending on whether the pixels PX are provided. The pixels PX may be provided in the display area DA. The drive circuit GDC and the pad portion PLD may be arranged in the non-display area NDA.

[0065] The pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2, and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0066] The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL may be connected to a corresponding pixel PX among the pixels PX, and each of the data lines DL may be connected to a corresponding pixel PX among the pixels PX. The power lines PL may be electrically connected to the pixels PX. The control signal lines CSL may be connected to the drive circuit GDC to provide control signals to the drive circuit GDC.

[0067] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the generated gate signal to the gate lines GL. The gate driving circuit may also output another control signal to the pixel driving circuit.

[0068] The pad portion PLD may be a component for connecting a flexible circuit board. The pad portion PLD may include pixel pads D-PD, and the pixel pads D-PD may be pads for connecting the flexible circuit board to the display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line SGL among the signal lines SGL. The pixel pads D-PD may be connected to the corresponding pixel PX via the signal line SGL. In addition, any of the pixel pads D-PD may be connected to the drive circuit GDC.

[0069] In addition, the pad portion PLD may further include an input pad. The input pad may be used to connect the flexible circuit board to the input sensor INS (see Figure 2 However, the present disclosure is not limited thereto, and in another embodiment, the input pad may be arranged on the input sensor INS (see Figure 2 ) and connected to the pixel pad D-PD and a separate circuit board. Optionally, the input sensor INS can be omitted (see Figure 2 ) and may not include input pads.

[0070] Figure 4 The display panel DP according to the embodiment of the present disclosure (see Figure 2 ) is an enlarged plan view of a portion of the display area DA. Figure 4 When the display module DM (see Figure 1B ) of the display surface IS (see Figure 1B ) is a plan view of the display module DM when viewed from FIG. 4 and shows the arrangement of the light emitting areas PXA-R, PXA-G and PXA-B.

[0071] refer to Figure 4 , the display area DA may include a first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B, and a peripheral area NPXA surrounding the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B. The first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may respectively correspond to areas from which light provided from the light emitting element is emitted. The display module DM (see FIG. 2 ) may be configured to be oriented in a manner such that the display area DA is ... Figure 2 ) distinguishes the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B by the color of the light emitted from the outside.

[0072] The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B can respectively provide first, second, and third color lights having different colors. For example, the first color light can be red, the second color light can be green, and the third color light can be blue. However, examples of the first to third color lights are not necessarily limited to the above examples.

[0073] Each of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be defined as a region in which the upper surface of the anode is formed by a light emitting opening OP-E (see FIG. Figure 5 The peripheral area NPXA may set a boundary between the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B and prevent color mixing between the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B.

[0074] The first light-emitting regions PXA-R, the second light-emitting regions PXA-G, and the third light-emitting regions PXA-B may be provided so that all of them are in plural numbers and may be repeatedly arranged in a specific arrangement in the display area DA. For example, the first light-emitting regions PXA-R and the third light-emitting regions PXA-B may be alternately arranged in the first direction DR1 to constitute a "first group." The second light-emitting regions PXA-G may be arranged in the first direction DR1 to constitute a "second group." Each of the "first group" and the "second group" may be provided in plural numbers, and the "first group" and the "second group" may be alternately arranged in the second direction DR2.

[0075] One second light emitting region PXA-G may be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0076] Figure 4 The arrangement form of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B is illustratively shown, but the present disclosure is not limited thereto, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be arranged in various forms. In an embodiment, as Figure 4 As shown in FIG, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have Optionally, the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B may also have a stripe arrangement or a diamond arrangement. Layout form.

[0077] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have various shapes on a plane. For example, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have a shape such as a polygonal shape, a circular shape, or an elliptical shape. Figure 4 The first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (or a diamond shape) on a plane and the second light emitting region PXA-G having an octagonal shape are illustratively shown.

[0078] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have the same shape on a plane or may have at least partially different shapes. Figure 4 The first and third light-emitting regions PXA-R and PXA-B having the same shape on a plane (i.e., in a plan view) and the second light-emitting region PXA-G having a shape different from those of the first and third light-emitting regions PXA-R and PXA-B are illustratively shown.

[0079] At least some of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have different areas on a plane. In an embodiment, the area of ​​the first light-emitting region PXA-R emitting red light may be larger than the area of ​​the second light-emitting region PXA-G emitting green light, and may be smaller than the area of ​​the third light-emitting region PXA-B emitting blue light. However, the size relationship between the areas of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA according to the color of the emitted light is not limited thereto, and may be determined according to the display module DM (see FIG. Figure 2 In addition, the present disclosure is not limited thereto, and in another embodiment, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may also have the same area on a plane.

[0080] Meanwhile, the display module DM (see Figure 2 ) of the first light emitting region PXA-R, the second light emitting region PXA-G and the third light emitting region PXA-B can be shaped, arranged and arranged in accordance with the color of the emitted light or the display module DM (see Figure 2 ) size and configuration to various designs, and is not limited to Figure 4 The embodiment shown in .

[0081] Figure 5 It is along Figure 3 A cross-sectional view of the display panel DP taken along line II'. Figure 5 In the description of Figure 2 Description will be made, and description of the same reference numerals will be omitted. Figure 5 The display area DA is shown in an enlarged manner (see Figure 4 ) in a light emitting region PXA, and Figure 5 The light emitting area PXA may correspond to Figure 4 One of the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B.

[0082] refer to Figure 5 The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0083] The display panel DP may include multiple insulating layers, multiple semiconductor patterns, multiple conductive patterns, and multiple signal lines. The insulating layers, semiconductor layers, and conductive layers are formed by coating or deposition, etc. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching. In this manner, the semiconductor patterns, conductive patterns, and signal lines included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed.

[0084] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal emission region SCL, first insulating layers 10, second insulating layers 20, third insulating layers 30, fourth insulating layers 40, and fifth insulating layers 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0085] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the coupling force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0086] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the present disclosure is not limited thereto, and in another embodiment, the semiconductor pattern may include amorphous silicon or metal oxide. Figure 5 Only a portion of the semiconductor pattern is illustratively shown, and the semiconductor pattern may also be arranged in a plurality of light emitting regions PXA-R, PXA-G, and PXA-B (see FIG. Figure 4). The semiconductor pattern can be arranged across the plurality of light-emitting regions PXA-R, PXA-G, and PXA-B in a specific pattern. The semiconductor pattern can have different electrical properties depending on whether the semiconductor pattern is doped. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0087] The conductivity of the first region is greater than that of the second region, and the first region can be substantially used as an electrode or a signal line. The second region can substantially correspond to the active region (or channel) of the transistor. In other words, a portion of the semiconductor pattern can be the active region of the transistor, another portion of the semiconductor pattern can be the source region or the drain region of the transistor, and another portion of the semiconductor pattern can be the conductive region.

[0088] The source region S, the active region A, and the drain region D of the transistor TR1 may be formed of a semiconductor pattern. Figure 5 A portion of a signal transmission region SCL formed of a semiconductor pattern is shown Although not separately shown, the signal transmission region SCL may be connected to the drain region D of the transistor TR1 on a plane.

[0089] The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be disposed on the buffer layer BFL. The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be an inorganic layer or an organic layer.

[0090] A first insulating layer 10 may be provided on the buffer layer BFL. The first insulating layer 10 may cover the source region S, active region A, drain region D, and signal transmission region SCL of the transistor TR1 provided on the buffer layer BFL. A gate G of the transistor TR1 may be provided on the first insulating layer 10. A second insulating layer 20 may be provided on the first insulating layer 10 to cover the gate G. An electrode EE may be provided on the second insulating layer 20. A third insulating layer 30 may be provided on the second insulating layer 20 to cover the electrode EE.

[0091] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal emission region SCL through a contact hole CNT-1 passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. A fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0092] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. A fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0093] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL and may include a light emitting element ED, a sacrificial pattern SP, a pixel defining layer PDL, a capping pattern CP, and an auxiliary electrode SE.

[0094] The light emitting element ED may include an anode AE ​​(or first electrode), a light emitting pattern EP, and a cathode CE (or second electrode). The light emitting element ED may be disposed in a light emitting opening OP-E and an auxiliary opening OP-SE to be described below.

[0095] The anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 via a contact hole CNT-3 defined via the fifth insulating layer 50. Thus, the anode AE ​​may be electrically connected to the signal emission region SCL via the first connection electrode CNE1 and the second connection electrode CNE2, and thus, electrically connected to the corresponding circuit element. The anode AE ​​may include a single-layer structure or a multi-layer structure. The anode AE ​​may include a plurality of layers including ITO and Ag. For example, the anode AE ​​may include a layer including ITO (hereinafter referred to as a lower ITO layer), a layer including Ag disposed on the lower ITO layer (hereinafter referred to as an Ag layer), and a layer including ITO disposed on the Ag layer (referred to as an upper ITO layer).

[0096] The sacrificial pattern SP may be disposed between the anode electrode AE ​​and the pixel defining film PDL. The sacrificial pattern SP may define (or have) a sacrificial opening OP-S through which a portion of the upper surface of the anode electrode AE ​​is exposed. The sacrificial opening OP-S may overlap with the light emitting opening OP-E described later in a plan view.

[0097] The pixel-defining film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The pixel-defining film PDL may define (or have) an emission opening OP-E. The emission opening OP-E may correspond to the anode AE, and the pixel-defining film PDL may expose at least a portion of the anode AE ​​through the emission opening OP-E.

[0098] In addition, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to an embodiment, the upper surface of the anode AE ​​may be spaced apart from the pixel defining film PDL in a cross-section with the sacrificial pattern SP interposed therebetween, and thus, damage to the anode AE ​​may be prevented during the process of forming the light emitting opening OP-E.

[0099] The area of ​​the light-emitting opening OP-E may be smaller than the area of ​​the sacrificial opening OP-S in a plan view. That is, the inner surface of the pixel-defining film PDL defining the light-emitting opening OP-E may be closer to the center of the anode AE ​​than the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, the present disclosure is not limited thereto, and in another embodiment, the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S may be substantially aligned with the inner surface of the pixel-defining film PDL defining the light-emitting opening OP-E. In this case, the light-emitting area PXA may be considered to be the area of ​​the anode AE ​​that is exposed from the corresponding sacrificial opening OP-S.

[0100] The pixel definition layer PDL may include an inorganic insulating material. For example, the pixel definition layer PDL may include silicon nitride (SiN x ). The pixel defining layer PDL may be disposed between the anode electrode AE ​​and the auxiliary electrode SE, and blocks electrical connection between the anode electrode AE ​​and the auxiliary electrode SE.

[0101] The light-emitting pattern EP may be disposed on the anode AE. Specifically, the light-emitting pattern EP may be disposed on the anode AE, the pixel-defining layer PDL, and the auxiliary electrode SE. The light-emitting pattern EP may include a light-emitting layer containing a light-emitting material. The light-emitting pattern EP may also include a hole injection layer and a hole transport layer disposed between the anode AE ​​and the light-emitting layer, and may also include an electron transport layer and an electron injection layer disposed on the light-emitting layer. The light-emitting pattern EP may be referred to as an "organic layer" or an "intermediate layer."

[0102] The light emitting pattern EP can be formed by the partition wall PW (see Figure 7C ) is patterned at a tip portion defined by the pixel defining film PDL. Details will be described later in the description of the method for manufacturing the display panel. The light-emitting pattern EP may be provided inside the sacrificial opening OP-S, the light-emitting opening OP-E, and the auxiliary opening OP-SE. However, this is shown illustratively, and the light-emitting pattern EP may be provided inside at least one of the sacrificial opening OP-S, the light-emitting opening OP-E, and the auxiliary opening OP-SE. The light-emitting pattern EP may cover a portion of the upper surface of the pixel defining film PDL and a portion of the upper surface of the auxiliary electrode SE.

[0103] The cathode CE may be disposed on the light emitting pattern EP. Specifically, the cathode CE may be disposed on the light emitting pattern EP and the auxiliary electrode SE. The end of the cathode CE may be in direct contact with the upper surface U_SE of the auxiliary electrode SE. Alternatively, the cathode CE may be in direct contact with the side surface S_SE of the auxiliary electrode SE (not shown). In other words, the cathode CE may be deposited wider than the light emitting pattern EP, may cover the light emitting pattern EP, and may be in direct contact with the upper surface U_SE and / or side surface S_SE of the auxiliary electrode SE.

[0104] The cathode CE may be formed by a tip portion defined by the partition wall PW (eg, the third partition wall layer L3 (see FIG. Figure 7C At least a portion of the cathode CE may be disposed in the auxiliary opening OP-SE. Figure 5 The cathode CE is illustratively shown to be disposed in the light emitting opening OP-E and the auxiliary opening OP-SE, but the present disclosure is not limited thereto. For another example, the cathode CE may be disposed only in the auxiliary opening OP-SE.

[0105] The cathode CE may be conductive. As long as the material is conductive, the cathode CE may be formed from various materials, such as metals, transparent conductive oxides ("TCO"), and conductive polymer materials. For example, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or compounds thereof. Unlike the auxiliary electrode SE, the cathode CE does not include titanium (Ti).

[0106] In an embodiment of the present disclosure, the display element layer DP-OLED may further include a capping pattern CP. The capping pattern CP may be disposed on the cathode CE. The capping pattern CP may be patterned by a tip portion defined by the partition wall PW (e.g., the third partition wall layer L3). In an embodiment, the capping pattern CP may be omitted.

[0107] The auxiliary electrode SE may be disposed on the pixel defining film PDL. The auxiliary electrode SE may define an auxiliary opening OP-SE. In a plan view, the auxiliary opening OP-SE may overlap with the light-emitting opening OP-E and expose at least a portion of the anode AE. In an embodiment, the auxiliary opening OP-SE may surround the light-emitting opening OP-E in a plan view, the area of ​​the auxiliary electrode opening OP-SE may be larger than the area of ​​the light-emitting opening OP-E in a plan view, and the auxiliary electrode SE may be positioned outside the light-emitting opening OP-E in a plan view. The auxiliary electrode SE is disposed in the peripheral area NPXA rather than in the light-emitting area PXA, and the light-emitting opening OP-E defines the light-emitting area PXA.

[0108] The auxiliary electrode SE can be formed by sequentially stacking multiple layers and removing some layers. This will be described in detail below. The auxiliary electrode SE may include a conductive material. The conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the auxiliary electrode SE may include titanium (Ti).

[0109] The auxiliary electrode SE may receive a driving voltage, and the cathode CE may be electrically connected to the auxiliary electrode SE. Therefore, the cathode CE may receive a driving voltage through the auxiliary electrode SE. Figure 5 The side surface S_SE of the auxiliary electrode SE is illustratively shown to extend perpendicularly to the upper surface of the pixel definition film PDL (ie, extend in the third direction DR3 ), but the present disclosure is not limited thereto. For another example, the auxiliary electrode SE may have a tapered shape or an inversely tapered shape at its end.

[0110] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, a common inorganic film CLIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0111] The lower encapsulation inorganic pattern LIL may correspond to the light emitting opening OP-E (or overlap with the light emitting opening OP-E) in a plan view. The lower encapsulation inorganic pattern LIL may be provided on the capping pattern CP to cover the light emitting element ED. That is, the lower encapsulation inorganic pattern LIL may be deposited wider than the light emitting element ED to cover the cathode CE and may be in direct contact with the upper surface U_SE of the auxiliary electrode SE. In addition, the end of the lower encapsulation inorganic pattern LIL may extend in the thickness direction of the base layer BL (i.e., the third direction DR3). The end of the lower encapsulation inorganic pattern LIL may protrude from the upper surface U_SE of the auxiliary electrode SE in the light emitting direction (e.g., the third direction DR3).

[0112] The common inorganic film CLIL may cover the lower encapsulation inorganic pattern LIL and have an integral shape. The common inorganic film CLIL may include an inorganic material. For example, the common inorganic film CLIL may include silicon nitride (SiN x ) and at least one of silicon oxynitride (SiON).

[0113] The encapsulation organic film OL may be disposed on the common inorganic film CLIL. The encapsulation organic film OL may cover the common inorganic film CLIL and provide a flat upper surface. The upper encapsulation inorganic film UIL may be disposed on the encapsulation organic film OL. The lower encapsulation inorganic pattern LIL, the common inorganic film CLIL, and the upper encapsulation inorganic film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the encapsulation organic film OL may protect the display element layer DP-OLED from foreign matter such as dust particles.

[0114] Figure 5 The thin film encapsulation layer TFE is illustratively shown to include a lower encapsulation inorganic pattern LIL, a common inorganic film CLIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL, but the present disclosure is not limited thereto. For another example, in an embodiment, the thin film encapsulation layer TFE may not include the common inorganic film CLIL.

[0115] wherein the cathode CE and the partition wall PW (see Figure 7C ). Unlike the structure of the cathode CE, which is in direct contact with the side surface of the auxiliary electrode SE containing titanium (Ti), in this embodiment, since the cathode CE is in direct contact with the auxiliary electrode SE containing titanium (Ti), contact defects caused by aluminum oxidation can be effectively reduced or eliminated. Furthermore, since the cathode CE is in contact with the upper surface U_SE of the auxiliary electrode SE, the contact length can be increased. Furthermore, the lower encapsulation inorganic pattern LIL is in direct contact with the upper surface U_SE of the auxiliary electrode SE while covering the cathode CE, thereby allowing the inorganic material and the metal material to be bonded to each other. Therefore, the contact reliability of the cathode CE can be effectively improved, and defects caused by moisture penetration into the display panel DP can be reduced or eliminated.

[0116] Unlike a structure in which patterning is performed using a partition wall PW and the partition wall PW is retained in the final structure, the display panel DP may have a structure in which the partition wall PW is removed after patterning and thereby is strong enough to withstand external impacts, and the luminous efficiency of the light-emitting element ED may be effectively increased by removing the partition wall PW positioned on the light-emitting path.

[0117] Figure 6 It is along Figure 4 sectional view of the display panel DP taken along line II-II'. Figure 6 A first light emitting region PXA-R, a second light emitting region PXA-G, and a third light emitting region PXA-B are shown in an enlarged manner, and Figure 5 The description of a light emitting region PXA can be equally applied to Figure 6 The first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B. Figure 6 In the description of Figure 5 The same / similar components described in will be referred to herein, and their repeated description will be omitted.

[0118] refer to Figure 6The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light-emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, a pixel defining layer PDL, a capping pattern CP, and an auxiliary electrode SE.

[0119] The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3 that emit light having different colors. The first light-emitting element ED1 may be provided as a plurality of first light-emitting elements ED1, the second light-emitting element ED2 may be provided as a plurality of second light-emitting elements ED2, and the third light-emitting element ED3 may be provided as a plurality of third light-emitting elements ED3. However, for convenience of description, the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 are hereinafter referred to in singular form.

[0120] The first light-emitting element ED1 may include a first anode AE1, a first emission pattern EP1, and a first cathode CE1. The second light-emitting element ED2 may include a second anode AE2, a second emission pattern EP2, and a second cathode CE2. The third light-emitting element ED3 may include a third anode AE3, a third emission pattern EP3, and a third cathode CE3. The first anode AE1, the second anode AE2, and the third anode AE3 may be provided in a plurality of patterns. In an embodiment, the first emission pattern EP1 may provide red light, the second emission pattern EP2 may provide green light, and the third emission pattern EP3 may provide blue light.

[0121] A first light-emitting opening OP1-E, a second light-emitting opening OP2-E, and a third light-emitting opening OP3-E may be defined in the pixel defining layer PDL. The first light-emitting opening OP1-E may expose at least a portion of the first anode AE1. The second light-emitting opening OP2-E may expose at least a portion of the second anode AE2. The third light-emitting opening OP3-E may expose at least a portion of the third anode AE3.

[0122] In an embodiment, the first light emitting region PXA-R may be defined as a region where the upper surface of the first anode AE1 is exposed by the first light emitting opening OP1-E. The second light emitting region PXA-G may be defined as a region where the upper surface of the second anode AE2 is exposed by the second light emitting opening OP2-E. The third light emitting region PXA-B may be defined as a region where the upper surface of the third anode AE3 is exposed by the third light emitting opening OP3-E.

[0123] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3 may be arranged on the upper surface of the first anode AE1, the upper surface of the second anode AE2, and the upper surface of the third anode AE3, respectively. A first sacrificial opening OP1-S, a second sacrificial opening OP2-S, and a third sacrificial opening OP3-S, which overlap with the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E, respectively, may be defined in the first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3, respectively.

[0124] First, second, and third auxiliary openings OP1-SE, OP2-SE, and OP3-SE respectively overlapping the first, second, and third light emitting openings OP1-E, OP2-E, and OP3-E in a plan view may be defined in the auxiliary electrode SE.

[0125] In the embodiment, the first light emitting pattern EP1, the second light emitting pattern EP2 and the third light emitting pattern EP3 and the first cathode CE1, the second cathode CE2 and the third cathode CE3 may be formed by the third partition wall layer L3 (see FIG. Figure 7C ) are physically separated and thus may be formed inside the sacrificial openings OP1-S, OP2-S, and OP3-S, the light emitting openings OP1-E, OP2-E, and OP3-E, and the auxiliary openings OP1-SE, OP2-SE, and OP3-SE. In addition, the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 may cover a portion of the upper surface of the pixel defining film PDL and a portion of the upper surface of the auxiliary electrode SE.

[0126] That is, the first light-emitting element ED1 can be formed inside the first sacrificial opening OP1-S, the first light-emitting opening OP1-E and the first auxiliary opening OP1-SE, and be arranged on the pixel-defining film PDL and the auxiliary electrode SE. The second light-emitting element ED2 can be formed inside the second sacrificial opening OP2-S, the second light-emitting opening OP2-E and the second auxiliary opening OP2-SE, and be arranged on the pixel-defining film PDL and the auxiliary electrode SE. The third light-emitting element ED3 can be formed inside the third sacrificial opening OP3-S, the third light-emitting opening OP3-E and the third auxiliary opening OP3-SE, and be arranged on the pixel-defining film PDL and the auxiliary electrode SE. The first light-emitting element ED1, the second light-emitting element ED2 and the third light-emitting element ED3 can be spaced apart from each other. In an embodiment, two adjacent cathodes (for example, the first cathode CE1 and the second cathode CE2) can be electrically connected to the auxiliary electrode SE between them.

[0127] According to the present disclosure, the plurality of first light emitting patterns EP1 may be formed by being defined on the partition wall PW (see FIG. Figure 7C ) is patterned and deposited in units of pixels. That is, the first light emitting patterns EP1 can be collectively formed using an open mask, but can be easily divided in units of pixels by partition walls PW.

[0128] On the other hand, when patterning the first light-emitting pattern EP1 using a fine metal mask ("FMM"), a support spacer protruding from the conductive partition wall to support the FMM should be provided. In addition, since the FMM is separated from the substrate surface on which patterning is performed by the height of the partition wall PW and the spacer, the realization of high resolution may be limited. In addition, since the FMM is in contact with the spacer, foreign matter may remain on the spacer after the patterning process of the first light-emitting pattern EP1, and the spacer may be damaged by the stamping of the mask. As a result, a defective display panel may be formed.

[0129] According to the embodiment, in the process of manufacturing the display panel DP, the partition wall PW is included so that the physical separation between the light emitting elements ED1, ED2, and ED3 can be easily performed. Therefore, current leakage or driving error between the adjacent light emitting areas PXA-R, PXA-G, and PXA-B can be prevented, and each of the light emitting elements ED1, ED2, and ED3 can be independently driven.

[0130] In particular, since the plurality of first light emitting patterns EP1 are not aligned with the display area DA (see FIG. Figure 1B ) is patterned without using a mask that contacts the internal components inside, thereby effectively reducing the defect rate, and thus providing a display panel DP with improved process reliability. Since patterning can be performed even when no separate supporting spacer protruding from the partition wall PW is provided, the areas of the light emitting regions PXA-R, PXA-G, and PXA-B can be miniaturized, and thus a display panel DP that easily achieves high resolution can be provided.

[0131] Furthermore, in manufacturing a large-area display panel DP, since the production of a large-area mask is omitted, a display panel DP can be provided that can reduce process costs, and since the display panel DP is not affected by defects that may occur in the large-area mask, process reliability can be improved. The description of the plurality of first light-emitting patterns EP1 is equally applicable to the plurality of second light-emitting patterns EP2 and the plurality of third light-emitting patterns EP3.

[0132] The thin film encapsulation layer TFE may include a plurality of lower encapsulation inorganic patterns LIL1 , LIL2 , and LIL3 , a common inorganic film CLIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0133] The plurality of lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 may include a first lower encapsulation inorganic pattern LIL1 covering the first light-emitting element ED1, a second lower encapsulation inorganic pattern LIL2 covering the second light-emitting element ED2, and a third lower encapsulation inorganic pattern LIL3 covering the third light-emitting element ED3. The first lower encapsulation inorganic pattern LIL1, the second lower encapsulation inorganic pattern LIL2, and the third lower encapsulation inorganic pattern LIL3 may overlap with the first light-emitting opening OP1-E, the second light-emitting opening OP2-E, and the third light-emitting opening OP3-E, respectively, in a plan view. The first lower encapsulation inorganic pattern LIL1, the second lower encapsulation inorganic pattern LIL2, and the third lower encapsulation inorganic pattern LIL3 may be provided in the form of patterns spaced apart from each other.

[0134] Outer surfaces OS1, OS2, and OS3 of the plurality of lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 may define a gap area BA (see FIG. Figure 7J For example, the gap area BA may be defined between the outer surface OS1 of the first and second lower encapsulation inorganic patterns LIL1 and LIL2 and between the outer surface OS2 of the second and third lower encapsulation inorganic patterns LIL2 and LIL3.

[0135] The common inorganic film CLIL may cover the first lower encapsulation inorganic pattern LIL1, the second lower encapsulation inorganic pattern LIL2, and the third lower encapsulation inorganic pattern LIL3 and have a unitary shape. The common inorganic film CLIL may cover the outer surfaces OS1, OS2, and OS3 of the plurality of lower encapsulation inorganic patterns LIL1, LIL2, and LIL3, as well as the upper surface U_SE of the auxiliary electrode SE. For example, the common inorganic film CLIL may cover the outer surface OS1 of the first lower encapsulation inorganic pattern LIL1, the upper surface U_SE of the auxiliary electrode SE, and the outer surface OS2 of the second lower encapsulation inorganic pattern LIL2, and may cover the outer surface OS2 of the second lower encapsulation inorganic pattern LIL2, the upper surface U_SE of the auxiliary electrode SE, and the outer surface OS3 of the third lower encapsulation inorganic pattern LIL3.

[0136] Figures 7A to 7L 1 is a cross-sectional view illustrating some operations of a method of manufacturing a display panel DP according to an embodiment of the present disclosure. Figures 7A to 7L In the description of FIG. 1 to FIG. Figure 6 The same / similar components will be denoted by the same / similar reference numerals, and repeated descriptions thereof will be omitted.

[0137] According to an embodiment of the present disclosure, a method for manufacturing a display panel may include: an operation of providing a preliminary display panel including a base layer and a pixel defining film disposed on the base layer; an operation of forming a preliminary partition wall including a first preliminary partition wall layer, a second preliminary partition wall layer, and a third preliminary partition wall layer and disposed on the preliminary display panel; an operation of forming a partition wall defining a plurality of partition wall openings therein and including a first partition wall layer, a second partition wall layer, and a third partition wall layer from the preliminary partition wall; an operation of forming a plurality of light-emitting openings overlapping with the plurality of partition wall openings by etching the pixel defining film; an operation of forming a plurality of light-emitting elements disposed on the pixel defining film and the first partition wall layer; an operation of forming a plurality of lower encapsulation inorganic patterns disposed on the plurality of light-emitting elements and the first partition wall layer and covering the plurality of light-emitting elements; and an operation of forming an auxiliary electrode by removing the second preliminary partition wall layer and the third preliminary partition wall layer.

[0138] In the following, we will Figures 7A to 7L A method of forming three light emitting elements ED1, ED2, and ED3, lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 covering the light emitting elements ED1, ED2, and ED3, a common inorganic film CLIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL is described. Figures 7A to 7L The display panel DP formed may correspond to Figure 6 display panel DP.

[0139] refer to Figure 7A The method of manufacturing a display panel according to the present disclosure may include an operation of providing a preliminary display panel DP-I. The preliminary display panel DP-I provided in the embodiment may include a base layer BL, a circuit element layer DP-CL, a first anode AE1, a second anode AE2, and a third anode AE3, a first preliminary sacrificial pattern SP1-I, a second preliminary sacrificial pattern SP2-I, and a third preliminary sacrificial pattern SP3-I, and a pixel defining layer PDL.

[0140] The circuit element layer DP-CL can be formed by a general method of manufacturing circuit elements, wherein an insulating layer, a semiconductor layer and a conductive layer are formed by a coating method or a deposition method, and the insulating layer, the semiconductor layer and the conductive layer are selectively patterned by a photolithography process and an etching process to form a semiconductor pattern, a conductive pattern or a signal line, etc.

[0141] The first anode AE1 and the first preliminary sacrificial pattern SP1-I may be formed through the same patterning process, the second anode AE2 and the second preliminary sacrificial pattern SP2-I may be formed through the same patterning process, and the third anode AE3 and the third preliminary sacrificial pattern SP3-I may be formed through the same patterning process. A pixel-defining film PDL may be disposed on the base layer BL. The pixel-defining film PDL may cover all of the first anode AE1, the second anode AE2, and the third anode AE3, as well as the first preliminary sacrificial pattern SP1-I, the second preliminary sacrificial pattern SP2-I, and the third preliminary sacrificial pattern SP3-I.

[0142] The method of manufacturing a display panel according to the present disclosure may include forming a preliminary partition wall PW-1 on a preliminary display panel DP-1. The preliminary partition wall PW-1 may include a first preliminary partition wall layer L1-1, a second preliminary partition wall layer L2-1, and a third preliminary partition wall layer L3-1.

[0143] A first preliminary partition wall layer L1-I may be formed on the pixel definition film PDL, a second preliminary partition wall layer L2-I may be formed on the first preliminary partition wall layer L1-I, and a third preliminary partition wall layer L3-I may be formed on the second preliminary partition wall layer L2-I. The first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, and the third preliminary partition wall layer L3-I may be formed by a process of depositing a conductive material. The first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, and the third preliminary partition wall layer L3-I may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the operation of forming the preliminary partition wall PW-I may include an operation of depositing a first preliminary partition wall layer L1-I containing titanium (Ti), an operation of depositing a second preliminary partition wall layer L2-I containing aluminum (Al), and an operation of depositing a third preliminary partition wall layer L3-I containing titanium (Ti).

[0144] The materials of the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, and the third preliminary partition wall layer L3-I are not limited to the above examples. For example, the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, and the third preliminary partition wall layer L3-I may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy, and may include indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide ("IGZO"), or aluminum zinc oxide.

[0145] In addition, the method of manufacturing a display panel according to the present disclosure may include an operation of forming a first photoresist layer PR1 on the preliminary partition wall PW-1. The first photoresist layer PR1 can be formed by forming a preliminary photoresist layer on the preliminary partition wall PW-1 and then patterning the preliminary photoresist layer using a photolithography mask. A first photolithography opening OP-PR1, a second photolithography opening OP-PR2, and a third photolithography opening OP-PR3 can be formed in the first photoresist layer PR1 through a patterning process. In a plan view, the first photolithography opening OP-PR1 can overlap with the first anode AE1, the second photolithography opening OP-PR2 can overlap with the second anode AE2, and the third photolithography opening OP-PR3 can overlap with the third anode AE3.

[0146] Afterwards, refer to Figure 7B and Figure 7C The method of manufacturing a display panel according to the present disclosure may include forming a primary partition wall PW-I (see Figure 7A ) An operation of forming a partition wall PW having partition wall openings OP1-P, OP2-P, and OP3-P. The operation of forming the partition wall PW may include an operation of dry-etching the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, and the third preliminary partition wall layer L3-I, and an operation of wet-etching the second preliminary partition wall layer L2-I.

[0147] First, if Figure 7B As shown in , in the operation of dry etching the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, and the third preliminary partition wall layer L3-I, the first photoresist layer PR1 can be used as a mask to dry etch the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, and the third preliminary partition wall layer L3-I. In a plan view, a portion of the preliminary partition wall PW-I that does not overlap with the first photoresist layer PR1 can be etched and removed. For example, a first preliminary partition wall opening OP1-PI can be formed at a portion that overlaps with the first photolithography opening OP-PR1 and is removed from the first photolithography opening OP-PR1, a second preliminary partition wall opening OP2-PI can be formed at a portion that overlaps with the second photolithography opening OP-PR2 and is removed from the second photolithography opening OP-PR2, and a third preliminary partition wall opening OP3-PI can be formed at a portion that overlaps with the third photolithography opening OP-PR3 and is removed from the third photolithography opening OP-PR3.

[0148] The preliminary dry etching process in the embodiment can be performed in an etching environment in which the etching selectivity ratios among the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, and the third preliminary partition wall layer L3-I are substantially the same. Therefore, the inner surface of the first preliminary partition wall layer L1-I, the inner surface of the second preliminary partition wall layer L2-I, and the inner surface of the third preliminary partition wall layer L3-I, which define the preliminary partition wall openings OP1-PI, OP2-PI, and OP3-PI, can be substantially aligned.

[0149] Afterwards, if Figure 7C As shown in FIG, in the second preliminary partition wall layer L2-I (see Figure 7B ) in an operation of wet etching, the second preliminary partition wall layer L2-1 may be wet etched using the first photoresist layer PR1 as a mask. Thus, a portion of the second preliminary partition wall layer L2-1 may be etched to form partition wall openings OP1-P, OP2-P, and OP3-P. The partition wall openings OP1-P, OP2-P, and OP3-P may include a first partition wall opening OP1-P, a second partition wall opening OP2-P, and a third partition wall opening OP3-P. In a plan view, the first partition wall opening OP1-P may be formed to overlap with the first anode AE1, the second partition wall opening OP2-P may be formed to overlap with the second anode AE2, and the third partition wall opening OP3-P may be formed to overlap with the third anode AE3. Furthermore, auxiliary openings OP1-SE, OP2-SE, and OP3-SE are formed in the first partition wall layer L1. The first partition wall layer L1, the second partition wall layer L2, and the third partition wall layer L3 formed by etching may form a partition wall PW.

[0150] The second wet etching process in the present disclosure may be performed in which the first preliminary partition wall layer L1-I (see Figure 7B ) and the third preliminary partition wall layer and L3-I (see Figure 7B ) and the second preliminary partition wall layer L2-I (see Figure 7B ) is performed in an environment where the etching selectivity ratio between the first and third preliminary partition wall layers L1 and L3 is high. Therefore, the inner surface of the partition wall PW defining the partition wall openings OP1-P, OP2-P, and OP3-P may have an undercut shape in cross section. In detail, the etching rate of the second preliminary partition wall layer L2-I relative to the etching solution is greater than the etching rate of the first preliminary partition wall layer L1-I and the third preliminary partition wall layer L3-I, and therefore, the second preliminary partition wall layer L2-I may be mainly etched. Therefore, the second partition wall layer L2 may be formed to be recessed inwardly compared to the first and third partition wall layers L1 and L3. A tip portion may be formed in the partition wall PW by portions of the first and third partition wall layers L1 and L3 that further protrude from the second partition wall layer L2.

[0151] Afterwards, refer to Figure 7D , the method of manufacturing a display panel according to the present disclosure may include an operation of etching a pixel defining film PDL to form light-emitting openings OP1-E, OP2-E, and OP3-E, which respectively overlap with a plurality of partition wall openings OP1-P, OP2-P, and OP3-P in a plan view.

[0152] In the operation of etching the pixel defining film PDL, the pixel defining film PDL can be dry-etched using the first photoresist layer PR1 and the partition wall PW (for example, the third partition wall layer L3) as a mask. In a plan view, the portion of the pixel defining film PDL that does not overlap with the first photoresist layer PR1 and the partition wall PW can be etched and removed. As a result, light-emitting openings OP1-E, OP2-E, and OP3-E that overlap with the partition wall openings OP1-P, OP2-P, and OP3-P, respectively, can be formed in the pixel defining film PDL in a plan view. In a plan view, the light-emitting openings OP1-E, OP2-E, and OP3-E may include a first light-emitting opening OP1-E overlapping with the first partition wall opening OP1-P, a second light-emitting opening OP2-E overlapping with the second partition wall opening OP2-P, and a third light-emitting opening OP3-E overlapping with the third partition wall opening OP3-P.

[0153] Thereafter, the method for manufacturing a display panel according to the present disclosure may further include etching the first preliminary sacrificial pattern SP1-I (see Figure 7C ), the second preliminary sacrificial pattern SP2-I (see Figure 7C ) and the third preliminary sacrificial pattern SP3-I (see Figure 7C ) to form the sacrificial patterns SP1, SP2, and SP3 having the sacrificial openings OP1-S, OP2-S, and OP3-S respectively overlapping with the light emitting openings OP1-E, OP2-E, and OP3-E in a plan view.

[0154] In the operation of etching the first preliminary sacrificial pattern SP1-I, the second preliminary sacrificial pattern SP2-I, and the third preliminary sacrificial pattern SP3-I, the first preliminary sacrificial pattern SP1-I, the second preliminary sacrificial pattern SP2-I, and the third preliminary sacrificial pattern SP3-I can be wet-etched using the first photoresist layer PR1 and the partition wall PW (e.g., the third partition wall layer L3) as a mask. In a plan view, portions of the first preliminary sacrificial pattern SP1-I, the second preliminary sacrificial pattern SP2-I, and the third preliminary sacrificial pattern SP3-I that do not overlap with the first photoresist layer PR1 and the partition wall PW can be etched and removed. As a result, the sacrificial patterns SP1, SP2, and SP3 can be formed from the first preliminary sacrificial pattern SP1-I, the second preliminary sacrificial pattern SP2-I, and the third preliminary sacrificial pattern SP3-I.

[0155] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. A first sacrificial opening OP1-S overlapping with the first light-emitting opening OP1-E in a plan view may be formed in the first sacrificial pattern SP1, a second sacrificial opening OP2-S overlapping with the second light-emitting opening OP2-E in a plan view may be formed in the second sacrificial pattern SP2, and a third sacrificial opening OP3-S overlapping with the third light-emitting opening OP3-E in a plan view may be formed in the third sacrificial pattern SP3.

[0156] The etching process of the sacrificial patterns SP1, SP2, and SP3 may be performed in an environment in which an etching selectivity ratio between the sacrificial patterns SP1, SP2, and SP3 and the anodes AE1, AE2, and AE3 is high, and thus, the anodes AE1, AE2, and AE3 may be prevented from being etched together. That is, the sacrificial patterns SP1, SP2, and SP3 having an etching rate higher than that of the anodes AE1, AE2, and AE3 are arranged between the pixel defining film PDL and the anodes AE1, AE2, and AE3, and thus, the anodes AE1, AE2, and AE3 may be prevented from being etched together and damaged during the etching process.

[0157] Afterwards, refer to Figure 7E The method for manufacturing a display panel according to the present disclosure may include removing the first photoresist layer PR1 (see Figure 7D ) After that, a plurality of light emitting elements (eg, first light emitting elements ED1) are formed on the pixel definition film PDL and the first partition wall layer L1. Figure 5 ) may include forming a light emitting pattern (e.g., first light emitting pattern EP1) on the pixel defining layer PDL and the first partition wall layer L1, and forming a cathode (e.g., first cathode CE1) on the light emitting pattern (e.g., first light emitting pattern EP1) so that an end of the cathode contacts the upper surface U_L1 of the first partition wall layer L1. Furthermore, the cathode may be formed to contact the side surface S_L1 of the first partition wall layer L1, and the cathode may be formed to contact the upper surface U_L1 and the side surface S_L1 of the first partition wall layer L1.

[0158] The operation of forming the first light-emitting pattern EP1 may include a process of depositing a light-emitting layer. For example, the operation of forming the first light-emitting pattern EP1 may include an operation of depositing the light-emitting layer by thermal evaporation. The light-emitting layer may be separated by the tip portion formed in the partition wall PW and may be deposited within the first sacrificial opening OP1-S, the second sacrificial opening OP2-S, and the third sacrificial opening OP3-S, the first light-emitting opening OP1-E, the second light-emitting opening OP2-E, and the third light-emitting opening OP3-E, and the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P, and on the partition wall PW. The light-emitting layer formed within the first sacrificial opening OP1-S, the first light-emitting opening OP1-E, and the first partition wall opening OP1-P may form the first light-emitting pattern EP1, and the light-emitting layer formed within the second partition wall opening OP2-P and the third partition wall opening OP3-P and on the partition wall PW may form the first dummy layer D1. That is, the first light emitting pattern EP1 may be formed on the first anode AE1 to overlap the first partition wall opening OP1 -P in a plan view, and may be formed to cover the first anode AE1 and the pixel defining layer PDL.

[0159] The first dummy layer D1 formed together with the first light emitting pattern EP1 in the operation of forming the first light emitting pattern EP1 may include an organic material. For example, the first dummy layer D1 may include the same material as the first light emitting pattern EP1. The first dummy layer D1 may be formed simultaneously with the first light emitting pattern EP1 through a single process and may be separated from the first light emitting pattern EP1 by the undercut shape of the partition wall PW.

[0160] The operation of forming the first cathode CE1 may include a process of depositing a cathode layer. For example, the operation of forming the first cathode CE1 may include an operation of sputtering the cathode layer. The angle at which the cathode layer is deposited may be greater than the angle at which the light-emitting layer is deposited. For example, when the angle formed between a direction perpendicular to the base layer BL (e.g., the third direction DR3) and the deposited material is referred to as an input angle, the input angle of the cathode layer may be greater than the input angle of the light-emitting layer.

[0161] The cathode layer may be separated by a tip portion formed in the partition wall PW and may be deposited within the first light-emitting opening OP1-E, the second light-emitting opening OP2-E, and the third light-emitting opening OP3-E, as well as the first, second, and third partition wall openings OP1-P, OP2-P, and OP3-P, and on the partition wall PW. The cathode layer formed within the first light-emitting opening OP1-E and the first partition wall opening OP1-P may form a first cathode CE1, and the cathode layer formed within the second and third partition wall openings OP2-P and OP3-P and on the partition wall PW may form a second dummy layer D2. The first cathode CE1 may be formed on the first light-emitting pattern EP1 so as to overlap with the first partition wall opening OP1-P in a plan view. Furthermore, the first cathode CE1 may be formed by having an input angle of the cathode layer greater than the input angle of the light-emitting layer to cover the first light-emitting pattern EP1 and may be formed to contact the upper surface U_L1 of the first partition wall layer L1. The first cathode CE1 may be formed to be in contact with the side surface S_L1 of the first partition wall layer L1, and the first cathode CE1 may be formed to be in contact with the side surface S_L1 and the upper surface U_L1 of the first partition wall layer L1.

[0162] The second dummy layer D2 formed together with the operation of forming the first cathode CE1 may include a conductive material. For example, the second dummy layer D2 may include the same material as the first cathode CE1. The second dummy layer D2 may be formed simultaneously with the first cathode CE1 through a single process and may be separated from the first cathode CE1 by the undercut shape of the partition wall PW.

[0163] The first anode AE1, the first light emitting pattern EP1, and the first cathode CE1 may be sequentially stacked in the third direction DR3. The first anode AE1, the first light emitting pattern EP1, and the first cathode CE1 may form a first light emitting element ED1.

[0164] The method for manufacturing a display panel according to the present disclosure may include an operation of forming a capping pattern CP. The operation of forming the capping pattern CP may include a process of depositing a capping pattern layer. The capping pattern layer may be separated by a tip portion formed in the partition wall PW, and may be deposited inside the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P and on the partition wall PW. The capping pattern layer formed inside the first partition wall opening OP1-P may form a capping pattern CP, and the capping pattern layer formed inside the second partition wall opening OP2-P and the third partition wall opening OP3-P and on the partition wall PW may form a third dummy layer D3.

[0165] The third dummy layer D3 formed together with the operation of forming the capping pattern CP may include a conductive material. For example, the third dummy layer D3 may include the same material as the capping pattern CP. The third dummy layer D3 may be formed simultaneously with the capping pattern CP through a single process and may be separated from the capping pattern CP by the undercut shape of the partition wall PW. In an embodiment of the present disclosure, the process of forming the capping pattern CP and the third dummy layer D3 may be omitted.

[0166] Afterwards, refer to Figure 7F and Figure 7G The method of manufacturing a display panel according to the present disclosure may include forming a plurality of lower encapsulation inorganic patterns (eg, first lower encapsulation inorganic patterns LIL1 ) covering a plurality of light emitting elements (eg, first light emitting elements ED1 ) on the light emitting elements and the first partition wall layer L1 .

[0167] First, refer to Figure 7F , the operation of forming the first lower encapsulation inorganic pattern LIL1 may include the operation of depositing the lower encapsulation inorganic layer LIL-I. The lower encapsulation inorganic layer LIL-I may be formed by a deposition process. In an embodiment, the lower encapsulation inorganic layer LIL-I may be formed by a chemical vapor deposition ("CVD") process. The lower encapsulation inorganic layer LIL-I may be deposited to cover the first cathode CE1 and to be in direct contact with the upper surface U_L1 of the first partition wall layer L1. In addition, the lower encapsulation inorganic layer LIL-I may be deposited to be in contact with the upper surface U_L1 of the first partition wall layer L1 and the side surface S_L2 of the second partition wall layer L2.

[0168] Afterwards, the method of manufacturing a display panel according to the present disclosure may include an operation of forming a second photoresist layer PR2. In the operation of forming the second photoresist layer PR2, the second photoresist layer PR2 may be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer using a photolithography mask. Through the patterning process, the second photoresist layer PR2 may be formed in the form of a pattern corresponding to the first light-emitting element ED1.

[0169] Afterwards, refer to Figure 7G The operation of forming the first lower encapsulation inorganic pattern LIL1 may include removing the lower encapsulation inorganic layer LIL-I (see Figure 7F ) does not overlap with the first light emitting element ED1 in a plan view.

[0170] In the operation of removing the portion of the lower encapsulation inorganic layer LIL-1 that does not overlap with the first light-emitting element ED1 in a plan view, the lower encapsulation inorganic layer LIL-1 may be dry-etched using the second photoresist layer PR2 as a mask. The portion of the lower encapsulation inorganic layer LIL-1 that does not overlap with the second photoresist layer PR2 in a plan view may be removed, and the first lower encapsulation inorganic pattern LIL1 may be formed in the remaining portion of the lower encapsulation inorganic layer LIL-1 that has not been etched.

[0171] Thereafter, the method for manufacturing a display panel according to the present disclosure may include removing the dummy layers D1, D2, and D3 (see FIG. Figure 7F Among the dummy layers D1, D2, and D3, the second dummy layer D2 and the third dummy layer D3 may be removed by wet etching, and among the dummy layers D1, D2, and D3, the first dummy layer D1 may be removed by a stripper.

[0172] Afterwards, refer to Figure 7H In the method for manufacturing a display panel according to the present disclosure, after removing the second photoresist layer PR2 (see Figure 7G ) After that, the second light emitting element ED2, the capping pattern CP and the second lower package inorganic pattern LIL2 may be formed. The process of forming the second light emitting element ED2, the capping pattern CP and the second lower package inorganic pattern LIL2 may be the same as that of the process of forming the second light emitting element ED2, the capping pattern CP and the second lower package inorganic pattern LIL2. Figures 7E to 7G The described processes of forming the first light emitting element ED1 , the capping pattern CP, and the first lower encapsulation inorganic pattern LIL1 are substantially the same.

[0173] refer to Figure 7I In the method of manufacturing a display panel according to the present disclosure, a third light emitting element ED3, a capping pattern CP, and a third lower encapsulation inorganic pattern LIL3 may be formed. The process of forming the third light emitting element ED3, the capping pattern CP, and the third lower encapsulation inorganic pattern LIL3 may be the same as that of the method of manufacturing a display panel according to the present disclosure. Figures 7E to 7G The described processes of forming the first light emitting element ED1 , the capping pattern CP, and the first lower encapsulation inorganic pattern LIL1 are substantially the same.

[0174] Afterwards, refer to Figure 7J The method of manufacturing a display panel according to the present disclosure may include removing the second partition wall layer L2 (see Figure 7I ) and the third partition wall layer L3 (see Figure 7I ) to form the auxiliary electrode SE.

[0175] The second partition wall layer L2 can be removed by wet etching, and the third partition wall layer L3 formed on the second partition wall layer L2 can be peeled off as the second partition wall layer L2 is removed. Through the above process, the second partition wall layer L2 and the third partition wall layer L3 can be removed, and the remaining first partition wall layer L1 can become the auxiliary electrode SE. In other words, the first partition wall layer L1 and the auxiliary electrode SE can have the same configuration / structure.

[0176] The operation of forming the auxiliary electrode SE may include the operation of forming a gap area BA between the outer surfaces OS1, OS2, and OS3 of the plurality of lower encapsulation inorganic patterns LIL1, LIL2, and LIL3. The first lower encapsulation inorganic pattern LIL1, the second lower encapsulation inorganic pattern LIL2, and the third lower encapsulation inorganic pattern LIL3 may be provided in the form of patterns spaced apart from each other, and the outer surfaces OS1, OS2, and OS3 of the plurality of lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 may define the gap area BA. For example, the gap area BA may be defined between the outer surface OS1 of the first lower encapsulation inorganic pattern LIL1 and the outer surface OS2 of the second lower encapsulation inorganic pattern LIL2, and between the outer surface OS2 of the second lower encapsulation inorganic pattern LIL2 and the outer surface OS3 of the third lower encapsulation inorganic pattern LIL3.

[0177] refer to Figure 7K The method of manufacturing a display panel according to the present disclosure may include an operation of forming a common inorganic film CLIL having an integral shape while covering outer surfaces OS1, OS2, and OS3 of the plurality of lower encapsulation inorganic patterns LIL1, LIL2, and LIL3. Alternatively, the method of manufacturing a display panel according to the present disclosure may include an operation of forming a common inorganic film CLIL contacting the upper surface U_SE of the auxiliary electrode SE while covering the plurality of lower encapsulation inorganic patterns LIL1, LIL2, and LIL3.

[0178] The common inorganic film CLIL may cover the outer surfaces OS1, OS2, and OS3 of the plurality of lower encapsulation inorganic patterns LIL1, LIL2, and LIL3, and the upper surface U_SE of the auxiliary electrode SE. For example, the common inorganic film CLIL may cover the outer surface OS1 of the first lower encapsulation inorganic pattern LIL1, the upper surface U_SE of the auxiliary electrode SE, and the outer surface OS2 of the second lower encapsulation inorganic pattern LIL2, and may cover the outer surface OS2 of the second lower encapsulation inorganic pattern LIL2, the upper surface U_SE of the auxiliary electrode SE, and the outer surface OS3 of the third lower encapsulation inorganic pattern LIL3.

[0179] Afterwards, refer to Figure 7LAccording to the present disclosure, the method for manufacturing a display panel may include completing the operation of the display panel DP by forming an encapsulation organic film OL and an upper encapsulation inorganic film UIL. The encapsulation organic film OL may be formed by applying an organic material using an inkjet method, but the present disclosure is not limited thereto. In another embodiment, the encapsulation organic film OL provides a flat upper surface. Thereafter, the upper encapsulation inorganic film UIL may be formed by depositing an inorganic material. Thus, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE may be formed.

[0180] According to the above description, unlike a structure in which the cathode contacts the side surface of a partition wall comprising aluminum (Al), since the cathode is in direct contact with an auxiliary electrode comprising titanium (Ti), contact defects caused by oxidation of aluminum can be effectively reduced or eliminated, and since the cathode is in contact with the upper surface of the auxiliary electrode, the contact length can be increased. In addition, the lower encapsulation inorganic pattern is in direct contact with the upper surface of the auxiliary electrode while covering the cathode, thereby forming a bond between the inorganic material and the metal material. Therefore, the contact reliability of the cathode can be improved, and defects caused by moisture penetration into the display panel can be effectively reduced or eliminated.

[0181] Unlike a structure in which patterning is performed using partition walls and the partition walls are ultimately retained, in an embodiment, the partition walls are removed after patterning, and thus the display panel can have a strong structure resistant to external impacts, and the partition walls positioned in the light emitting path are removed, and thus the light emitting efficiency of the light emitting element can be effectively increased.

[0182] Although the above description has been made with reference to the embodiments of the present disclosure, it is understood that those skilled in the art or those with ordinary knowledge in the art may make various modifications and changes to the present disclosure without departing from the spirit and technical scope of the present disclosure as described in the appended claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of this specification, but should be defined by the appended claims.

Claims

1. A display panel, wherein: The display panel includes: base layer; a pixel defining film disposed on the base layer and defining a light emitting opening in the pixel defining film; an auxiliary electrode, disposed on the pixel defining film and comprising a conductive material; a light-emitting element comprising an anode, a light-emitting pattern disposed on the pixel definition film and the auxiliary electrode, and a cathode disposed on the auxiliary electrode and the light-emitting pattern; and The lower packaging inorganic pattern is configured to cover the light emitting element.

2. The display panel according to claim 1, wherein An end of the cathode directly contacts an upper surface of the auxiliary electrode.

3. The display panel according to claim 1, wherein: The light emitting pattern is in direct contact with a side surface of the auxiliary electrode.

4. The display panel according to claim 1, wherein: The lower encapsulation inorganic pattern covers the cathode and is in direct contact with an upper surface of the auxiliary electrode.

5. The display panel according to claim 1, wherein: The auxiliary electrode defines an auxiliary opening therein, and the auxiliary opening overlaps the light emitting opening in a thickness direction of the base layer. The display panel according to claim 5 , wherein: The light emitting pattern is disposed inside the light emitting opening and the auxiliary opening.

7. The display panel according to claim 1, wherein: The auxiliary electrode includes titanium.

8. The display panel according to claim 1, wherein: An end of the lower encapsulation inorganic pattern extends in a thickness direction of the base layer.

9. The display panel according to claim 1, wherein: The light emitting element and the lower package inorganic pattern are each provided in plural numbers, and The plurality of light emitting elements are spaced apart from each other, and the plurality of lower encapsulation inorganic patterns are spaced apart from each other while respectively covering the plurality of light emitting elements.

10. The display panel according to claim 9, wherein: The display panel further includes: a common inorganic film having an integral shape and covering the plurality of lower encapsulation inorganic patterns; an encapsulating organic film disposed on the common inorganic film; and The upper encapsulation inorganic film is arranged on the encapsulation organic film.

11. The display panel according to claim 10, wherein: A plurality of outer surfaces of the plurality of lower encapsulation inorganic patterns define a gap region, and The common inorganic film covers the outer surfaces of the lower encapsulation inorganic patterns and the upper surface of the auxiliary electrode.

12. A display panel, wherein: The display panel includes: base layer; a pixel defining film disposed on the base layer and defining a first light emitting opening and a second light emitting opening in the pixel defining film; an auxiliary electrode, disposed on the pixel defining film; a first light-emitting element comprising a first anode, a first light-emitting pattern, and a first cathode sequentially arranged in a thickness direction of the base layer; a second light emitting element comprising a second anode, a second light emitting pattern, and a second cathode sequentially arranged in the thickness direction of the base layer; a first encapsulation inorganic pattern disposed on the first light emitting element and the auxiliary electrode and configured to cover the first light emitting element; a second encapsulation inorganic pattern disposed on the second light emitting element and the auxiliary electrode, configured to cover the second light emitting element, and spaced apart from the first encapsulation inorganic pattern; and A common inorganic film is configured to cover the upper surface and outer side surfaces of the first encapsulation inorganic pattern, the upper surface and outer side surfaces of the second encapsulation inorganic pattern, and the upper surface of the auxiliary electrode.

13. A method for manufacturing a display panel, wherein: The method comprises: providing a preliminary display panel including a base layer and a pixel-defining film disposed on the base layer; forming a preliminary partition wall including a first preliminary partition wall layer, a second preliminary partition wall layer, and a third preliminary partition wall layer and disposed on the preliminary display panel; forming a partition wall defining a plurality of partition wall openings therein and including a first partition wall layer, a second partition wall layer, and a third partition wall layer from the preliminary partition wall; forming a plurality of light-emitting openings overlapping the plurality of partition wall openings by etching the pixel definition film; forming a plurality of light emitting elements disposed on the pixel definition film and the first partition wall layer; forming a plurality of encapsulation inorganic patterns disposed on the plurality of light emitting elements and the first partition wall layer and covering the plurality of light emitting elements; and An auxiliary electrode is formed by removing the second preliminary partition wall layer and the third preliminary partition wall layer.

14. The method according to claim 13, wherein: The forming of the partition wall includes: dry-etching the first to third preliminary partition wall layers; and wet etching the second preliminary partition wall layer, Wherein, compared with the first partition wall layer and the third partition wall layer, the second partition wall layer is recessed inward.

15. The method according to claim 13, wherein The forming of the plurality of light emitting elements includes: forming a light emitting pattern disposed on the pixel definition film and the first partition wall layer; and A cathode disposed on the light emitting pattern is formed such that an end of the cathode contacts an upper surface of the first partition wall layer.

16. The method according to claim 15, wherein The forming of the plurality of encapsulation inorganic patterns includes: An encapsulating inorganic layer is deposited such that the encapsulating inorganic layer covers the cathode and is in direct contact with the upper surface of the first partition wall layer.

17. The method according to claim 15, wherein: The forming of the plurality of encapsulation inorganic patterns includes: An encapsulating inorganic layer is deposited such that the encapsulating inorganic layer contacts the upper surface of the first partition wall layer and side surfaces of the second partition wall layer.

18. The method according to claim 13, wherein The forming of the auxiliary electrode includes: A gap region is formed between the plurality of outer surfaces of the plurality of encapsulating inorganic patterns.

19. The method according to claim 18, wherein The method further comprises: A common inorganic film is formed that has an integral shape and covers the plurality of outer surfaces of the plurality of encapsulation inorganic patterns.

20. The method according to claim 18, wherein The method further comprises: A common inorganic film is formed to contact an upper surface of the auxiliary electrode and cover the plurality of encapsulation inorganic patterns.

21. The method according to claim 13, wherein The forming of the preliminary partition wall includes: depositing the first preliminary partition wall layer comprising titanium; depositing the second preliminary partition wall layer comprising aluminum; and The third preliminary partition wall layer including titanium is deposited.

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