Display device, LED module and manufacturing method thereof

Abstract

A display device (10-70) is provided. The display device (10-70) includes a display panel (100 '), a scan drive circuit (120'), and a data drive circuit (130 '). A scan unit (121a, 121x) of the scan drive circuit (120 ') includes a first module (MD1), a second module (MD2), and a third module (MD3). Wherein the first module (MD1) comprises a first transistor (M1) and a second transistor (M2), and the first transistor (M1) and the second transistor (M2) are respectively provided with a first end, a second end and a control end. A signal received by the first end of the first transistor (M1) is subjected to level change for at least one time in each frame period, and the signal received by the first end of the first transistor (M1) is maintained at a high level when the signal received by the control end of the first transistor (M1) is at a high level.

Description

Display device, LED module and manufacturing method thereof Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display device, an LED module, and a manufacturing method thereof. Background Art

[0002] In modern display technology, display devices play a vital role. These devices are widely used in a variety of devices such as televisions, computer monitors, and smartphones. The display panel is the core part of the display device, which is responsible for generating the image visible to the user. Existing display panel technologies include liquid crystal display (LCD), organic light emitting diode (OLED), and quantum dot display (QLED). Among them, LCD display technology relies on a backlight module to illuminate the display panel. The backlight module usually includes a light emitting diode (LED) as a light source and a light guide plate to evenly distribute the light. In addition, the pixel array in the display panel is crucial for generating high-quality images. Each pixel contains red, green, and blue sub-pixels, which work together to produce colorful images. However, existing technologies often face challenges in energy efficiency and manufacturing costs while providing high resolution and high color accuracy.

[0003] In LED manufacturing and design, the size of LEDs varies depending on their application. Large-sized LEDs can be used in lighting or disinfection (such as UV LEDs), while small-sized LEDs (such as mini-LEDs or micro-LEDs) can be used in display backlight modules or directly used as pixels in display panels (such as self-luminous display panels such as OLEDs).

[0004] Even within the same application, individual LED dimensions can vary due to differences in manufacturing processes and manufacturing techniques. Furthermore, due to manufacturing tolerances and material properties, it's difficult to maintain completely consistent environmental conditions for each LED during installation. These variations often result in individual LEDs being positioned at different heights and not aligned horizontally, leading to poor flatness in the LED module. This poor flatness, in turn, can further impact the yield and reliability of subsequent manufacturing processes.

[0005] In the design of a backlight module, whether it is a direct-lit or side-lit type, its basic components include at least a light guide plate, a diffuser plate, and a reflector plate to guide and diffuse light, so that the light can be evenly illuminated to every area of ​​the display panel to achieve a better display effect.

[0006] As one of the key components of the backlight module, the light guide plate is usually made of plastic material. However, there are many problems with traditional light guide plate materials, some of the main problems include poor optical performance, difficulty in processing, high production cost, and considerations of the heat resistance and stability of the material itself. In addition, since the backlight module must use additional components such as diffusers and reflectors to optimize the optical performance, and these additional components increase the cost and manufacturing difficulty during the production process, there will also be reliability issues in the assembly between components. On the other hand, if the backlight module uses a light guide plate made of plastic material, it is usually necessary to provide a rigid reinforcement plate bonded to the light guide plate to provide rigid support, so as to prevent the plastic light guide plate from bending due to force and affecting the display effect. However, the provision of a rigid reinforcement plate as a structural reinforcement may significantly increase the cost of the backlight module.

[0007] Quantum dot films are also widely used in backlight modules, improving display brightness, color saturation, and contrast. In common applications, quantum dot films typically use a sandwich structure, where a layer of quantum dot material is sandwiched between two layers of insulating films.

[0008] However, these quantum dot film backlight modules are susceptible to moisture and oxygen, making them susceptible to failure. Furthermore, they lack the reliability requirements required for applications such as automotive and other applications with high environmental variation. In general display applications, quantum dot film is also susceptible to moisture and oxygen, resulting in a reduced lifespan.

[0009] In the design of display panels, thin film transistors (TFTs) are devices used as switching elements to control pixel operation in general display devices. TFTs can be roughly divided into amorphous silicon (a-Si) thin film transistors and polycrystalline silicon (poly-Si) thin film transistors based on the material composition of their active layers.

[0010] Amorphous silicon thin-film transistors have become the mainstream design for large-size panels due to their low cost and relatively simple manufacturing process. In addition, compared to polycrystalline silicon, amorphous silicon can be manufactured at lower temperatures, making it more suitable for some portable devices. However, the current amorphous silicon thin-film transistors have low carrier mobility, typically only 0.2 to 0.5 cm 2 / V×S, such component characteristics will lead to limitations in product applications.

[0011] On the other hand, packaging technology is a key link in the manufacturing process of display devices, which affects the performance and reliability of the equipment. The main goal of packaging technology is to effectively integrate the microelectronic components of the display screen into the display panel. Among them, the chip on glass (COG) packaging technology is a technology that directly mounts the integrated driving circuit (i.e., the driving chip, or driver IC) in the display device onto the glass substrate, so that the driver IC directly outputs the voltage or signal required by the display module to each pixel. COG packaging technology is relatively mature, has cost advantages, and production capacity is easy to adjust. However, because it requires the driver IC to be set on the glass substrate, limitations such as IC size and routing requirements will make it difficult for display devices using COG packaging to achieve a narrow frame design.

[0012] In COG packaging technology, integrating the scan driver design onto the glass substrate is known as GOP (Gate Driver on Panel). In a GOP-driven design, the scan driver circuit (or gate driver circuit) is fabricated using the same manufacturing process as the thin-film transistors (TFTs) in the pixel array, with only a few timing control signals provided by an external circuit. This reduces the number of scan driver-related integrated circuits and reduces the production cost of LCDs. Furthermore, because the GOP-driven design requires only a few timing control signals to operate, it can optimize the space required for signal routing in the external circuit, thereby increasing the effective display area.

[0013] With the evolution of technology, Chip on Film (COF) packaging technology has emerged, which can directly package the driver IC on the flexible circuit board and bend it to the back of the display panel. Because the driver IC does not need to be placed on the glass substrate, the border area can be effectively reduced, making the narrow border requirement easier to meet. However, although COF packaging technology can reduce the border size, its technical threshold is high, the production cost is relatively high, and it will also limit production capacity. The above two types of technologies have their limitations in achieving narrow border design, and it is difficult to take into account both cost and effect considerations at the same time.

[0014] Furthermore, existing scan driver circuit designs, regardless of the drive method used, inevitably require a DC voltage to maintain circuit operation. However, applying a DC voltage to transistors in the circuit for extended periods of time can easily cause transistor characteristics to shift, leading to a gradual increase in leakage current. Over time, this can lead to display anomalies and limit the lifespan of the display panel.

[0015] On the other hand, inherent limitations in ULED / Mini-LED display panels, such as production yield, production costs, and color shift, make single large-size ULED / Mini-LED displays difficult to manufacture. Therefore, tiled ULED / Mini-LED displays are widely used to address these large-screen design challenges. The use of tiled displays not only significantly reduces the production costs of large-size screens, meeting the demands of applications requiring maximum size, but also offers improved brightness, color saturation, and contrast, while offering greater flexibility in size and specifications.

[0016] However, the main problem with tiled displays is that the gaps between the display panels are easily visible, causing the image to be cut by the black lines of the tiled gaps, affecting the viewing experience.

[0017] Summary of the Invention

[0018] One of the objectives of the present disclosure is to provide a display device, an LED module, and a manufacturing method thereof, which can ensure the surface flatness of the LED module.

[0019] One of the objectives of the present disclosure is to provide a quantum dot film and a display and a backlight module using the same, which can avoid the problem of being easily affected by water and oxygen and causing a reduction in device life.

[0020] One of the objectives of the present disclosure is to provide a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof, which have good device characteristics and thereby improve the display effect and life of the product.

[0021] One of the objectives of the present disclosure is to provide a display device and a driving circuit thereof, which are used to solve the problems mentioned in the background art, such as solving the narrow frame design problem and / or the service life problem of the display panel in COG package and GOP package display devices.

[0022] One of the purposes of the present disclosure is to provide a light guide plate and a backlight module thereof, which can achieve optimized performance between display effect / light source conversion efficiency and structural protection, effectively simplify the manufacturing process of the light guide plate and reduce manufacturing cost and cycle, as well as reduce maintenance cost and expenses.

[0023] One of the objectives of the present disclosure is to provide a spliced ​​display panel, a display and a manufacturing method thereof, which can eliminate the visual impact of splicing seams and have no visible splicing stripes or optical color difference.

[0024] An embodiment of the present disclosure proposes a method for manufacturing an LED module, comprising the following steps: forming a first circuit layer on a substrate; arranging a plurality of light-emitting elements on the first circuit layer through a bonding portion so that the first electrode of each of the light-emitting elements is electrically connected to the first circuit layer; forming a protective layer on the substrate to cover the plurality of light-emitting elements, wherein the thickness of the protective layer is greater than or equal to the height of the plurality of light-emitting elements; removing the protective layer covering the second electrode of each of the light-emitting elements to form an opening between each of the plurality of light-emitting elements and the protective layer; and forming a second circuit layer on the protective layer, wherein the second circuit layer is electrically connected to the second electrode of each of the light-emitting elements through the opening.

[0025] An embodiment of the present disclosure proposes a method for manufacturing an LED module, comprising the following steps: forming a first circuit layer on a substrate; arranging a plurality of light-emitting elements on the first circuit layer through a coupling portion so that a first electrode of each of the light-emitting elements is electrically connected to the first circuit layer; applying a force toward the substrate to the plurality of light-emitting elements so as to embed at least part of the light-emitting elements into the coupling portion; filling insulating material into gaps between the light-emitting elements to form a protective layer; and forming a second circuit layer on the protective layer so that a second electrode of each light-emitting element is electrically connected to the second circuit layer.

[0026] The embodiment of the present disclosure proposes a quantum dot film, characterized in that it includes an active layer, a supporting layer, a bonding layer and a water-blocking layer. The active layer contains a plurality of quantum dots and is used to excite light with a second wavelength based on the received light of a first wavelength. The supporting layer is used to support the active layer. The bonding layer is arranged between the active layer and the supporting layer to provide a bonding force between the active layer and the supporting layer so that the active layer is arranged on the supporting layer through the bonding layer. The water-blocking layer directly or indirectly covers at least a portion of the surface of the active layer. The embodiment of the present disclosure proposes a thin film transistor, comprising a gate, an insulating layer, an active layer, a source electrode and a drain electrode. The insulating layer is formed on the gate electrode. The active layer is formed on the insulating layer. The source electrode is formed on one of the two end portions of the active layer. The drain electrode is formed on the other of the two end portions of the active layer. The active layer includes a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer stacked in sequence. The first semiconductor material layer is formed on the insulating layer and has an ordered lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disordered lattice structure; and the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disordered lattice structure, and is doped with N-type ions. Semiconductor oxide is substantially absent at the interface between the first semiconductor material layer and the second semiconductor material layer.

[0027] The present disclosure provides a thin film transistor comprising a gate, an insulating layer, an active layer, a source electrode, and a drain electrode. The insulating layer is formed on the gate electrode. The active layer is formed on the insulating layer. The source electrode is formed on one of the two end portions of the active layer. The drain electrode is formed on the other of the two end portions of the active layer. The active layer comprises a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer stacked in sequence. The first semiconductor material layer is formed on the insulating layer and has an ordered lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disordered lattice structure; and the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disordered lattice structure, and is doped with N-type ions. The first semiconductor material layer is doped with Group 3A ions.

[0028] The present disclosure provides a thin film transistor comprising a gate, an insulating layer, an active layer, a source electrode, and a drain electrode. The insulating layer is formed on the gate electrode. The active layer is formed on the insulating layer. The source electrode is formed on one of the two end portions of the active layer. The drain electrode is formed on the other of the two end portions of the active layer. The active layer comprises a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer stacked in sequence. The first semiconductor material layer is formed on the insulating layer and has an ordered lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disordered lattice structure; and the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disordered lattice structure, and is doped with N-type ions. The thickness ratio of the second semiconductor material layer to the third semiconductor material layer is between 5:8 and 8:5.

[0029] The presently disclosed embodiment proposes a method for manufacturing a thin film transistor, comprising the following steps: forming a first metal layer and an insulating layer covering the first metal layer on a substrate; forming an amorphous semiconductor thin film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; forming second and third semiconductor material layers on the first semiconductor material layer to form an active layer, wherein the thickness ratio of the second semiconductor material layer to the third semiconductor material layer is between 5:8 and 8:5; forming a second metal layer on the active layer; and performing etching to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source and a drain.

[0030] The presently disclosed embodiment proposes a method for manufacturing a thin film transistor, comprising the following steps: forming a first metal layer and an insulating layer covering the first metal layer on a substrate; forming an amorphous semiconductor thin film on the insulating layer; performing ion implantation on the amorphous semiconductor thin film to implant Group 3A ions into the amorphous semiconductor thin film; performing heat treatment on the amorphous semiconductor thin film implanted with the Group 3A ions to convert the amorphous semiconductor thin film into a first semiconductor material layer; forming second and third semiconductor material layers on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing etching to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source and a drain.

[0031] The presently disclosed embodiment proposes a method for manufacturing a thin film transistor, comprising the following steps: forming a first metal layer and an insulating layer covering the first metal layer on a substrate; forming an amorphous semiconductor thin film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; forming second and third semiconductor material layers on the first semiconductor material layer to form an active layer; performing carrier removal treatment on the active layer to reduce the number of carriers at the side walls of the active layer; forming a second metal layer on the active layer; and performing etching treatment to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source and a drain.

[0032] An embodiment of the present disclosure provides a display device comprising a display panel, a data driver circuit, a connection module, and a control circuit. The display panel comprises a substrate and a pixel array. The data driver circuit is disposed on the substrate and electrically connected to the pixel array via a first transmission unit. One end of the connection module is disposed on the substrate and electrically connected to the data driver circuit via a second transmission unit. A control circuit is coupled to the other end of the connection module and electrically connected to the data driver circuit via the connection module and the second transmission unit. The data driver circuit comprises a driver circuit board, a functional unit, a first electrical connection unit, and a second electrical connection unit. The functional unit is disposed on the driver circuit board. The first electrical connection unit is disposed on the driver circuit board and located on one side of the functional unit, wherein the first electrical connection unit electrically connects the functional unit to the first transmission unit. The second electrical connection unit is disposed on the driver circuit board and located on the other side of the functional unit, wherein the second electrical connection unit electrically connects the functional unit to the second transmission unit. The second electrical connection unit comprises a first connection terminal and a second connection terminal, wherein the distance from the second connection terminal to the edge of the driver circuit board is greater than the distance from the first connection terminal to the edge of the driver circuit board.

[0033] The present disclosure provides a display device comprising a display panel, a scan driver circuit, and a data driver circuit. The display panel comprises a substrate and a pixel array. The scan driver circuit is disposed on the substrate and electrically connected to the pixel array, and is configured to generate a plurality of scan signals to turn on the pixel array row by row. The data driver circuit is disposed on the substrate and electrically connected to the pixel array, and is configured to provide data driver signals in coordination with the turn-on timing of the pixel array, so that the display panel presents a corresponding image in response to the data driver signals. The scan driver circuit comprises a plurality of first scan units for electrically connecting one of the odd-numbered scan lines and the even-numbered scan lines in the pixel array, and a plurality of second scan units for electrically connecting the other of the odd-numbered scan lines and the even-numbered scan lines in the pixel array. At least one of the plurality of first scan units comprises a first module, a second module, and a third module. The first module is configured to receive scan signals from the first two stages and the second two stages of the first scan units, and to generate a drive signal at a first node accordingly. The second module is electrically connected to the first module via the first node and determines a pull-up time point of the scan signal at the scan output terminal based on the drive signal, the first clock signal, and the reference signal. The third module is electrically connected to the second module and the scan output terminal and determines a pull-down time point of the scan signal at the scan output terminal based on the second clock signal and the reference signal. The first module includes a first transistor and a second transistor, each having a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of the first transistor are electrically connected together to receive the scan signals of the first two stages of the first scan unit.

[0034] The present disclosure provides a scanning drive circuit for a display device, which includes a multi-level first scanning unit and a multi-level second scanning unit. The multi-level first scanning unit is electrically connected to one of the odd-numbered scanning lines and the even-numbered scanning lines in the pixel array. The multi-level second scanning unit is electrically connected to the other of the odd-numbered scanning lines and the even-numbered scanning lines in the pixel array. Each of the first scanning units includes a first module, a second module, and a third module. The first module is used to receive scanning signals from the first two levels and the second two levels of the first scanning units, and generate a driving signal at a first node accordingly. The second module is electrically connected to the first module via the first node, and determines the pull-up time point of the scanning signal on the scanning output end based on the driving signal, the first clock signal, and the reference signal. The third module is electrically connected to the second module and the scanning output end, and determines the pull-down time point of the scanning signal on the scanning output end based on the second clock signal and the reference signal. Among them, the first module includes a first transistor and a second transistor, the first transistor and the second transistor respectively have a first end, a second end and a control end, and the first end and the control end of the first transistor are electrically connected together to receive the scanning signals of the first two levels of the first scanning units.

[0035] An embodiment of the present disclosure provides a data driving circuit for a display device, comprising a driving circuit board, a functional portion, a first electrical connection portion, and a second electrical connection portion. The functional portion is disposed on the driving circuit board. The first electrical connection portion is disposed on the driving circuit board and is located on one side of the functional portion, wherein the first electrical connection portion is used to electrically connect the functional portion to a display panel. The second electrical connection portion is disposed on the driving circuit board and is located on the other side of the functional portion, wherein the second electrical connection portion is used to electrically connect the functional portion to a flexible printed circuit board. The second electrical connection portion comprises a first connecting terminal and a second connecting terminal, wherein the distance from the second connecting terminal to the edge of the driving circuit board is greater than the distance from the first connecting terminal to the edge of the driving circuit board. An embodiment of the present disclosure provides a light guide plate, comprising a light incident surface, a first surface, and a second surface. The first surface of the light guide plate is substantially perpendicular to the light incident surface and serves as the light exit surface of the light guide plate, wherein the glossiness of the first surface is less than 1. The second surface of the light guide plate is located on the other side opposite to the second surface, wherein the glossiness of the second surface is greater than 95.

[0036] The present disclosure provides a light guide plate, comprising a light incident surface, a first surface, a second surface, and a plurality of side surfaces. The first surface is substantially perpendicular to the light incident surface and serves as a light emitting surface of the light guide plate. The second surface is located on the other side of the first surface, wherein the glossiness of the second surface is greater than 95%. The plurality of side surfaces are non-parallel to the first surface and are connected to the first surface and the second surface, wherein the glossiness of at least one of the plurality of side surfaces is greater than 95.

[0037] The presently disclosed embodiment provides a light guide plate comprising a main body and a reinforcement portion. The main body has a first surface and a second surface. The reinforcement portion is formed on at least one of the first surface and the second surface and comprises a plurality of columnar support units. The plurality of support units are light-transmissive, have an elastic recovery rate greater than or equal to 95, and are arranged in sequence on the main body. The plurality of support units include at least one support unit formed in the central area of ​​the main body, and support units formed at the four corners of the main body, respectively.

[0038] The present disclosure provides a light guide plate comprising a main body, the main body comprising a plurality of light guide units having a parallelogram structure, wherein adjacent light guide units are joined and fixed together by a joint portion, so that the joined light guide units form a substantially continuous first surface and a second surface opposite to the first surface.

[0039] The present disclosure provides a light guide plate including a body having a first surface and a second surface opposite to the first surface, wherein the body has a positive curvature at a center point of the first surface and a negative curvature at a center point of the second surface.

[0040] The present disclosure provides a backlight module comprising the aforementioned light guide plate and a light-emitting portion. The light-emitting portion is disposed toward the light incident surface and comprises a plurality of light-emitting elements, wherein the plurality of light-emitting elements are arranged at regular intervals.

[0041] The present disclosure provides a backlight module suitable for providing a backlight source for a display panel. The backlight module comprises a light guide plate and a light-increasing plate. The light guide plate comprises a light incident surface, a first surface, and a second surface. The first surface of the light guide plate is substantially perpendicular to the light incident surface and serves as the light emitting surface of the light guide plate, wherein the glossiness of the first surface is less than 1. The second surface of the light guide plate is located on the other side of the second surface, wherein the glossiness of the second surface is greater than 95.

[0042] An embodiment of the present disclosure proposes a display panel, characterized in that it includes a substrate, a plurality of light-emitting elements and a splicing unit. The substrate has a display area and a non-display area surrounding the display area. The plurality of light-emitting elements are arranged in an array in the display area of ​​the substrate, wherein there is a first spacing between adjacent light-emitting elements, and the non-display area is at least partially defined as a splicing area. The splicing unit is arranged on the substrate in the splicing area to cover at least part of the side wall of the substrate, wherein there is a second spacing between the side wall and the closest light-emitting element. The thickness of the splicing unit on the side wall of the substrate plus the second spacing is equal to half of the first spacing.

[0043] In some embodiments of the present disclosure, the carrier removal step includes: patterning the active layer to form sidewalls; and over-etching the sidewalls. The sidewalls are uniform planes formed by continuous side surfaces of the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer.

[0044] In some embodiments of the present disclosure, the method for manufacturing a thin film transistor further includes: performing an oxidation treatment to form a silicon oxide layer on the sidewall.

[0045] In some embodiments of the present disclosure, the carrier removal process includes: patterning the active layer to form sidewalls; and performing ion implantation to implant Group 3A ions into the sidewalls.

[0046] In some embodiments of the present disclosure, the total thickness of the second semiconductor material layer and the third semiconductor material layer is between to between.

[0047] In some embodiments of the present disclosure, the thickness of the second semiconductor material layer is between to And the third semiconductor material layer has a corresponding thickness so that the sum of the thicknesses of the second semiconductor material layer and the third semiconductor material layer is The present disclosure proposes a method for manufacturing a thin film transistor, which includes the following steps: forming a first metal layer and an insulating layer covering the first metal layer on a substrate; forming an amorphous semiconductor thin film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; performing interface cleaning treatment on the first semiconductor material layer to remove native semiconductor oxide on the surface of the first semiconductor material layer; forming second and third semiconductor material layers on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing etching treatment to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source and a drain.

[0048] In some embodiments of the present disclosure, the method for manufacturing the thin film transistor further includes the following steps: before performing the heat treatment, performing ion implantation on the amorphous semiconductor film to implant Group 3A ions into the amorphous semiconductor film.

[0049] In some embodiments of the present disclosure, the method for manufacturing the thin film transistor further includes the following steps: before forming the second and third semiconductor material layers, performing an interface cleaning treatment on the first semiconductor material layer to remove native semiconductor oxide on the surface of the first semiconductor material layer.

[0050] In some embodiments of the present disclosure, a plurality of reflective film structures are formed on the light incident surface of the light guide plate, and the plurality of reflective film structures are arranged at fixed intervals, wherein the glossiness of each of the reflective film structures is greater than 95.

[0051] In some embodiments of the present disclosure, a plurality of reflective film structures are formed on the light incident surface, and each of the reflective film structures is formed in a spacing region between adjacent light-emitting elements.

[0052] In some embodiments of the present disclosure, the plurality of support units include a first support unit having a first height and a second support unit having a second height, wherein the first height is greater than the second height.

[0053] In some embodiments of the present disclosure, at least part of the plurality of light guide units has a diamond structure, and at least another part has a triangular structure.

[0054] In some embodiments of the present disclosure, the curvatures of the first surface and the second surface are both greater than 1500R.

[0055] An embodiment of the present disclosure provides a display, characterized by comprising: a plurality of display panels as described above, wherein the plurality of display panels are spliced ​​together and driven synchronously to collaboratively display images.

[0056] The embodiment of the present disclosure provides a pixel array substrate including a thin film transistor manufactured according to the above-mentioned thin film transistor manufacturing method.

[0057] An embodiment of the present disclosure provides a display device including the pixel array substrate described above.

[0058] Through one of the technical solutions described in the embodiments of the present disclosure, the display device, LED module and manufacturing method thereof proposed in the embodiments of the present disclosure can basically maintain the upper surfaces of all light-emitting elements at the same level without any height differences, so that the subsequent production process will not be affected by the flatness of the LED module, thereby effectively improving the yield and reliability of the production process.

[0059] Through one of the technical solutions described in this disclosure, the quantum dot film proposed in the embodiment of this disclosure can not only provide a preliminary water-blocking effect through the support layer and the bonding layer, but also utilize the water-blocking layer covering the active layer to further block water vapor from the active layer, making the active layer less susceptible to water vapor, significantly improving the reliability of the backlight module and display. In addition, because the water-blocking layer significantly improves the water-blocking properties of the quantum dot film, the design of the quantum dot film can provide more choices for the materials of the support layer and the bonding layer to meet design considerations while also taking into account cost requirements.

[0060] Through one of the technical solutions described in the present disclosure, the thin-film transistor, pixel array substrate, display device, and manufacturing method thereof proposed in the embodiments of the present disclosure can, through a specific interface cleaning process in the thin-film transistor manufacturing process, substantially eliminate the presence of semiconductor oxides that are prone to causing bonding defects between the microcrystalline or polycrystalline silicon layer and the amorphous silicon layer in the active layer. This allows the various thin films in the active layer to be well bonded without the problem of film peeling, and effectively improves the carrier mobility and switching ratio of the thin-film transistor. In addition, the embodiments of the present disclosure also propose increasing the critical voltage of the thin-film transistor by ion implanting the active layer before the heat treatment step, so that the finished product can have better device characteristics.

[0061] Through one of the technical solutions described in the present disclosure, the display device and its scanning driving circuit proposed in the embodiment of the present disclosure can omit the number of signal lines by changing the circuit configuration of the scanning unit, thereby reducing the width of the non-display area of ​​the display panel to achieve the effect of reducing the border width.

[0062] Through one of the technical solutions described in this disclosure, the light guide plate and its backlight module proposed in the embodiment of this disclosure achieve structural reinforcement of the light guide plate by forming a columnar support unit structure on the main body of the light guide plate. Since no additional rigid reinforcement plate is required, the cost of the entire backlight module can be effectively controlled. In addition, by configuring a first support unit and a second support unit with a height difference, a step support can be formed on the light guide plate to achieve optimal performance between display effect and structural protection.

[0063] On the other hand, in the light guide plate and its backlight module proposed in some embodiments of the present disclosure, the light guide plate is composed of a standard module with a parallelogram structure, which can effectively reduce the directivity of the light source, so that the light can be diffused more evenly on the entire light guide plate, so that the backlight module can obtain a more uniform surface light source. In addition, even if the light guide plate formed by joining the light guide units is squeezed, the stress of the squeeze can be absorbed by the joint part without the risk of warping like the traditional whole-surface light guide plate. The risk of deformation of the light guide plate caused by thermal expansion and moisture expansion can also be effectively reduced / eliminated. On the other hand, it can also effectively simplify the manufacturing process of the light guide plate and reduce the manufacturing cost and cycle, as well as reduce the cost and expenses of maintenance.

[0064] In the light guide plate and backlight module thereof proposed in some embodiments of the present disclosure, by providing a light guide plate with a curved structure, the light source in the central area can be more evenly diffused to the peripheral area, thereby achieving higher light source conversion efficiency.

[0065] Through one of the technical solutions described in this disclosure, the display panel, display, and manufacturing method proposed in the embodiments of this disclosure, through the structural configuration of the splicing unit, ensures that the spacing between the light-emitting elements at the seam is equal to the spacing between the light-emitting elements within the panel, thereby effectively eliminating the visual impact of the splicing seam, without visible splicing stripes or optical color difference. In addition, because no additional components such as optical microstructures or light strips are required, there is a significant advantage in manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] 1A to 1D are schematic diagrams of display devices according to different embodiments of the present disclosure;

[0067] 2A and 2B are schematic diagrams showing configurations of LED modules according to different embodiments of the present disclosure;

[0068] FIG3 is a schematic cross-sectional view of an LED module according to some embodiments of the present disclosure;

[0069] 4A to 4G are schematic cross-sectional views of LED modules according to different embodiments of the present disclosure;

[0070] 5A and 5C are flowcharts of steps of manufacturing methods of LED modules according to different embodiments of the present disclosure;

[0071] 6A to 6H are schematic flow charts of a method for manufacturing an LED module according to the embodiment of FIG. 5A ;

[0072] 7A to 7I are schematic flow charts of a method for manufacturing an LED module according to another embodiment of FIG. 5A ;

[0073] 8A to 8F are schematic flow charts of a method for manufacturing an LED module according to an embodiment of FIG. 5B and FIG. 5C ;

[0074] FIG9 is a schematic cross-sectional view of a thin film transistor according to some embodiments of the present disclosure;

[0075] 10A to 10E are flowcharts of methods for manufacturing thin film transistors according to different embodiments of the present disclosure;

[0076] 11A to 11F are schematic flow charts illustrating a method for manufacturing the thin film transistor of FIG. 10A ;

[0077] 12A to 12F are schematic flow charts of a method for manufacturing the thin film transistor according to FIG. 10B ;

[0078] 13A to 13F are schematic flow charts of a method for manufacturing the thin film transistor according to FIG. 10C ;

[0079] FIG14 is an SEM photograph of a thin film transistor manufactured according to the manufacturing method of an embodiment of the present disclosure and a comparative example;

[0080] FIG15 is a schematic diagram showing the on-state current of a thin film transistor manufactured according to the manufacturing method of an embodiment of the present disclosure and a comparative example;

[0081] FIG16 is a current-voltage characteristic curve of a thin film transistor manufactured according to a manufacturing method according to an embodiment of the present disclosure at different ion implantation concentrations;

[0082] FIG17 is a current-voltage characteristic curve of a thin film transistor with different thicknesses of active layers manufactured according to a manufacturing method of an embodiment of the present disclosure;

[0083] FIG18 shows current-voltage characteristic curves of a thin film transistor manufactured through a carrier removal process according to an embodiment of the present disclosure and a comparative example;

[0084] FIG19 shows current-voltage characteristic curves of a thin film transistor manufactured through a carrier removal process according to an embodiment of the present disclosure and a comparative example;

[0085] 20A to 20E are schematic diagrams of the structural configurations of backlight modules according to different embodiments of the present disclosure;

[0086] 21A to 21D are schematic diagrams showing configurations of light guide plates according to different embodiments of the present disclosure;

[0087] 22A and 22B are schematic diagrams of light incident surface coating structures according to different embodiments of the present disclosure;

[0088] 23A to 26 are schematic diagrams showing configurations of light guide plates according to different embodiments of the present disclosure;

[0089] FIG27 is a schematic diagram of a backlight module according to some embodiments of the present disclosure;

[0090] FIG28 is a schematic diagram of a bonding layer of a quantum dot film according to some embodiments of the present disclosure;

[0091] 29A to 29F are schematic cross-sectional views of quantum dot films according to different embodiments of the present disclosure;

[0092] FIG30 is a diagram showing the chemical structure of the water-blocking layer material of quantum dot films according to different embodiments of the present disclosure;

[0093] FIG31 is a table showing the mechanical properties of water-blocking layer materials according to different embodiments of the present disclosure;

[0094] FIG32 is a schematic diagram of light transmittance of water-blocking layer materials at different wavelengths according to different embodiments of the present disclosure;

[0095] FIG33 is a flowchart of a method for manufacturing a quantum dot film according to some embodiments of the present disclosure;

[0096] FIG34 is a schematic diagram of a spliced ​​display device according to some embodiments of the present disclosure;

[0097] 35A to 35D are schematic diagrams showing configurations of display panels used in the spliced ​​display device of FIG. 34 according to different embodiments;

[0098] 36A to 36D are schematic diagrams showing configurations of spliced ​​display devices according to different embodiments of the present disclosure;

[0099] FIG37 is a flowchart of a method for manufacturing a display panel according to some embodiments of the present disclosure;

[0100] FIG38 is a schematic diagram of a scan driving circuit according to some embodiments of the present disclosure;

[0101] 39A and 39B are schematic circuit diagrams of an embodiment of a scan driving circuit;

[0102] 40A to 40D are schematic diagrams of signal waveforms of the scan driving circuit described in FIG. 39A and FIG. 39B ;

[0103] 41A to 41D are schematic circuit diagrams of scan driving circuits according to some embodiments of the present disclosure;

[0104] FIG42 is a schematic diagram of a data driving circuit according to some embodiments of the present disclosure;

[0105] 43A to 43C are schematic diagrams illustrating configurations of data driving circuits according to some embodiments of the present disclosure; and

[0106] 44A to 44D are partially enlarged schematic diagrams of electrical connection portions of a data driving circuit according to different embodiments of the present disclosure. DETAILED DESCRIPTION

[0107] To make the above-mentioned objectives, features, and advantages of this technical solution more clearly understood, specific embodiments of the proposed technical solution are described in detail below with reference to the accompanying drawings. The following descriptions of the various embodiments of the technical solution of the present invention are for illustrative purposes only and are not intended to be all embodiments of the present invention or to limit the present invention to specific embodiments. Based on the embodiments disclosed herein, all other embodiments obtained by persons of ordinary skill in the art without creative effort should fall within the scope of protection of the present invention.

[0108] It should be noted that when an element is referred to as being "disposed on" another element, it may be directly on the other element or there may also be an element centered thereon. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an element centered thereon at the same time. The terms "vertical", "horizontal", "left", "right", "up", "down" and similar expressions used herein are only intended to indicate relative positional relationships based on the accompanying drawings, and do not limit the elements using the terms to being implemented only in a representative manner. When the absolute position of the object being described changes, the description of the relative position may also change accordingly.

[0109] The descriptions of "substantially", "substantially", "approximately" and the like in this document are used to recognize the error range implied by possible unintended effects and deviations in the manufacturing process or material selection. The error range may include a range of changes that do not significantly change the material structure, configuration, characteristics, or effect, such as a range of 0%-10% deviation, wherein the error range is clear to those skilled in the art. For example, when describing "two objects being substantially parallel", if it is actually observed that there is a slight height difference between the two objects, but this height difference is negligible (e.g., less than 10%) relative to the size of the objects themselves and does not affect the effect, then the relative configuration of the two objects observed will still be interpreted as being within the range of "substantially parallel" described herein.

[0110] All descriptions of specific numerical values ​​herein, even when not explicitly stated, include the meaning of "approximately" or "substantially." This means that these specific values ​​include a possible range of numerical errors, which is used to account for possible unintended effects and deviations in the manufacturing process or material selection. This numerical error range may include changes in values ​​that do not significantly alter the material structure, properties, or effects, such as a range of 0% to 10%. This error range is clear to those skilled in the art.

[0111] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. The terms used herein in the specification of this disclosure are intended only to describe specific embodiments and are not intended to limit this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0112] 1A and 1B are schematic diagrams of display devices according to different embodiments of the present disclosure, wherein FIG. 1A is a schematic diagram of a configuration of a non-self-luminous display device, and FIG. 1B is a schematic diagram of a configuration of a self-luminous display device.

[0113] Please first refer to Figure 1A. The display device 10 of this embodiment may be, for example, a liquid crystal display device (LCD device), which includes a backlight module 100 and a display panel 100', wherein the backlight module 100 and the display panel 100' are arranged on the xy plane, and the display panel 100' is arranged on the backlight module 100 along the z-axis. The backlight module 100 is used to provide a light source with sufficient brightness and uniform distribution toward the display panel 100'. The display panel 100' is used to control and adjust the light passing therethrough to present a corresponding image thereon. In this embodiment, the display device 10 can be any electronic device with a display function, such as a television, a screen, a laptop computer or a mobile phone, but the present disclosure is not limited thereto.

[0114] The backlight module 100 includes a light-emitting layer 110, wherein the light-emitting layer 110 includes a plurality of light-emitting elements (LEDs) arranged in an array. The LEDs can be used to emit light toward the display panel 100'. In some embodiments, the LEDs can be white, red, green, or blue light-emitting diodes (or LEDs emitting light with a wavelength between white, red, green, and blue), or a combination of these light-emitting diodes, but the present disclosure is not limited thereto.

[0115] Furthermore, in some embodiments, the backlight module 100 may further include a quantum dot film 120 and an optical adjustment layer 130, wherein the quantum dot film 120 is disposed on the light-emitting layer 110, and the optical adjustment layer 130 is disposed on the quantum dot film 120, that is, the quantum dot film 120 is disposed between the light-emitting layer 110 and the optical adjustment layer 130. In embodiments in which the quantum dot film 120 is disposed, the light-emitting elements LEDs may be, for example, blue light-emitting diodes.

[0116] The quantum dot film 120 is disposed on the light transmission path of the light-emitting layer 110 and is used to adjust the wavelength of a portion of the light emitted by the light-emitting element LEDs, while allowing another portion of the light emitted by the light-emitting element LEDs to pass directly without adjustment. For example, when the light-emitting element LEDs emit light in the blue wavelength range (e.g., 400nm to 520nm), the quantum dot film 120 can adjust the wavelength of the first portion of the received light to the red wavelength range (e.g., 610nm to 720nm), adjust the wavelength of the second portion of the received light to the green wavelength range (e.g., 520nm to 610nm), and directly output the third portion of the received light without adjustment, maintaining it in the blue wavelength range. In this way, the first to third portions of light emitted by the light-emitting layer 110 can be mixed to form white light after passing through the quantum dot film 120.

[0117] Optical adjustment layer 130 is also located in the light transmission path of light-emitting layer 110 and is used to adjust the direction of received light to ensure a more uniform light source. In some embodiments, optical adjustment layer 130 includes a plurality of optical microstructures (not shown) and / or optical films (not shown) for adjusting light direction, but the present disclosure is not limited thereto.

[0118] The display panel 100' includes, for example, a pixel array substrate, an opposing substrate, and a non-self-luminous display medium, wherein the pixel array substrate and the opposing substrate are disposed opposite each other, and the non-self-luminous display medium is disposed between the pixel array substrate and the opposing substrate. In some embodiments, the non-self-luminous display medium may be, for example, liquid crystal, but the present disclosure is not limited thereto.

[0119] 1B , the display device 20 of this embodiment may be, for example, an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, or another type of self-luminous display device, and includes a self-luminous display panel 200, wherein the self-luminous display panel 200 includes a self-luminous pixel layer 210. The self-luminous pixel layer 210 includes a plurality of light-emitting elements (LEDs) (e.g., mini-LEDs or micro-LEDs), wherein individual or multiple light-emitting elements (LEDs) constitute pixels arranged in an array and are controlled to adjust their light emission states to present corresponding images.

[0120] Furthermore, in some embodiments, the self-luminous display panel 200 may further include an optical adjustment layer 230 disposed on the self-luminous pixel layer 210. The optical adjustment layer 230 is similar to the optical adjustment layer 130 described in the embodiment of FIG1A , and is configured in the light transmission path of the self-luminous pixel layer 210 to adjust the direction of received light.

[0121] In the above embodiments, the light-emitting layer 110 in the backlight module 100 or the self-luminous pixel layer 210 in the self-luminous display panel 200 both have a similar structural configuration of an array of light-emitting elements disposed on a substrate, and therefore can be collectively referred to as an LED module. In other words, the structural configuration of the LED module described later herein can be applied to either the non-self-luminous display device 10 of FIG. 1A or the self-luminous display device 20 of FIG. 1B , and the present disclosure is not limited thereto.

[0122] From the perspective of circuit configuration and display driving, as shown in Figures 1C and 1D , Figure 1C is a top view of the display device 30, and Figure 1D is a side view of the display device 30. For ease of illustration, Figure 1C shows the internal components of the display device 30 unfolded on the xy plane, while Figure 1D shows the internal components of the display device 30 arranged within the housing.

[0123] In this embodiment, in addition to the aforementioned LED module, the display device 30 may also include a scan driver circuit 120', a data driver circuit 130', a connection module 140', and a control circuit 150' for driving the display panel 100'. The display panel 100' has a display area DR and a non-display area SR. The display area DR is used to display images, while the non-display area SR is an area where the display panel 100' does not display images. The non-display area SR typically surrounds the display area DR and can also be considered the border area of ​​the display device 100. The scan driver circuit 120' and the data driver circuit 130' are disposed in the non-display area SR of the display panel 100'. In the figure, the scan driver circuit 120' is shown as being disposed in the non-display area SR on the left and right sides of the display panel 100', and the data driver circuit 130' is shown as being disposed in the non-display area SR on the bottom side of the display panel 100', but the present disclosure is not limited to this. One end of the connection module 140 ′ is disposed on a side of the non-display region SR close to the data driving circuit 130 ′, and the control circuit 150 ′ is coupled to the other end of the connection module 140 ′.

[0124] Specifically, the display panel 100' may include a substrate 111' and a pixel array 112' located in the display region DR. The pixel array 112' is disposed on the substrate 111' and includes, for example, pixel units Pu arranged in an m×n array, i.e., m columns and n rows. m and n may be natural numbers selected according to design requirements and are not limited in this disclosure.

[0125] In some embodiments, each pixel unit Pu may correspond to a light-emitting element, and the light-emitting element may be, for example, a white light-emitting diode or a blue light-emitting diode, but the present disclosure is not limited thereto. The light-emitting element may be a sub-millimeter light-emitting diode (mini-LED), a micro light-emitting diode (micro-LED), or an organic light-emitting diode (OLED), but the present disclosure is not limited thereto. In other embodiments, the light-emitting element LEDs may also be of other sizes and / or types. Depending on the type of light-emitting element selected, the display panel 100 may be, for example, a ULED panel, a mini-LED panel, a micro-LED panel, or an OLED panel, but the present disclosure is not limited thereto.

[0126] In some embodiments, each pixel unit Pu may include a plurality of sub-pixels, such as a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B. The first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are each controlled to emit light having different wavelengths. For example, the first sub-pixel R may include a light-emitting element having a red wavelength range (e.g., 610nm to 720nm), the second sub-pixel G may include a light-emitting element having a green wavelength range (e.g., 520nm to 610nm), and the third sub-pixel B may include a light-emitting element having a blue wavelength range (e.g., 400nm to 520nm). In some embodiments, the light-emitting elements of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B may be a red light-emitting diode (or a light-emitting diode having a wavelength in the red range), a green light-emitting diode (or a light-emitting diode having a wavelength in the green range), and a blue light-emitting diode (or a light-emitting diode having a wavelength in the blue range), respectively. Similarly, the light-emitting element of each sub-pixel R / G / B may be a mini-LED or a micro-LED, but the present disclosure is not limited thereto.

[0127] In terms of the electrical relationship between the components, the scan driver circuit 120' is electrically connected to the display panel 100' via the wiring on the substrate 111'. The data driver circuit 130' is electrically connected to the display panel 100' via the first transmission unit WR1 and to the flexible circuit board 140' via the second transmission unit WR2. On the other hand, the control circuit 150' is electrically connected to the data driver circuit 130' via the connection module 140' and the second transmission unit WR2. The first transmission unit WR1 and the second transmission unit WR2 can be transmission lines formed on the substrate 111'.

[0128] The scan driver circuit 120' is configured to generate scan signals that turn on / enable pixels row by row based on timing control signals. In this embodiment, the scan driver circuit 120' is illustrated as two configurations, one for enabling pixels in odd and one for enabling pixels in even rows. The scan driver circuit 120' on the left side includes scan units s121_1, s121_3, ..., s121_m-1, respectively, connected to odd-numbered scan lines, while the scan driver circuit 120' on the right side includes scan units s121_2, s121_4, and s121_m, respectively, connected to even-numbered scan lines. However, the present disclosure is not limited to this embodiment. In this embodiment, scan unit s121_x represents any one of the scan units s121_1, s121_3, ..., s121_m-1 on the left side, and scan unit s121_y represents any one of the scan units s121_2, s121_4, and s121_m on the right side. In other words, x may be any odd number less than m, and y may be any even number less than or equal to m, where m is an even number, but the present disclosure is not limited thereto.

[0129] The data driver circuit 130' is configured to generate a drive signal for driving the pixel array 112' based on the data control signal. While the figures of this embodiment illustrate a single data driver circuit 130', the present disclosure is not limited thereto. In some embodiments, the data driver circuit 130' may be integrated into multiple driver chips, where the multiple driver chips can collaboratively drive pixels in different portions / regions of the pixel array 112'.

[0130] More specifically, pixels in the same column of pixel array 112' correspond to the same scan line, and pixels in the same row correspond to the same data line of pixel array 112'. Pixel array 112' is electrically connected to scan driver circuit 120' via scan lines to receive scan signals, and is electrically connected to data driver circuit 130' via data lines and first transmission unit WR1 to receive data driver signals provided by data driver circuit 130'. Data driver circuit 130' provides data driver signals in conjunction with the activation timing of pixel array 112', so that pixel array 112' adjusts the light passing through according to the data driver signals, thereby presenting a corresponding image in display area DR.

[0131] The connection module 140' is used to provide a signal transmission path between the data driver circuit 130' and the control circuit 150', allowing the data control signals generated by the control circuit 150' to be transmitted to the data driver circuit 130' via the connection module 140' and the second transmission unit WR2. In some embodiments, the connection module 140' may be a flexible printed circuit board (hereinafter referred to as the flexible printed circuit board 140'). As shown in FIG1D , the flexible printed circuit board 140' has multiple connection terminals at each end. The connection terminals on the side of the flexible printed circuit board 140' closest to the data driver circuit 130' are disposed on the substrate 111', while the connection terminals on the side of the flexible printed circuit board 140' closest to the control circuit 150' are disposed on the circuit board of the control circuit 150'. The portion of the flexible printed circuit board 140' closest to the data driver circuit 130', where the connection terminals are disposed, is attached to the substrate 111'. The width of the attached portion is approximately the distance from the top of the connection terminals of the flexible printed circuit board 140 to the substrate edge 111e.

[0132] During assembly of the display device 30, the flexible printed circuit board is bent so that the control circuit 150' is positioned on the back side of the display panel 100' (i.e., on the other side of the substrate 111' relative to the display area DR). In other words, when the display device 30 is assembled, the control circuit 150', substrate 111', and data driver circuit 130' within the display device 30 are arranged sequentially along the z-axis.

[0133] The pixel array 112' of the display panel 100' includes a plurality of thin-film transistors (not shown). These thin-film transistors are turned on or off in response to received signals to control the operation of corresponding pixels, thereby achieving the aforementioned effect of adjusting the light passing therethrough according to the data drive signal to display the corresponding image in the display area DR. The following embodiments will further describe various implementation examples of these thin-film transistors.

[0134] Figures 2A and 2B are schematic diagrams of the configuration of LED modules according to different embodiments of the present disclosure. Referring first to Figure 2A , the LED module 310 of this embodiment includes light-emitting elements (LEDs), a substrate 311, a circuit layer 312, and a protective layer 313. The circuit layer 312 is disposed on the substrate 311. The light-emitting elements (LEDs) are disposed on the circuit layer 312 to receive a driving signal for controlling their lighting through the circuit layer 312. Each light-emitting element (LED) has two electrodes, and the two electrodes are located on the same side of the light-emitting element (LED) to be electrically connected to the circuit layer 312. The protective layer 312 covers the light-emitting elements (LEDs) to prevent short circuits between the light-emitting elements (LEDs).

[0135] Referring to FIG. 2B , the LED module 410 of this embodiment includes light-emitting elements (LEDs), a substrate 411, a first circuit layer 412, a protective layer 413, and a second circuit layer 414. The first circuit layer 412 is disposed on the substrate 411. The light-emitting elements (LEDs) are disposed on the first circuit layer 412, wherein each light-emitting element (LED) has two electrodes, which are located on opposite sides of the light-emitting element (LED). The electrode (or lower electrode) on the side of each light-emitting element (LED) close to the first circuit layer 412 (or the lower side) is electrically connected to the first circuit layer 412. The protective layer 413 covers at least a portion of the surface of each light-emitting element (LED) to prevent short circuits between the light-emitting element (LEDs). The protective layer 413 at least exposes the electrode (or upper electrode) on the other side of the light-emitting element (LED) (i.e., the side away from the first circuit layer 412, or the upper side). The second circuit layer 414 is disposed on the protective layer 413 and electrically connected to the electrodes on the other side of the light emitting elements LEDs. The light emitting elements LEDs can receive driving signals for controlling their lighting through the first circuit layer 412 and the second circuit layer 414 .

[0136] Specifically, in the embodiment of FIG2A , the light-emitting elements LEDs may be, for example, face-mounted or flip-chip packaged light-emitting diodes, wherein the electrodes of each light-emitting diode are disposed on the same side, and thus can receive a driving signal via a circuit layer 312 located on a substrate 311. On the other hand, in the embodiment of FIG2B , the light-emitting elements LEDs may be, for example, vertically packaged light-emitting diodes, wherein the electrodes of each light-emitting diode are disposed on opposite sides, and thus can receive a driving signal via a first circuit layer 412 and a second circuit layer 414 located on opposite sides of the light-emitting elements LEDs.

[0137] In some embodiments, the light-emitting elements LEDs include, for example, red, green, and blue light-emitting elements, and the three-color light-emitting elements are arranged in a certain order on the circuit layer 112. For example, they are arranged in the order of red (R) → green (G) → blue (B), but the present disclosure is not limited to this.

[0138] It should be noted that although FIG1C illustrates the display panel 100′ and the peripheral circuitry as a single display device 30 (or display), the present disclosure is not limited thereto. In other embodiments, the display panels 100′ may also be spliced ​​to form a spliced ​​display. This will be further described in subsequent embodiments.

[0139] The following further describes the design of the LED module in the display device 10 / 20 / 30.

[0140] In the application of the LED module 410 using vertically packaged light-emitting element LEDs, since the actual size and configuration of each light-emitting element LED are different, the position of the upper electrode of each light-emitting element LED will be different and not on the same plane, as shown in Figure 3, where Figure 3 is a schematic diagram of the cross-sectional structure of the LED module in area Px.

[0141] In this embodiment, the first circuit layer 412 includes lower electrode wires (or first electrode wires) 4121, 4122, and 4123, wherein the lower electrode wires 4121, 4122, and 4123 are respectively electrically connected to the lower electrodes of the light-emitting elements LED1, LED2, and LED3 via corresponding joints AD. Meanwhile, the second circuit layer 414 includes upper electrode wires (or second electrode wires) 4141, 4142, and 4143, wherein the upper electrode wires 4141, 4142, and 4143 are respectively electrically connected to the upper electrodes of the light-emitting elements LED1, LED2, and LED3.

[0142] In some embodiments, the LED module may further include a light shielding portion 415 , which is disposed on the protective layer 413 and spaced apart from the upper electrode wires 4141 - 4143 to prevent the light emitted by adjacent light emitting elements LED1 - LED3 from affecting each other.

[0143] The light-emitting element LED1 on the left side of FIG3 is configured in an ideal state. That is, when the light-emitting element LED1 is disposed on the substrate 411 through the joint AD and connected to the lower electrode wire 4121, the height H1 of the lower electrode wire 4121, the joint AD, and the light-emitting element LED1 (i.e., the maximum distance from the bottom of the lower electrode wire 4121 to the top of the light-emitting element LED1) is exactly the same as the height of the protective layer, so that the upper electrode of the light-emitting element LED1 is exposed and located at a position substantially flush with the upper edge of the protective layer (i.e., the upper electrode and the upper side of the protective layer are substantially in the same plane). Therefore, in an ideal state, the upper electrode wire 4141 formed on the protective layer 413 can be easily electrically connected to the exposed upper electrode, and the upper electrode wire 4141 can still have a uniform line width (here, the width of the upper electrode wire 4141 in the xz plane) to ensure electrical signal transmission.

[0144] The light-emitting elements LED2 and LED3 illustrate configuration states that may often occur in actual situations. In the configuration of the light-emitting element LED2, the height of the light-emitting element LED2 and the corresponding junction AD are slightly smaller than the height of the light-emitting element LED1 and its junction AD. This causes the height H2 of the lower electrode wire 4122, the junction AD, and the light-emitting element LED2 as a whole to be smaller than the height of the protective layer 413 (i.e., approximately the height H1). This causes the protective layer 413 to cover the upper electrode of the light-emitting element LED2 during formation. Consequently, when the upper electrode wire 4142 is formed on the protective layer 413, because the upper electrode of the light-emitting element LED2 is covered by the protective layer 413, the upper electrode wire 4142 cannot be effectively electrically connected to the upper electrode of the light-emitting element LED2, causing the light-emitting element LED2 to be unable to receive a driving signal and light up. The configuration state of the light-emitting element LED2 can be considered to be a configuration state that is too low.

[0145] Regarding the configuration of the light-emitting element LED3, the height of the light-emitting element LED3 is slightly greater than the height of the light-emitting element LED. This causes the height H3 of the lower electrode wire 4123, the joint AD, and the light-emitting element LED3 as a whole to be greater than the height of the protective layer 413. This causes the upper side of the light-emitting element LED3 to protrude beyond the upper surface of the protective layer 413, resulting in the upper electrode of the light-emitting element LED3 and the upper surface of the protective layer 413 not being on the same plane. Consequently, when forming the upper electrode wire 4143 on the protective layer 413, because the upper electrode of the light-emitting element LED is higher than the upper surface of the protective layer 413, the upper electrode wire 4143 must be bent to extend to and electrically connect to the upper electrode of the light-emitting element LED3. The wire width at the bend (here, the width of the upper electrode wire 4143 in the xz plane) is relatively thin, which can easily cause the wire to break, preventing proper transmission of electrical signals. The configuration of the light-emitting element LED3 can be considered to be too high.

[0146] As can be seen from the above, in typical LED module configurations, due to variations in thickness during actual manufacturing of the light-emitting elements LED1-LED3, the lower electrode leads 4121-4143 and the corresponding joint AD may also have different thicknesses / heights during the manufacturing process. These various manufacturing process and material differences accumulate when the LED module is packaged, resulting in the upper electrodes of the light-emitting elements LED1-LED3 having different heights (e.g., H1-H3), which can lead to the aforementioned poor connection of the upper electrode leads 4141-4143 during formation / installation.

[0147] To address the aforementioned issues, the present disclosure proposes various novel structural configurations to achieve a flattened LED module surface. Figures 4A to 4G illustrate cross-sectional views of LED modules according to various embodiments of the present disclosure. In some embodiments of these structural configurations, the protective layer of the LED module is designed to have a thickness exceeding the height of the light-emitting elements, their corresponding lower electrode leads, and the joint, so that the upper surface of the protective layer is higher than the upper electrode of each light-emitting element. Subsequently, a specific manufacturing process (e.g., photolithography) is utilized to expose the upper electrode covered by the protective layer, creating a structure with an opening between the upper electrode of each light-emitting element and the protective layer. Thus, the upper electrode lead can be electrically connected to the upper electrode within the opening through the opening, thereby achieving a flattened LED module structure (as shown in the embodiments of Figures 4A to 4F). In other embodiments of these structural configurations, a force is applied to the light-emitting elements toward the substrate during placement, causing the light-emitting elements to experience different displacements depending on their individual size / height, resulting in different substrate spacings, thereby maintaining the upper electrodes of the light-emitting elements in the same plane. Thus, the LED module can form a flat surface to facilitate the placement of the upper electrode wires and the electrical connection with each light-emitting element, thereby achieving a flat LED module structure (such as the embodiment of FIG4G). The structures of the embodiments of FIG4A to FIG4G are described below.

[0148] Referring first to Figure 4A , the LED module 510a of this embodiment includes a substrate 511, a first circuit layer 512, a plurality of light-emitting elements LED1-LED3, a second circuit layer 514, and a light shielding portion 515. The first circuit layer 512 is disposed on the substrate 511. The light-emitting elements LED1-LED3 are disposed on the first circuit layer 512 via corresponding joints AD, such that the lower electrodes of the light-emitting elements LED1-LED3 are electrically connected to the first circuit layer 512 via the joints AD. A protective layer 513 is formed on the substrate 511 and covers the first circuit layer 512, the joint AD, and the surrounding areas of the light-emitting elements LED1-LED3. This layer is used to prevent unintended short circuits between adjacent light-emitting elements LED1-LED3. The protective layer 513 exposes at least part or all of the top electrodes of the light-emitting elements LED1-LED3. The height / thickness of the protective layer 513 formed on the substrate 511 is greater than or equal to the height H1-H3 corresponding to any of the light-emitting elements LED1-LED3, thereby forming an opening OP in at least one or more of the light-emitting elements LED1-LED3. The height H1-H3 corresponding to any of the light-emitting elements LED1-LED3 referred to herein may, for example, be the sum of the height / thickness of any light-emitting element LED1-LED3 and its corresponding first circuit layer 512 and the joint AD. A second circuit layer 514 is disposed on the protective layer 513 and extends toward the opening OP to electrically connect to the top electrodes of each of the light-emitting elements LED1-LED3 through the opening OP.

[0149] More specifically, the first circuit layer 512 includes lower electrode conductors 5121-5123, and the second circuit layer 514 includes upper electrode conductors 5141-5143. The lower electrodes of the light-emitting elements LED1-LED3 are electrically connected to the lower electrode conductors 5121-5123 via corresponding joints AD, and the upper electrodes of the light-emitting elements LED1-LED3 are electrically connected to the upper electrode conductors 5141-5143 within corresponding openings OP. Through the above configuration, light-emitting elements LED1-LED3 of different heights H1-H3 can achieve better electrical connection through the upper electrode conductors 5141-5143 extending to the opening OP, and the poor connection described in Figure 3 will not occur due to the light-emitting elements being configured too low (such as LED2) or too high (such as LED3). Furthermore, because the height differences between the light-emitting elements LED1-LED3 are compensated for by the upper electrode conductors 5141-5143 extending to the openings, the entire upper electrode conductor 5141 (including the portion located on the upper surface of the protective layer 513) can have a uniform line width. This ensures the transmission of electrical signals while also avoiding manufacturing risks such as breakage and poor contact caused by bending the wiring.

[0150] In other words, through the structural configuration of FIG. 4A , the top surfaces of all light-emitting elements LED1 - LED3 can be maintained at substantially the same level without any height differences. Therefore, subsequent manufacturing processes will not be affected by the flatness of the LED module, thereby effectively improving the yield and reliability of the manufacturing process.

[0151] In this embodiment, the substrate 511 can be a soft or rigid substrate such as a printed circuit board, a glass substrate or a film substrate, and the substrate 511 can be transparent or opaque depending on the selected material and the required application type, but the present disclosure is not limited to this.

[0152] In some embodiments, the material of the bonding portion AD can be any material capable of providing adhesion to stably bond the light-emitting elements LED1-LED3 to the first circuit layer 512, such as solder paste, anisotropic conductive film (ACF), or other adhesive materials. Furthermore, the bonding process for attaching the light-emitting elements LED1-LED3 to the first circuit layer 512 via the bonding portion AD can be performed by screen printing, inkjet printing (IJP), or exposure, development, and baking, etc., although the present disclosure is not limited thereto.

[0153] Referring to FIG4B , LED module 510b of this embodiment is substantially the same as that of FIG4A , including a substrate 511, a first circuit layer 512, a plurality of light-emitting elements LED1-LED3, a second circuit layer 514, and a light shielding portion 515. The description of the relevant components and configurations can be found in the embodiment of FIG4A above and will not be repeated here.

[0154] The main difference between this embodiment and the embodiment shown in FIG. 4A is that the LED module 510b further includes a conductive extension 516. The conductive extension 516 is disposed within the opening OP corresponding to the light-emitting element LED2 and is electrically connected to the top electrode of the light-emitting element LED2. The height of the conductive extension 516 is less than or equal to the depth of the opening OP of the light-emitting element LED2, and the top electrode wire 5142 is electrically connected to the top electrode of the light-emitting element LED2 via the conductive extension 516.

[0155] Specifically, the light emitting element LED2 of this embodiment is in a configuration too low state (H2

[0156] ​It should be noted that the conductive extension 516 of this embodiment can be disposed only in the opening of the light emitting element that is too low in height, and other light emitting elements that can be directly connected to the upper electrode wire do not need a similar configuration.

[0157] Referring to FIG4C , the LED module 510c of this embodiment is substantially the same as that of the embodiment of FIG4A and FIG4B , and includes a substrate 511, a first circuit layer 512, a plurality of light-emitting elements LED1-LED3, a second circuit layer 514, and a light shielding portion 515. The description of the relevant components and configurations can be found in the aforementioned embodiments of FIG4A and FIG4B , and will not be repeated here.

[0158] The main difference between this embodiment and the embodiment of Figure 4B mentioned above is that the LED module 510c includes a plurality of conductive extension portions 5161-5163 corresponding to the light-emitting elements LED1-LED3, respectively, wherein the conductive extension portions 5161-5163 are respectively arranged in the openings OP of the light-emitting elements LED1-LED3 and are electrically connected to the upper electrodes of the corresponding light-emitting elements LED1-LED3.

[0159] In this embodiment, each conductive extension 5161-5163 completely fills the corresponding opening CP, so that the upper surface of the conductive extension 5161-5163 and the upper surface of the protective layer are substantially flush with each other. In other words, the height H1-H3 of each light-emitting element LED1-LED3 plus the height of the corresponding conductive extension 5161-5163 equals the height of the protective layer 513.

[0160] It should be noted that the conductive extensions 5161-5163 of this embodiment can be disposed within the opening OP of each light-emitting element LED1-LED3, so that the equivalent height of each light-emitting element LED1-LED3 is equal to the height of the protective layer 513. This allows the upper electrode wires 5141-5143 formed on the protective layer 513 to extend horizontally to connect to the conductive extensions 5161-5163, and to be electrically connected to the upper electrodes of the corresponding light-emitting elements LED1-LED3 through the conductive extensions 5161-5163. Therefore, the upper electrode wires 5141-5143 of this embodiment can maintain a uniform line width, achieving better electrical signal transmission characteristics.

[0161] Referring to FIG4D , LED module 510d of this embodiment is substantially the same as that of FIG4A , including a substrate 511, a first circuit layer 512, a plurality of light-emitting elements LED1-LED3, a second circuit layer 514, and a light shielding portion 515. The description of the relevant components and configurations can be found in the embodiment of FIG4A above and will not be repeated here.

[0162] The primary difference between this embodiment and the embodiment of FIG. 4A is that the protective layer 513 of the LED module 510d includes a spacer portion 5131 and a flattened portion 5132. The spacer portion 5131 is disposed on the substrate 511 and covers the first circuit layer 512, the bonding portion AD, and a portion of the light-emitting elements LED1-LED3. The flattened portion 5132 is disposed on the spacer portion, covering another portion of the light-emitting elements LED1-LED3 and exposing the top electrodes of the light-emitting elements LED1-LED3. In this embodiment, the combined height of the spacer portion 5131 and the flattened portion 5132 (i.e., the height of the protective layer 513) is configured to be greater than or equal to the maximum height of the light-emitting elements LED1-LED3, thereby forming an opening OP in at least one or a portion of the light-emitting elements LED1-LED3. The second circuit layer 512 is disposed on the flattened portion 5132 and is electrically connected to the light-emitting elements LED1-LED3 through the opening OP.

[0163] Specifically, compared to the embodiment shown in FIG4A , the protective layer 513 in this embodiment utilizes a two-layer structure. The lower layer (spacer 5131) primarily provides insulation and support, while the upper layer (flattening portion 5132) primarily provides a flat upper surface. The material used is removable using a specific manufacturing process, allowing the upper electrodes of the light-emitting elements LED1-LED3 to be exposed after the removal process. Therefore, the structural configuration shown in FIG4D further improves the surface flatness of the LED module 510d.

[0164] In some embodiments, the spacer 5131 can be made of a material with filling and insulating properties, such as SiNx, SiOx, acrylic, epoxy, or a silicon-based high molecular weight organic polymer, although the present disclosure is not limited thereto. Furthermore, the flattening portion 5132 can be made of a material with excellent surface flatness after coating, such as acrylic, epoxy, or a silicon-based high molecular weight organic polymer, although the present disclosure is also not limited thereto.

[0165] Referring to FIG. 4E , LED module 510e of this embodiment is substantially the same as that of the embodiments of FIG. 4B and FIG. 4D , and includes a substrate 511, a first circuit layer 512, a plurality of light-emitting elements LED1-LED3, a second circuit layer 514, a light shielding portion 515, and a conductive extension 516. The description of the relevant components and configurations can be found in the aforementioned embodiments of FIG. 4B and FIG. 4D , and will not be repeated here.

[0166] The main difference between this embodiment and the embodiment of Figure 4B is that the protective layer 513 of the LED module 510e adopts a double-layer structure configuration as shown in Figure 4D, which includes a spacing portion 5131 and a flat portion 5132. The relevant configuration and material description of the spacing portion 5131 and the flat portion 5132 can be referred to the embodiment of Figure 4D above and will not be repeated here.

[0167] Referring to Figure 4F , LED module 510f of this embodiment is substantially similar to the embodiments of Figures 4C and 4D , comprising a substrate 511, a first circuit layer 512, a plurality of light-emitting elements LED1-LED3, a second circuit layer 514, a light shielding portion 515, and a plurality of conductive extensions 5161-5163. The description of the relevant components and configurations can be found in the embodiments of Figures 4C and 4D above and will not be repeated here.

[0168] The main difference between this embodiment and the embodiment of Figure 4C is that the protective layer 513 of the LED module 510f adopts a double-layer structure configuration as shown in Figure 4D, which includes a spacing portion 5131 and a flat portion 5132. The relevant configuration and material description of the spacing portion 5131 and the flat portion 5132 can be referred to the embodiment of Figure 4D above and will not be repeated here.

[0169] Figure 4G is a schematic cross-sectional view of an LED module according to an embodiment of the present disclosure. Referring to Figure 4G , the LED module 610 according to this embodiment includes a substrate 611, a first circuit layer 612, a plurality of light-emitting elements LED1-LED3, a protective layer 613, a second circuit layer 614, a light shielding portion 615, and a support portion 616. The first circuit layer 612 is disposed on the substrate 611. The light-emitting elements LED1-LED3 are each disposed on the first circuit layer 612 via corresponding joints AD, such that the lower electrodes of the light-emitting elements LED1-LED3 are electrically connected to the first circuit layer 612 via the joints AD. A protective layer 613 is formed on the substrate 611 and covers the first wiring layer 612, the joint AD, and the surrounding areas of the light-emitting elements LED1-LED3. This layer prevents unintended short circuits between adjacent light-emitting elements LED1-LED3. The protective layer 613 exposes at least part or all of the top electrodes of the light-emitting elements LED1-LED3. The height / thickness of the protective layer 613 on the substrate 611 is substantially equal to the height HL of each light-emitting element LED1-LED3. The height HL of any light-emitting element LED1-LED3 referred to herein may be, for example, the sum of the height / thickness of any light-emitting element LED1-LED3 and its corresponding first wiring layer 612 and joint AD. A second wiring layer 614 and a light shielding portion 615 are disposed on the protective layer 613 and the top electrodes of the light-emitting elements LED1-LED3. The second wiring layer 614 is electrically connected to the top electrodes of each light-emitting element LED1-LED3. Furthermore, a support portion 616 is provided within the protective layer 613 between adjacent light-emitting elements LED1-LED3. The support portion 616 is used to provide support against forces applied to the light-emitting elements LED1-LED3 during the manufacturing process, thereby defining the position of the top electrodes of the light-emitting elements LED1-LED3. The top side of the support portion 616 and the top electrodes of the light-emitting elements LED1-LED3 are substantially coplanar. In this embodiment, the support portion 616 is, for example, cylindrical and has a height less than or equal to the lowest of the light-emitting elements LED1-LED3, but the present disclosure is not limited thereto.

[0170] More specifically, the first circuit layer 612 includes lower electrode conductors 6121-6123, and the second circuit layer 614 includes upper electrode conductors 6141-6143. The lower electrodes of the light-emitting elements LED1-LED3 are electrically connected to the lower electrode conductors 6121-6123 via corresponding joints AD. During the installation process, a planar force is applied to each light-emitting element LED1-LED3 toward the substrate 611 to embed the lower electrodes of the light-emitting elements LED1-LED3 into the joints AD. Due to differences in size / height, each light-emitting element LED1-LED3 has a different embedding depth in the joints AD, resulting in corresponding differences in the spacing between each light-emitting element LED1-LED3 and the substrate 611. For example, as shown in FIG4G , the height H1 of light-emitting element LED1 is greater than the height H2 of light-emitting element LED2. Therefore, when a force is applied, the distance between light-emitting element LED1 and substrate 611 becomes smaller than the distance between light-emitting element LED2 and substrate 611, so that the sum of the height H1 of light-emitting element LED1 and the corresponding distance between light-emitting element LED2 and substrate 611 is substantially equal to the sum of the height H2 of light-emitting element LED2 and the corresponding distance between light-emitting element LED2, i.e., equal to height HL. Similarly, the height H1 of light-emitting element LED1 is less than the height H3 of light-emitting element LED3. Therefore, when a force is applied, the distance between light-emitting element LED1 and substrate 611 becomes greater than the distance between light-emitting element LED3 and substrate 611, so that the sum of the height H1 of light-emitting element LED1 and the corresponding distance between light-emitting element LED3 and substrate 611 is substantially equal to the sum of the height H3 of light-emitting element LED3 and the corresponding distance between light-emitting element LED3 and substrate 611.

[0171] Through the above configuration, the light-emitting elements LED1-LED3 with different heights H1-H3 will have different substrate spacings, so that the total height HL corresponding to each light-emitting element LED1-LED3 is roughly the same, thereby forming a flat surface on the LED module. In this way, the poor connection described in Figure 3 will not occur due to the light-emitting element being in a configuration state that is too low (such as LED2) or too high (such as LED3). In addition, since the height differences H1-H3 of each light-emitting element LED1-LED3 have been compensated to the same height HL by the different substrate spacings, the electrode wires 6141-6143 can have a uniform line width as a whole. Therefore, the transmission of electrical signals can be guaranteed, and at the same time, the manufacturing process risks such as broken wires and poor contact caused by bending the wiring can be avoided.

[0172] In other words, through the structural configuration of FIG. 4G , the top surfaces of all light-emitting elements LED1 - LED3 can be maintained at substantially the same level without any height differences. Therefore, subsequent manufacturing processes will not be affected by the flatness of the LED module, thereby effectively improving the yield and reliability of the manufacturing process.

[0173] In this embodiment, the substrate 611 can be a soft or rigid substrate such as a printed circuit board, a glass substrate or a film substrate, and the substrate 611 can be transparent or opaque depending on the selected material and the required application type, but the present disclosure is not limited to this.

[0174] In some embodiments, the material of the bonding portion AD can be any material capable of providing adhesion to stably bond the light-emitting elements LED1-LED3 to the first circuit layer 612, such as solder paste, anisotropic conductive film (ACF), or other adhesive materials. Furthermore, the bonding process for attaching the light-emitting elements LED1-LED3 to the first circuit layer 612 via the bonding portion AD can be performed by screen printing, inkjet printing (IJP), or exposure, development, and baking, etc., although the present disclosure is not limited thereto.

[0175] 5A is a flowchart of a method for manufacturing an LED module according to an embodiment of the present disclosure. The method for manufacturing an LED module according to this embodiment can be applied to manufacturing the LED modules 501a-501f as shown in FIG. 4A to FIG. 4F. 5A , the manufacturing method of the LED module of this embodiment includes the following steps: forming a first circuit layer (such as 512) on a substrate (such as 511) (step S110); disposing a plurality of light-emitting elements (such as LED1-LED3) on the first circuit layer through a coupling portion (such as AD) so that the first electrode of each light-emitting element (such as the lower electrode of the light-emitting element) is electrically connected to the first circuit layer (step S120); forming a protective layer (such as 513) on the substrate to cover the light-emitting elements, wherein the thickness of the protective layer is greater than or equal to the light-emitting element with the largest height among the plurality of light-emitting elements (such as LED3) (step S130); removing the protective layer covering the second electrode of each light-emitting element (such as the upper electrode of the light-emitting element) to form an opening (such as OP) (step S140); and forming a second circuit layer (such as 514) on the protective layer, wherein the second circuit layer is electrically connected to the second electrode of each light-emitting element through the opening (step S150).

[0176] FIG5B is a flowchart of the steps of a method for manufacturing an LED module according to an embodiment of the present disclosure. The method for manufacturing an LED module according to this embodiment can be applied to manufacturing the LED module 610 described in FIG4G . Referring to FIG5B , the method for manufacturing an LED module according to this embodiment includes the following steps: forming a first circuit layer (e.g., 612) on a substrate (e.g., 611) (step S210); disposing a plurality of light-emitting elements (e.g., LED1-LED3) on the first circuit layer via a joint (e.g., AD) such that the first electrode (e.g., the lower electrode) of each light-emitting element is electrically connected to the first circuit layer (step S220); applying a force toward the substrate to at least partially embed the light-emitting element in the joint (step S230) so that the upper sides of the light-emitting elements are maintained in the same plane; filling the gaps between the light-emitting elements with an insulating material to form a protective layer (e.g., 613) (step S240); and forming a second circuit layer (e.g., 614) on the protective layer and the light-emitting elements, wherein the second circuit layer is electrically connected to the second electrode (e.g., the upper electrode) of each light-emitting element (step S250).

[0177] In some embodiments, the above-mentioned step S230 can be further implemented using the step flow of Figure 5C. Referring to Figure 5C, in this embodiment, after the step S220 of preliminarily setting the light-emitting element on the first circuit layer through the joint, the support portion (such as 616) will be set between adjacent light-emitting elements (step S232), and the environmental conditions are changed to make the joint portion change to a state that can be deformed in response to the force (such as liquid or molten state) (step S234). In the above-mentioned step S234, the method of changing the state of the joint portion can be, for example, heating the LED module, wherein the joint portion is, for example, solder paste. After heating, the solder paste will be in a molten state and can be deformed when pushed by the light-emitting element to make the light-emitting element move closer to the substrate. After the joint portion changes state, the pressure portion applies a planar force toward the substrate to the light-emitting element until the upper surface of each light-emitting element and the support portion are at the same height (step S236).

[0178] 6A to 6H illustrate the steps of manufacturing an LED module 510e having a structural configuration as shown in FIG4E based on the manufacturing method of FIG5A, and FIG7A to 7I illustrate the steps of manufacturing an LED module 510f having a structural configuration as shown in FIG4F based on the manufacturing method of FIG5A.

[0179] Please first refer to Figure 6A. In steps S110 and S120, the lower electrode wires 5121-5123 in the first circuit layer will be formed on the substrate 511, and the light-emitting elements LED1-LED3 will be respectively arranged on the corresponding lower electrode wires 5121-5123 of the first circuit layer 511 through the corresponding joints AD, so that the lower electrodes of the light-emitting elements LED1-LED3 and the lower electrode wires 5121-5123 are electrically connected.

[0180] In step S130, as shown in FIG6B , spacers 5131 in protective layer 513 are first formed on substrate 511, covering lower electrode leads 5121-5123, bonding portion AD, and portions of light-emitting elements LED1-LED3, while also filling the spaces between light-emitting elements LED1-LED3. Next, as shown in FIG6C , flattened portions 5132 in protective layer 513 are further formed on spacers 5131, covering light-emitting elements LED1-LED3. The thickness of protective layer 513 (i.e., the thickness of the spacers plus the thickness of the flattened portions) is greater than or equal to the highest light-emitting element LED1-LED3 (e.g., LED3).

[0181] In step S140, the flattened portion 5132 covering the upper electrodes of the light-emitting elements LED1-LED3 can be removed through a removal process (e.g., a yellow light photolithography process), thereby exposing the upper electrodes of the light-emitting elements LED1-LED3. In this embodiment, for example, in the extreme case where the electrodes of the light-emitting elements LED1-LED3 are unevenly positioned, the lower-lying light-emitting element LED2 may not be exposed even after the removal process due to the thicker flattened portion 5132 covering its electrode.

[0182] In this case, in step S140, further detection and removal of the remaining covering material can be performed, as shown in Figures 6E and 6F. The flat portion 5132r remaining on the upper electrode of the light-emitting element LED2 can be detected and removed in a targeted manner. For example, in some applications, automated optical inspection (AOI) equipment can be used to determine which positions of the upper electrode are not exposed through autofocus and depth of field algorithms. The laser can then be used to remove the remaining flat portion 5132 on the upper electrode to form a complete opening and expose the upper electrode of the lower-positioned light-emitting element LED2.

[0183] In step S150, since light-emitting element LED2 has been determined to be positioned lower, a conductive extension 516 electrically connected to the top electrode of light-emitting element LED2 is first formed within opening OP of light-emitting element LED2, as shown in FIG6G . Next, a second circuit layer 514 and a light-shielding portion 515 for connecting the top electrodes of light-emitting elements LED1-LED3 are formed on the flattened portion 5132. The top electrode conductors 5141-5143 of the second circuit layer 514 extend through the corresponding openings OP to connect to light-emitting elements LED1-LED3, electrically connecting the top electrodes of light-emitting elements LED1-LED3 to the corresponding top electrode conductors 5141-5143. Since light-emitting element LED2 is positioned lower, its top electrode conductor 5142 is electrically connected to the top electrode of light-emitting element LED2 via the conductive extension, as shown in FIG6H . This successfully completes the structural configuration of LED module 510e, as shown in FIG4E .

[0184] Based on the above description, those skilled in the art can also achieve the structural configurations of Figures 4A, 4B, and 4D by omitting certain steps in the aforementioned steps. For example, to produce LED module 510a as shown in Figure 4A, only the step of forming protective layer 513 needs to be implemented with a single-layer structure, and the step of forming conductive extension 516 in step S150 can be omitted. For another example, to produce LED module 510b as shown in Figure 4B, only the step of forming protective layer 513 needs to be implemented with a single-layer structure. For another example, to produce LED module 510d as shown in Figure 4D, only the step of forming conductive extension 516 in step S150 can be omitted.

[0185] 7A to 7I are further used below to illustrate the steps of manufacturing the LED module 510f shown in FIG. 4F , wherein FIG. 7A to 7F corresponding to steps S110 to S140 are similar to / identical to the aforementioned FIG. 6A to 6F , and therefore the relevant descriptions may refer to the aforementioned embodiment and will not be repeated here.

[0186] The main difference between this embodiment and the embodiment shown in Figures 6A to 6H is that after forming a structure with openings OP exposing the top electrode (as shown in Figure 7F ), in step S150, a conductive layer 517 is formed on the flat portion 5132. The conductive layer 517 completely fills the openings OP of each of the light-emitting elements LED1-LED3 and has a certain height above the flat portion 5132, as shown in Figure 7G . The conductive layer 517 can be made of, for example, a metal material.

[0187] Next, the conductive layer 517 will be removed through a surface cleaning process (such as a chemical / mechanical polishing process) to remove the portion of the conductive layer 517 located on the upper side of the flat portion 5132, thereby exposing the upper surface of the flat portion 5132; and the portion of the conductive layer 517 filled in the opening OP will be left and form the conductive extension portions 5161-5163 of the light-emitting elements LED1-LED3 respectively, as shown in Figure 7H.

[0188] Next, a second circuit layer 514 and a light shielding portion 515 for connecting the top electrodes of light-emitting elements LED1-LED3 are formed on the flattened portion 5132. The top electrode wires 5141-5143 of the second circuit layer 514 are connected to the light-emitting elements LED1-LED3 via corresponding conductive extensions 5161-5163, electrically connecting the top electrodes of the light-emitting elements LED1-LED3 to the corresponding top electrode wires 5141-5143, as shown in FIG7I . This successfully completes the structural configuration of the LED module 510f shown in FIG4F .

[0189] After the above description, those skilled in the art can also implement the structure of FIG4C by omitting certain steps in the above steps. For example, to manufacture the LED module 510c shown in FIG4C, only a single-layer structure is required in the step of forming the protective layer 513.

[0190] 8A to 8F are used to illustrate the steps of manufacturing the LED module 610 having the structure shown in FIG4G based on the manufacturing method of FIG5B and FIG5C.

[0191] Please first refer to Figure 8A. In steps S210 and S220, the lower electrode wires 6121-6123 in the first circuit layer 612 will be formed on the substrate 611, and the light-emitting elements LED1-LED3 will be respectively arranged on the corresponding lower electrode wires 6121-6123 of the first circuit layer 611 through the corresponding joints AD, so that the lower electrodes of the light-emitting elements LED1-LED3 and the lower electrode wires 6121-6123 are electrically connected.

[0192] In step S230, as shown in FIG8B , insulating material is first applied between the junctions AD. A spacer 6131 is formed on the substrate 611 to cover the lower electrode leads 6121-6123 and at least a portion of the junctions AD. In the current step, insulating material has not yet been applied between the light-emitting elements LED1-LED3. Next, a support portion 616 is positioned between adjacent light-emitting elements LED1-LED3 and on the spacer 6131. ​​The height of the support portion 616 is slightly less than the height H2 of the light-emitting element LED2. This ensures that, when subjected to an applied force, the light-emitting elements LED1-LED3 will displace toward the substrate 611, rather than being offset by the support portion 616 before the force reaches the lowest light-emitting element, LED2.

[0193] After the support portion 616 is set, the LED module will be heated to transform the state of the bonding portion into a molten bonding portion AD_mel, as shown in FIG8C . In some embodiments, the bonding portion AD is solder paste, and step S234 may be to place the LED module into a reaction chamber for vacuum treatment, and then heat the LED module under vacuum to reflow the solder paste. The pressure range of the above-mentioned vacuum treatment may be, for example, less than 100 Pa (pa), and the temperature of the above-mentioned heating may be, for example, 100°C to 300°C. The above-mentioned vacuum degree and temperature selection can ensure that the state of the bonding portion AD is transformed into a state that can respond to the applied force and deform without damaging the material / component properties.

[0194] Next, as shown in FIG8D , the pressurizing portion 617 is used to apply a force toward the substrate 611 to the light-emitting elements LED1-LED3, causing them to displace toward the substrate 611. During this force application, the molten bonding portion AD_mel is squeezed by the light-emitting elements LED1-LED3 and overflows outward. At this point, the support portion 616 acts as a barrier to prevent the bonding portion AD from short-circuiting with adjacent light-emitting elements / bonding portions. The pressurizing portion 617 continues to apply force toward the substrate 611 until it abuts the support portion 616 and the force is offset by the support portion 616, causing the light-emitting elements LED1-LED3 and the upper surface of the support portion to be approximately aligned (step S236 ). This means that the overall height of each light-emitting element LED1-LED3 is approximately equal to the height HL. In this embodiment, the pressurizing portion 617 can be made of a relatively rigid and non-deformable material, such as glass or metal, and can be a flat plate with a smooth surface, but the present disclosure is not limited thereto.

[0195] After completing step S230, the pressurizing portion 617 is removed, and the LED module is left to rest to allow the joint AD to return to its original state. Next, in step S240, insulating material is further filled into the gaps between the light-emitting elements LED1-LED3 and the support portion 616, thereby forming a protective layer 613 together with the insulating material previously used as the spacer. The upper surface of the protective layer 613 is also substantially flush with the light-emitting elements LED1-LED3 and the support portion 616, thereby forming a flat module surface SUF, as shown in FIG8E .

[0196] Next, a second circuit layer 614 and a light shield 615 for connecting the upper electrodes of light-emitting elements LED1-LED3 are formed on the module surface SUF. The upper electrode wires 6141-6143 of the second circuit layer 614 are electrically connected to the light-emitting elements LED1-LED3, as shown in FIG8F . This successfully completes the structure of the LED module 610 shown in FIG4G .

[0197] It should be noted that the aforementioned configuration may apply only to a portion of the LED module or to the entire module. In other words, any LED module having at least a portion of its light-emitting elements conforming to the aforementioned configuration or manufactured using the aforementioned method is within the scope of this disclosure and intended to be protected.

[0198] The following further describes the structural design of the display panel portion of the display device 10 / 30.

[0199] In some embodiments, the structure of the thin film transistor described in the embodiments of FIG. 1C and FIG. 1D may be configured as shown in FIG. 9 , which is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present disclosure. Referring to FIG. 9 , the thin film transistor 1120 includes a gate 1121, an insulating layer 1122, an active layer 1123, a source electrode 1124S, and a drain electrode 1124D. The gate 1121, the insulating layer 1122, and the active layer 1123 are stacked in sequence from bottom to top (based on the direction shown in the figure), wherein the source electrode 1124S and the drain electrode 1124D are formed at both ends of the active layer 1123, respectively, and the middle region of the active layer 1123 is etched to form a channel region CHA.

[0200] The gate 1121, source 1124S, and drain 1124D may be formed of a metal such as molybdenum (Mo), aluminum (Al), titanium (Ti), copper (Cu), or a stacked combination of these metals, but the present disclosure is not limited thereto. The insulating layer 1122 may be a non-metallic dielectric material such as silicon dioxide (SiOx), silicon nitride (SiNx), or a stacked combination of these materials, but the present disclosure is also not limited thereto.

[0201] The active layer 1123 of this embodiment has a three-layer stacked structure at both ends, including a first semiconductor material layer 1123f, a second semiconductor material layer 1123s, and a third semiconductor material layer 1123t stacked in order from bottom to top. The first semiconductor material layer 1123f is formed on the insulating layer 1122 and has an ordered lattice structure, such as microcrystalline silicon or polycrystalline silicon. The second semiconductor material layer 1123s is formed on the first semiconductor material layer 1123f and has a disordered lattice structure, such as amorphous silicon (a-Si). The third semiconductor material layer 1123t is formed on both sides of the second semiconductor material layer 1123s, wherein the third semiconductor material layer 1123t has a disordered lattice structure and is doped with N-type ions. In other words, at both ends of the active layer 1123 , the second semiconductor material layer 1123 s and the third semiconductor material layer 1123 t may both be made of amorphous silicon, the difference being that the N-type ion concentration of the third semiconductor material layer 1123 t is higher than that of the second semiconductor material layer 1123 s .

[0202] On the other hand, the thickness of the active layer 1123 within the channel region CHA is thinner than the thickness outside the channel region CHA (i.e., at both ends). Furthermore, the active layer 1123 within the channel region CHA is etched to remove the third semiconductor material layer 1123t, thereby exposing the second semiconductor material layer 1123s. In other words, only a two-layer structure of the first semiconductor material layer 1123f and the second semiconductor material layer 1123s exists within the channel region CHA.

[0203] The thin film transistor 1120 having the active layer 1123 formed by the first to third semiconductor material layers 1123f-1123t has a higher carrier mobility than the conventional amorphous silicon thin film transistor. Under the structure of this embodiment, the carrier mobility can be increased to 6-8cm 2 / V×SM; In some embodiments, when the drain-source voltage is 10V, the on-state current can reach 10 -5 A, which is more than 10 times that of traditional amorphous silicon thin-film transistors.

[0204] In addition, in this embodiment, most of the native semiconductor oxide (e.g., SiOx) between the first semiconductor material layer 1123f and the second semiconductor material layer 1123s is removed, so that substantially no semiconductor oxide exists at the interface between the first semiconductor material layer 1123f and the second semiconductor material layer 1123s. Therefore, the first semiconductor material layer 1123f and the second semiconductor material layer 1123s can be well bonded without the problem of film peeling, and the device characteristics of the thin film transistor 1120, such as carrier mobility and on / off ratio, can be effectively improved.

[0205] It should be noted here that although the carrier mobility of the thin film transistor 1120 is significantly improved compared to the traditional amorphous silicon thin film transistor, the critical voltage may be relatively low. In some embodiments, in order to further optimize the electrical properties of the thin film transistor 1120, the first semiconductor material layer 1123f can also be doped with 3A group ions (i.e., boron group) by ion implantation during the manufacturing process, wherein the doped 3A group ions will form covalent bonds with the semiconductor material in the first semiconductor material layer 1123f to provide holes, so that the current-voltage characteristic curve of the thin film transistor moves to the right, thereby increasing the critical voltage and effectively improving the problem of low critical voltage. In some embodiments, the ion concentration of the 3A group ions injected into the first semiconductor material layer 1123f can be between 10 12 ~10 13 ions / cm 3 In the embodiment of implanting boron ions, the ion concentration may be, for example, 2×10 12 , 4×10 12 or 6×10 12 , and the injection energy is, for example, 10 to 20 keV, and the cavity is, for example, at room temperature, but the present disclosure is not limited thereto.

[0206] In addition, the thin film transistor having the structure of FIG9 generally has a leakage current (Ioff) that may be higher than that of a conventional amorphous silicon thin film transistor because the sidewalls of the active layer have more broken links and carriers after etching. In the case of high leakage current, a display using the thin film transistor may have problems such as poor contrast, whitening, and flickering when displaying images. In some embodiments, in order to further optimize the electrical properties of the thin film transistor 1120, the active layer 1123 may be subjected to a carrier removal process during formation to reduce the number of free ions on the sidewalls of the active layer 1123, thereby reducing the leakage current at the sidewalls.

[0207] The source electrode 1124S and the drain electrode 1124D are respectively formed on both ends of the active layer 1123 and extend from the side surfaces of the active layer 1123 to cover a portion of the insulating layer 1122. More specifically, the source electrode 1124S and the drain electrode 1124D respectively contact the top of the third semiconductor material layer 1123t (i.e., the side away from the second semiconductor material layer 1123s) and the sidewalls of the first semiconductor material layer 1123f, the second semiconductor material layer 1123s, and the third semiconductor material layer 1123t (i.e., the side of the active layer 1123 away from the channel region CHA), and extend through the sidewalls to contact the top of the insulating layer 1122 (i.e., the side away from the gate 1121).

[0208] In some embodiments, the thin film transistor 1120 may further include a functional layer 1125 covering the surface of the device, wherein the functional layer 1125 may be formed, for example, on the source electrode 1124S, the drain electrode 1124D, and a portion or all of the exposed surface of the active layer 1123. In some embodiments, the functional layer 1125 may be a protective film made of silicon nitride (SiN), for example, but the present disclosure is not limited thereto.

[0209] It should also be noted that because the signal transmission impedance between the source 1124S and the drain 1124D of the thin-film transistor 1120 is relatively large, when a low voltage (e.g., less than 1V) is applied to the drain-source, the on-current of the thin-film transistor 1120 may be lower than that of a traditional amorphous silicon thin-film transistor. In other words, when the drain-source voltage (Vds) of the thin-film transistor 1120 is low, its on-off ratio may be lower than that of a traditional amorphous silicon thin-film transistor.

[0210] In some embodiments, by adjusting the thickness ratio of the second semiconductor material layer 1123s to the third semiconductor material layer 1123t during the manufacturing process, the problem of low drain-source on-state current at low voltage can be improved. For example, when the total thickness of the second semiconductor material layer 1123s and the third semiconductor material layer 1123t is fixed, their thickness ratio can be between 5:8 and 8:5.

[0211] In some embodiments, the total thickness of the second semiconductor material layer 1123s and the third semiconductor material layer 1123t is approximately The thickness of the second semiconductor material layer 1123s is and In the case of and This allows the on-state current to be maintained even at low source-drain voltages. This section will be further explained with experimental results.

[0212] FIG10A is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. The method of FIG10A can be used to manufacture the thin film transistor 1120 described in the embodiment of FIG9 . The manufacturing process of the thin film transistor 1120 is described below with reference to FIG11A to FIG11F , wherein FIG11A to FIG11F are schematic flow charts of the method for manufacturing the thin film transistor according to FIG10A .

[0213] 10A and 11A , first, a first metal layer 1121 and an insulating layer 1122 covering the first metal layer 1121 are formed on a substrate SUB (step S310 ), wherein the first metal layer 1121 is used as a gate of a thin film transistor 1120 .

[0214] Next, please refer to Figures 10A, 11B and 11C, an amorphous semiconductor film NSTF is formed on the insulating layer 1122 (step S320), and the amorphous semiconductor film NSTF is heat-treated to convert the amorphous semiconductor film NSTF into a first semiconductor material layer 1123f having an ordered lattice structure (step S330).

[0215] In some embodiments, the non-crystalline semiconductor thin film NSTF is, for example, amorphous silicon. The heat treatment may be, for example, an excimer laser annealing (ELA) technique in which an excimer laser is irradiated on the amorphous silicon to transform the amorphous silicon into microcrystalline silicon or polycrystalline silicon (i.e., the first semiconductor material layer 1123f) having an orderly lattice structure, but the present disclosure is not limited thereto.

[0216] After the amorphous semiconductor film NSTF is converted into the first semiconductor material layer 1123f, this embodiment further performs an interface cleaning process on the first semiconductor material layer 1123f to remove the native semiconductor oxide SO on the surface of the first semiconductor material layer 1123f (step S340).

[0217] In some embodiments, the interface cleaning process may be performed using a surface treatment process such as wet etching (e.g., chemical treatment) or dry etching (e.g., plasma treatment). In the case of wet etching, the interface cleaning process may be performed using a chemical solution that is corrosive to the semiconductor oxide SO, such as a diluted buffered oxide etchant (BOE), diluted hydrofluoric acid (HF), or a mixture of hydrofluoric acid and ammonium fluoride (NH4F), but the present disclosure is not limited thereto.

[0218] In the embodiment of using a corrosive chemical solution for interface cleaning, the chemical solution can be diluted to an etching rate of 5 to 10% for semiconductor oxide SO. The interface cleaning process is performed for 5 to 30 seconds to prevent corrosion of the insulating layer 1122 and / or the first semiconductor material layer 1123f while removing the semiconductor oxide SO. In some embodiments, if the chemical solution is HF or BOE, the dilution concentration may be, for example, 1% to 2%, but the present disclosure is not limited thereto.

[0219] 10A and 11D , after the interface cleaning process is completed, a second semiconductor material layer 1123s and a third semiconductor material layer 1123t are formed on the first semiconductor material layer 1123f (step S350 ). The first to third semiconductor material layers 1123f to 1123t stacked in sequence from bottom to top constitute the active layer 1123 of the thin film transistor 1120. In this embodiment, the second semiconductor material layer 1123s is composed of amorphous silicon, for example, and the third semiconductor material layer 1123t is composed of n-doped amorphous silicon, for example, but the present disclosure is not limited thereto.

[0220] In some embodiments, to ensure that the semiconductor oxide SO removed in step S340 does not regenerate during the manufacturing process, the time interval between step S340 and step S350 needs to be set to less than 1 hour. In other words, the steps of forming the second and third semiconductor material layers 1123s-1123t need to be performed within one hour after the interface cleaning process is completed.

[0221] In some embodiments, the second semiconductor material layer 1123s is formed to a thickness between to and the third semiconductor material layer 1123t is formed with a corresponding thickness so that the total thickness of the second semiconductor material layer 1123s and the third semiconductor material layer 1123t is approximately between to In some preferred embodiments, the second semiconductor material layer 1123s is formed to a thickness between to and the third semiconductor material layer 1123t is formed with a corresponding thickness so that the total thickness of the second semiconductor material layer 1123s and the third semiconductor material layer 1123t is approximately However, the present disclosure is not limited thereto.

[0222] 10A and 11E , after the active layer 1123 is formed, the active layer 1123 may be patterned, and a second metal layer 1124 may be formed on the patterned active layer 1123 (step S360 ).

[0223] Please refer to Figures 10A and 11F. After the second metal layer 1124 is formed, the element is etched to expose the second semiconductor material layer 1123s of the channel region CHA, and the second metal layer 1124 is separated into two left and right parts by the channel region CHA (step S370), wherein the second metal layer 1124 on the left side serves as the source 1124S of the thin film transistor 1120, and the second metal layer 1124 on the right side serves as the drain 1124D of the thin film transistor 1120.

[0224] In some embodiments, after step S370 , a functional layer 1125 covering the source 1124S, the drain 1124D and the channel region CHA may be further formed on the device according to design or device requirements.

[0225] FIG10B is a flowchart of a method for manufacturing a thin film transistor according to another embodiment of the present disclosure. The method of FIG10B can be used to manufacture the thin film transistor 1120 described in the embodiment of FIG9 . The manufacturing process of the thin film transistor 1120 is described below with reference to FIG12A to FIG12F , wherein FIG12A to FIG12F are schematic flow charts of the method for manufacturing the thin film transistor according to FIG10B .

[0226] 10B and 12A , first, a first metal layer 1121 and an insulating layer 1122 covering the first metal layer 1121 are formed on a substrate SUB (step S410 ), wherein the first metal layer 1121 is used as a gate of a thin film transistor 1120 .

[0227] 10B and 12B , an amorphous semiconductor film NSTF is formed on the insulating layer 1122 (step S420 ), and ion implantation is performed on the amorphous semiconductor film NSTF (step S430 ) to implant Group 3A ions into the amorphous semiconductor film NSTF.

[0228] Next, referring to FIG. 10B and FIG. 12C , the amorphous semiconductor film NSTF implanted with the Group 3A ions is thermally treated to convert the amorphous semiconductor film NSTF into the first semiconductor material layer 1123 f (step S440 ).

[0229] In other words, the manufacturing method of this embodiment is mainly different from the embodiment of FIG. 10A before heat treatment in that this embodiment performs ion implantation step S430 to dope Group 3A ions into the amorphous semiconductor film NSTF.

[0230] In some embodiments, the non-crystalline semiconductor film NSTF is, for example, amorphous silicon, and the implanted material into the non-crystalline semiconductor film NSTF may be, for example, boron ions (B+). The heat treatment may be, for example, excimer laser annealing (ELA) of amorphous silicon doped with boron ions by irradiating an excimer laser to transform the amorphous silicon into microcrystalline silicon or polycrystalline silicon (i.e., the first semiconductor material layer 1123f) having an ordered lattice structure, but the present disclosure is not limited thereto.

[0231] 10B and 12D , after the heat treatment is completed, a second semiconductor material layer 1123s and a third semiconductor material layer 1123t are formed on the first semiconductor material layer 1123f (step S450 ). The first to third semiconductor material layers 1123f to 1123t, stacked sequentially from bottom to top, constitute the active layer 1123 of the thin film transistor 1120. In this embodiment, the second semiconductor material layer 1123s is, for example, composed of amorphous silicon, and the third semiconductor material layer 1123t is, for example, composed of n-doped amorphous silicon, but the present disclosure is not limited thereto.

[0232] 10B and 12E , after the active layer 1123 is formed, the active layer 1123 may be patterned, and a second metal layer 1124 may be formed on the patterned active layer 1123 (step S460 ).

[0233] Please refer to Figures 10B and 12F. After the second metal layer 1124 is formed, the element is etched to expose the second semiconductor material layer 1123s of the channel region CHA, and the second metal layer 1124 is separated into two left and right parts by the channel region CHA (step S470), wherein the second metal layer 1124 on the left side serves as the source 1124S of the thin film transistor 1120, and the second metal layer 1124 on the right side serves as the drain 1124D of the thin film transistor 1120.

[0234] In some embodiments, after step S470 , a functional layer 1125 covering the source 1124S, the drain 1124D and the channel region CHA may be further formed on the device according to design or device requirements.

[0235] Compared to the traditional thin film transistor manufacturing process, the purpose of step S430 in this embodiment is to adjust the critical voltage value rather than to be used as a region for configuring the source / drain. Therefore, the concentration of the injected / doped ions does not need to be too high, and there is no need to perform a rapid thermal annealing (RTA) process on the first semiconductor layer 1123f again to activate the ions, which effectively simplifies the complexity of the manufacturing process.

[0236] FIG10C is a flowchart of a method for manufacturing a thin film transistor according to another embodiment of the present disclosure. The method of FIG10C can be used to manufacture the thin film transistor 1120 described in the embodiment of FIG9 . The manufacturing process of the thin film transistor 1120 is described below with reference to FIG13A to FIG13F , wherein FIG13A to FIG13F are schematic flow charts of the method for manufacturing the thin film transistor according to FIG10C .

[0237] 10C , 13A , and 13B , first, a first metal layer 1121 and an insulating layer 1122 covering the first metal layer 1121 are formed on a substrate SUB (step S510), wherein the first metal layer 1121 is used as a gate of a thin film transistor 1120. Next, an amorphous semiconductor thin film NSTF is formed on the insulating layer 1122 (step S520), and the amorphous semiconductor thin film NSTF is heat-treated to convert the amorphous semiconductor thin film NSTF into a first semiconductor material layer 1123f having an orderly lattice structure (step S530).

[0238] In some embodiments, the non-crystalline semiconductor thin film NSTF is, for example, amorphous silicon. The heat treatment may be, for example, an excimer laser annealing (ELA) technique in which an excimer laser is irradiated on the amorphous silicon to transform the amorphous silicon into microcrystalline silicon or polycrystalline silicon (i.e., the first semiconductor material layer 1123f) having an ordered lattice structure, but the present disclosure is not limited thereto.

[0239] 10C and 13C , after the heat treatment is completed, a second semiconductor material layer 1123s and a third semiconductor material layer 1123t are formed on the first semiconductor material layer 1123f (step S540 ). The first to third semiconductor material layers 1123f to 1123t stacked sequentially from bottom to top constitute the active layer 1123 of the thin film transistor 1120. In this embodiment, the second semiconductor material layer 1123s is composed of amorphous silicon, for example, and the third semiconductor material layer 1123t is composed of n-doped amorphous silicon, for example, but the present disclosure is not limited thereto.

[0240] 10C and 13D , after the active layer 1123 is formed, a carrier removal process may be performed on the active layer 1123 (step S550 ).

[0241] In some embodiments, the carrier removal step S550 may include, for example, first patterning the active layer 1123 to form sidewalls SW of the active layer 1123. The sidewalls SW may be formed, for example, by uniformly continuous surfaces of the first semiconductor material layer 1123f, the second semiconductor material layer 1123s, and the third semiconductor material layer 1123t. After the patterning is completed, the sidewalls SW of the patterned active layer 1123 are further subjected to over-etching or ion implantation to reduce carrier generation on the sidewalls SW of the active layer 1123.

[0242] In some embodiments, the normal direction of the sidewall SW is not parallel to the normal direction of the substrate SUB; in some embodiments, the angle between the normal direction of the sidewall SW and the normal direction of the substrate SUB is less than 45 degrees, but the present disclosure is not limited thereto.

[0243] In some embodiments, after the patterning process is completed, the carrier removal process step S550 may further include an oxidation process for the sidewall SW, wherein the oxidation process may be performed by introducing oxygen gas, and by properly controlling the time of introducing oxygen gas, a uniform and thin silicon oxide layer is formed on the surface of the sidewall SW, thereby further reducing the leakage current at the sidewall SW. In some embodiments, the thickness of the silicon oxide layer formed on the surface of the sidewall SW may be, for example, between to However, the present disclosure is not limited thereto.

[0244] 10C and 13E , after the active layer 1123 is formed, the active layer 1123 may be patterned, and a second metal layer 1124 may be formed on the patterned active layer 1123 (step S560 ).

[0245] Please refer to Figures 10C and 13F. After the second metal layer 1124 is formed, the element is etched to expose the second semiconductor material layer 1123s of the channel region CHA, and the second metal layer 1124 is separated into two left and right parts by the channel region CHA (step S570), wherein the second metal layer 1124 on the left side serves as the source 1124S of the thin film transistor 1120, and the second metal layer 1124 on the right side serves as the drain 1124D of the thin film transistor 1120.

[0246] In some embodiments, after step S570 , a functional layer 1125 covering the source 1124S, the drain 1124D and the channel region CHA may be further formed on the device according to design or device requirements.

[0247] Compared with the conventional thin film transistor manufacturing process, the purpose of step S550 in this embodiment is to reduce the number of carriers at the sidewall SW of the active layer 1123, thereby effectively reducing the leakage current of the thin film transistor 1120, thereby effectively improving the on / off ratio of the thin film transistor 1120.

[0248] Specifically, in the embodiment of step S550, if a process of patterning followed by over-etching is adopted, the total etching time of the patterning process plus the over-etching process may be, for example, 60 seconds to 130 seconds, but the present disclosure is not limited thereto.

[0249] It should be noted that in the above-mentioned process of performing over-etching after patterning, the over-etching step can be achieved by extending the etching time of the patterning process. In other words, from the perspective of actual manufacturing process, the patterning process and the over-etching process can be a continuous process that cannot be clearly distinguished. The focus of the over-etching process is to further etch the sidewalls SW after completing the patterning of the active layer 1123 to reduce the number of carriers. This effect is achieved by appropriately extending the etching time. Therefore, although it may not be possible to actually distinguish the difference in the step process from the appearance, the extended etching time can be used to determine whether the over-etching process is performed.

[0250] In some embodiments, if the carrier removal process step S550 is a process of first patterning the active layer 1123 to form a side wall SW in the active layer 1123, and then performing ion implantation on the side wall SW, the ion implantation can be, for example, implanting 3A group ions (such as boron ions) with a light dose and light energy, so that the 3A group ions provide holes in the active layer 2 to obtain free electrons, thereby reducing the leakage current at the side wall SW.

[0251] In some embodiments, during the process of ion implantation into the sidewall SW, the implanted ion concentration may be between 5×10 12 ~5×10 13 ions / cm 3 The implantation energy may be, for example, 10-20 keV and performed in a room temperature chamber, but the present disclosure is not limited thereto.

[0252] FIG10D is a flow chart of a method for manufacturing a thin film transistor according to another embodiment of the present disclosure, wherein the manufacturing method of FIG10D can be used to manufacture the thin film transistor 1120 as described in the embodiment of FIG9 .

[0253] Referring to FIG10D , this embodiment is substantially the same as the embodiment of FIG10A and / or FIG10B . The difference between this embodiment and FIG10A is that, before performing the heat treatment step S640, this embodiment further performs the ion implantation process described in step S430 of FIG10B , thereby doping the first semiconductor material layer with Group 3A ions. From another perspective, the difference between this embodiment and FIG10B is that, after performing the heat treatment step S640, this embodiment further performs the interface cleaning process step S650 described in step S340 of FIG10A , thereby removing the native semiconductor oxide on the first semiconductor material layer.

[0254] In addition, the relevant description of step S610 of this embodiment can refer to step S310 of Figure 10A and step S410 of Figure 10B, the relevant description of step S620 of this embodiment can refer to step S320 of Figure 10A and step S420 of Figure 10B, the relevant description of step S630 of this embodiment can refer to step S430 of Figure 10B, the relevant description of step S640 of this embodiment can refer to step S330 of Figure 10A and step S440 of Figure 10B, the relevant description of step S650 of this embodiment can refer to step S340 of Figure 10A, and the relevant description of steps S660 to S680 of this embodiment can refer to steps S350 to S370 of Figure 10A and steps S450 to S470 of Figure 10B, so the repeated parts will not be repeated here.

[0255] More specifically, compared to the manufacturing method process of Figures 10A and 10B mentioned above, this embodiment not only performs an ion implantation process (step S630) to improve the critical voltage characteristics, but also further performs an interface cleaning treatment (step S650) on the amorphous semiconductor film (NSTF) doped with 3A group ions after converting it into a polycrystalline or microcrystalline first semiconductor material layer (1123f) to improve the bonding strength between the first semiconductor material layer and the second semiconductor material layer, so that the overall device characteristics of the thin film transistor are better.

[0256] FIG10E is a flow chart of a method for manufacturing a thin film transistor according to another embodiment of the present disclosure, wherein the method of FIG10E can be used to manufacture the thin film transistor 1120 as described in the embodiment of FIG9 .

[0257] Please refer to Figure 10E. This embodiment is substantially the same as the embodiment of Figure 10D described above. The difference between this embodiment and the embodiment of Figure 10D is that, before forming the second metal layer in step S780, this embodiment further performs a carrier removal process as described in step S550 of Figure 10C, thereby reducing the number of carriers on the sidewalls of the active layer.

[0258] In addition, the relevant descriptions of steps S710-S760 of this embodiment can refer to steps S610-S660 of the aforementioned Figure 10D, the relevant descriptions of step S770 of this embodiment can refer to step S550 of the aforementioned Figure 10C, and the relevant descriptions of steps S780 and S790 of this embodiment can refer to steps S670 and S680 of the aforementioned Figure 10C, so the repeated parts will not be repeated here.

[0259] More specifically, compared to the manufacturing method process of Figure 10C above, this embodiment further performs carrier removal processing on the side walls of the active layer after patterning the active layer (step S770) to reduce the number of carriers at the side walls of the active layer, thereby reducing the leakage current of the thin film transistor and further improving the switching ratio.

[0260] FIG14 is an SEM photograph of a thin film transistor manufactured according to the manufacturing method of an embodiment of the present disclosure and a comparative example. Referring to FIG14 , the comparative example on the left is a thin film transistor manufactured using a preparation process that does not include step S340 of the interface cleaning process, and includes a gate electrode 2121, an insulating layer 2122, and an active layer consisting of a first semiconductor layer to a third semiconductor layer 2123f-2123t. From the experimental comparison results, it can be seen that the thin film transistor manufactured using the manufacturing method of FIG10A does not have any film peeling between the first semiconductor material layer 1123f and the second semiconductor material layer 1123s compared to the comparative example.

[0261] FIG15 is a schematic diagram showing the on-state current of thin-film transistors of an experimental example and a comparative example manufactured according to the manufacturing method of an embodiment of the present disclosure. Referring to FIG15 , the experimental results show that the on-off ratio of the thin-film transistor of the experimental example manufactured using the process flow of FIG10A is significantly higher than the on-off ratio of the comparative example that did not undergo the interface cleaning process (step S340).

[0262] In addition, in some experimental examples, the carrier mobility of the thin film transistor manufactured by the step process of FIG10A can reach 11.12 cm 2 / V×S. In contrast, in the comparative example without the interface cleaning process (step S340), the carrier mobility may be affected by the defects and is only about 1.29 cm 2 / V×S.

[0263] FIG16 is a current-voltage characteristic curve of a thin film transistor manufactured according to the manufacturing method of an embodiment of the present disclosure at different ion implantation concentrations. As can be seen from the characteristic curve of FIG16, the critical voltage of the thin film transistor increases as the concentration of the 3A group ions implanted in step S430 / S530 of the above-mentioned manufacturing method increases. In summary, the thin film transistor, pixel array substrate, display device and manufacturing method thereof proposed in the embodiment of the present disclosure can be processed through a specific interface cleaning process in the manufacturing process of the thin film transistor, so that there is substantially no semiconductor oxide that is prone to causing bonding defects between the microcrystalline or polycrystalline silicon layer (such as the first semiconductor material layer) and the amorphous silicon layer (such as the second semiconductor material layer) in the active layer. This allows the various thin films in the active layer to be well bonded without the problem of film peeling, and effectively improves the carrier mobility and switching ratio of the thin film transistor 1120. In addition, the embodiment of the present disclosure also proposes to increase the critical voltage of the thin film transistor by ion implanting the active layer before the heat treatment step, so that the finished product can have better device characteristics.

[0264] FIG17 shows the current-voltage characteristic curves of the active layer of the thin film transistor manufactured according to the manufacturing method of the embodiment of the present disclosure at different thicknesses, wherein FIG16 shows the relative relationship between the on-state current and the gate voltage under the condition of applying a drain-source voltage of 0.5V for the active layer in four different thickness combinations (a) to (d). It can be seen from the characteristic curves of FIG16 that when the total thickness of the second semiconductor material layer 1123s and the third semiconductor material layer 1123t is fixed at In the case of (Combination (d)) dropped to (Combination (a)) and the thickness of the third semiconductor material layer 1123t corresponds to Rise to Therefore, the above experimental results show that even at a low voltage of 0.5V for drain-source voltage, the on-current can still reach about 10 -6 A, and the cut-off current will not be significantly affected, so the switching ratio can be effectively improved.

[0265] Figure 18 shows the current-voltage characteristic curves of a thin-film transistor fabricated through a carrier removal process and a comparative example. The carrier removal process is performed using a patterning process, an overetching process, and an oxidation process. Referring to Figure 18 , the experimental comparison results show that the thin-film transistor fabricated through the carrier removal process (step S550) exhibits significantly better off-current (Ioff) characteristics, i.e., lower leakage current, than the comparative example (which does not utilize step S550).

[0266] Figure 19 shows the current-voltage characteristic curves of a thin-film transistor fabricated through a carrier removal process, which utilizes a patterning and ion implantation process, and a comparative example. Referring to Figure 19 , the experimental comparison results show that the thin-film transistor fabricated through the carrier removal process (step S550) exhibits significantly better off-current characteristics than the comparative example (which does not utilize step S550).

[0267] The following further describes the design of the backlight module in the display device 10 / 30.

[0268] 20A to 20C are schematic diagrams of the structural configurations of backlight modules according to different embodiments of the present disclosure, wherein FIG. 20A is a structural configuration of a direct-lit backlight module 100a, and FIG. 20B and FIG. 20C are structural configurations of side-lit backlight modules 100b and 100c.

[0269] Referring first to Figure 20A , the backlight module 100a includes a light-emitting portion 110a and an optical adjustment layer 130a. The optical adjustment layer 130a includes a light guide plate 131a, a diffuser plate 132, and a reflector plate 133. In this embodiment, the diffuser plate 132, the light guide plate 131a, the light-emitting portion 110a, and the reflector plate 133 are arranged in order along the z-axis from the side closest to the display panel 100' to the side farthest from the display panel 100', and each component is substantially parallel to one another. In other words, in the backlight module 100a, the diffuser plate 132 is closest to the display panel 100', and the reflector plate 133 is farthest from the display panel 100'. With the display panel 100' positioned at the top, the light-emitting portion 110a can be considered to be positioned above the reflector plate 133, the light guide plate 131a is positioned above the light-emitting portion 110a, and the diffuser plate 132 is positioned above the light guide plate 131a.

[0270] In some embodiments, the optical adjustment layer 130a may further include a light enhancement plate 134, wherein the light enhancement plate 134 is disposed on the upper side of the diffuser plate 132, that is, between the display panel 100' and the diffuser plate 132. In other words, in embodiments having the light enhancement plate 134, the component of the backlight module 100a closest to the display panel 100' may be the light enhancement plate 134. However, the present disclosure is not limited to this.

[0271] Specifically, the light guide plate 131a is used to transmit the light provided by the light emitting portion 110a through the optical effects of refraction and / or reflection so that the light can be evenly emitted from the light emitting surface of the light guide plate 131a. In other words, after the light provided by the light emitting portion 110a passes through the light guide plate 131a, the light emitted toward the display panel 100' can be more evenly emitted to each area of ​​the display panel 100' compared to when there is no light guide plate 131a. In the present embodiment, the light emitting surface of the light guide plate 131a is the surface close to the side of the display panel 100'; and the light incident surface of the light guide plate 131a is located on the other side opposite to the light emitting surface, that is, the surface close to the side of the light emitting portion 110a. In other words, the backlight module 100a of the present embodiment is of a direct-down configuration.

[0272] The light guide plate 131a of this embodiment may be made of any transparent material, such as glass or plastic material (such as PMMA, MS, PS, etc.), wherein the light guide plate 131a may include a plurality of optical microstructures, but the present disclosure is not limited thereto.

[0273] The diffuser plate 132 is used to diffuse and refract the received light, further dispersing it and evenly distributing it throughout the display panel 100'. In this embodiment, one side of the diffuser plate 132 is positioned on the light-emitting surface of the light guide plate 131a, while the other side is positioned relative to the display panel 100'. This allows the light emitted from the light-emitting surface of the light guide plate 131a to pass through the diffuser plate 132 and be further evenly distributed throughout each area of ​​the display panel 100'.

[0274] The diffuser plate 132 of this embodiment can be made of a plastic sheet or other transparent material with a roughened surface, but the present disclosure is not limited thereto. The diffuser plate 132 can be connected / assembled with the light guide plate 131a by gluing or other bonding methods, but the present disclosure is not limited thereto.

[0275] The reflector 133 is used to optically reflect received light, allowing light not directed toward the display panel 100' to be directed toward the display panel 100', thereby improving the light source utilization efficiency of the light-emitting portion 110a. In this embodiment, the light-emitting portion 110a is disposed on the reflective surface of the reflector 133. Part of the light emitted by the light-emitting portion 110a through the light guide plate 131a is emitted in a direction non-parallel to the z-axis (i.e., not toward the display panel 100').

[0276] The reflector 133 of this embodiment can be made of aluminum foil or a reflective material with a metal coating. The reflector 133 can be connected / assembled to the light guide plate 131a by gluing or other bonding methods, but the present disclosure is not limited to this. It should be noted that although the reflector 133 of this embodiment is illustrated as a sheet, the present disclosure is not limited to this. In some embodiments, the reflector can extend to the side of the light-emitting portion 110a to improve reflection efficiency, depending on the packaging structure of the backlight module 100a.

[0277] In the embodiment of the backlight module 100a including the light-enhancing plate 134, the light-enhancing plate 134 is used to increase the amount and angle of incidence of light through the optical effects of refraction and reflection, thereby further diffusing the received light toward the display panel 100', thereby improving the overall brightness and viewing angle of the light source. In this embodiment, the light-enhancing plate 134 is disposed on the diffuser plate 132 and is located between the display panel 100' and the diffuser plate 132.

[0278] The light enhancement plate 134 of this embodiment can be implemented using a transparent material coated with a high refractive index material, but the disclosure is not limited thereto. The light enhancement plate 134 can be connected / assembled with the diffuser plate 132 by gluing or other bonding methods, but the disclosure is also not limited thereto.

[0279] More specifically, in backlight module 100a, light emitted by light-emitting portion 110a is emitted from its light-emitting surface through the optical function of light guide plate 131a, and is sequentially transmitted through diffuser plate 132 and light-intensifying plate 134 to display panel 100'. Furthermore, light diffused from the periphery of light-emitting portion 110a and / or light guide plate 131a is reflected back by reflector 133 back to light guide plate 131a, where it is emitted to display panel 100' through a similar optical path as described above. Referring now to FIG. 20B , backlight module 100b includes light-emitting portion 110b and optical adjustment layer 130b, wherein optical adjustment layer 130b includes light guide plate 131b, diffuser plate 132, and reflector 133. In the present embodiment, the diffuser 132, the light guide plate 131b, and the reflector 133 are arranged in sequence on the z-axis from the side closest to the display panel 100' to the side farthest from the display panel 100', and the components are substantially parallel to each other. The light-emitting portion 110b is arranged on the side of the light guide plate 131b, wherein the light-emitting direction of the light-emitting portion 110b is not parallel to the normal direction of the planes such as the diffuser 132, the light guide plate 131b, and the reflector 133. More specifically, the light-emitting direction of the light-emitting portion 110b of the present embodiment may be substantially perpendicular to the normal direction of the planes such as the diffuser 132, the light guide plate 131b, and the reflector 133. In the backlight module 100b, the diffuser 132 is closest to the display panel 100', and the reflector 133 is farthest from the display panel 100'. From the perspective of the display panel 100 ′ being located at the uppermost side, the light guide plate 131 b is disposed above the reflector 133 , the diffuser 132 is disposed above the light guide plate 131 b , and the light emitting portion 110 b is disposed on the side of the light guide plate 131 b .

[0280] In some embodiments, the optical adjustment layer 130b may also include a light enhancement plate 134, where the light enhancement plate 134 is disposed on the upper side of the diffuser plate 132, that is, between the display panel 100' and the diffuser plate 132. In other words, in embodiments having the light enhancement plate 134, the component of the backlight module 100b closest to the display panel 100' may be the light enhancement plate 134. However, the present disclosure is not limited to this.

[0281] Specifically, the light guide plate 131b is used to refract and / or reflect the light provided by the light-emitting portion 110b, allowing the light to be evenly distributed from the light-emitting surface of the light guide plate 131b. In other words, after the light provided by the light-emitting portion 110b passes through the light guide plate 131b, the light emitted toward the display panel 100' is more evenly distributed across all areas of the display panel 100' compared to when the light guide plate 131b is absent. In this embodiment, the light-emitting surface of the light guide plate 131b is the surface closest to the display panel 100', and the light-incident surface of the light guide plate 131b is the side surface perpendicular / non-parallel to the light-emitting surface, i.e., the surface closest to the light-emitting portion 110b. In other words, compared to the embodiment described above in FIG. 20A , the backlight module 100b of this embodiment is configured with side-incident illumination. It should be noted that while FIG. 20B illustrates the light-emitting portion 110b being positioned on the right side of the light guide plate 131b, this is not intended to limit the present disclosure to this configuration. In other embodiments, the light emitting portion 110 b may also be disposed on other sides of the light guide plate (such as the left side, top side, and bottom side in the drawings).

[0282] For the structural composition / connection configuration embodiment of the light guide plate 131b of this embodiment, reference may be made to the description of the light guide plate 131a in the embodiment of FIG20A , which will not be repeated here.

[0283] The diffuser plate 132 is used to diffuse and refract received light, further dispersing it and evenly distributing it throughout the display panel 100'. In this embodiment, one side of the diffuser plate 132 is positioned on the light-emitting surface of the light guide plate 131b, while the other side is positioned relative to the display panel 100'. This allows light emitted from the light-emitting surface of the light guide plate 131b to pass through the diffuser plate 132 and be further evenly distributed throughout every area of ​​the display panel 100'.

[0284] Regarding the structural composition / connection configuration embodiment of the diffusion plate 132 of this embodiment, reference may be made to the description of the embodiment shown in FIG20A above, and no further details will be given here.

[0285] The reflector 133 is used to optically reflect received light, allowing light not directed toward the display panel 100' to be reflected toward the display panel 100', thereby improving the light source utilization efficiency of the light-emitting portion 110b. In this embodiment, the light guide plate 131b is disposed on the reflector 133, wherein the surface of the light guide plate 131b opposite the light-emitting surface faces the reflective surface of the reflector 133, so that the portion of light emitted by the light guide plate 131b that is not directed toward the display panel 100' is reflected back toward the light guide plate 131b.

[0286] For the structural composition / connection configuration embodiment of the reflector 133 of this embodiment, reference may be made to the description of the embodiment shown in FIG20A above, and no further details will be given here.

[0287] In the embodiment of the backlight module 100b including the light-enhancing plate 134, the light-enhancing plate 134 is used to increase the amount and angle of incidence of light through the optical effects of refraction and reflection, thereby further diffusing the received light toward the display panel 100', thereby improving the overall brightness and viewing angle of the light source. In this embodiment, the light-enhancing plate 134 is disposed on the diffuser plate 132 and is located between the display panel 100' and the diffuser plate 132.

[0288] Regarding the structural composition / connection configuration embodiment of the light-enhancing plate 134 of this embodiment, reference may be made to the description of the embodiment shown in FIG. 20A , which will not be repeated here.

[0289] More specifically, in backlight module 100b, light emitted by light-emitting portion 110b is emitted from its light-emitting surface through the optical function of light guide plate 131b, and is sequentially transmitted through diffuser plate 132 and light-intensifying plate 134 to display panel 100'. Furthermore, light diffused from the periphery of light-emitting portion 110b and / or light guide plate 131b is reflected back by reflector 133 toward light guide plate 131b, and is emitted to display panel 100' through a similar optical path as described above.

[0290] Compared to the direct-lit backlight module 100a of FIG. 20A , the light-emitting portion 110b of the backlight module 100b of this embodiment is located on the side of the light guide plate 131b rather than overlapping with the light guide plate 131b / reflection plate 133, thereby effectively reducing the thickness of the backlight module 100b.

[0291] In the aforementioned backlight modules 100a and 100b, the light guide plates 131a / 131b can be made of, for example, a plastic material. The disclosed embodiments propose a novel plastic light guide plate structural design that reinforces the overall rigidity of the light guide plates 131a / 131b by forming a transparent support structure on the surface of the light guide plates 131a / 131b. This eliminates the need for additional rigid reinforcement plates to prevent deformation of the light guide plates 131a / 131b in the backlight modules 100a / 100b, significantly reducing the cost of the backlight modules 100a / 100b. Furthermore, this design does not affect the light output characteristics of the backlight modules 100a / 100b. The aforementioned plastic light guide plate structural design will be further described in subsequent embodiments.

[0292] Referring next to FIG. 20C , the backlight module 100c includes a light-emitting portion 110c and an optical adjustment layer 130c. Compared to FIG. 20A and FIG. 20B , the optical adjustment layer 130c in this embodiment may only include a light guide plate 131c and a reflector 133. Specifically, the light-emitting surface of the light guide plate 131c (i.e., the light-emitting surface or the surface closer to the display panel 100 ′) in this embodiment undergoes a special surface treatment to impart the optical properties of a diffuser plate (e.g., 132 ) to the light guide plate 131c. Therefore, the backlight module 100c in this embodiment can omit the diffuser plate, and the optical adjustment layer 130c may only include the light guide plate 131c and the reflector 133.

[0293] In some embodiments, the optical adjustment layer 130c may also include a light enhancement plate 134. The light enhancement plate 134 is disposed above the light guide plate 131c, that is, between the display panel 100' and the light guide plate 131c. One side of the light enhancement plate 134 faces the light-emitting surface of the light guide plate 131c, and the other side of the light enhancement plate 134 faces the display panel 100'. In other words, in embodiments having the light enhancement plate 134, the component of the backlight module 100c closest to the display panel 100' may be the light enhancement plate 134. However, the present disclosure is not limited to this.

[0294] More specifically, the light guide plate 131c of this embodiment is made of glass, which is a material characterized by transparency, brittleness, and a certain degree of hardness. The upper surface of the light guide plate 131c undergoes surface treatment to impart the optical properties of a diffuser. Therefore, the diffuser plate 132 described in Figures 20A and 20B can be omitted in the backlight module 100c of this embodiment.

[0295] Referring next to Figure 20D , a backlight module 100d includes a light-emitting portion 110d and an optical adjustment layer 130d. Compared to Figures 20A and 20B , the optical adjustment layer 130d in this embodiment may only include a light guide plate 131d and a diffuser plate 132. Specifically, the surface of the light guide plate 131d opposite the light-emitting surface in this embodiment undergoes a special surface treatment to impart the optical properties of a reflective plate (e.g., 133). Therefore, the backlight module 100d in this embodiment can omit the reflective plate, and the optical adjustment layer 130d may only include the light guide plate 131d and the diffuser plate 132.

[0296] In some embodiments, the optical adjustment layer 130d may also include a light enhancement plate 134, where the light enhancement plate 134 is disposed on the upper side of the diffuser plate 132, that is, between the display panel 100' and the diffuser plate 132. In other words, in embodiments having the light enhancement plate 134, the component of the backlight module 100d closest to the display panel 100' may be the light enhancement plate 134. However, the present disclosure is not limited to this.

[0297] More specifically, this embodiment also utilizes a glass light guide plate 131d, and its surface opposite the light-emitting surface is surface-treated to impart the optical properties of a reflector. Therefore, the reflector plate 133 described in Figures 20A and 20B can be omitted from the backlight module 100d of this embodiment. Referring next to Figure 20E , the backlight module 100e includes a light-emitting portion 110e and an optical adjustment layer 130e. Compared to Figures 20A and 20B , the optical adjustment layer 130e of this embodiment may comprise only the light guide plate 131e. Specifically, the upper surface (i.e., the light-emitting surface or the surface on the side close to the display panel 100') and the lower surface (i.e., the surface on the other side opposite the light-emitting surface) of the light guide plate 131e of this embodiment are specially surface-treated so that the light guide plate 131e can simultaneously have the optical properties of a diffuser plate (such as 132) and a reflector plate (such as 133). Therefore, the backlight module 100e of this embodiment can omit the configuration of the diffuser plate and the reflector, and the optical adjustment layer 130e only includes the light guide plate 131e.

[0298] In some embodiments, the optical adjustment layer 130e may also include a light enhancement plate 134. The light enhancement plate 134 is disposed above the light guide plate 131e, that is, between the display panel 100' and the light guide plate 131e. One side of the light enhancement plate 134 faces the light-emitting surface of the light guide plate 131e, and the other side of the light enhancement plate 134 faces the display panel 100'. In other words, in embodiments having the light enhancement plate 134, the component of the backlight module 100e closest to the display panel 100' may be the light enhancement plate 134. However, the present disclosure is not limited to this.

[0299] More specifically, the light guide plate 131e of this embodiment is similar to the combination of the embodiments shown in Figures 20C and 20D above, wherein the upper surface of the glass light guide plate 131e has the optical properties of a diffuser plate after surface treatment, and the lower surface has the optical properties of a reflector plate after surface treatment. Therefore, the diffuser plate 132 and the reflector plate 133 described in Figures 20A and 20B can be omitted in the backlight module 100e of this embodiment.

[0300] The configurations shown in Figures 20C to 20E further simplify the manufacturing process of the backlight modules 100c / 100d / 100e, thereby improving production efficiency. Furthermore, since the diffuser and / or reflector are omitted, the effects of light uniformity and durability that may be caused by the connection between components are also improved.

[0301] For example, if the light guide plate and diffuser / reflector are assembled by gluing, air bubbles may form during the gluing process, affecting the optical performance of the backlight module. Furthermore, uneven adhesive application can cause uneven pressure between components during gluing (more serious in the case of large-sized panels), which can also lead to reduced optical performance. By omitting the diffuser and reflector, all of these issues can be alleviated.

[0302] The following further illustrates the specific structural examples of the glass light guide plate described in the embodiment of Figures 20C to 20E , with reference to Figures 21A to 21D . Figures 21A to 21D are schematic diagrams of the configurations of light guide plates according to different embodiments of the present disclosure. Referring first to Figure 21A , the light guide plate 231 includes a main body 2311, an optical microstructure 2312, and a reflective portion 2313. The optical microstructure 2312 is formed on one side of the main body 2311, and the reflective portion 2313 is formed on the opposite side of the main body 2311. The surface of the light guide plate 231 on the side where the optical microstructure 2312 is formed is a first surface S1, which faces the display panel 100 ′ (i.e., toward the light enhancement plate 134). The surface of the light guide plate 231 on the opposite side of the main body 2311 where the reflective portion 2313 is formed is a second surface S2. In this embodiment, the first surface S1 serves as the light-emitting surface of the light guide plate 231.

[0303] Specifically, the first surface S1 of the light guide plate 231 (i.e., the surface of the optical microstructures 2312) is frosted to have a roughened structure RS. This reduces the glossiness of the first surface S1, causing light passing through the first surface S1 to be scattered and refracted, thereby imparting the optical properties of a diffuser. In some embodiments, the glossiness of the frosted first surface S1 may be, for example, less than 20. In some preferred embodiments, the glossiness of the first surface S1 may be less than 1, for example, between 0.85 and 0.9, but the present disclosure is not limited thereto.

[0304] More specifically, since the light guide plate 231 is made of glass, a rough structure RS can be formed on the first surface S1 through a frosting method such as sandblasting, grinding wheels, chemical etching, wet grinding, and texture printing. For example, in some embodiments, by soaking the first surface S1 of the light guide plate 231 in hydrofluoric acid, a rough structure RS as shown in FIG21A can be formed on the surface of the optical microstructure 2312 / first surface S1 without damaging the optical microstructure 2312. In this way, the glossiness of the first surface S1 / light-emitting surface can be reduced by roughening the surface of the optical microstructure 2312 while ensuring the light guiding performance of the light guide plate 231, thereby imparting the scattering and refractive optical properties of a diffuser plate to the first surface S1.

[0305] In some embodiments, the main body 2311 and the optical microstructure 2312 of the light guide plate 231 may be integrally formed.

[0306] In some embodiments, in addition to the above-mentioned frosting method for forming the rough structure RS on the first surface S1 , the rough structure RS may also be formed by laser cutting and / or 3D printing, but the present disclosure is not limited thereto.

[0307] Meanwhile, the second surface S2 of the light guide plate 231 undergoes a coating process, coating it with a reflective film to form a reflective portion 2313. The reflective portion 1313 reflects light toward the first surface of the light guide plate 231. The reflective film can be made of a high-gloss metal material, such as aluminum or silver, but the present disclosure is not limited thereto. After the aforementioned coating process, the reflective portion 2313 formed on the light guide plate 231 possesses the optical properties of a reflective plate, and can therefore replace the reflective plate 133 shown in Figures 20A and 20B.

[0308] In some embodiments, the glossiness of the reflective portion 1313 may be greater than 95, for example.

[0309] The light guide plate 231 of this embodiment can be used in the backlight module 100e as shown in FIG20E . Furthermore, if only the first surface S1 of the light guide plate 231 of this embodiment is subjected to the aforementioned frosting treatment or other surface roughening treatment to reduce the glossiness to that of a diffuser, the light guide plate 231 can be used in the backlight module 100c as shown in FIG20C . If only the second surface S2 of the light guide plate 231 of this embodiment is subjected to a coating treatment to increase the glossiness to that of a reflector, the light guide plate 231 can be used in the backlight module 100d as shown in FIG20D .

[0310] Referring to Figure 21B , the light guide plate 331 includes main bodies 3311a and 3311b, optical microstructures 3312, and a reflective portion 3313. The optical microstructures 3312 are formed between the main bodies 3311a and 3311b, and the optical microstructures 3312 and the reflective portion 3313 are formed on opposite sides of the main body 3311a. The surface of the main body 3311b facing away from the optical microstructures 3312 is a first surface S1, which faces the display panel 100' (i.e., toward the light enhancement plate 134). The surface of the light guide plate 331 located on the other side of the main body 3311a, where the reflective portion 3313 is formed, is a second surface S2. In this embodiment, the first surface S1 serves as the light-emitting surface of the light guide plate 331.

[0311] Specifically, this embodiment is similar to the embodiment of Figure 21A above, and the main difference is that the optical microstructure 3312 of this embodiment is formed between the two layers of the main body 3311a and 3311b (that is, located in the glass material), so the rough structure RS of this embodiment is formed on the main body 3311b, rather than on the surface of the optical microstructure 3312.

[0312] In this embodiment, the first surface S1 of the light guide plate 331 (i.e., the upper surface of the main body 3311b / the surface away from the optical microstructures 3312) is frosted to have a roughened structure RS. This reduces the glossiness of the first surface S1, causing light passing through the first surface S1 to be scattered and refracted, thereby imparting the optical properties of a diffuser. Similarly, in some embodiments, the glossiness of the frosted first surface S1 may be, for example, less than 20. In some preferred embodiments, the glossiness of the first surface S1 may be less than 1, for example, between 0.85 and 0.9, but the present disclosure is not limited thereto.

[0313] On the other hand, regarding the formation and configuration of the reflective portion 3313, reference may be made to the description of the embodiment shown in FIG21A above, and will not be repeated here.

[0314] From the perspective of the light guide plates 231 and 331 as a whole, the light guide plates 231 / 331 can be regarded as including a light incident surface, a first surface S1 and a second surface S2. The first surface S1, as the light emitting surface of the light guide plate 231 / 331, is substantially perpendicular to the light incident surface, and the second surface S2 is located on the other side opposite the light emitting surface. The glossiness of the first surface S1 is less than 20, and the glossiness of the second surface S2 is greater than 80. In some embodiments, the glossiness of the first surface S1 is less than 1, and the glossiness of the second surface S2 is greater than 95. In some embodiments, the glossiness of the first surface S1 is between 0.85 and 0.9, and the glossiness of the second surface S2 is greater than 95.

[0315] Similar to the above-described embodiments, the light guide plate 331 of this embodiment can be used in the backlight module 100e as shown in FIG20E . Furthermore, if only the first surface S1 of the light guide plate 331 of this embodiment undergoes the aforementioned frosting treatment or other surface roughening treatment to reduce the glossiness to that of a diffuser, the light guide plate 331 can be used in the backlight module 100c as shown in FIG20C . If only the second surface S2 of the light guide plate 331 of this embodiment undergoes a coating treatment to increase the glossiness to that of a reflector, the light guide plate 331 can be used in the backlight module 100d as shown in FIG20D .

[0316] Referring to FIG21C , the light guide plate 431 of this embodiment includes a main body 4311, optical microstructures 4312, and a reflective portion 4313. The cross-sectional structure of this embodiment is depicted as similar to that of the embodiment of FIG21A for illustrative purposes, but the present disclosure is not limited thereto. The light guide plate 431 of this embodiment may also have the structure shown in FIG21B .

[0317] This embodiment is substantially the same as the aforementioned embodiments of FIG. 21A and FIG. 28B , with the main difference being that the reflective portion 4313 of this embodiment is not only formed on the second surface S2 , but also extends to at least a portion of the side surface of the light guide plate 431 .

[0318] Specifically, the side surfaces herein are, for example, surfaces S3-S5 of the light guide plate 431 that are substantially perpendicular (or non-parallel) to the first surface S1 and / or the second surface S2, excluding the light incident surface S0. Referring to FIG. 21C , the side surfaces include, for example, the lower surface S3, the left surface S3, and the upper surface S5 of the light guide plate 431.

[0319] In this embodiment, the reflective film on the reflective portion 4313 extends from the second surface S2 to at least one of the side surfaces S3-S5. In some embodiments, the reflective film covers the second surface S2 and all of the side surfaces S3-S5. This configuration of the reflective portion 4313 not only reflects light directed toward the second surface S2 back toward the display panel, but also reflects light from other directions by the reflective film on the side surfaces S3-S5, further improving light source utilization and thus enhancing the brightness of the backlight module.

[0320] The light guide plate 431 of this embodiment can be applied to the backlight module 100d as shown in FIG20D (the first surface S1 is not subjected to surface roughening treatment), or applied to the backlight module 100e as shown in FIG20E (the first surface S1 is subjected to surface roughening treatment), but the present disclosure is not limited thereto.

[0321] Referring to FIG. 21D , the light guide plate 531 of this embodiment includes a main body 5311, optical microstructures 5312, and a reflective portion 5313. This embodiment is similar to the embodiment shown in FIG. 21C , so the relevant configuration description can be found in the description of the aforementioned embodiment and will not be repeated here. The primary difference between this embodiment and the embodiment shown in FIG. 21C is that the light guide plate 531 of this embodiment further includes reflective film structures 5314 arranged at intervals on its light incident surface S0.

[0322] Specifically, the reflective film structure 5314 on the light-entering surface S0 is formed corresponding to the positions of the light-emitting elements LEDs on the light-emitting portion 110. The reflective film structure 5314 is formed in the area between adjacent light-emitting elements LEDs to avoid blocking the light path of the light-emitting elements LEDs. By forming the reflective film structure 5314 in the area between adjacent light-emitting elements LEDs, the light guide plate 531 can effectively reduce the dark areas between the light-emitting elements LEDs, making the backlight module emit light more uniformly.

[0323] The light guide plate 531 of this embodiment can also be applied to the backlight module 100d described in FIG. 20D or the backlight module 100e described in FIG. 20E , but the present disclosure is not limited thereto. It should be noted that although the above-mentioned embodiments of FIG. 21C and FIG. 21D illustrate the light incident surface S0 as the right side surface of the light guide plate as an example (i.e., the light emitting portion 110 is configured on the right side of the light guide plate), the present disclosure is not limited thereto. In other embodiments, the light emitting portion 110 can be configured on any one or more side surfaces according to design requirements, wherein the side surface on which the light emitting portion 110 is configured is deemed to be the light incident surface.

[0324] Figures 22A and 22B further illustrate exemplary configurations of the reflective film structure 5314 on the light-entering surface S0. Referring first to Figure 22A, the reflective film structure 5314a of this embodiment can be formed in a rectangular pattern and located within the spacing between two adjacent light-emitting elements. In other words, the width of the reflective film structure 5314a is determined based on the distance between adjacent light-emitting elements, while the height of the reflective film structure 5314a is determined based on the thickness of the light guide plate.

[0325] 22B , the reflective film structure 5314b of this embodiment can be formed into a circular / elliptical pattern and is also located in the spacing area between two adjacent light-emitting elements. In other words, the diameter / long axis length of the reflective film structure 5314b is selected based on the distance between adjacent light-emitting elements.

[0326] Figures 23A to 23C illustrate an embodiment of a first type of light guide plate structure, which can be used in the configurations of backlight modules 100a and 100b described in the embodiments of Figures 20A and 20B above. Referring first to Figure 23A , the upper portion of Figure 23A illustrates a side view of a light guide plate 631, and the lower portion of Figure 23A illustrates a top view of the light guide plate 631. The light guide plate 631 of this embodiment includes a main body 6311 and reinforcement portions 6312a and 6312b, respectively formed on opposite sides of the main body 6311. The surface of the light guide plate 631 on the side with the reinforcement portion 6312a is a first surface S1, which faces the display panel 100' (i.e., the light enhancement plate 134). The surface on the other side of the main body 2311 is a second surface S2, which faces the reflective plate 133. In this embodiment, the first surface S1 serves as the light-emitting surface of the light guide plate 631. Specifically, the reinforcement portions 6312a and 6312b each include a plurality of columnar support units SP. Each support unit SP is light-transmissive and has a certain degree of rigidity. Taking the reinforcement portion 6312a as an example, the support units SP have a height Ph and are sequentially arranged and spaced apart on the first surface S1, with a spacing Pw between adjacent support units SP. The height Ph of the support units SP can be, for example, between 2 μm and 3 μm, but this disclosure is not limited thereto.

[0327] More specifically, in this embodiment, the pitch Pw between the support units SP of two adjacent columns may be a fixed pitch Pwc, and the pitch Pw between the support units SP of two adjacent rows may be a fixed pitch Pwr. In other words, the support units SP in each row are sequentially arranged at a fixed pitch Pwc, and the support units SP in each column are sequentially arranged at a fixed pitch Pwr, thereby forming an array configuration on the first surface S1.

[0328] While this embodiment illustrates a 5×5 array of support units SP, the present disclosure is not limited thereto. In some embodiments, at least two support units SP in each row / column are disposed in a peripheral region of the light guide plate 631. The peripheral region may be, for example, a region with a vertical distance from the edge of the main body 6311 between 0.01 mm and 0.5 mm, but the present disclosure is not limited thereto.

[0329] In some embodiments, the fixed pitches Pwc and Pwr can be designed according to the size of the light guide plate 631 , and they can be the same or different, and the present disclosure is not limited thereto.

[0330] In some embodiments, the transparency of the support unit SP can be, for example, greater than or equal to 99% (preferably 99.9%), and the elastic recovery rate (ER) of the support unit SP can be greater than 95%, but the present disclosure is not limited thereto. In some embodiments, the support unit SP can be, for example, a photo spacer formed on the body portion 6311 by a photolithography process and can be implemented using one or a combination of the following materials: a polymer, an oligomer, a photoinitiator, a curing agent, a surfactant, and a solvent.

[0331] In some embodiments, the high molecular weight polymer may, for example, include an acrylic polymer, which is primarily used to improve the mechanical properties of the support unit SP and the development characteristics during photolithography. The oligomer may, for example, include an acrylic multifunctional monomer, which is primarily used to adjust the mechanical properties and crosslink density of the support unit SP and may also be used to affect the development characteristics. The photosensitive initiator is primarily used to control the photoresistance, crosslink density, and crosslink formation control during the formation of the support unit SP. The crosslinker may, for example, include a thermal crosslinking monomer, which is primarily used to increase the mechanical strength after thermal baking. The surfactant may be used to adjust the surface tension and coating characteristics of the support unit SP before curing. The solvent may, for example, be 1,2-propylene glycol methyl ether acetate (PGMEA), cyclohexanone, or 3-methoxybutyl acetate, which is primarily used to adjust the volatilization rate, the photoresist leveling range, and the compatibility with other solvents during the photolithography process.

[0332] Referring next to Figure 23B , this embodiment is substantially identical to the embodiment shown in Figure 23A . Similar portions can be found in the description of the aforementioned embodiment and will not be repeated here. The primary difference between the embodiment shown in Figure 23B and the embodiment shown in Figure 23A lies in the arrangement of the support units SP. In this embodiment, the support units SP are arranged in an "X" shape within the central region Sc on the first surfaces S1 and S2 of the main body 6311. In the peripheral regions outside the central region Sc, the support units SP are arranged in a similar manner to that shown in Figure 23A , with regular intervals Pwc in the x-direction and regular intervals Pwr in the y-direction.

[0333] From another perspective, the support units SP of this embodiment are sequentially arranged at a fixed interval Pwd1 in the first direction d1, and are sequentially arranged at a fixed interval Pwd2 in the second direction d2 perpendicular to the first direction d1. The support units SP arranged along the first direction d1 share the same support unit SP at the center point with the support units SP arranged along the second direction d2, thereby forming an "X"-shaped arrangement configuration.

[0334] Referring now to Figure 23C , this embodiment is substantially identical to the embodiment shown in Figure 23A . Similar details can be found in the description of the aforementioned embodiment and will not be repeated here. The primary difference between the embodiment shown in Figure 23C and the embodiment shown in Figure 23A is that the support units SP in this embodiment are arranged in a "M" shape on the first surfaces S1 and S2 of the main body portion 6311.

[0335] From another perspective, the support units SP of this embodiment are arranged in sequence at a fixed interval Pwd1 in the first direction d1, in sequence at a fixed interval Pwd2 in the second direction d2 perpendicular to the first direction d1, and in sequence at fixed intervals Pwx and Pwy in the x and y directions, respectively. The support units SP arranged along the first direction d1, the support units SP arranged along the second direction d2, and the support units SP arranged along the x direction share the same support unit SP at the center point, thereby forming a "R"-shaped arrangement configuration.

[0336] Figures 24A to 24D illustrate an embodiment of a second type of light guide plate structure, which can be applied to the backlight modules 100a and 100b described in the embodiments of Figures 20A and 20B . Referring first to Figure 24A , the upper portion of Figure 24A illustrates a side view of a light guide plate 731, and the lower portion of Figure 24A illustrates a top view of the light guide plate 731. The light guide plate 731 of this embodiment includes a main body 7311 and reinforcement portions 7312a and 7312b, respectively formed on opposite sides of the main body 7311. The surface of the light guide plate 731 on the side with the reinforcement portion 7312a is a first surface S1, which faces the display panel 100' (i.e., the light enhancement plate 134). The surface of the light guide plate 731 on the other side of the main body 7311 is a second surface S2, which faces the reflective plate 133. In this embodiment, the first surface S1 is the light-emitting surface of the light guide plate 731. Specifically, the reinforcement portions 7312a and 7312b respectively include a plurality of columnar first support units SPm and second support units SPs, wherein the first support units SPm and the second support units SPs are both light-transmissive and have a certain degree of rigidity. Taking the reinforcement portion 7312a as an example, the first support unit SPm has a height Ph1, and the second support unit SPs has a height Ph2, wherein the height Ph1 is greater than the height Ph2, and the first support units SPm and the second support units SPs are formed on the first surface S1 at intervals. The spacing between adjacent first support units SPm and second support units SPs is Pw. The height of the first support unit SPm may be, for example, between 2 μm and 3 μm, and the height Ph2 of the second support unit SPs may be, for example, between 1.5 μm and 2.5 μm, but the present disclosure is not limited thereto.

[0337] In this embodiment, the pitch Pw between two adjacent columns of support units SP can be a fixed pitch Pwc, and the pitch Pw between two adjacent rows of support units SP can be a fixed pitch Pwr. In other words, the support units SP in each row are arranged sequentially at a fixed pitch Pwc, and the support units SP in each column are arranged sequentially at a fixed pitch Pwr, thereby forming an array configuration on the first surface S1. In this embodiment, any support unit SPm / SPs may have a different height from an adjacent support unit, where "adjacent support unit" refers to the support unit closest in the x-direction or y-direction. For example, for any first support unit SPm, second support units SPs are arranged above, below, to the left, and to the right of it.

[0338] Specifically, because the height Ph2 of the second support units SPs is less than the height Ph1 of the first support units SPm, when the first support units SPm are deformed / retracted due to stress, the second support units SPs can provide further support when the first support units SPm reach a certain level of deformation, thereby preventing the main body 7311 of the light guide plate 731 from being squeezed and bent. In other words, the configuration of the first support units SPm and the second support units SPs allows the light guide plate 731 to have different support heights Ph1 and Ph2. This allows the first support units SPm and the second support units SPs to provide a differential support force when the light guide plate 731 is squeezed, thereby preventing display defects.

[0339] More specifically, when each support unit SPm / SPs is subjected to stress, its support point on the main body 7311 will still be relatively stressed, resulting in slight deformation, which may affect the display effect. Therefore, compared to the embodiment of Figure 23A, this embodiment replaces some of the first support units SPm with second support units SPs of lower height. That is, by configuring the first and second support units SPm with a height difference, the number of support units SPm / SPs actually subjected to stress is reduced in the normal state (i.e., the state in which the first support units SPm alone can support the stress exerted on the light guide plate 731 by the front and rear components). In the stressed state (i.e., the first support units SPm are deformed to the extent that the stress acts on the second support units SPs), the second support units SPs provide additional support, thereby achieving an optimal balance between display effect and structural protection.

[0340] Please refer to Figure 24B next. This embodiment is roughly the same as the embodiment of Figure 24A above. Similar parts can refer to the description of the above embodiment and will not be repeated here. The main difference between the embodiment of Figure 24B and the embodiment of Figure 24A is that the arrangement configuration of the first support unit SPm and the second support unit SPs of this embodiment is different. In this embodiment, the first support unit SPm is configured in the manner shown in Figure 23A, so the spacing between two adjacent first support units SPm is Pw. The second support unit SPs will be formed between adjacent first support units SPm and have roughly the same spacing Pw' as the adjacent first support units SPm. In other words, the spacing Pw' is roughly slightly less than half of the spacing Pw.

[0341] From another perspective, the first support units SPm and the second support units SPs of this embodiment are arranged in sequence at a fixed interval Pwr in the x-direction or the y-direction (this embodiment is illustrated as an example of arrangement in the y-direction, but the present disclosure is not limited to this), wherein each column of the first support units SPm are alternately arranged with each column of the second support units SPs, so that there is a fixed interval Pwc between adjacent first support units SPm and second support units SPs.

[0342] Referring next to Figure 24C , the support unit configuration of this embodiment is substantially the same as that of the embodiment of Figure 23B . Therefore, similar portions may be referred to the description of the aforementioned embodiment and will not be repeated here. The primary difference between the embodiment of Figure 24C and the embodiment of Figure 23B is that this embodiment utilizes first support units SPm and second support units SPs of varying heights to form an "X"-shaped arrangement. In the first direction d1 and the second direction d2, the first support units SPm and the second support units SPs are staggered and arranged at intervals, achieving the effects described in the embodiment of Figure 24A .

[0343] Referring next to Figure 24D , the support unit configuration of this embodiment is substantially the same as that of the embodiment of Figure 23C , so similar portions may be referred to the description of the aforementioned embodiment and will not be repeated here. The primary difference between the embodiment of Figure 24D and the embodiment of Figure 23C is that this embodiment utilizes first support units SPm and second support units SPs of varying heights to form a "R"-shaped arrangement. In the x-direction, y-direction, first direction d1, and second direction d2, the first support units SPm and second support units SPs are staggered in an interlaced manner, achieving the effects described in the embodiment of Figure 24A .

[0344] From another perspective, in this embodiment, a first support unit SPm is provided at the center of the main body 7311 , and second support units SPs surround the first support unit SPm as a step support.

[0345] It should be noted that while the embodiments shown in Figures 23A to 24D above are primarily described with respect to the reinforcement portion 7312a on the first surface S1, those skilled in the art will appreciate that similar structural configurations can also be applied to the reinforcement portion 7312b on the second surface S2. Furthermore, the reinforcement portions 7312a and 7312b can have the same or different support structures, as explained above.

[0346] In addition, it can be seen from the above-mentioned embodiments of Figures 23A to 24D that the support units are at least formed in the central area (especially the center) and four corners of the main body to provide more stable structural support.

[0347] FIG25 illustrates an embodiment of a third type of light guide plate structure, which can be used in the configurations of the backlight modules 100a to 100e described in the embodiments of FIG20A to FIG20E . Referring to FIG25 , the upper portion of FIG25 illustrates a side view of the light guide plate 831, and the lower portion of FIG25 illustrates a top view of the light guide plate 831. The light guide plate 831 of this embodiment includes a main body 8311 composed of a plurality of light guide units LGu. Adjacent light guide units LGu are joined and fixed together by joints adv, such that the joined light guide units LGu form a substantially continuous first surface S1 (i.e., the first surface S1 of the light guide plate 831) and a second surface S2 opposite the first surface S1 (i.e., the second surface S2 of the light guide plate 831). The first surface S1 faces the display panel 100 ′ (i.e., the light enhancement plate 134), while the second surface S2 faces the reflective plate 133. In this embodiment, the first surface S1 is the light emitting surface of the light guide plate 731 .

[0348] It should be noted that the substantially continuous first surface S1 / second surface S2 means that when the light guide units LGu are joined together via the joint portion adv, the upper and lower surfaces of the individual light guide units LGu are substantially coplanar. In other words, the height difference between the joined light guide units LGu is within a tolerance range, and does not create a visually uneven appearance.

[0349] Specifically, the light guide unit LGu can be a standard module with a parallelogram structure (that is, each module has the same size within the tolerance range). By joining multiple light guide units LGu to form a light guide plate 831, the directionality of the light-emitting portion 110 can be effectively destroyed, so that the light can be more evenly diffused over the entire main body 8311 and emitted from the light-emitting surface. Therefore, the backlight module using the light guide plate 831 can obtain a more uniform surface light source, thereby effectively improving the overall light source uniformity of the backlight module. At the same time, since the light guide plate 831 will not cause the light source to be additionally shielded and reduce the light intensity, the luminous efficiency of the backlight module can be greatly improved and the overall power consumption can be reduced.

[0350] Furthermore, because the joints adv can be implemented using optical adhesive (OCA) or other adhesive materials with a certain degree of viscoelasticity, even if the light guide plate 831 formed by the light guide units LGu is squeezed, the stress of the squeeze can be absorbed by the joints adv without the risk of warping that occurs with traditional solid-surface light guide plates. The risk of light guide plate deformation caused by thermal expansion and moisture expansion is also effectively reduced or eliminated.

[0351] On the other hand, since light guide plates 831 of any size can be manufactured by simply increasing or decreasing the number of joined light guide units LGu, there is no need to adjust the mold and manufacturing process to suit the size requirements of the backlight module in different products. This effectively simplifies the manufacturing process of light guide plates 831 and reduces manufacturing costs and cycle time. Furthermore, since light guide plates 831 are composed of multiple small modules, if a single module fails, it can be repaired or replaced directly without replacing the entire light guide plate 831, effectively reducing repair costs and expenses.

[0352] In some embodiments, the plurality of light guide units LGu may have a diamond structure, wherein a first diagonal length of each light guide unit LGu is between 10 mm and 100 mm, and a second diagonal length is between 17.32 mm and 173.2 mm, but the present disclosure is not limited thereto.

[0353] In some embodiments, to form a rectangular light guide plate 831, non-parallelogram (or non-rhombus) light guide units LGe are included at the edges of the body portion 8311. As shown in FIG. 25 , the light guide units LGe at the edges of the body portion 8311 may, for example, have triangular structures corresponding to the dimensions of the parallelogram-shaped light guide units LGu, thereby forming a rectangular light guide plate 831 at the edges and corners together with the parallelogram-shaped (or rhombus-shaped) light guide units LGu.

[0354] In some embodiments, the LED of the light-emitting portion may be attached to the side or bottom of the light guide plate 831 to guide light into the light guide plate 831 and achieve a backlight effect; wherein, the LED may be attached to the edge of the light guide unit LGe, but the present disclosure is not limited to this.

[0355] FIG26 illustrates an embodiment of a fourth type of light guide plate structure, which can be used in the configurations of backlight modules 100a through 100e described in the embodiments of FIG20A through FIG20E . Referring to FIG26 , the upper portion of FIG26 illustrates a top view of a light guide plate 931, and the lower portion of FIG26 illustrates a bottom view of the light guide plate 931. The light guide plate 931 of this embodiment includes a body portion 9311 having a curved surface structure. The body portion 9311 has a positive curvature at a center point O of a first surface S1 and a negative curvature at a center point O' of a second surface S2 opposite the first surface S1. In other words, the main body 9311 is configured as a raised structure in the central area so that the shortest distance between at least one point on the first surface S1 in the central area and the display panel 100' (or the light-enhancing plate 134) is smaller than the shortest distance between at least one point on the peripheral area and the display panel 100'; similarly, the shortest distance between at least one point on the second surface S2 in the central area and the reflective plate 133 is larger than the shortest distance between at least one point on the peripheral area and the reflective plate 133.

[0356] In some embodiments, the curvature of the body portion 9311 may be set to be greater than 1500R, but the present disclosure is not limited thereto. In addition, in some embodiments, the LED of the light-emitting portion may be attached to the edge or bottom of the body portion 9311, but the present disclosure is not limited thereto.

[0357] Through the curved light guide plate 931 structure as shown in Figure 26, the light source projected onto the central area of ​​the main body 9311 can be affected by the curved surface and cross-interfere, thereby allowing the light to be evenly diffused to the peripheral area of ​​the main body 9311, thereby achieving higher light source conversion efficiency.

[0358] In addition, the configuration of the surface light guide plate 931 can also achieve a special light source effect of the backlight module to improve the exclusive performance.

[0359] It should be noted here that those skilled in the art should understand that the various light guide plate embodiments proposed in the present disclosure can not only be used alone in the backlight module, but can also be used in combination with each other in the same light guide plate design with reference to the above description. For example, the surface light guide plate 931 shown in FIG26 can also have an optical microstructure (such as 2312) and a reflective portion (such as 2313) as shown in FIG21A to FIG21D, and the present disclosure is not limited to this. In other words, although the present disclosure does not exhaust all possible combinations of embodiments, those skilled in the art should be able to derive possible arrangements and combinations of implementation methods within a reasonable range after referring to the above-mentioned embodiment descriptions, so any combination of embodiments of the present disclosure is supported by the present disclosure specification.

[0360] The following further describes the design of the quantum dot film portion of the backlight module in the display device 10 / 30.

[0361] The configuration of the backlight module 100 in FIG. 1A of the embodiment of the present disclosure can be shown in FIG. FIG. 27 is a schematic diagram of a backlight module according to one embodiment of the present disclosure. Referring to FIG. 27 , in this embodiment, the light-emitting layer 110 includes light-emitting elements (LEDs), a substrate 111, and a protective layer 112. The light-emitting elements (LEDs) are disposed on the substrate 111 and emit light toward the quantum dot film 120. The protective layer 112 covers the light-emitting elements (LEDs).

[0362] The quantum dot film 120 includes an active layer 121, a supporting layer 122, a bonding layer 123, and a water-blocking layer 124. The active layer 121 may include a substrate (not shown) and quantum dots (not shown) doped in the substrate, wherein the substrate may be, for example, a light-transmitting polymer material (such as a resin material), and the quantum dots may be, for example, semiconductor quantum dots synthesized from nanocrystalline semiconductor materials (such as II-VI semiconductor materials, III-V semiconductor materials, or other combination materials), but the present disclosure is not limited thereto. When the quantum dots are irradiated with light, they will excite colored light of a different wavelength from the irradiated light. For example, when the quantum dots are irradiated with blue light, they can excite green light and red light.

[0363] The support layer 122 is disposed on the light-emitting surface MS of the light-emitting layer 110 and is used to support / fix the active layer 121, allowing the material of the active layer 121 to adhere to / be coated on the support layer 122. The support layer 122 can be formed, for example, from an organic polymer and / or an inorganic material that is both light-transmissive and supportive. The organic polymer can be, for example, polyvinylidene chloride (PVdC), cyclic olefin copolymer (COC), high-density polyethylene (HDPE), polyethylene terephthalate (PET), polyimide (PI), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), or a combination thereof. The inorganic material can be, for example, a metal oxide (e.g., SiOx, Si6Ny, etc.).

[0364] In some embodiments, the support layer 122 may be a polymer barrier film formed using PVdC and COC materials, which may provide a certain degree of water and oxygen barrier properties.

[0365] The bonding layer 123 is used to provide a bonding force to effectively and reliably attach / fix the active layer 121 and the support layer 122. The bonding layer 123 can be formed, for example, from an optical clear adhesive (OCA) or a primer. In some embodiments, the bonding layer 123 can also include a dielectric material to enhance the insulating properties of the bonding layer 123, as shown in FIG28 .

[0366] Figure 28 is a schematic diagram of the bonding layer of a quantum dot film according to one embodiment of the present disclosure. Referring to both Figures 27 and 28, the bonding layer 123 is disposed between the active layer 121 and the support layer 122. The bonding layer 123 of this embodiment includes an adhesive layer 1231 and an insulating layer 1232. The adhesive layer 1231 may be formed using an optical adhesive or a surface treatment agent, and the insulating layer 1232 may be formed using a dielectric material. The dielectric material may be, for example, silicon nitride, silicon oxide, or other metal oxides, but the present disclosure is not limited thereto.

[0367] It should be noted that while the bonding layer 123 in the accompanying drawings illustrates the adhesive layer 1231 and the insulating layer 1232 as being sequentially arranged, the present disclosure is not limited thereto. In some embodiments, the material of the insulating layer 1232 may be doped into the adhesive layer 1231, such that no distinct delamination exists between the adhesive layer 1231 and the insulating layer 1232.

[0368] In addition, although the accompanying drawings show that the bonding layer 123 has a certain thickness, the proportions shown here are only for ease of explanation and do not represent the thickness ratios of the various layers in the actual product. Since the bonding layer 123 may be a layer of optical adhesive coated on the support layer, the bonding layer 123 is not necessarily visually visible in the cross-sectional structure of the actual quantum dot film, and may require observation with a higher magnification electron microscope to confirm it. In fact, if it can be observed in the quantum dot film that the sandwich structure formed by the support layer 122 and the active layer 121 can be effectively and reliably bonded, those skilled in the art will understand that there must be a bonding layer 123 between the support layer 122 and the active layer 121. Therefore, in the comparison of actual products, the presence or absence of the bonding layer 123 is not determined by whether it is visually visible.

[0369] Referring again to FIG. 27 , the water-blocking layer 124 directly or indirectly covers at least a portion of the surface of the active layer 121 to prevent the active layer 121 from being affected by moisture and unable to function normally, thereby extending the service life of the active layer 121. Specifically, the water-blocking layer 124 can be implemented using a protective polymer film. For example, the water-blocking layer 124 can be implemented using polyparaxylene (Parylene, also known as Parylene). The polyparaxylene has the characteristics of being resistant to high and low temperatures, corrosion-resistant, acid- and alkali-resistant, waterproof and moisture-proof, transparent, and having high dielectric strength. Therefore, when the water-blocking layer 124 covers the active layer 121, it can effectively isolate the active layer 121 from the effects of moisture.

[0370] In traditional applications, the water and oxygen barrier properties of quantum dot films rely primarily on the material properties of the support and bonding layers, which limits material choices and makes cost reduction difficult. Furthermore, the industry typically utilizes a sandwich structure for the production of quantum dot films. However, with this structure, the support and bonding layers alone are unable to fully protect the active layer, making typical quantum dot films susceptible to environmental issues such as moisture and humidity, shortening their operating lifespan.

[0371] The quantum dot film 120 proposed in the disclosed embodiments not only provides a preliminary water-blocking effect through the support layer 122 and the bonding layer 123, but also the water-blocking layer 124 covering the active layer 121 further blocks moisture from entering the active layer 121, making the active layer 121 less susceptible to moisture. Furthermore, because the water-blocking layer 124 significantly enhances the water-blocking properties of the quantum dot film 120, a wider range of material options are available for the support layer 122 and the bonding layer 123 to meet design considerations while also balancing cost requirements.

[0372] The structural configuration of the water-blocking layer 124 in different embodiments is described in more detail below with reference to FIG. 29A to FIG. 29F , wherein FIG. 29A to FIG. 29F are schematic cross-sectional views of quantum dot films in different embodiments of the present disclosure.

[0373] Referring first to FIG. 29A , the quantum dot film 220 of this embodiment includes an active layer 221, support layers 222a and 222b, bonding layers 223a and 223b, and a water-blocking layer 224. In this embodiment, the support layers 222a and 222b are disposed on opposite sides of the active layer 221 and are connected to the active layer 221 via bonding layers 223a and 223b, respectively. Referring to FIG. 29A , the lower surface of the active layer 221 is connected to / attached to the upper surface of the support layer 222a via bonding layer 223a; and the upper surface of the active layer 221 is connected to / attached to the lower surface of the support layer 222b via bonding layer 223b. In other words, the support layers 222a and 222b and the bonding layers 223a and 223b form a sandwich structure on opposite sides of the active layer 221.

[0374] The water-blocking layer 224 covers the exposed surfaces of the active layer 221, the supporting layers 222a and 222b, and the bonding layers 223a and 223b. Furthermore, although not shown in the cross-sectional schematic diagram of FIG29A , the water-blocking layer 224 also covers the sandwich structure in the y-axis direction. Furthermore, the exposed surfaces of the active layer 221, the supporting layers 222a and 222b, and the bonding layers 223a and 223b in the xz plane may also be covered by the water-blocking layer 224.

[0375] In other words, the water-blocking layer 224 of this embodiment covers the entire sandwich structure formed by the active layer 221 , the supporting layers 222 a and 222 b , and the bonding layers 223 a and 223 b .

[0376] Furthermore, although the active layer 221, the supporting layers 222a and 222b, and the bonding layers 223a and 223b of this embodiment are depicted as having the same width (i.e., the same length in the x-axis direction), the present disclosure is not limited thereto. In other embodiments, the active layer 221, the supporting layers 222a and 222b, and the bonding layers 223a and 223b may also have different widths.

[0377] 29B , the quantum dot film 320 of this embodiment includes an active layer 321, support layers 322a and 322b, bonding layers 323a and 323b, and a water-blocking layer 324. The configuration of the active layer 321, support layers 322a and 322b, and bonding layers 323a and 323b in this embodiment is similar to that described in FIG29A . The support layers 322a and 322b are disposed on opposite sides of the active layer 321 and connected to the active layer 321 via bonding layers 323a and 323b, respectively. The difference is that the width of the support layers 322a and 322b in this embodiment is greater than the width of the active layer 321 and the bonding layers 323a and 323b.

[0378] In this embodiment, the water-blocking layer 324 covers the sidewalls of the active layer 321 and the bonding layers 323a and 323b to prevent moisture from invading the active layer 321 through the exposed sidewalls. In other words, compared to the embodiment of FIG29A , which completely covers the sandwich structure, the water-blocking layer 324 in this embodiment only covers a portion of the active layer 321 (i.e., the sidewalls).

[0379] 29C , the quantum dot film 420 of this embodiment includes an active layer 421, support layers 422a, 422b, and 422c, bonding layers 423a and 423b, and a water-blocking layer 424. This embodiment is substantially the same as the embodiment of FIG. 29A , differing from the embodiment of FIG. 29A in that the quantum dot film 420 of this embodiment further includes a support layer 422c disposed on a side closer to the light-emitting layer.

[0380] In other words, the sandwich structure consisting of the active layer 421, support layers 422a and 422b, and bonding layers 423a and 423b, encased in the water-blocking layer 424, is disposed on the support layer 422c. The quantum dot film 420 is connected to the light-emitting layer via the support layer 422c. This further enhances the water-blocking properties of the quantum dot film 420 on the side closest to the light-emitting layer and further distances the quantum dot film 420 from heat sources, preventing them from being affected.

[0381] In addition, although not shown in FIG. 29C , in some embodiments, a bonding layer may be formed on the supporting layer 422 c to be bonded to the water-blocking layer 424 .

[0382] Referring to Figure 29D , the quantum dot film 520 of this embodiment includes an active layer 521, support layers 522a, 522b, and 522c, bonding layers 523a and 523b, and a water-blocking layer 524. This embodiment is substantially similar to the embodiment shown in Figure 29C , differing from the embodiment shown in Figure 29C in that the support layer 522c of this embodiment is positioned closer to the optical adjustment layer.

[0383] In other words, the support layer 522c is disposed on a sandwich structure consisting of the active layer 521, support layers 522a and 522b, and bonding layers 523a and 523b, which is covered by the water-blocking layer 524. Furthermore, the quantum dot film 520 is connected to the optical adjustment layer via the support layer 522c. This further enhances the water-blocking properties of the quantum dot film 520 on the side closest to the optical adjustment layer.

[0384] Referring to Figure 29E , the quantum dot film 620 of this embodiment includes an active layer 621, support layers 622a, 622b, 622c, and 622d, bonding layers 623a and 623b, and a water-blocking layer 624. This embodiment is substantially similar to the aforementioned embodiments of Figures 29C and 29D , differing from the embodiments of Figures 29C and 11D in that this embodiment includes both a support layer 622c disposed near the light-emitting layer and a support layer 622d disposed further near the optical adjustment layer.

[0385] In other words, the sandwich structure consisting of the active layer 621, the supporting layers 622a and 622b, and the bonding layers 623a and 623b, which are covered by the water-blocking layer 624, is disposed between the supporting layers 622c and 622d. The quantum dot film 620 is connected to the light-emitting layer through the supporting layer 622c and to the optical adjustment layer through the supporting layer 622d.

[0386] Referring to Figure 29F , the quantum dot film 720 of this embodiment includes an active layer 721, support layers 722a and 722b, bonding layers 723a and 723b, and water-blocking layers 724a and 724b. This embodiment is substantially similar to the embodiment shown in Figure 29A , with the difference being that the water-blocking layers 724a and 724b are formed on the support layers 722a and 722b, respectively. The support layers 722a and 722b, with the water-blocking layers 724a and 724b attached thereto, then form a sandwich structure with the active layer 721 via corresponding bonding layers 723a and 723b.

[0387] In other words, the water-blocking layers 724a and 724b of this embodiment indirectly cover the lower surface (i.e., the surface closer to the light-emitting layer) and upper surface (i.e., the surface closer to the optical adjustment layer) of the active layer 721 via the bonding layers 723a and 723b, respectively. This structure can be considered as utilizing the water-blocking layers 724a and 724b to further enhance the water-blocking properties of the supporting layers 722a and 722b.

[0388] The following Figures 30 to 33 illustrate the properties of the water-blocking layer 124 made from various material embodiments. Please first refer to Figures 30 and 31 , where Figure 30 shows the chemical structure of the water-blocking layer material of the quantum dot film according to various embodiments of the present disclosure, and Figure 31 lists the mechanical properties of the water-blocking layer material according to various embodiments of the present disclosure.

[0389] FIG30 shows the chemical structures of the water-blocking layer materials of Experimental Examples 1 to 4, which are: Experimental Example 1) Parylene N, also known as N-type parylene; Experimental Example 2) Parylene C, also known as C-type parylene; Experimental Example 3) Parylene D, also known as D-type parylene; and Experimental Example 4) Parylene HT.

[0390] Figure 31 lists the mechanical properties of Experimental Examples 1-4 and Comparative Examples 1-4, where the materials used in Comparative Examples 1-4 are, in order, acrylic (AR), epoxy (ER), polyurethane (PU), and silicone (SR). The mechanical properties in Figure 31 demonstrate that the water-blocking layer formed using the materials of Experimental Examples 1-4 exhibits lower moisture and gas permeability than the materials used in Comparative Examples 1-4, while also exhibiting higher dielectric strength.

[0391] Figure 32 shows the light transmittance of Experimental Examples 1-4 at different wavelengths. From Figure 32, it can be seen that the materials of Experimental Examples 1-4 have good light transmittance when the wavelength exceeds 400nm.

[0392] Figure 33 is a flow chart of the steps of the method for manufacturing a quantum dot film according to an embodiment of the present disclosure. Referring to Figure 33, the method for manufacturing a quantum dot film according to this embodiment is suitable for manufacturing a quantum dot film as described in Figures 29A to 29F above. In the step flow of this embodiment, first, a support layer is provided (step S810), and then a bonding layer is formed on the support layer (step S820). The step of forming a bonding layer on the support layer may, for example, be coating an optical adhesive or a surface treatment agent on the support layer. After the bonding layer is formed, an active layer is formed on the support layer with the bonding layer as a connection interface (step S830). Then, a water-blocking layer is formed on at least a portion of the surface of the active layer, directly or indirectly covering the surface (step S840).

[0393] In this embodiment, although the above steps are illustrated as being performed sequentially, the present disclosure is not limited thereto. Depending on the structural configuration of the quantum dot film in actual application, the above steps may be replaced or repeated in order. For example, taking the production of the quantum dot film 220 shown in FIG. 29A as an example, in step S810, support layers 222a and 222b are provided as connecting the lower surface and upper surface of the active layer 221, respectively. Then, in step S820, adhesive materials such as optical glue or surface treatment agent are applied to the surfaces of the support layers 222a and 222b facing the active layer 221 to form bonding layers 223a and 223b. In step S830, the active layer 221 material may be coated on the bonding layer 223a and / or 223b by sandwich coating, and the active layer 221 is sandwiched between the support layers 222a and 222b to form a sandwich structure.

[0394] The intermediate product after step S830 can be cut to a size that meets the end product, and then the cut sandwich structure is subjected to step S840 to coat the surface of the sandwich structure with a water-blocking layer 224, thereby forming a structure as shown in FIG. 29A.

[0395] For example, in the production of quantum dot film 720 as shown in Figure 29F , step S810 provides support layers 722a and 722b, respectively, to connect the lower and upper surfaces of active layer 721. The process then proceeds to step S840 to form water-blocking layers 724a and 724b on the surfaces of support layers 722a and 722b, respectively. Subsequently, steps S820 and S830 are performed to combine support layers 722a and 722b, coated with water-blocking layers 724a and 724b, with active layer 721 to form a sandwich structure.

[0396] The production process of other quantum dot films 320-620 can be derived by referring to the above description, so it will not be repeated here.

[0397] The following further describes the design of the spliced ​​display device formed by splicing the display panels 100 ′.

[0398] Figure 34 is a schematic diagram of a spliced ​​display device according to an embodiment of the present disclosure. The display device 40 is composed of a plurality of display panels spliced ​​together. In this embodiment, a 3×3 splicing combination is illustrated as an example, that is, the display device 40 includes 9 display panels 200_1 to 200_9 as an example, but the present disclosure is not limited to this. The spliced ​​display panels 200_1 to 200_9 will be driven synchronously to collaboratively display the various parts of a complete image, thereby forming a larger image to achieve the effect of a large-size screen display. The display device 40 of this embodiment can be any electronic device with a display function, such as a television, a screen, an LED billboard, etc., and the present disclosure is not limited to this.

[0399] In this embodiment, at least a portion of the non-display area of ​​each display panel 200_1-200_9 is used as a splicing region JR (such as the shaded area in FIG. 34 ) to be spliced ​​with adjacent display panels 200_1-200_9. The display device 40 also includes a splicing unit (not shown) disposed in the splicing region JR. The splicing unit is used to reduce the visual effect caused by the gap at the splicing of the display panels 200_1-200_9, making the splicing seams of the display panels 200_1-200_9 less noticeable. The splicing unit can be implemented using a specific substrate structure design, additional LED light strips, or a specific optical structure, as further described in subsequent embodiments.

[0400] The display panels 200_1 to 200_9 of this embodiment can be implemented with the structural configurations of FIG. 35A to FIG. 35D according to design requirements, where FIG. 35A to FIG. 35D are schematic diagrams of configurations of display panels used in the display device of FIG. 34 according to different embodiments.

[0401] Referring first to FIG. 35A , in this embodiment, the surrounding areas of display panel 200a are defined as a splicing region JR. In other words, the non-display area of ​​this embodiment is designed as a splicing region JR for arranging splicing units. Therefore, display panel 200a of this embodiment can be used as any of display panels 200_1 to 200_9 in the spliced ​​display device 40 of FIG. 34 .

[0402] Referring again to FIG. 35B , in this embodiment, three sides of the display panel 200b are defined as the splicing region JR. Only the non-display region SR on the left short side is not defined as the splicing region JR. In other words, in this embodiment, the splicing units are only configured on the three sides of the display panel 200b defined as the splicing region JR. The display panel 200b of this embodiment can be used as the display panel 200_4 or 200_6 in the spliced ​​display device 40 of FIG. 34 .

[0403] Referring to FIG. 35C , in this embodiment, three sides of the display panel 200c are defined as the splicing region JR. Only the non-display region SR on the upper long side is not defined as the splicing region JR. In other words, in this embodiment, the splicing units are only configured on the three sides of the display panel 200c defined as the splicing region JR. The display panel 200c of this embodiment can be used as the display panel 200_2 or 200_8 in the spliced ​​display device 40 of FIG. 34 .

[0404] Referring to FIG. 35D , in this embodiment, two adjacent sides of display panel 200d are defined as splicing regions JR, while the other two opposite non-display regions SR are not defined as splicing regions JR. In other words, in display panel 200d of this embodiment, the splicing units are only configured on the adjacent long and short sides of display panel 200c defined as splicing regions JR. Display panel 200d of this embodiment can be used as display panel 200_1, 200_3, 200_7, or 200_9 in the spliced ​​display device 40 of FIG. 34 .

[0405] In addition, although not shown in the above embodiments, in some embodiments, only one side of the display panel can be defined as the splicing region JR, that is, the splicing units are only provided on a single side of the display panel. This configuration is applicable to a 2×1 spliced ​​display device, but the present disclosure is not limited thereto.

[0406] Figures 36A to 36D illustrate various embodiments of the splicing unit. Please first refer to Figure 36A, which is a schematic diagram illustrating the configuration of a display device according to one embodiment of the present disclosure. Figure 36A illustrates a partially enlarged schematic diagram of the splicing location of two adjacent display panels 300a and 300b in a display device 50. The display panels 300a and 300b have similar / identical configurations. While this embodiment illustrates the splicing of the short sides as an example, the present disclosure is not limited thereto.

[0407] The display panel 300a / 300b includes light-emitting elements LEDs, a substrate 310a / 310b, a device protection layer 320a / 320b, and a splicing unit 330a / 330b, wherein the substrate 310a / 310b includes an insulating layer 311a / 311b and a circuit layer 312a / 312b.

[0408] Here, the display panel 300b is used for illustration. The display panel 300a can be configured in the same manner as described below, so the details will not be repeated. The splicing unit 330b is disposed at the edge of the substrate 310b and covers the sidewall of the substrate 310b and the exposed edge area of ​​the circuit layer 312b (i.e., the area not covered by the device protection layer 320b), so as to form a certain thickness / distance d extending from the substrate 310b toward the adjacent substrate 310a. j The thickness d of the splicing structure described in this embodiment j It is defined as the shortest distance from the sidewall of the substrate 310b in the joint region JR to the edge of the joint unit 330b.

[0409] On the other hand, the width of the substrate 310b in the joint area JR is limited / reduced so that the distance ds between the edge of the substrate 310b and the nearest light-emitting element LEDs is limited to a certain range, wherein the distance ds is selected to have a corresponding relationship according to the spacing between the light-emitting elements LEDs. For example, when the spacing between adjacent light-emitting elements LEDs is D, the distance ds of the substrate 310b is s Add the distance d of the splicing unit 330b j Through the above configuration, when adjacent display panels 300a and 300b are spliced ​​together, the spacing between the two closest light-emitting element LEDs on the two display panels 300a and 300b can be maintained the same as that between adjacent light-emitting element LEDs within the same display panel 300a / 300b, thereby preventing a noticeable splicing gap.

[0410] As shown in the partially enlarged structure of FIG36A , the above configuration allows the spacing D between the red light-emitting element R at the edge of display panel 300b and the blue light-emitting element B at the edge of display panel 300a, which is the same as the spacing between the red light-emitting element R and the green light-emitting element G in display panel 300b. This eliminates the seam.

[0411] More specifically, the splicing unit 330a / 330b may include, for example, an extended conductive layer 331a / 331b and a sidewall protective layer 332a / 332b. The extended conductive layer 331a / 331b is electrically connected to the corresponding circuit layer 312a / 312b and extends through the sidewall of the substrate 310a / 310b to the back side of the insulating layer 311a / 311b (i.e., the side not in contact with the circuit layer 312a / 312b), so that other circuits (not shown) can be electrically connected to the light-emitting elements LEDs of the display panel 300a / 300b through the extended conductive layers 331a and 331b and the corresponding circuit layers 312a and 312b. The thickness of the extended conductive layer 331a / 331b on the sidewall of the substrate 310a / 310b is d1, that is, the extended conductive layer 331a / 331b in the splicing direction x is d1. j The thickness is d1.

[0412] The sidewall protection layer 332a / 332b covers at least a portion of the extended conductive layer 331a / 331b to prevent the adjacent extended conductive layers 331a and 331b from being accidentally short-circuited. The sidewall protection layer 332a / 332b, for example, covers at least the sidewall of the extended conductive layer 331a / 331b, that is, the side of the extended conductive layer 331a / 331b close to the adjacent substrate 310a / 310b, and has a thickness d2, that is, the sidewall protection layer 332a / 332b has a thickness of d2 in the splicing direction x. j In some embodiments, the sidewall protection layer can be made of, for example, acrylic material combined with resin.

[0413] In this embodiment, the extended conductive layer 331a / 331b and the sidewall protection layer 332a / 332b are connected in the splicing direction x. j The sum of the thicknesses (d1+d2) on the joint unit 330a / 330b is equal to the thickness d j It should be noted that the extended conductive layer 331a / 331b is in the splicing direction x j The thickness d1 of the extended conductive layer 331a / 331b is the thickness of the extended conductive layer 331a / 331b in the splicing direction x j The shortest distance between the top and the substrate 310a / 310b; and the sidewall protection layer 332a / 332b in the splicing direction x j The thickness d2 of the side wall protection layer 332a / 332b is the thickness of the side wall protection layer 332a / 332b in the splicing direction xj The shortest distance between the upper and extended conductive layers 331a / 331b is defined, but the present disclosure is not limited thereto.

[0414] The display panel 300b is also used for illustration. According to the configuration of the above embodiment, the extended conductive layer 331b and the sidewall protection layer 332b are arranged in the splicing direction x. j The thickness d1 and d2 on the substrate 310b can be the distance d s The design is matched so that the thickness d1 and d2 and the distance d s The sum of the distances D between the LEDs is substantially equal to half (i.e., D / 2). This allows the distances between the LEDs on both sides of the splicing area to be the same as the distance D between the LEDs in the display panel 300b, thereby eliminating the visual impact of the splicing seam.

[0415] FIG36B further illustrates the structural configuration of one of the display panels 300c of the display device 50 at different edges. Referring to FIG36B , this embodiment illustrates the structural differences between the non-display area SR defined as the splicing area JR and the non-display area SR not defined as the splicing area JR. For example, for the general non-display area SR on the left edge of the display panel 300c, the edge of its substrate 310c and the one / column of light-emitting elements LEDs (such as R) closest to the edge will have a wider distance to maintain the electrical connection reliability of the light-emitting elements LEDs. On the contrary, in the non-display area SR on the right, since this part of the non-display area SR needs to be provided with a splicing unit to be spliced ​​with the adjacent display panel, the original width of the substrate 310c of the non-display area SR (at the dotted line) will be reduced to a spacing that meets the above requirements. Therefore, for the display panel 30c having both a stitching area JR defined as a stitching area JR and a non-display area SR not defined as a stitching area JR, the configuration of its light-emitting elements LEDs may have an asymmetric structure in appearance, that is, some edge columns / rows of light-emitting elements LEDs may be farther away from the edge of the substrate 310c, while other edge columns / rows of light-emitting elements LEDs may be closer to the edge of the substrate 310c.

[0416] FIG36C is a schematic diagram illustrating the configuration of a display device according to another embodiment of the present disclosure, wherein this embodiment uses an optical microstructure as a splicing unit of a display device 60. Referring to FIG36C , a partially enlarged schematic diagram illustrating the splicing location of two adjacent display panels 400a and 400b in the display device 60 is shown. The display panels 400a and 400b have similar / identical configurations, and this embodiment is also illustrated using short-side splicing as an example, but the present disclosure is not limited thereto.

[0417] In this embodiment, the display device 60 further includes an optical microstructure 42 serving as a splicing unit. The optical microstructure 42 is disposed at the splicing region JR between the display panels 400a and 400b and is configured to refract adjacent light rays, allowing the refracted light rays to pass over the splicing region JR, thereby reducing the visual impact of the splicing seam. In other words, the splicing unit of this embodiment utilizes a microstructure to reduce the apparent lines at the splicing region of the display device 60 by refraction of light.

[0418] FIG36D is a schematic diagram illustrating the configuration of a display device according to another embodiment of the present disclosure, wherein this embodiment uses a lamp as an example of a splicing unit of display device 70. Referring to FIG36D , a partially enlarged schematic diagram illustrating the splicing location of two adjacent display panels 500a and 500b in display device 70 is shown. Display panels 500a and 500b have similar / identical configurations, and this embodiment also illustrates the splicing location along the short side, but the present disclosure is not limited thereto.

[0419] In this embodiment, the display device 70 further includes a light bar 52 as a splicing unit. The light bar 52 is disposed at the splicing joint JR between the display panels 500a and 500b and is configured to emit controlled light to reduce the visual impact of the splicing seam.

[0420] Specifically, for the splicing unit embodiments shown in Figures 36A to 36D above, the embodiments described in Figures 36A and 36B use structural configuration to make the spacing between the light-emitting elements at the joint equal to the spacing between the light-emitting elements within the panel, thereby eliminating the effect of the splicing seam. Therefore, the embodiments of Figures 36A and 36B only need to set the substrate within the required specifications and add simple structures (such as the extended conductive layer 331b and the sidewall protection layer 332b) to achieve the effect of eliminating the splicing seam. Compared with the embodiments of Figures 37 and 38, the embodiments of Figures 36A and 36B do not require the addition of additional devices such as the optical microstructure 42 or the light bar 52, which has a significant advantage in terms of manufacturing cost.

[0421] Furthermore, whether it is the secondary construction of the splicing unit, such as the embodiment of Figure 36C or Figure 36D, there is no way to make the pixels in the splicing area JR emit light in an orderly manner. Therefore, it can only make the splicing lines less obvious. The splicing effect still has visible splicing stripes or optical color aberration when viewed directly. In contrast, the embodiments of Figures 36A and 36B do not have this problem and can provide a better display effect.

[0422] In general, the above-mentioned embodiments of Figures 36A and 36B define the pixel size based on the size of the LED chip and the resolution requirements of the product, change the distance from the edge of the light-emitting element to the edge of the substrate in the splicing area JR, and then match the thickness of the side extension conductive layer and the thickness of the side wall protective layer. Taking into account all production process tolerances, they perfectly solve the problem of transitioning from one display panel to another in the splicing display device, making the splicing lines in the splicing area difficult for users to observe, and there will be no color deviation or discontinuity in the display caused by the light strips, achieving a perfect splicing display effect, and no need for additional components and assembly costs.

[0423] Figure 37 is a flow chart of the steps of a method for manufacturing a display panel according to an embodiment of the present disclosure. Referring to Figure 37, the method for manufacturing a display panel according to the present embodiment is suitable for manufacturing the display panel as described in Figures 34 to 36B. In the step flow of the present embodiment, the display area (such as DR) and the non-display area (such as SR) of the display panel are first defined according to the size of the light-emitting elements and the resolution requirements used in the display panel to be manufactured, wherein the light-emitting elements in the display area are set to have a first spacing (step S910). The size of the light-emitting element may be, for example, between 2μm and 5μm, but the present disclosure is not limited thereto. The first spacing will be related to the size of the display panel, the size of the light-emitting element and the resolution requirements, and may be, for example, between 40μm and 100μm, but the present disclosure is not limited thereto.

[0424] Next, according to the splicing requirements of the display panel, a splicing area (such as JR) is defined from the non-display area (step S920). Similar to the embodiments described in Figures 35A to 35D above, the display panel can have different splicing area JR configurations according to its splicing position.

[0425] After defining the stitching area, the width of the substrate in the stitching area is reduced so that a second spacing exists between the edge of the substrate and the nearest light-emitting element (step S930). In step S930, the width of the substrate can be reduced by cutting and / or grinding. In actual applications, the second spacing is related to the allowable manufacturing process tolerance in subsequent manufacturing processes and can be, for example, between 10 μm and 20 μm, but the present disclosure is not limited thereto.

[0426] Next, a splicing unit (such as 330a / 330b) is provided at the reduced edge of the substrate in the splicing area to cover the sidewall of the substrate, wherein the thickness of the splicing unit on the sidewall of the substrate is equal to the difference between half of the first spacing and the second spacing (step S940). The relationship between the thickness of the splicing unit, the first spacing, and the second spacing can be expressed by the following formula:

[0427] d j =D / 2-ds ;

[0428] where d j is the thickness of the splicing unit, D is the first spacing, and d s In some embodiments, the thickness d of the splicing unit is j For example, the thickness may be between 10 μm and 30 μm, but the present disclosure is not limited thereto.

[0429] It should be noted that if the present disclosure defines the relationship between the thickness, first spacing, and second spacing of the above-mentioned splicing unit in the claims, those skilled in the art should understand that the above three must be within the feasible range, and the numerical combination that does not fall within the feasible range does not fall within the scope of the claims, so there is no support or implementation problem. For example, if the first spacing D is equal to 40μm, then the thickness d of the splicing unit is j and the second spacing d s The sum of the distances d is 20 μm. s The feasible implementation range of may be, for example, between 10 μm and 20 μm, but those skilled in the art will appreciate that under this configuration, the second spacing d s It will not be 20μm, because this will cause the thickness of the splicing unit to be j Falling into the unfeasible range.

[0430] It should also be noted that although steps S930 and S940 are depicted as being performed sequentially, the present disclosure is not limited thereto. In some embodiments, the display panel manufacturing method may also perform step S940 first and then step S930, i.e., first determining the thickness of the splicing unit and then determining the substrate width to be reduced.

[0431] In some embodiments, step S940 may include forming an extended conductive layer (such as 331a / 331b) at the edge of the substrate covering the sidewall of the substrate and at least part of the insulating layer, and then forming a sidewall protection layer (such as 332a / 332b) covering at least part of the extended conductive layer, wherein the extended conductive layer has a first thickness on the sidewall of the substrate, and the sidewall protection layer has a second thickness on the sidewall of the extended conductive layer, and the sum of the first thickness and the second thickness is equal to the thickness of the splicing unit.

[0432] Specifically, after the size and resolution of the product are determined, the product design and development department will define the specifications and size of the LED during the product development stage. In the manufacturing method of this embodiment, the allowable manufacturing process tolerance of the subsequent manufacturing process can be increased by selecting LED chips with the minimum particle size that meets the product specification requirements. Furthermore, by concentrating the metal circuit area on the display panel circuit layer as much as possible or close to the LED chip, the non-display area can be left empty to maximize the specifications and tolerances of the splicing area cutting and grinding area. After determining the thickness of the extended conductive layer (such as d1) and the thickness of the side wall protection layer (such as d2) required for splicing, the distance from the area where the substrate needs to be cut on the splicing side to the outermost LED chip (such as d s ), so that the thickness of the extended conductive layer on the side to be spliced ​​(such as d1) and the thickness of the side wall protection layer (such as d2) plus the distance from the side of the LED to the side of the substrate (such as d s ), the total length of the three added together will be equal to half of the distance between the two LEDs (such as D). The mathematical formula is: d s +d1+d2=D / 2.

[0433] When the display panels manufactured by the above-mentioned display panel manufacturing method are spliced, theoretically, the LED spacing in the splicing area will be the same as the spacing within the display panel, thereby obtaining a perfect splicing result. In this way, no additional microstructure or light strip is required to make the splicing unit. As for the selection of materials for the extended conductive layer and the sidewall protective layer in the splicing area, it is necessary to take into account the electrical requirements and the subsequent requirements of the LED light emission in the splicing area, so that the dimming can take into account the requirements of brightness and color light. In some embodiments, the sidewall protective layer can be selected from a material that is structurally scratch-resistant, wear-resistant and can protect the extended conductive layer to avoid separation or disconnection problems.

[0434] The following further describes the driving portion of the display device 10 - 70 .

[0435] The functional module configuration of each scanning unit 121_1-121_m in the scan driver circuit 120' described in this embodiment can be shown in Figure 38, which is a schematic diagram of the scan driver circuit in some embodiments of the present disclosure. Referring to Figure 38, the scanning unit 121a in this embodiment can represent the scanning unit connected to the a-th scan line (i.e., a can be any natural number between 1 and m). In this embodiment, the scanning unit 121a includes a first module MD1, a second module MD2, and a third module MD3.

[0436] The first module MD1 is electrically connected to the scanning output terminal G of the scanning unit of the first two stages. a-2 And the scan output G of the scanning unit of the last two stages a+2 , and based on the scan output G a-2 and Ga+2 The second module MD2 is electrically connected to the first module MD1 through the node N1, and determines the output from the scan output terminal G according to the drive signal on the node N1, the clock signal CK1 / CK3 and the reference signal VSS. a The third module MD3 is electrically connected to the second module MD2 and the scan output terminal G a , and determines the output from the scan output terminal G according to the clock signal CK3 / CK4 and the reference signal VSS. a The pull-down time point of the output scan signal.

[0437] In some embodiments, clock signals CK1-CK4 have different phases. In some embodiments, clock signals CK1 and CK2 are in phase with each other, and clock signals CK3 and CK4 are in phase with each other. In some embodiments, the phase of clock signal CK3 lags approximately 90 degrees behind the phase of clock signal CK1, the phase of clock signal CK2 lags approximately 90 degrees behind the phase of clock signal CK3, and the phase of clock signal CK4 lags approximately 90 degrees behind the phase of clock signal CK2.

[0438] In some embodiments, the circuit configuration of the scan driving circuit 120' may be as shown in Figures 39A and 39B, and Figure 40A is a signal waveform schematic diagram of the scan driving circuit of Figures 39A and 39B, where Figure 39A is a circuit configuration of the scanning unit 121_x, and Figure 39B is a circuit configuration of the scanning unit 121_y.

[0439] Referring first to FIG. 39A and FIG. 40A , the scanning unit 121_x of this embodiment includes transistors M1-M7 and capacitors C1 and C2. Transistors M1 and M2 may constitute the first module MD1 described in FIG. 38 , transistors M3-M5 and capacitors C1 and C2 may constitute the second module MD2 described in FIG. 38 , and transistors M6 and M7 may constitute the third module MD3 described in FIG. In other words, the first module MD1 of FIG. 38 may, for example, include transistors M1 and M2, the second module MD2 may, for example, include transistors M3-M5 and capacitors C1 and C2, and the third module MD3 may, for example, include transistors M6 and M7. However, the present disclosure is not limited to this.

[0440] In this embodiment, transistors M1-M7 each have a first terminal, a second terminal, and a control terminal. Each transistor M1-M7 may be, for example, an N-type transistor or a P-type transistor, but the present disclosure is not limited thereto. If the transistor is an N-type transistor, the first terminal may be, for example, a drain, the second terminal may be, for example, a source, and the control terminal may be, for example, a gate. If the transistor is a P-type transistor, the first terminal may be, for example, a source, the second terminal may be, for example, a drain, and the control terminal may be, for example, a gate.

[0441] The first terminal of the transistor M1 is used to receive the first scan control signal D2U, the second terminal of the transistor M1 is electrically connected to the node N1, and the control terminal of the transistor M1 is used to receive the scan output terminal G of the first two stages of the scan unit. x-2 The first end of the transistor M2 is electrically connected to the second end of the transistor M1. The second end of the transistor M2 is used to receive the second scan control signal U2D, and the control end of the transistor M2 is used to receive the scan output end G of the scan unit of the next two stages. x+2 .

[0442] The first end of transistor M3 is electrically connected to the second end of transistor M1 and the first end of transistor M2 via node N1, and the second end of transistor M3 is used to receive clock signal CK1. The first end of transistor M4 is electrically connected to the control end of transistor M3, and the second end of transistor M4 is used to receive reference signal VSS, and the control end of transistor M4 is electrically connected to node N1. The reference signal VSS in this embodiment is a reference low level as an example. The first end of transistor M5 is electrically connected to the scan output terminal G of scan unit 121_x. x The second end of the transistor M5 is used to receive the clock signal CK1, and the control end of the transistor M5 is electrically connected to the first end of the transistor M3 and the node N1. The first end of the capacitor C1 is electrically connected to the control end of the transistor M3 and the first end of the transistor M4, and the second end of the capacitor C1 is used to receive the clock signal CK1. The first end of the capacitor C2 is electrically connected to the first end of the transistor M5 and the scan output terminal G x , and a second end of the capacitor C2 is electrically connected to the first end of the transistor M3, the control end of the transistor M5 and the node N1.

[0443] The first terminal of the transistor M6 is electrically connected to the scan output terminal G x The second end of the transistor M6 is used to receive the reference signal VSS, and the control end of the transistor M6 is electrically connected to the control end of the transistor M3, the first end of the transistor M4 and the first end of the capacitor C1. The first end of the transistor M7 is electrically connected to the first end of the transistor M6 and the scan output terminal G xThe second terminal of the transistor M7 is used to receive the reference signal VSS, and the control terminal of the transistor M7 is used to receive the clock signal CK2.

[0444] Referring next to FIG. 39B , scanning unit 121_y in this embodiment includes transistors M8-M14 and capacitors C3 and C4. Transistors M8-M14 are configured similarly to transistors M1-M7 in the embodiment of FIG. 39A , and capacitors C3 and C4 are configured similarly to capacitors C1 and C2 in the embodiment of FIG. This embodiment differs from the embodiment of FIG. 39A in that transistors M10-M12 operate primarily with reference to clock signal CK3 , and transistor M14 operates with reference to clock signal CK4 . Other connections refer to the description of the previous embodiment and are not repeated here.

[0445] FIG40A is a schematic diagram of signal waveforms for the scan driving circuit described in FIG39A and FIG39B. Referring to FIG39A, FIG39B, and FIG40A, in this embodiment, the first scan control signal D2U is stably maintained at a DC high level VGH, the second scan control signal U2D is stably maintained at a DC low level VGL, and the clock signals CK1, CK3, CK2, and CK4 are sequentially phase-delayed 90 degrees, with a duty cycle of approximately 0.5. However, the present disclosure is not limited to this embodiment.

[0446] Through the above circuit configuration and signal input, the scanning unit 121_x can scan the output terminal G x The phase generated is roughly behind the scan output G x-2 The signal on the scan output G is 180 degrees and roughly leads x+2 The scanning signal of 180 degrees on the signal is used to drive the corresponding odd-numbered scanning line, and the scanning unit 121_y can be output at the scanning output terminal G y The phase generated is roughly behind the scan output G y-2 The signal on the scan output G is 180 degrees and roughly leads y+2 The 180-degree scanning signal on the signal drives the corresponding even-numbered scanning lines.

[0447] However, because the driving architectures of Figures 39A and 39B require a DC voltage to control the operation of the transistors, applying a DC voltage to the transistors for a long time can easily cause the transistor characteristics to shift, thereby causing display anomalies in the display panel during long-term use or aging testing. For example, referring to Figures 39A and 39B, transistors M1 / M8 continuously receive a DC voltage from the first scan control signal D2U during operation. As the operating time increases, the current-voltage characteristic curve (IV curve) of transistors M1 / M8 gradually shifts to the right, causing the leakage current of transistors M1 / M8 to gradually increase. Over time, this can cause display anomalies.

[0448] In addition, with the configurations of FIG. 39A and FIG. 39B , at least seven signal lines must be provided on the display panel to provide the control signals and clock signals (such as U2D, D2U, CK1-CK4, VSS, etc.) required for the operation of the scanning units 121_x / 121_y. This limits the size of the non-display area of ​​the display panel, making a narrow-frame design difficult to implement. In order to address the above-mentioned issues and effectively improve the quality of the display panel and extend the service life of the display panel under the GOP packaging architecture, and further implement a narrow-frame design, the embodiments of the present disclosure propose an improved control method for a scan drive circuit and a new circuit design.

[0449] Please refer to FIG39A, FIG39B and FIG40B, wherein FIG40B is a schematic diagram of signal waveforms of a control method of the scan driving circuit in one embodiment of the present disclosure. The main difference between this embodiment and the control method of the embodiment of FIG40A is that the first scan control signal D2U of this embodiment is a first scan output terminal G2U of the first two scan units. x-2 A pulse signal that is synchronized with the signal on the .

[0450] When controlled using the signal waveforms shown in FIG40B , transistors M1 / M8 are only applied a high-level first scan control signal D2U to their first terminals when their control terminals receive a high-level signal. Otherwise, the first terminals of transistors M1 / M8 remain at a low level during the display period of a single frame. This control method significantly shortens the time that transistors M1 / M8 withstand DC voltage, making transistors M1 / M8 less susceptible to characteristic shift, thereby further extending the life of the display panel.

[0451] 39A, 39B, and 40C, wherein FIG40C is a schematic diagram of signal waveforms of a control method for the scan driving circuit according to another embodiment of the present disclosure. The main difference between this embodiment and the control method of the embodiment shown in FIG40B is that the first scan control signal D2U is a pulse signal, for example, a pulse signal synchronized with the clock signal CK2.

[0452] Similarly, when controlled by the signal waveform shown in FIG40C , the period during which transistors M1 / M8 receive a DC voltage in each frame is only half that of FIG40A (using a pulse signal with a duty cycle of 0.5 as an example, but the present disclosure is not limited thereto). Therefore, transistors M1 / M8 are not affected by the high-level DC voltage for most of the time. It should be noted that the first scan control signal D2U of this embodiment can also be a pulse signal that is not synchronized with the clock signal CK2. As long as the control terminal of transistors M1 / M8 receives a high-level signal, the signal will remain at a high level, so that transistors M1 / M8 can operate normally.

[0453] Please refer to Figures 39A, 39B and 40D, where Figure 40D is a schematic diagram of signal waveforms of a control method for the scan drive circuit according to another embodiment of the present disclosure. The main difference between this embodiment and the control method of the embodiment shown in Figure 40B is that the first scan control signal D2U is a pulse signal whose pulse period partially overlaps with the clock signal CK2. In this embodiment, the first scan control signal D2U is connected to the scan output terminal G x-2 / G y-2 The signals on the CMOS are converted to high level at about the same time and are output at the scan output G x+2 / G y+2 When the signal on the scanning output terminal G is converted to a low level, it is converted to a low level at about the same time. In other words, the pulse period of the first scanning control signal D2U is about x-2 / G y-2 The pulse period of the signal is tripled, but the present disclosure is not limited thereto.

[0454] Similarly, when controlled by the signal waveform shown in Figure 40D, the period during which transistor M1 / M8 receives DC voltage in each frame is only the length of the three pulse periods of clock signals CK1-CK4, so transistor M1 / M8 is not affected by high-level DC voltage most of the time.

[0455] In short, according to the embodiments described in Figures 40B to 40D above, as long as the first scanning control signal D2U received by the first terminal of the transistor M1 / M8 undergoes a level change at least once during each frame period, causing the signal level to drop from a high level to a low level, and during the period when the signal received by the control terminal of the transistor M1 / M8 is at a high level, the first scanning control signal D2U received by the first terminal of the transistor M1 / M8 is also maintained at a high level, the above-mentioned reduction in the long-term influence of the DC voltage on the transistor M1 / M8 can be achieved.

[0456] In some embodiments, the first scan control signal D2U maintains a high level for no more than 30% of each frame period (i.e., a pulse period). In some embodiments, the first scan control signal D2U maintains a high level for 1%-10% of each frame period. However, the present disclosure is not limited thereto.

[0457] Figures 41A and 41B are schematic circuit diagrams of scan drive circuits according to some embodiments of the present disclosure, which can be used to implement the control method described in Figure 40B above. Referring first to Figure 41A , the scan unit 121_x of this embodiment includes transistors M1-M7 and capacitors C1 and C2. Transistors M1 and M2 may form a first module MD1 as described in Figure 41 , transistors M3-M5 and capacitors C1 and C2 may form a second module MD2 as described in Figure 41 , and transistors M6 and M7 may form a third module MD3 as described in Figure 41 . In other words, the first module MD1 in Figure 41 may, for example, include transistors M1 and M2, the second module MD2 may, for example, include transistors M3-M5 and capacitors C1 and C2, and the third module MD3 may, for example, include transistors M6 and M7. However, the present disclosure is not limited to this.

[0458] In this embodiment, the configuration of transistors M1-M7 is similar to that of the transistors M1-M7 in the embodiment of FIG39A , and the configuration of capacitors C1 and C2 is similar to that of capacitors C1 and C2 in the embodiment of FIG39A . Therefore, similar or identical parts can be referred to the description of FIG39A , and will not be repeated here.

[0459] The main difference between this embodiment and the embodiment of FIG. 39A is that the first terminal of the transistor M1 is electrically connected to its control terminal to utilize the scan output terminal G of the first two stages. x-2 In addition, the second end of the transistor M2 is electrically connected to a signal line having a reference signal VSS for replacing the original second scan control signal U2D with the reference signal VSS.

[0460] From another perspective, the transistor M1 is equivalent to a diode element through the connection configuration as shown in Figure 41A. Therefore, when the control end of the transistor M1 is applied with a scan signal of an enable level (such as a high level), the transistor M1 can directly transfer the enable level to its second end.

[0461] Referring next to FIG. 41B , the scanning unit 121_y of this embodiment includes transistors M8-M14 and capacitors C3 and C4. Transistors M8 and M9 may constitute the first module MD1 described in FIG. 38 , transistors M10-M12 and capacitors C3 and C4 may constitute the second module MD2 described in FIG. 38 , and transistors M13 and M14 may constitute the third module MD3 described in FIG. In other words, the first module MD1 of FIG. 38 may, for example, include transistors M8 and M9, the second module MD2 may, for example, include transistors M10-M12 and capacitors C3 and C4, and the third module MD3 may, for example, include transistors M13 and M14. However, the present disclosure is not limited thereto.

[0462] In this embodiment, the configuration of transistors M8-M14 is similar to that of transistors M8-M14 in the embodiment of FIG. 39B , and the configuration of capacitors C3 and C4 is similar to that of capacitors C3 and C4 in the embodiment of FIG. Therefore, similar or identical parts can be referred to the description of FIG. 39B , and will not be repeated here.

[0463] Similar to the embodiment of FIG. 41A , the main difference between this embodiment and the embodiment of FIG. 39B is that the first terminal of the transistor M8 is electrically connected to its control terminal to utilize the scan output terminal G of the first two stages. y-2 The control terminal of transistor M8 is electrically connected to a signal line having a reference signal VSS, so as to replace the original second scan control signal U2D with the reference signal VSS. From another perspective, transistor M8 is equivalent to a diode element through the connection configuration shown in FIG41B . Therefore, when a scan signal having an enable level (e.g., a high level) is applied to the control terminal of transistor M8, transistor M8 can directly transmit the enable level to its second terminal.

[0464] More specifically, as shown in FIG40A , because the first scan control signal D2U is a DC high level and the second scan control signal U2D is a DC low level. For transistors M1 / M8, as long as they are turned on (i.e., when the control terminal receives the enabled scan signal), their first terminals can receive a DC high level, which does not affect the operation of transistors M1 / M8. Similarly, for transistors M2 / M9, electrically connecting their second terminals to the reference signal VSS has the same effect as connecting to the second scan control signal U2D. Therefore, by electrically connecting the first terminals of transistors M1 / M8 to their control terminals, the scan output terminals G of the first two stages are connected to the reference signal VSS. x-2 / G y-2 The scanning signal of the transistor M2 / M9 is used as the first scanning control signal D2U, and the second end of the transistor M2 / M9 is electrically connected to the signal line transmitting the reference signal VSS. In this configuration, the signal line for transmitting the first scanning control signal D2U and the second scanning control signal U2D can be omitted, thereby further reducing the width of the non-display area of ​​the display panel.

[0465] Figures 41C and 41D are schematic circuit diagrams of scan drive circuits according to other embodiments of the present disclosure, which can be used to implement the control method described in Figure 40C . Referring first to Figure 41C , the scan unit 121_x of this embodiment includes transistors M1-M7 and capacitors C1 and C2. Transistors M1 and M2 may form the first module MD1 described in Figure 38 , transistors M3-M5 and capacitors C1 and C2 may form the second module MD2 described in Figure 38 , and transistors M6 and M7 may form the third module MD3 described in Figure 38 . In other words, the first module MD1 of Figure 38 may, for example, include transistors M1 and M2, the second module MD2 may, for example, include transistors M3-M5 and capacitors C1 and C2, and the third module MD3 may, for example, include transistors M6 and M7. However, the present disclosure is not limited to this embodiment.

[0466] In this embodiment, the configuration of transistors M1-M7 is similar to that of the transistors M1-M7 in the embodiment of FIG39A , and the configuration of capacitors C1 and C2 is similar to that of capacitors C1 and C2 in the embodiment of FIG39A . Therefore, similar or identical parts can be referred to the description of FIG39A , and will not be repeated here.

[0467] The main difference between this embodiment and the embodiment of FIG. 39A is that the first terminal of transistor M1 is electrically connected to a signal line of clock signal CK2, thereby replacing the first scanning control signal D2U, which is originally a DC high level, with the clock signal CK2. Furthermore, the second terminal of transistor M2 is electrically connected to a signal line of reference signal VSS, thereby replacing the second scanning control signal U2D with the reference signal VSS.

[0468] Referring next to FIG. 41D , the scanning unit 121_y of this embodiment includes transistors M8-M14 and capacitors C3 and C4. Transistors M8 and M9 may constitute the first module MD1 described in FIG. 38 , transistors M10-M12 and capacitors C3 and C4 may constitute the second module MD2 described in FIG. 38 , and transistors M13 and M14 may constitute the third module MD3 described in FIG. In other words, the first module MD1 of FIG. 38 may, for example, include transistors M8 and M9, the second module MD2 may, for example, include transistors M10-M12 and capacitors C3 and C4, and the third module MD3 may, for example, include transistors M13 and M14. However, the present disclosure is not limited thereto.

[0469] In this embodiment, the configuration of transistors M8-M14 is similar to that of transistors M8-M14 in the embodiment of FIG. 39B , and the configuration of capacitors C3 and C4 is similar to that of capacitors C3 and C4 in the embodiment of FIG. Therefore, similar or identical parts can be referred to the description of FIG. 39B , and will not be repeated here.

[0470] Similar to the embodiment of FIG. 41A , the primary difference between this embodiment and the embodiment of FIG. 39B is that the first terminal of transistor M8 is electrically connected to a signal line for clock signal CK4, thereby replacing the previously high DC first scan control signal D2U with the clock signal CK4. Furthermore, the second terminal of transistor M9 is electrically connected to a signal line for reference signal VSS, thereby replacing the previously high DC second scan control signal U2D with the reference signal VSS.

[0471] More specifically, through the above configuration, when transistor M1 / M8 is turned on (i.e., when the control terminal receives an enabled scan signal), a DC high level can be applied to the first terminal of transistor M1 / M8 via clock signal CK2 / CK4, without affecting the operation of transistor M1 / M8. Similarly, for transistor M2 / M9, electrically connecting its second terminal to the reference signal VSS has the same effect as connecting it to the second scan control signal U2D. Therefore, by electrically connecting the first terminal of transistor M1 / M8 to the signal line of clock signal CK2 / CK4, thereby using clock signal CK2 / CK4 as the first scan control signal D2U, and electrically connecting the second terminal of transistor M2 / M9 to the signal line transmitting the reference signal VSS, the signal lines used to transmit the first scan control signal D2U and the second scan control signal U2D can be omitted, thereby further reducing the width of the non-display area of ​​the display panel.

[0472] The configuration of the data driver circuit 130' can be shown in Figure 42, which is a schematic diagram of a data driver circuit according to one embodiment of the present disclosure. Referring to Figure 42, the data driver circuit 130' of this embodiment includes a driver circuit board 131', a functional unit 132', a first electrical connection unit 133', and a second electrical connection unit 134'. The functional unit 132', the first electrical connection unit 133', and the second electrical connection unit 134' are all disposed on the driver circuit board 131'. That is, the driver circuit board 131' can be, for example, the substrate of the data driver circuit 130'. The functional unit 132' is located between the first electrical connection unit 133' and the second electrical connection unit 134' and includes circuitry for generating drive signals. The first electrical connection unit 133' is coupled to the first transmission unit WR1 and serves as a signal output interface for the functional unit 132', transmitting the drive signals generated by the functional unit 132' to the pixel array 111' via the first transmission unit WR1. The second electrical connection portion 134 ′ is coupled to the second transmission portion WR2 and serves as a signal input interface of the functional portion 132 ′ to transmit the data control signal on the second transmission portion WR2 to a specific circuit in the functional portion 132 ′.

[0473] The first electrical connection portion 133' and the second electrical connection portion 134' may each include, for example, a plurality of connection terminals, each of which may be connected to a transmission line in the corresponding transmission portion WR1 / WR2 to achieve electrical connection. In some embodiments, the electrical connection portion 133' / 134' and the corresponding transmission portion WR1 / WR2 may be electrically connected using a bump press-fit process, and thus the plurality of connection terminals may be a plurality of bumps, but the present disclosure is not limited thereto.

[0474] In terms of the connection configuration between the display panel 100' and the data driver circuit 130', the non-display area SR of the display panel 100', located on the side where the data driver circuit 130' is located, generally has a larger width. The width of this area is primarily determined by the dimensions of the first transmission portion WR1, the data driver circuit 130', the second transmission portion WR2, and the flexible printed circuit board 140', and also determines the bezel width of the display device 100. The bezel width at the bottom of the display device 100 is essentially equal to the sum of the widths of the transmission portions WR1 and WR2 on the substrate 111', the width of the data driver circuit 130', and the width of the portion of the flexible printed circuit board 140' attached to the substrate 111'. The width described in this embodiment refers to the length along the y-axis.

[0475] To ensure reliable signal transmission, the first transmission portion WR1, the second transmission portion WR2, and the connection terminals on the flexible printed circuit board 140' all meet specific specifications. For example, the connection terminals of the flexible printed circuit board 140' attached to the substrate 111' can be rectangular solder pads. The length and width of these solder pads ensure reliable signal transmission and also affect the bonding strength between the flexible printed circuit board 140' and the substrate 111'. To shorten the solder pad length, in order to achieve the same / similar conductivity, a more conductive adhesive must be used, which increases costs.

[0476] Furthermore, the length, width, and turning angle of the transmission lines of the transmission sections WR1 / WR2 are subject to certain requirements based on the size of the display panel 100', the size and number of the connection terminals, and the relative positions of the components at both ends of the transmission sections WR1 / WR2 to ensure transmission reliability. For example, wiring specifications for transmission lines prohibit routing at right or sharp angles to prevent charge concentration at the trace tips from affecting signal transmission.

[0477] Furthermore, the size of the data driver circuit 130' and the relative positioning between the data driver circuit 130' and the flexible printed circuit board 140' also affect the routing and length of the second transmission unit WR2. For example, because the width of the integrated data driver circuit 130' is generally smaller than the width of the flexible printed circuit board 140', the lateral spacing between the connection terminals near the edge (leftmost or rightmost) of the second electrical connection portion 134' and the corresponding solder pads on the flexible printed circuit board 140' is larger. As a result, the transmission line of the second transmission unit WR2 cannot be routed along the shortest path, requiring additional line segments to ensure that the routing method complies with the specification. This situation is also one of the main reasons why the size of the second transmission unit WR2 cannot be reduced.

[0478] The aforementioned limitations are the reason why narrow-frame designs are difficult to achieve in a COG packaging architecture. To address these issues and achieve narrow-frame designs in a COG packaging architecture, the present disclosure proposes a configuration of a data driver circuit 130', as shown in Figures 43A to 43C. Figures 43A to 43C are schematic diagrams of the configuration of a data driver circuit according to one embodiment of the present disclosure.

[0479] Please first refer to Figures 43A and 43B. In this embodiment, the first electrical connection portion 133' of the data driving circuit 130' includes a plurality of connection terminals Po, and the second electrical connection portion 134' includes a first connection unit 134a and a second connection unit 134b, wherein the first connection unit 134a and the second connection unit 134b respectively include a plurality of connection terminals Pa and Pb.

[0480] In the first electrical connection portion 133', the plurality of connection terminals Po are arranged in sequence along the horizontal direction on the upper side of the driver circuit board 131'. Conversely, in the second electrical connection portion 134', the connection terminals Pa and Pb in the first connection unit 134a and the second connection unit 134b are arranged in sequence along the horizontal direction on the lower side of the driver circuit board 131'. The connection terminals Pa in the first connection unit 134a and the connection terminals Pb in the second connection unit 134b are arranged at different distances from the edge of the driver circuit board 131' (also known as the inter-substrate spacing).

[0481] As shown in FIG43B , in this embodiment, the distance Ha between the connection terminal Pa and the edge of the driver circuit board 131' is smaller than the distance Hb between the connection terminal Pb and the edge of the driver circuit board 131'. That is, the connection terminal Pa in the first connection unit 134a is closer to the edge of the driver circuit board 131' than the connection terminal Pb in the second connection unit 134b. The distance described in this embodiment refers to the shortest distance from the side of the connection terminal Pa / Pb closest to the edge of the driver circuit board 131' to the edge of the driver circuit board 131'.

[0482] With the above configuration, since the connection terminal Pb is retracted closer to the functional portion 132 ′, the second transmission portion WR2 can have a larger wiring space, thereby effectively shortening the wiring length of the second transmission portion WR2 on the substrate.

[0483] Specifically, the relative configuration between the data driving circuit 130' and the transmission lines of the first transmission part WR1 and the second transmission part WR2 can be as shown in Figure 43C, wherein the trace width formed by the first transmission part WR1 on the substrate is HWR1, the width of the driving circuit board 131' is Hd, the trace width formed by the second transmission part WR2 on the substrate is HWR2, and the width of the part of the flexible circuit board 140' attached to the substrate is Hfp. The sum of the above widths defines the limit of the minimum border width.

[0484] Since the connection terminal Pb of the second connection unit 134b is connected to the corresponding solder pad Ps on the rightmost side of the flexible circuit board 140', the routing between the two must maintain a certain distance (e.g., Hb + HWR2) to comply with routing specifications. In this embodiment, since the second transmission portion WR2 connecting the second connection unit 134b can form a transmission line TL using the area from the connection terminal Pb to the edge of the driver circuit board 131' (i.e., the area at a distance Hb), the routing width HWR2 caused by the transmission line TL on the substrate can be relatively shortened. In other words, because part of the line segment of the transmission line TL overlaps with the area of ​​the driver circuit board 131', the portion exposed outside the driver circuit board 131' can be relatively reduced, thereby reducing the width of the frame.

[0485] It should be noted that although the drawings illustrate that the connection terminals Pa in the first connection unit 134a have the same / similar pitch Ha, and the connection terminals Pb in the second connection unit 134b have the same / similar pitch Hb, the present disclosure is not limited to this. In some embodiments, some or all of the connection terminals Pa / Pb in the first connection unit 134a and the second connection unit 134b may have different pitches.

[0486] Furthermore, although the figures illustrate only a single second connection unit 134b located to the right of the first connection unit 134a, the present disclosure is not limited thereto. In some embodiments, there may be multiple second connection units 134b, and they may be disposed to the left of the first connection unit 134a or arranged in an alternating pattern with the first connection unit 134a.

[0487] In other words, any configuration in which the data driver circuit 130' includes at least two connection terminals with different spacings, such that the connection terminals with a larger spacing provide more wiring space for the transmission lines, thereby shortening the line width on the substrate, falls within the scope of protection of this disclosure. The following embodiments will further illustrate several different exemplary configurations.

[0488] Figures 44A to 44D are partially enlarged schematic diagrams of the electrical connection portion of the data driver circuit according to various embodiments of the present disclosure. Referring first to Figure 44A, in this embodiment, the data driver circuit 230' includes a driver circuit board 231', a first connection unit 234a, and a second connection unit 234b. In the first connection unit 234a, the distance between the connection terminal Pa and the edge of the driver circuit board 231' is Ha. In the second connection unit 234b, the distance between each connection terminal Pb and the edge of the driver circuit board 231' varies and increases sequentially from left to right. For example, the distance between the connection terminal Pb1 located to the right of the connection terminal Pa and the edge of the driver circuit board 231' is Hb1, where Hb1 is greater than Ha. The distance between the connection terminal Pb2 located to the right of the connection terminal Pb1 and the edge of the driver circuit board 231' is Hb2, where Hb2 is greater than Hb1. In other words, in this embodiment, the second connection unit 224b includes at least two connection terminals Pb1 and Pb2, and the distance Hb2 from the connection terminal Pb2 to the edge of the driving circuit board 231' is greater than the distance Hb1 from the connection terminal Pb1 to the edge of the driving circuit board 231'.

[0489] Referring to Figure 44B , in this embodiment, the data driver circuit 330' includes a driver circuit board 331', a first connection unit 334a, and a second connection unit 334b. This embodiment has a substantially similar configuration to the embodiment shown in Figure 44A , differing only in that the connection terminals in the second connection unit 334b ​​can be divided into multiple groups, with the connection terminals in different groups having different inter-substrate spacings, while the connection terminals within the same group have the same inter-substrate spacings. As shown in Figure 44B , two connection terminals Pb1 are in the same group, while two connection terminals Pb2 are in another group. The inter-substrate spacings of connection terminals Pb1 are Hb1, while the inter-substrate spacings of connection terminals Pb2 are Hb2, which is greater than Hb1.

[0490] Referring to Figure 44C , in this embodiment, the data driver circuit 430' includes a driver circuit board 431', a first connection unit 434a, and a second connection unit 434b. This embodiment has substantially the same configuration as the embodiment shown in Figures 43A to 43C , differing only in that, in addition to the different substrate spacings, the connection terminals Pa and Pb also have different terminal sizes. For example, in this embodiment, the connection terminals Pa and Pb can be rectangular bumps, where the length HPa of the connection terminal Pa is greater than the length HPb of the connection terminal Pb, and the width WPa of the connection terminal Pa is less than the width WPb of the connection terminal Pb. In this way, in addition to increasing the substrate spacing by retracting the position of the connection terminal Pb, the substrate spacing can be further increased by reducing the bump length, while simultaneously increasing the bump width to ensure that conductivity is not affected.

[0491] In some embodiments, connecting terminal Pb can also achieve the effect of increasing the inter-substrate pitch by simply reducing the bump length. That is, in this embodiment, the top of connecting terminal Pb can be substantially aligned with connecting terminal Pa, but the length HPb of connecting terminal Pb is shorter, so that the inter-substrate pitch Hb is greater than the inter-substrate pitch Ha.

[0492] Referring to Figure 44D , in this embodiment, the data driver circuit 530' includes a driver circuit board 531', a first connection unit 534a, and multiple second connection units 534b. This embodiment differs from the previous embodiment in that the connection terminals on the left and right sides of the driver circuit board 531' are configured as connection terminals Pb of the second connection units 534b, while the terminals in the middle area are configured as connection terminals Pa of the first connection units 534a. In other words, the substrate spacing Hb between the connection terminals Pb on the left and right sides of the driver circuit board 531' is greater than the substrate spacing Ha between the connection terminals in the middle area. This solves the problem of difficult wiring of the connection terminals on both sides of the data driver circuit 530'.

[0493] Although the above examples illustrate possible exemplary configurations using different embodiments, the present disclosure is not limited thereto. For those skilled in the art, other possible configurations can be understood directly and without ambiguity after referring to the above embodiments. For example, those skilled in the art will understand that the configurations of the embodiments of Figures 44A and 44D can be combined so that the connection terminals Pb in each second connection unit 534b in Figure 44D are arranged in sequence in the manner of Figure 44A. For another example, those skilled in the art will understand that the configurations of the embodiments of Figures 44A and 44C can be combined so that the connection terminals Pb in the second connection unit 534b in Figure 44A have the size specifications shown in Figure 44C.

[0494] In other words, any configuration that can be understood and anticipated by a person skilled in the art with reference to the above-mentioned Figures 43A to 44D and related descriptions falls within the scope disclosed and to be protected by the present disclosure, and is therefore described here in advance.

[0495] In summary, the display devices, LED modules, and manufacturing methods proposed in some embodiments of the present disclosure can achieve this by setting the protective layer higher than or equal to the top electrode of the light-emitting element and forming an opening structure. In this configuration, the surface flatness of the LED module is determined by the protective layer and is therefore unaffected by the size and process of the LEDs. Furthermore, the design of the opening structure can compensate for the height differences between the individual LEDs due to size and process, while also ensuring that the top electrode conductors can be electrically connected to the top electrodes of each LED through the opening. This ensures that the top electrode conductors formed on the protective layer have a uniform line width, ensuring the electrical signal transmission characteristics of each LED. In other embodiments of the present disclosure, the display devices, LED modules, and manufacturing methods proposed in some embodiments can apply a force to the light-emitting element toward the substrate during the manufacturing process, causing the light-emitting element to produce different displacements based on its individual size / height and having different substrate spacings, thereby maintaining the top electrodes of the light-emitting elements in the same plane. In this configuration, the size differences between individual LEDs are compensated by the different substrate spacings, unaffected by the size and process of the LEDs, resulting in a smooth module surface. As a result, the top electrode conductors formed on the protective layer have a uniform line width, ensuring the electrical signal transmission characteristics of each LED. Because the top surfaces of all light-emitting components can be maintained at essentially the same level, with no height differences, subsequent manufacturing processes will not be affected by the flatness of the LED modules, effectively improving manufacturing process yield and reliability.

[0496] Furthermore, the quantum dot film proposed in the disclosed embodiments not only provides a preliminary water-blocking effect through the support layer and the bonding layer, but also utilizes the water-blocking layer covering the active layer to further block moisture from the active layer, making the active layer less susceptible to moisture, significantly improving the reliability of the backlight module and display. Furthermore, because the water-blocking layer significantly enhances the water-blocking properties of the quantum dot film, the design of the quantum dot film allows for a wider range of material options for the support layer and the bonding layer to meet design considerations while also balancing cost requirements.

[0497] Furthermore, in the light guide plate and backlight module proposed in some embodiments of the present disclosure, a columnar support unit structure is formed on the main body of the light guide plate to achieve structural reinforcement of the light guide plate. Since no additional rigid reinforcement plate is required, the cost of the overall backlight module can be effectively controlled. Furthermore, by configuring a first support unit and a second support unit with a height difference, a stepped support can be formed on the light guide plate, achieving an optimal balance between display quality and structural protection.

[0498] In addition, in the light guide plate and its backlight module proposed in some embodiments of the present disclosure, the light guide plate is composed of a standard module with a parallelogram structure, which can effectively reduce the directivity of the light source, so that the light can be diffused more evenly on the entire light guide plate, so that the backlight module can obtain a more uniform surface light source. In addition, even if the light guide plate formed by joining the light guide units is squeezed, the stress of the squeeze can be absorbed by the joint part without the risk of warping like the traditional full-surface light guide plate. The risk of deformation of the light guide plate caused by thermal expansion and moisture expansion can also be effectively reduced / eliminated. On the other hand, it can also effectively simplify the manufacturing process of the light guide plate and reduce the manufacturing cost and cycle, as well as reduce the cost and expenses of maintenance.

[0499] In addition, in the light guide plate and backlight module thereof proposed in some embodiments of the present disclosure, by providing a light guide plate with a curved structure, the light source in the central area can be more evenly diffused to the peripheral area, thereby achieving a higher light source conversion efficiency.

[0500] Furthermore, the display panel, display device, and manufacturing method proposed in the embodiments of the present disclosure utilize a splicing unit configuration that ensures the spacing between light-emitting elements at the seam is equal to the spacing within the panel. This effectively eliminates the visual impact of the splicing seam, resulting in no visible splicing stripes or optical color aberration. Furthermore, since no additional components such as optical microstructures or light strips are required, significant manufacturing cost advantages are achieved.

[0501] Furthermore, the display device and its data driver circuit proposed in the embodiments of the present disclosure can increase the routing space for transmission lines through the differentiated configuration of connection terminals, thereby solving the problem of difficult routing at the edge of the driver circuit while also achieving the effect of reducing the width of the bezel. Furthermore, it can effectively improve the quality of the display panel and extend the service life of the display panel within the GOP packaging architecture.

[0502] Although the present disclosure has been disclosed using the above-mentioned embodiments, they are not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications to the above-mentioned embodiments without departing from the spirit and scope of the present disclosure, and these changes and modifications still fall within the technical scope protected by the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the claims.

Claims

1. A display device, characterized in that: Include: A display panel comprising a first substrate and a pixel array; A scanning driving circuit, disposed on the first substrate and electrically connected to the pixel array, for generating a plurality of scanning signals to turn on the pixel array row by row; as well as a data driving circuit, disposed on the first substrate and electrically connected to the pixel array, for providing a data driving signal in coordination with the start-up timing of the pixel array, so that the display panel presents a corresponding image in response to the data driving signal, The scanning driving circuit includes a plurality of first scanning units for electrically connecting one of the odd-numbered scanning lines and the even-numbered scanning lines in the pixel array, and a plurality of second scanning units for electrically connecting the other of the odd-numbered scanning lines and the even-numbered scanning lines in the pixel array. Wherein, at least one of the plurality of first scanning units comprises: A first module is used to receive scanning signals from the first scanning units of the first two stages and the second two stages, and generate a driving signal at the first node accordingly; a second module, electrically connected to the first module via the first node, and determining a pull-up time point of the scan signal on the scan output terminal based on the drive signal, the first clock signal and the reference signal; and a third module, electrically connected to the second module and the scan output terminal, and determining a pull-down time point of the scan signal on the scan output terminal based on a second clock signal and the reference signal, The first module includes a first transistor and a second transistor, wherein the first transistor and the second transistor respectively have a first terminal, a second terminal and a control terminal. The signal received by the first end of the first transistor undergoes a level change at least once during each frame period, and the signal received by the first end of the first transistor is maintained at a high level during a period in which the signal received by the control end of the first transistor is at a high level.

2. The display device according to claim 1, wherein: The first end and the control end of the first transistor are electrically connected together to receive the scanning signals of the first two stages of the first scanning units.

3. The display device according to claim 1, wherein: The data driving circuit is electrically connected to the pixel array via a first transmission unit, and the display device further comprises: a connecting module, one end of which is disposed on the first substrate and is electrically connected to the data driving circuit via a second transmission part; as well as A control circuit is coupled to the other end of the connection module and is electrically connected to the data driving circuit through the connection module and the second transmission unit. Wherein, the data driving circuit comprises: Driver circuit board; A functional part is arranged on the driving circuit board; a first electrical connection portion, disposed on the driving circuit board and located at one side of the functional portion, wherein the first electrical connection portion electrically connects the functional portion and the first transmission portion; and a second electrical connection portion, which is disposed on the driving circuit board and is located on the other side of the functional portion, wherein the second electrical connection portion electrically connects the functional portion and the second transmission portion, The second electrical connection portion includes a first connection terminal and a second connection terminal, and the distance from the second connection terminal to the edge of the driving circuit board is greater than the distance from the first connection terminal to the edge of the driving circuit board.

4. The display device according to claim 1, wherein: The first substrate has a display area and a non-display area surrounding the display area, and the display device further includes: A plurality of light emitting elements are arranged in an array in the display area of ​​the first substrate, wherein adjacent light emitting elements have a first spacing therebetween, and the non-display area is at least partially defined as a splicing area; as well as a splicing unit, arranged on the first substrate in the splicing area, for covering at least a portion of a side wall of the first substrate, wherein a second distance exists between the side wall and the light emitting element closest thereto, Wherein, the thickness of the splicing unit on the side wall of the first substrate plus the second spacing is equal to half of the first spacing.

5. The display device according to claim 4, characterized in that The splicing unit comprises: an extended conductive layer electrically connected to the circuit layer of the first substrate and covering the sidewall of the first substrate in the splicing area, wherein the extended conductive layer has a first thickness on the sidewall of the first substrate; and a sidewall protection layer, covering at least a portion of the extended conductive layer, wherein the sidewall protection layer has a second thickness on the sidewall of the extended conductive layer, The sum of the first thickness and the second thickness is equal to the thickness of the splicing unit on the side wall of the first substrate.

6. The display device according to claim 1, wherein: The pixel array includes a plurality of thin film transistors arranged in an array, wherein at least one of the thin film transistors includes: Gate; an insulating layer formed on the gate; an active layer formed on the insulating layer; A source electrode formed on one of the two ends of the active layer; as well as A drain electrode is formed on the other of the two ends of the active layer, The active layer includes a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer stacked in sequence. The first semiconductor material layer is formed on the insulating layer and has an orderly arranged lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disordered arranged lattice structure; And the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disordered lattice structure and is doped with N-type ions.

7. The display device according to claim 6, wherein: There is substantially no semiconductor oxide on the interface between the first semiconductor material layer and the second semiconductor material layer.

8. The display device according to claim 6, wherein: The first semiconductor material layer is doped with 3A group ions.

9. The display device according to claim 6, wherein: The thickness ratio of the second semiconductor material layer to the third semiconductor material layer is between 5:8 and 8:

5.

10. The display device according to claim 9, characterized in that The total thickness of the second semiconductor material layer and the third semiconductor material layer is between to between.

11. The display device according to claim 10, wherein: The thickness of the second semiconductor material layer is between to And the third semiconductor material layer has a corresponding thickness so that the sum of the thicknesses of the second semiconductor material layer and the third semiconductor material layer is 12. The display device according to claim 6, wherein: The thin film transistor is formed by the following steps: forming a first metal layer and an insulating layer covering the first metal layer on the first substrate; forming an amorphous semiconductor thin film on the insulating layer; performing a thermal treatment on the amorphous semiconductor film so as to convert the amorphous semiconductor film into the first semiconductor material layer; forming the second semiconductor material layer and the third semiconductor material layer on the first semiconductor material layer to form the active layer; The active layer is subjected to a carrier removal process to reduce the number of carriers at the sidewall of the active layer. quantity; forming a second metal layer on the active layer; as well as An etching process is performed to expose the second semiconductor material layer in the channel region and separate the second metal layer into the source and the drain.

13. The display device according to claim 12, wherein: The steps of the carrier removal process include: performing patterning on the active layer to form the sidewall; and The sidewalls are overetched.

14. The display device according to claim 13, wherein: The side wall is a uniform plane formed by the continuous side surfaces of the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer.

15. The display device according to claim 13, wherein: A silicon oxide layer is formed on the sidewall through oxidation treatment.

16. The display device according to claim 12, wherein: The steps of the carrier removal process include: performing patterning on the active layer to form sidewalls; and Ion implantation is performed to implant Group 3A ions at the sidewalls.

17. The display device according to claim 1, wherein: Also included is an LED module, wherein the LED module is manufactured by the following method: forming a first circuit layer on the second substrate; Arranging a plurality of light-emitting elements on the first circuit layer through a combining portion so that a first electrode of each of the light-emitting elements is electrically connected to the first circuit layer; forming a protective layer on the second substrate to cover the plurality of light emitting elements, wherein a thickness of the protective layer is greater than or equal to a height of the plurality of light emitting elements; removing the protective layer covering the second electrode of each of the light-emitting elements to form an opening between each of the plurality of light-emitting elements and the protective layer; as well as A second circuit layer is formed on the protection layer, wherein the second circuit layer is electrically connected to the second electrode of each of the light-emitting elements through the opening.

18. The display device according to claim 1, wherein: Also included is an LED module, wherein the LED module is manufactured by the following method: forming a first circuit layer on the second substrate; Arranging a plurality of light-emitting elements on the first circuit layer through a combining portion so that a first electrode of each of the light-emitting elements is electrically connected to the first circuit layer; Applying a force toward the second substrate to the plurality of light emitting elements so as to embed at least a portion of the light emitting elements into the combining portion; Filling the gaps between the light emitting elements with insulating material to form a protective layer; as well as A second circuit layer is formed on the protection layer so that the second electrodes of each of the plurality of light emitting elements are electrically connected to the second circuit layer.

19. The display device according to claim 1, wherein: Also includes: A backlight module is used to provide light source toward the display panel, wherein the backlight module includes a light-emitting layer and an optical adjustment layer located on the light transmission path of the light-emitting layer, the light-emitting layer includes a plurality of light-emitting elements arranged in an array, and the optical adjustment layer is used to adjust the direction of the received light.

20. The display device according to claim 19, wherein: The backlight module further comprises a quantum dot film, wherein the quantum dot film comprises: An active layer, comprising a plurality of quantum dots, for exciting light having a second wavelength based on the received light having a first wavelength; A supporting layer, used to support the active layer; A bonding layer, disposed between the active layer and the supporting layer, for providing a bonding force between the active layer and the supporting layer, so that the active layer is disposed on the supporting layer through the bonding layer; as well as The water-blocking layer directly or indirectly covers at least a portion of the surface of the active layer.

21. The display device according to claim 19, wherein: The optical adjustment layer comprises: A light guide plate, comprising a light incident surface, a first surface and a second surface, wherein: The first surface is substantially perpendicular to the light incident surface and serves as a light emitting surface of the light guide plate, wherein the glossiness of the first surface is less than 1; and The second surface is located on the other side opposite to the second surface, wherein the glossiness of the second surface is greater than 95.

22. The display device according to claim 19, wherein: The optical adjustment layer comprises: A light guide plate, comprising a light incident surface, a first surface and a second surface, wherein: A first surface, substantially perpendicular to the light incident surface and serving as a light emitting surface of the light guide plate; A second surface located on the other side of the first surface, wherein the glossiness of the second surface is greater than 95; and A plurality of side surfaces are not parallel to the first surface and are connected to the first surface and the second surface, wherein the glossiness of at least one of the plurality of side surfaces is greater than 95.

23. The display device according to claim 22, characterized in that A plurality of reflective film structures are formed on the light incident surface, and the plurality of reflective film structures are arranged at fixed intervals, wherein the glossiness of each of the reflective film structures is greater than 95.

24. The display device according to claim 19, wherein: The optical adjustment layer includes a light guide plate, and the light guide plate includes: a body portion having a first surface and a second surface; and The reinforcing portion is formed on at least one of the first surface and the second surface, and includes a plurality of columnar supporting units, wherein the plurality of supporting units are light-transmissive, have an elastic recovery rate greater than or equal to 95, and are sequentially arranged on the main body. The plurality of support units include at least one support unit formed in the central area of ​​the main body, and support units respectively formed in four corners of the main body.

25. The display device according to claim 24, characterized in that The plurality of support units include a first support unit having a first height and a second support unit having a second height, wherein the first height is greater than the second height.

26. The display device according to claim 19, wherein: The optical adjustment layer includes a light guide plate, and the light guide plate includes: The main body includes a plurality of light guide units with parallelogram structures, wherein adjacent light guide units are mutually joined and fixed together by a joining portion, so that the mutually joined plurality of light guide units form a substantially continuous first surface and a second surface opposite to the first surface.

27. The display device according to claim 26, characterized in that At least part of the plurality of light guide units has a rhombus structure, and at least another part has a triangle structure.

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