Generating virtual blocks using partially good blocks

Abstract

Aspects of the present disclosure configure a system component, such as a memory subsystem controller, to generate a virtual or superblock using a plurality of partially good blocks. The controller identifies a first partial good block (PGB) in a set of memory components, the first PGB having a first subset of word line groups (WGRs) classified as defect-free. The controller searches the set of memory components for a second PGB having a second subset of WGRs classified as non-defective. The controller calculates a total number of WGRs based on a first number of WGRs in the first subset of WGRs and a second number of WGRs in the second subset of WGRs, and in response, combines the first PGB and the second PGB to form individual virtual blocks.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Provisional Application No. 63 / 441,342, filed on January 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to providing adaptive media management for memory components, such as memory dies. Background Art

[0004] The memory subsystem may be a storage system such as a solid-state drive (SSD) and may include one or more memory components that store data. For example, the memory components may be non-volatile memory components and volatile memory components. Generally, a host system may utilize the memory subsystem to store data on the memory components and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0006] Figure 1 is a block diagram illustrating an example computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0007] Figure 2 is a block diagram of an example media operations manager according to some embodiments of the present disclosure.

[0008] Figure 3 is a block diagram of an example plurality of virtual blocks composed of partially good blocks (PGBs) according to some embodiments of the present disclosure.

[0009] Figure 4 and 5 is a flowchart of an example method to perform memory operations to generate virtual blocks from PGBs, according to some embodiments of the present disclosure.

[0010] Figure 6 is a block diagram illustrating a diagrammatic representation of a machine in the form of a computer system within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure configure system components, such as a memory subsystem controller, to combine multiple partially good blocks (PGBs) to form one or more virtual blocks (VBs). The memory subsystem controller may access configuration data associated with a set of memory components. The configuration data may include a table that associates different word line groups (WGRs) of blocks of the memory components with indications of whether the WGRs are defective or non-defective. Based on the configuration data (which may be stored on a memory of the memory components and / or the controller), the controller may identify those PGBs with the lowest number or percentage of non-defective WGRs. The controller may then combine multiple such PGBs to form one or more VBs. This improves the overall efficiency of operating the memory subsystem by utilizing memory blocks even when they contain some defective WGRs.

[0012] The memory subsystem can be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. Generally speaking, a host system may utilize a memory subsystem that includes one or more memory components, such as memory devices (e.g., memory dies) that store data. The host system may send access requests (e.g., write commands, read commands) to the memory subsystem, for example, to store data at the memory subsystem and to read data from the memory subsystem. Data (or data sets) specified by the host are hereinafter referred to as "host data," "application data," or "user data."

[0013] The memory subsystem can initiate media management operations, such as write operations, on host data stored on the memory device. For example, as part of a junk collection management operation, the memory subsystem's firmware can overwrite previously written host data from a location on the memory device to a new location. The data that is overwritten (e.g., as initiated by the firmware) is referred to hereinafter as "junk collection data." "User data" can include host data and junk collection data. "System data," hereinafter, refers to data created and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical to physical address mapping tables), data from log records, scratchpad data, and the like.

[0014] Many different media management operations can be performed on a memory device. For example, these can include different scan rates, different scan frequencies, different wear leveling, different read disturb management, different near-error error correction (ECC), and / or different dynamic data refreshes. Wear leveling ensures that all blocks in a memory component approach their defined erase cycle budget at the same time, rather than some blocks approaching it earlier than others. Read disturb management counts all read operations on the memory component. If a certain threshold is reached, the surrounding area is refreshed. Near-error ECC refreshes all data read by the application that exceeds a configured error threshold. As a background operation, dynamic data refresh scans all data and identifies error conditions for all blocks. If a certain error threshold for each block or ECC unit is exceeded during this scan, a refresh operation is triggered.

[0015] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies (or die). Each die may include one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. For some memory devices, a block is the smallest area that can be erased. Each block includes a set of pages. Each page includes a set of memory cells that store data bits. The memory device may be a raw memory device (e.g., NAND), which is externally managed, for example, by an external controller. The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller for memory management within the same memory device package.

[0016] Typical memory systems utilize VBs (also known as superblocks), which are collections of blocks across multiple memory planes and / or dies. That is, each superblock may be of equal size and may contain a corresponding collection of blocks across multiple planes and / or dies. When allocated, a superblock allows the controller to simultaneously write data to a larger portion of memory spanning multiple blocks (across multiple planes and / or dies) with a single address. A VB typically consists of blocks from the upper and lower levels of the WGRs of a memory component. If any WGR in the upper level is defective, a conventional system can utilize a WGR from the lower level, or vice versa. This avoids wasting memory resources. However, if both the upper and lower levels have defective WGRs, the entire block formed by the upper and lower levels is discarded and marked as unusable for forming a VB. This can reduce the efficiency of generating superblocks because less memory space is available to form superblocks. This can lead to poor or unreliable memory performance.

[0017] Aspects of the present disclosure address the above-mentioned and other deficiencies by providing a memory controller that can combine multiple PGBs to form one or more VBs, even in the presence of defective WGRs on upper and lower levels of the memory components. A memory subsystem controller can access configuration data associated with a set of memory components. The configuration data can include a table that associates different WGRs for blocks of the memory components with an indication of whether the WGRs are defective or non-defective. Based on the configuration data, the controller can identify those PGBs that have a reference or minimum number or percentage (e.g., 30%) of non-defective WGRs. The controller can then combine multiple such PGBs to form one or more VBs. This improves the overall efficiency of operating the memory subsystem by utilizing memory blocks even when they contain some defective WGRs.

[0018] In some examples, the memory controller identifies a first PGB in the set of memory components. The first PGB may have a first subset of WGRs that are classified as non-defective. The memory controller searches the set of memory components for a second PGB that has a second subset of WGRs that are classified as non-defective. The memory controller calculates a total number of WGRs based on a first number of WGRs in the first subset of WGRs and a second number of WGRs in the second subset of WGRs. In response to determining that the total number of WGRs corresponds to a threshold number of WGRs, the memory controller combines the first PGB with the second PGB to form a separate virtual block.

[0019] In some examples, the memory controller accesses configuration data. The configuration data includes a table that associates different WGRs of a block of the set of memory components with corresponding categories indicating defect types in the different WGRs. In some examples, the defect types include recoverable and unrecoverable defects. Recoverable defects may include at least one of a wordline (WL) to WL short, an open WL, a slow-programming WL, or a WL that fails to meet a read bit error rate threshold. Unrecoverable defects may include at least one of a wordline (WL) to pillar short, a source-to-gate (SG) short, or a dummy WL short.

[0020] In some examples, the first subset of WGRs and the second subset of WGRs are each associated with a recoverable defect. In some examples, the memory controller stores a table in a one-time programming area of ​​the memory subsystem, the table identifying individual block addresses and a list of defective WGRs. In some examples, individual VBs include Super Blocks distributed across multiple memory dies. In some examples, individual VBs include Super Blocks distributed across multiple memory planes. In some examples, the memory controller stores a table. The table includes a first entry associating a first group of blocks of a first PGB and a second group of blocks of a second PGB with a first virtual block address.

[0021] In some examples, the memory controller generates a PGB list based on configuration data. In some examples, the memory controller generates the PGB list by counting the number of non-defective WGRs in individual blocks of the set of memory components. The memory controller determines whether a percentage of non-defective WGRs for the individual block exceeds a threshold percentage of WGRs and adds the individual block to the PGB list. In some examples, the memory controller adds the individual block to the PGB list by storing an address of the individual block and an identification of a defective WGR.

[0022] In some examples, the memory controller generates a PGB list by counting the number of non-defective WGRs in individual blocks of the set of memory components and determining that a percentage of non-defective WGRs for the individual blocks fails to exceed a threshold percentage of WGRs; and excludes the individual blocks from the PGB list.

[0023] In some examples, the memory controller determines that the total number of WGRs fails to correspond to a threshold number of WGRs. The memory controller searches a group of memory components for a third PGB having a third subset of WGRs classified as non-defective and calculates the total number of WGRs based on a first number of WGRs in the first subset of WGRs, a second number of WGRs in the second subset of WGRs, and a third number of WGRs in the third subset of WGRs. In response to determining that the total number of WGRs corresponds to the threshold number of WGRs, the memory controller forms a separate virtual block using a combination of the first PGB, the second PGB, and the third PGB.

[0024] In some examples, the memory controller determines that a PGB of a particular virtual block is failing. In response to determining that the PGB of the particular virtual block is failing, the memory controller replaces the PGB with a spare PGB having a subset of WGRs classified as non-defective corresponding to the number of WGRs in the PGB to repair the particular virtual block. In some examples, the memory controller determines that the PGB is failing in response to determining that a read bit error rate (RBER) associated with the PGB exceeds a threshold RBER.

[0025] Although various embodiments are described herein as being implemented with respect to a memory subsystem (eg, a controller of a memory subsystem), some or all portions of the embodiments may be implemented with respect to a host system (eg, a software application or operating system of the host system).

[0026] Figure 1An example computing environment 100 including a memory subsystem 110 according to some examples of the present disclosure is illustrated. Memory subsystem 110 may include media, such as memory components 112A-112N (hereinafter also referred to as "memory devices"). Memory components 112A-112N may be volatile memory devices, non-volatile memory devices, or a combination thereof. Memory components 112A-112N may be implemented by individual dies, such that first memory component 112A may be implemented by a first memory die (or a first set of memory dies) and second memory component 112N may be implemented by a second memory die (or a second set of memory dies).

[0027] In some examples, a first memory component 112A, a block or page of the first memory component 112A, or a group of memory components including the first memory component 112A may be associated with a first reliability (capability) level, value, or metric. The terms "reliability level," "value," and "metric" may be used interchangeably throughout and may have the same meaning. A second memory component 112N, or a group of memory components including the second memory component 112N, may be associated with a second reliability (capability) level, value, or metric. In some examples, each memory component 112A-112N may store respective configuration data specifying a respective reliability level. In some examples, a memory or register may be associated with all memory components 112A-112N that may store a table mapping different groups, bins, or sets of memory components 112A-112N to respective reliability levels.

[0028] In some embodiments, the PGBs within first memory component 112A may be grouped together with the PGBs within second memory component 112N to form a super block, or VB, having a predetermined, reference, or threshold number of blocks and WGRs. The VBs may be collectively addressable using a single address. In such cases, a logical-to-physical address (LTP or L2P) table may store an association between the single address and each of the PGBs of first memory component 112A and second memory component 112N associated with the single address. In some examples, some of the WGRs within a given block within first memory component 112A may have a reliability level below a threshold or may be characterized as defective or non-defective. Such blocks may be processed to determine whether the number of non-defective WGRs relative to the total number of WGRs for the block is greater than a minimum or reference percentage threshold. Alternatively or additionally, such blocks may be processed to determine whether the number of defective WGRs relative to the total number of WGRs for the block is less than a minimum or reference percentage threshold. If the number of non-defective WGRs relative to the total number of WGRs for the block is greater than the minimum or reference percentage threshold, then the block is marked as a PGB and may be used to form a VB. A memory or table may be created to list the PGBs and their corresponding WGRs, whether defective or non-defective.

[0029] In some embodiments, the memory subsystem 110 is a storage system. The memory subsystem 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual inline memory modules (NVDIMMs).

[0030] The computing environment 100 may include a host system 120 coupled to a memory system. The memory system may include one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0031] Host system 120 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing devices that include memory and processing devices. Host system 120 may include or be coupled to memory subsystem 110, such that host system 120 can read data from or write data to memory subsystem 110. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Serial Attached SCSI (SAS) interface, and the like. The physical host interface may be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM Express (NVMe) interface to access memory components 112A-112N. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 .

[0032] Memory components 112A-112N may include any combination of different types of nonvolatile memory components and / or volatile memory components. An example of a nonvolatile memory component includes NAND-type flash memory. Each of memory components 112A-112N may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., TLC or QLC). In some embodiments, a particular memory component 112 may include both an SLC portion and an MLC portion of memory cells. Each of the memory cells may store one or more data bits (e.g., a block) used by the host system 120. Although nonvolatile memory components such as NAND-type flash memory are described, memory components 112A-112N may be based on any other type of memory, such as volatile memory. In some embodiments, memory components 112A-112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), NOR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory cells can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. In addition, the memory cells of memory components 112A-112N can be grouped into memory pages or blocks, which can refer to the unit of memory component 112 used to store data. For example, a single first row spanning memory components 112A through 112N may correspond to or be grouped as a first Super Block, and a single second row spanning memory components 112A through 112N may correspond to or be grouped as a second Super Block. If the single first row contains all good blocks (e.g., each block in the single first row has a reliability level above a threshold), then the first Super Block is a first Complete Super Block. If the single first row contains some bad blocks (e.g., one or more blocks in the single first row have a reliability level below a threshold), then the first Super Block is a first Incomplete Super Block.

[0033] The memory subsystem controller 115 may communicate with the memory components 112A-112N to perform memory operations, such as reading data, writing data, or erasing data, and other such operations, at the memory components 112A-112N. The memory subsystem controller 115 may communicate with the memory components 112A-112N to perform various memory management operations, such as different scan rates, different scan frequencies, different wear leveling, different read disturb management, different near-error ECC operations, and / or different dynamic data refreshes.

[0034] The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor. The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers that store memory pointers, extracted data, etc. The local memory 119 may also include a read-only memory (ROM) for storing microcode. Although it has been described Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor 117 or controller separate from the memory subsystem 110).

[0035] Generally speaking, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert these commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A-112N. In some examples, the commands or operations received from the host system 120 may specify configuration data for the memory components 112N-112N. The configuration data may describe reliability levels and / or indications of defects in certain WGRs associated with different groups of memory components 112N-112N and / or different blocks within each of the memory components 112N-112N. In some cases, the reliability levels are dynamic and may be updated by the memory subsystem controller 115 in response to determining that certain error rates exceeding an error rate threshold have been reached. For example, if a non-defective WGR begins to have an error rate exceeding a threshold, the non-defective WGR may become a defective WGR. In such cases, the configuration data is updated and any VBs containing the now-defective WGR are updated with replacement or spare PGBs to maintain the performance of the VBs above a minimum or reference performance rating.

[0036] The memory subsystem controller 115 may be responsible for other memory management operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation. The memory subsystem controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system 120 into command instructions to access the memory components 112A-112N and convert responses associated with the memory components 112A-112N into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM or other temporary storage location or device) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory components 112A-112N.

[0038] The memory device may be a raw memory device (e.g., NAND), which is externally managed, for example, by an external controller (e.g., memory subsystem controller 115). The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller (e.g., a local media controller) within the same memory device package for memory management. Any of the memory components 112A-112N may include a media controller (e.g., media controller 113A and media controller 113N) to manage the memory cells of the memory component (e.g., perform one or more memory management operations), communicate with the memory subsystem controller 115, and execute memory requests (e.g., reads or writes) received from the memory subsystem controller 115.

[0039] The memory subsystem controller 115 may include a media operations manager 122. The media operations manager 122 may be configured to combine multiple PGBs to form one or more VBs. The memory subsystem controller 115 may access configuration data associated with a set of memory components. The configuration data may include a table that associates different WGRs for blocks of the memory components with indications of whether the WGRs are defective or non-defective. Based on the configuration data, the memory subsystem controller 115 may identify PGBs that have a reference or minimum number or percentage (e.g., 30%) of non-defective WGRs. The memory subsystem controller 115 may then combine multiple such PGBs to form one or more VBs. This can improve the overall efficiency of operating the memory subsystem by utilizing memory blocks even when they contain some defective WGRs. This improves the efficiency of operating the memory system.

[0040] As an example, the media operations manager 122 may identify a first PGB in a group of memory components 112. The first PGB may have a first subset of WGRs that are classified as non-defective. The media operations manager 122 searches the group of memory components for a second PGB that has a second subset of WGRs that are classified as non-defective. The media operations manager 122 calculates a total number of WGRs based on a first number of WGRs in the first subset of WGRs and a second number of WGRs in the second subset of WGRs. In response to determining that the total number of WGRs corresponds to a threshold number of WGRs, the media operations manager 122 combines the first PGB with the second PGB to form a separate virtual block.

[0041] Depending on the embodiment, the media operations manager 122 may include logic (e.g., a set of transient or non-transient machine instructions, such as firmware) or one or more components that enable the media operations manager 122 to perform the operations described herein. The media operations manager 122 may include tangible or non-tangible units capable of performing the operations described herein. Additional details regarding the operation of the media operations manager 122 are described below.

[0042] Figure 2 is a block diagram of an example media operations manager 200 according to some embodiments of the present disclosure. The media operations manager 200 may include Figure 1 As illustrated, the media operations manager 122 includes configuration data 220, a partial block identification module 230, and a virtual block generation module 240. For some embodiments, the components or arrangements of the media operations manager 122 may be similar to those of the media operations manager 122 shown in FIG. Figure 2 The components or arrangements described in the examples may be different (eg, fewer or more components).

[0043] Configuration data 220 accesses and / or stores configuration data associated with memory components 112A-112N. In some examples, configuration data 220 is programmed into media operations manager 122 during the manufacture of memory subsystem 110. Media operations manager 122 can communicate with memory components 112A-112N to obtain configuration data and store configuration data 220 locally on media operations manager 122. In some examples, media operations manager 122 communicates with host system 120. Host system 120 receives input from an operator or user specifying parameters including indications of defects present on different WGRs, different bins, groups, blocks, or collections of memory components 112A-112N. Media operations manager 122 receives configuration data from host system 120 and stores the configuration data in configuration data 220.

[0044] In some examples, the media operations manager 122 performs one or more test operations on different groups or blocks of memory components 112A-112N. The test operations are configured to determine and detect which WGRs of each block of memory components 112A-112N have recoverable defects (non-defective) and which WGRs have unrecoverable defects (defective). Recoverable defects include at least one of a wordline (WL) to WL short, an open WL, a slow-programming WL, or a WL that fails to meet a read bit error rate threshold. Unrecoverable defects include at least one of a wordline (WL) to pillar short, a source-to-gate (SG) short, or a dummy WL short.

[0045] Based on the results of the test operation, the media operations manager 122 may store or update the PGBs identified in the configuration data 220. In some examples, the media operations manager 122 may periodically or routinely perform the test operation to update which WGRs have changed from non-defective to defective, thereby causing the PGB to fail. The configuration data 220 may also store a reference or minimum threshold percentage of non-defective WGRs that an individual block may have in order to function as a PGB.

[0046] In some examples, the partial block identification module 230 accesses the configuration data 220 to generate a list of PGBs. In such cases, the partial block identification module 230 may obtain a list of WGRs and their corresponding defect type indications (e.g., recoverable or unrecoverable) from the configuration data 220. The partial block identification module 230 may determine the number of WGRs with recoverable defects for each individual block. The partial block identification module 230 may calculate the total number of WGRs (with recoverable and unrecoverable defects) for each individual block. The partial block identification module 230 may calculate a ratio or percentage of the number of WGRs with recoverable defects to the total number of WGRs. The partial block identification module 230 may obtain a reference or minimum threshold percentage of non-defective WGRs that each individual block may have in order to function as a PGB from the configuration data 220. The partial block identification module 230 may determine that the ratio or percentage of the number of WGRs with recoverable defects to the total number of WGRs exceeds a reference or minimum threshold percentage of non-defective WGRs (e.g., 30%). In such cases, the partial block identification module 230 may add the individual block to the PGB list by storing the address of the block corresponding to the PGB and the list of WGRs with unrecoverable defects or defects. If the ratio or percentage of the number of WGRs with recoverable defects to the total number of WGRs fails to exceed a reference or minimum threshold percentage, the individual block is discarded and excluded from the PGB list to avoid using the block as a PGB for forming a VB.

[0047] The partial block identification module 230 may similarly continue processing all blocks of memory components 112A-112N to compile a list of all PGBs whose number of non-defective WGRs exceeds a reference or threshold percentage relative to the total number of WGRs. In some examples, in response to determining that the ratio or percentage of the number of WGRs with recoverable defects to the total number of WGRs exceeds a reference or minimum threshold percentage of non-defective WGRs (e.g., 30%), the partial block identification module 230 may perform additional reliability testing on the remaining non-defective WGRs. The partial block identification module 230 may determine that the remaining WGRs of a particular block pass the additional reliability test. For example, the partial block identification module 230 may determine that the read bit error rate (RBER) of the non-defective WGRs is lower than a reference RBER. If the remaining WGRs of a particular block pass the additional reliability test, the PGB is maintained or added to the PGB list. If the remaining WGRs of a particular block fail the additional reliability test, the particular block is discarded and excluded from the PGB list to prevent it from being used as a PGB for forming a VB.

[0048] After generating the PGB list, the virtual block generation module 240 may access the PGB list to form one or more VBs using different groups of PGBs in the list. For example, the virtual block generation module 240 may determine a minimum or reference number of WGRs required to form a particular VB. Next, the virtual block generation module 240 may search the PGB list to identify multiple PGBs that can be selected to form the particular VB. Specifically, the virtual block generation module 240 may select a first PGB from the PGB list. The virtual block generation module 240 may determine how many non-defective WGRs are included in the first PGB. The virtual block generation module 240 may subtract or compare a first number of non-defective WGRs included in the first PGB with a minimum or reference number of WGRs required to form the particular VB. In response to determining that the first number of non-defective WGRs included in the first PGB is less than the minimum or reference number of WGRs required to form the particular VB, the virtual block generation module 240 searches the PGB list for another PGB.

[0049] In some examples, the virtual block generation module 240 may calculate the fraction or percentage of the minimum or reference number of WGRs required to form a particular VB that is satisfied by a first number of non-defective WGRs included in a first PGB. For example, the virtual block generation module 240 may determine that the first number of non-defective WGRs included in a first PGB can be used to complete 30% of the WGRs for the particular VB. In such a case, the virtual block generation module 240 may search the PGB list to find a second PGB with a certain number of WGRs that can be used to complete the remaining portion of the WGRs for the particular VB. For example, the virtual block generation module 240 may search for a PGB that can be used to fill 70% of the WGRs for the particular VB. In some cases, the virtual block generation module 240 may determine the number of WGRs missing from the VB by subtracting the first number of non-defective WGRs from the minimum or reference number of WGRs. The virtual block generation module 240 may search the PGB list to find a second PGB with the number of WGRs missing from the VB or less.

[0050] The virtual block generation module 240 may select a second PGB for forming an individual VB. The virtual block generation module 240 may combine or add the number of WGRs in the first PGB with the number of WGRs in the second PGB. The virtual block generation module 240 may determine whether the total number of WGRs in the non-defective first and second PGBs exceeds or corresponds to a minimum or reference number of WGRs required to form an individual VB. If the total number does not exceed or correspond to the minimum or reference number, the virtual block generation module 240 updates the L2P table to store the addresses of the first and second PGBs in association with the address of the individual VB. If the total number does not exceed or correspond to the minimum or reference number, the virtual block generation module 240 searches for a third PGB that has a certain number of WGRs missing from the minimum or reference number of WGRs required to form an individual VB. Once the third PGB is found, the virtual block generation module 240 may then determine whether the total number of WGRs in the non-defective first, second, and third PGBs exceeds or corresponds to the minimum or reference number of WGRs required to form an individual VB. If the total number exceeds or corresponds to the minimum or reference number, the virtual block generation module 240 updates the L2P table to store the addresses of the first, second, and third PGBs in association with the addresses of the individual VBs.

[0051] Figure 3 is a block diagram of an example plurality of VBs 300 comprised of PGBs, according to some embodiments of the present disclosure. For example, the plurality of VBs 300 may be formed from multiple planes (P0, P1, P2, and P3) of a respective memory die. As shown, a first VB 340 may be formed by combining a first subset of WGRs 314 of a first PGB 310 on a given plane. The first subset of WGRs 314 may be non-defective. The first PGB 310 may include a second subset of WGRs 312 that is defective. The media operations manager 122 may calculate a percentage based on the number of the first subset of WGRs 314 relative to a minimum or reference number of WGRs for the first VB 340. In this case, the media operations manager 122 may determine that the first PGB 310 includes 30% of the WGRs of the minimum or reference number of WGRs for the first VB 340. In such a case, the media operations manager 122 searches for a second PGB 320 on the same or a different plane of the memory die.

[0052] Second PGB 320 may include a second set of non-defective WGRs 322. Media operations manager 122 may calculate a percentage based on the number of second WGR subset 322 relative to the minimum or reference number of WGRs for first VB 340. In this case, media operations manager 122 may determine that second PGB 320 includes 40% of the WGRs for the minimum or reference number of WGRs for first VB 340. Media operations manager 122 accumulates or adds the percentages of first WGR subset 314 and second WGR subset 322 to determine how many or what percentage of WGRs are missing from the minimum or reference number of WGRs for first VB 340. For example, media operations manager 122 may determine that first PGB 310 and second PGB 320 include a total of non-defective WGRs that are 70% of the total required WGRs that can be used to make up first VB 340. In such a case, media operations manager 122 searches for a third PGB 330 on the same or a different plane of the memory die.

[0053] The media operations manager 122 forms a first VB 340 using the WGR 332 of the non-defective third PGB 330, along with the WGR 314 of the first PGB 310 and the WGR 322 of the second PGB 320. The media operations manager 122 stores identifiers of the first PGB 310, the second PGB 320, and the third PGB 330 in association with the address of the first VB 340. In some cases, the third PGB 330 includes more or missing WGRs than are required to form the first VB 340 in combination with the WGR 314 of the first PGB 310 and the WGR 322 of the second PGB 320. For example, when formed using the first PGB 310 and the second PGB 320, the first VB 340 may be missing 30% of the WGRs, but the number of WGRs of the third PGB 330 may correspond to 40% of the missing WGRs. In such cases, the media operations manager 122 may still use less than all of the WGRs of the third PGB 330 (e.g., a number of WGRs of the third PGB 330 that corresponds to 30% of the minimum or reference WGR of the first VB 340) to form the first VB 340. The remaining WGRs that are not used to form the first VB 340, which may correspond to 10% of the minimum or reference WGR of the first VB 340, may be used as spare WGRs. These spare WGRs may be used to replace WGRs of the first VB 340 that are determined to be failing, for example, because the RBER of some of the WGRs of the first VB 340 has reached a threshold RBER. In such cases, the WGRs that have reached the threshold RBER are removed from use in the first VB 340 and replaced with one or more of the WGRs that remain as spare WGRs of the third PGB 330.

[0054] Figure 4 is a flow chart of an example method 400 for performing memory operations to generate virtual blocks from PGBs according to some embodiments of the present disclosure. The method 400 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The processes are executed by the media operations manager 122. Although the processes are shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0055] Reference Figure 4 The method (or process) 400 begins at operation 405, where the media operations manager 122 of a memory subsystem (e.g., memory subsystem 110) identifies a first portion of good blocks (PGBs) in a set of memory components, the first PGB having a first subset of word line groups (WGRs) that are classified as non-defective. Next, at operation 410, the media operations manager 122 of the memory subsystem searches the set of memory components for a second PGB having a second subset of WGRs that are classified as non-defective. Thereafter, at operation 415, the media operations manager 122 calculates a total number of WGRs based on a first number of WGRs in the first subset of WGRs and a second number of WGRs in the second subset of WGRs. At operation 420, in response to determining that the total number of WGRs corresponds to a threshold number of WGRs, the media operations manager 122 combines the first PGB with the second PGB to form a separate virtual block.

[0056] Figure 5 is a flow chart of an example method 500 for performing memory operations to generate virtual blocks from PGBs according to some embodiments of the present disclosure. The method 500 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1The processes are executed by the media operations manager 122. Although the processes are shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only. The illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0057] Reference Figure 5 Method (or process) 500 begins at operation 510, where the media operations manager 122 of a memory subsystem (e.g., memory subsystem 110) begins screening configuration data to obtain a list of recoverable bad blocks for each individual block of a set of memory components 112A through 112N. At operation 520, the media operations manager 122 identifies PGB information containing a list of defective WGRs for the individual block. At operation 530, the media operations manager 122 begins a screening test process for selectively adding the individual block to the PGB list. Specifically, at operation 540, the media operations manager 122 determines whether the number or percentage of non-defective WGRs for the individual block exceeds a threshold percentage or number. If the number or percentage exceeds the threshold percentage or number, the media operations manager 122 proceeds to operation 550, where additional reliability testing is performed on the non-defective WGRs for the individual block. If the number or percentage of defect-free WGRs for the individual block fails to exceed the threshold percentage or number, the media operations manager 122 performs operation 560 where the individual block is marked as a bad block and is not used to form the individual VB.

[0058] At operation 550, the media operations manager 122 determines whether the non-defective WGRs of the individual block pass the additional reliability test. If they pass, the media operations manager 122 proceeds to operation 570 to add the individual block to the PGB list along with an indication of which WGRs are defective or non-defective. If the non-defective WGRs of the individual block fail the additional reliability test, the media operations manager 122 performs operation 560, in which the individual block is marked as a bad block and is not used to form the individual VB.

[0059] In view of the above disclosure, various examples are described below. It should be noted that one or more features of the examples taken alone or in combination should be considered within the disclosure of this application.

[0060] Example 1. A system comprising: a set of memory components of a memory subsystem; and a processing device operatively coupled to the set of memory components, the processing device configured to perform operations comprising: identifying a first partial good block (PGB) of the set of memory components, the first PGB having a first subset of word line groups (WGRs) classified as non-defective; searching the set of memory components for a second PGB having a second subset of WGRs classified as non-defective; calculating a total number of WGRs based on a first number of WGRs in the first subset of WGRs and a second number of WGRs in the second subset of WGRs; and in response to determining that the total number of WGRs corresponds to a threshold number of WGRs, combining the first PGB with the second PGB to form an individual virtual block.

[0061] Example 2. The system of example 1, the operations comprising accessing configuration data, wherein the configuration data comprises a table associating different WGRs of blocks of the set of memory components with respective categories indicating a type of defect in the different WGRs.

[0062] Example 3. The system of example 2, wherein the defect types include recoverable and unrecoverable defects.

[0063] Example 4. The system of example 3, wherein the recoverable defect comprises at least one of a wordline (WL) to WL short, an open WL, a slowly programmed WL, or a WL that fails to meet a read bit error rate threshold.

[0064] Example 5. The system of any of examples 3-4, wherein the unrecoverable defect comprises at least one of a word line (WL) to pillar short, a source to gate (SG) short, or a dummy WL short.

[0065] Example 6. The system of any of examples 3-5, wherein the first WGR subset and the second WGR subset are each associated with a recoverable defect.

[0066] Example 7. The system of any of examples 1 to 6, the operations comprising storing the table in a one-time programming area of ​​the memory subsystem, the table identifying individual block addresses and a list of defective WGRs.

[0067] Example 8. The system of any of examples 1-7, wherein the individual virtual blocks comprise super blocks distributed across multiple memory dies.

[0068] Example 9. The system of any of examples 1-8, wherein the individual virtual blocks comprise super blocks distributed across multiple memory planes.

[0069] Example 10. The system of any of examples 1 to 9, the operations comprising storing a table comprising a first entry associating a first group of blocks of the first PGB and a second group of blocks of the second PGB with a first virtual block address.

[0070] Example 11. The system of any of Examples 1 to 10, the operations comprising: accessing configuration data, wherein the configuration data comprises a table associating different WGRs of blocks of the set of memory components with respective categories indicating defect types in the different WGRs; and generating a PGB list based on the configuration data.

[0071] Example 12. The system of Example 11, wherein the operation for generating the PGB list comprises: calculating a number of non-defective WGRs in individual blocks of the set of memory components; determining that a percentage of non-defective WGRs of the individual blocks exceeds a threshold percentage of WGRs; and adding the individual blocks to the PGB list.

[0072] Example 13. The system of example 12, wherein adding the individual block to the PGB list comprises storing an address of the individual block and an identification of the WGR that is defective.

[0073] Example 14. The system of any of examples 11 to 13, wherein the operation for generating the PGB list comprises: calculating a number of non-defective WGRs in individual blocks of the set of memory components; determining that a percentage of non-defective WGRs of the individual blocks fails to exceed a threshold percentage of WGRs; and excluding the individual blocks from the PGB list.

[0074] Example 15. The system of any one of Examples 1 to 14, wherein the operations include: determining that the total number of WGRs fails to correspond to the threshold number of WGRs; searching the set of memory components for a third PGB having a third subset of WGRs classified as non-defective; calculating the total number of WGRs based on the first number of WGRs in the first subset of WGRs, the second number of WGRs in the second subset of WGRs, and the third number of WGRs in the third subset of WGRs; and in response to determining that the total number of WGRs corresponds to the threshold number of WGRs, forming the individual virtual blocks using a combination of the first PGB, the second PGB, and the third PGB.

[0075] Example 16. A system according to any one of Examples 1 to 15, wherein the operation includes: determining that the individual PGB of the individual virtual block begins to fail; and in response to determining that the individual PGB of the individual virtual block begins to fail, replacing the individual PGB with a spare PGB having a subset of individual WGRs classified as non-defective corresponding to the number of WGRs in the individual PGB to repair the individual virtual block.

[0076] Example 17. The system of example 16, wherein the individual PGB is determined to be beginning to fail in response to determining that a read bit error rate (RBER) associated with the individual PGB exceeds a threshold RBER.

[0077] Methods and computer-readable storage media having instructions for performing any of the above examples.

[0078] Figure 6 An example machine is illustrated in the form of a computer system 600 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or can be used to perform operations of the controller (for example, execute an operating system to execute corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in server-client user network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0079] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a network switch, a network bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0080] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM)), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0081] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, processing device 602 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing another instruction set, or multiple processors implementing a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communicating over a network 620.

[0082] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functionality described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, with the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0083] In one embodiment, instructions 626 implement the instructions corresponding to Figure 1 The functionality of the media operations manager 122 is provided. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methodologies of the present disclosure. Thus, the term "machine-readable storage medium" should be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0084] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0085] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0086] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks; read-only memory (ROM); random access memory (RAM); erasable programmable read-only memory (EPROM); EEPROM; magnetic or optical cards; or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0087] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the methods. The structures of a variety of these systems will appear as set forth in the description above. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0088] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0089] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: A set of memory components of a memory subsystem; and a processing device operatively coupled to the set of memory components, the processing device configured to perform operations comprising: identifying a first portion of good blocks (PGBs) in the set of memory components, the first PGBs having a first subset of word line groups (WGRs) classified as non-defective; searching the set of memory components for a second PGB having a second subset of WGRs classified as non-defective; calculating a total number of WGRs based on a first number of WGRs in the first subset of WGRs and a second number of WGRs in the second subset of WGRs; and In response to determining that the total number of WGRs corresponds to a threshold number of WGRs, the first PGB is combined with the second PGB to form an individual virtual block.

2. The system of claim 1, wherein the operations comprise: Configuration data is accessed, wherein the configuration data includes a table associating different WGRs of blocks of the set of memory components with respective categories indicating a type of defect in the different WGRs.

3. The system of claim 2, wherein the defect types include recoverable and unrecoverable defects.

4. The system of claim 3, wherein the recoverable defects include at least one of a word line (WL) to WL short, an open WL, a slow programming WL, or a WL that fails to meet a read bit error rate threshold.

5. The system of claim 3, wherein the unrecoverable defect comprises at least one of a word line (WL) to pillar short, a source to gate (SG) short, or a dummy WL short.

6. The system of claim 3, wherein the first WGR subset and the second WGR subset are each associated with a recoverable defect.

7. The system of claim 2, wherein the operations comprise: The table is stored in a one-time programming area of ​​the memory subsystem, the table identifying individual block addresses and a list of defective WGRs.

8. The system of claim 1, wherein the individual virtual blocks comprise super blocks distributed across multiple memory dies.

9. The system of claim 1, wherein the individual virtual blocks comprise superblocks distributed across multiple memory planes.

10. The system of claim 1, wherein the operations comprise: A table is stored that includes a first entry associating a first group of blocks of the first PGB and a second group of blocks of the second PGB with a first virtual block address.

11. The system of claim 1 , wherein the operations comprise: accessing configuration data, wherein the configuration data comprises a table associating different WGRs of blocks of the set of memory components with respective categories indicating types of defects in the different WGRs; and A PGB list is generated based on the configuration data.

12. The system of claim 11, wherein the operation for generating the PGB list comprises: counting a number of non-defective WGRs in individual blocks of the set of memory components; determining that a percentage of defect-free WGRs for the individual blocks exceeds a threshold percentage of WGRs; and The individual block is added to the PGB list.

13. The system of claim 12, wherein adding the individual block to the PGB list comprises storing an address of the individual block and an identification of the WGR that is defective.

14. The system of claim 11, wherein the operation for generating the PGB list comprises: counting a number of non-defective WGRs in individual blocks of the set of memory components; determining that a percentage of defect-free WGR for the individual block fails to exceed a threshold percentage of WGR; and The individual block is excluded from the PGB list.

15. The system of claim 1, wherein the operations comprise: determining that the total number of WGRs fails to correspond to the threshold number of WGRs; searching the set of memory components for a third PGB having a third subset of WGRs classified as non-defective; calculating the total number of WGRs based on the first number of WGRs in the first WGR subset, the second number of WGRs in the second WGR subset, and the third number of WGRs in the third WGR subset; and In response to determining that the total number of WGRs corresponds to the threshold number of WGRs, the individual virtual block is formed using a combination of the first PGB, the second PGB, and the third PGB.

16. The system of claim 1, wherein the operations comprise: Determining that the individual PGB of the individual virtual block begins to fail; and In response to determining that the individual PGB of the individual virtual block begins to fail, the individual PGB is replaced with a spare PGB having a subset of individual WGRs classified as non-defective corresponding to the number of WGRs in the individual PGB to repair the individual virtual block. 17 . The system of claim 16 , wherein the individual PGB is determined to be beginning to fail in response to determining that a read bit error rate (RBER) associated with the individual PGB exceeds a threshold RBER.

18. A method comprising: identifying a first portion of good blocks (PGBs) in a group of memory components, the first PGBs having a first subset of word line groups (WGRs) classified as non-defective; searching the set of memory components for a second PGB having a second subset of WGRs classified as non-defective; calculating a total number of WGRs based on the first number of WGRs in the first subset of WGRs and the second number of WGRs in the second subset of WGRs; and In response to determining that the total number of WGRs corresponds to a threshold number of WGRs, the first PGB is combined with the second PGB to form an individual virtual block.

19. The method according to claim 18, comprising: Configuration data is accessed, wherein the configuration data includes a table associating different WGRs of blocks of the set of memory components with respective categories indicating a type of defect in the different WGRs.

20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: identifying a first portion of good blocks (PGBs) in a group of memory components, the first PGBs having a first subset of word line groups (WGRs) classified as non-defective; searching the set of memory components for a second PGB having a second subset of WGRs classified as non-defective; calculating a total number of WGRs based on the first number of WGRs in the first subset of WGRs and the second number of WGRs in the second subset of WGRs; and In response to determining that the total number of WGRs corresponds to a threshold number of WGRs, the first PGB is combined with the second PGB to form an individual virtual block.

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