Providing content aware cache replacement and insertion policies in processor-based device

Abstract

Providing content aware cache replacement and insertion policies in a processor-based device is disclosed. In some aspects, a processor-based device includes a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device based on a plurality of bit values for each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 18 / 163,446, filed on February 2, 2023, entitled “PROVIDING CONTENT-AWARE CACHEREPLACEMENT AND INSERTION POLICIES IN PROCESSOR-BASED DEVICES,” which is incorporated herein by reference in its entirety. background

[0003] I. Technical Field

[0004] The technology of this disclosure generally relates to the use of cache memory devices in processor-based devices, and in particular to cache replacement and insertion policies.

[0005] II. Background Technology

[0006] Processor-based devices are subject to a phenomenon known as memory access latency, which is the time interval between the time a processor initiates a memory access request for data (i.e., by executing a memory load instruction) and the time the processor actually receives the requested data. If the memory access latency for a memory access request is large enough, the processor may be forced to halt further execution of instructions while waiting for the memory access request to complete. One way to minimize the impact of memory access latency is to use a cache memory device (also simply called a "cache"). A cache is a memory device that has a smaller capacity than system memory but can be accessed more quickly by the processor due to the type of memory used and / or the physical location of the cache relative to the processor. A cache can be used to store copies of data retrieved from frequently accessed memory locations in system memory (or from higher-level caches such as the last-level cache (LLC)), thereby reducing memory access latency.

[0007] Due to the limited capacity of a cache, the cache may quickly fill up with copies of recently retrieved data. In such cases, a processor-based device may need to select cache entries within the cache to evict and replace with newly retrieved data, and / or determine whether to cache the results of a particular memory access request in full. To select cache entries to evict, a processor-based device may employ any of a variety of cache replacement policies, including, as non-limiting examples, round-robin, least recently used (LRU), and most recently used (MRU) cache replacement policies. However, for some caches, such as LLC, the miss rate associated with the cache may be less sensitive to different cache replacement policies, such that the selection of a given cache replacement policy may have little effect on the number of misses in cache usage. Furthermore, conventional cache replacement and insertion policies may have limited impact on other costs associated with memory access requests, such as the increased energy consumption associated with moving data values ​​within the processor and / or between the processor and system memory. Summary of the Invention

[0008] Various aspects disclosed in the specific embodiments include providing content-aware cache replacement and insertion strategies in a processor-based device. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, the processor-based device provides a cache memory device and a cache controller circuit associated with the cache memory device. The cache controller circuit is configured to select cached data values ​​for eviction from the cache memory device based on the content cost of the cached data values, so that cached data values ​​with lower content costs are evicted earlier. As used herein, the "content cost" of a data value refers to a numerical value corresponding to the energy consumption of the processor-based device caused by the bit values ​​of multiple bits of the data value, such as the energy consumption when storing and / or transmitting the data value.

[0009] Thus, when the cache controller circuitry determines that an eviction is required from the cache memory device, the cache controller circuitry determines a content cost for each cached data value in a plurality of cached data values ​​in the cache memory device (e.g., cached data values ​​stored in a plurality of ways of a group of the cache memory device). Each content cost is determined based on a bit value of a plurality of bits of each corresponding cached data value. For example, in some aspects, each content cost may include a count of the number of occurrences of a specified bit value (e.g., a value of one (1) or a value of zero (0)) in the plurality of bit values ​​of the corresponding cached data value. Some aspects may provide that each content cost may include a count of the number of changes in each bit value in the plurality of bit values ​​of the most recently evicted data value compared to the bit value of the corresponding cached data value. The cache controller circuitry uses the content cost to identify the cached data value in the plurality of cached data values ​​that is associated with the lowest content cost as a target cached data value. The cache controller circuitry then evicts the target cached data value from the cache memory device. In this way, the cache controller circuitry implements a content-aware cache replacement policy that ensures that subsequent retransmission and / or restoring of evicted data values ​​will incur a lower energy cost, while retaining cached data values ​​that would incur a greater energy cost if retransmitted and / or restoring.

[0010] Some aspects may provide that the cache controller circuitry may receive a data value to be cached and may also determine a content cost for the data value. In some such aspects, before identifying a target cached data value, the cache controller circuitry may determine whether all of a plurality of content costs for the cached data values ​​have the same value (i.e., whether a particular cached data value cannot be transferred from system memory and / or stored in system memory with a lower energy cost than any other cached data value). If so, the cache controller circuitry may use an alternative cache replacement policy (e.g., as a non-limiting example, a "least recently used" cache replacement policy) to identify the target cached data value. According to some such examples, if the cache controller circuitry determines that not all of the plurality of content costs have the same value, the cache controller circuitry may further determine whether the content cost of the data value to be cached is lower than all of the plurality of content costs (i.e., whether the data value to be cached has a lower energy cost than any of the cached data values). If so, the cache controller circuitry may bypass caching of the data value.

[0011] In some aspects, cache controller circuitry may receive a cache hint based on a plurality of bit values ​​of a data value to be cached (e.g., received from a client device such as a neural signal processor (NSP), as a non-limiting example). The cache hint may include, for example, an indication that the data value is associated with a relatively high content cost or memory access latency, or a relatively low content cost or memory access latency, and thus, the data value should or should not be cached by the cache controller circuitry, respectively. In such aspects, the cache controller circuitry may then determine, based on the cache hint, whether to cache the data value based on the cache hint or to bypass caching for the data value.

[0012] In another aspect, a processor-based device is provided. The processor-based device includes a cache memory device and cache controller circuitry of the cache memory device. The cache controller circuitry is configured to determine a plurality of content costs for each of a plurality of cached data values ​​in the cache memory device based on a plurality of bit values ​​of each of the plurality of cached data values. The cache controller circuitry is configured to, based on the plurality of content costs, identify a cached data value associated with a lowest content cost among the plurality of cached data values ​​as a target cached data value. The cache controller circuitry is further configured to evict the target cached data value from the cache memory device.

[0013] In another aspect, a processor-based device is provided. The processor-based device includes means for determining a plurality of content costs for each of a plurality of cached data values ​​in a cache memory device based on a plurality of bit values ​​of each cached data value in the plurality of cached data values. The processor-based device also includes means for identifying a cached data value in the plurality of cached data values ​​associated with a lowest content cost as a target cached data value based on the plurality of content costs. The processor-based device also includes means for evicting the target cached data value from the cache memory device.

[0014] In another aspect, a method for providing a content-aware cache replacement and insertion policy in a processor-based device is provided. The method includes determining, by cache controller circuitry, a plurality of content costs for each of a plurality of cached data values ​​in a cache memory device based on a plurality of bit values ​​of each cached data value in the plurality of cached data values. The method also includes identifying, by the cache controller circuitry, a cached data value in the plurality of cached data values ​​associated with a lowest content cost as a target cached data value based on the plurality of content costs. The method also includes evicting, by the cache controller circuitry, the target cached data value from the cache memory device.

[0015] In another aspect, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium stores computer-executable instructions thereon that, when executed, cause a processor to determine a plurality of content costs for each of a plurality of cached data values ​​in a cache memory device based on a plurality of bit values ​​of each cached data value in the plurality of cached data values. The computer-executable instructions further cause the processor to identify a cached data value in the plurality of cached data values ​​associated with a lowest content cost as a target cached data value based on the plurality of content costs. The computer-executable instructions further cause the processor to evict the target cached data value from the cache memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram illustrating an exemplary processor-based device including a cache memory device and associated cache controller circuitry configured to provide content-aware cache replacement and insertion policies according to some aspects;

[0017] Figures 2A to 2B This is an example based on some aspects Figure 1 A block diagram of a cache controller circuit of the invention using a content-aware cache replacement policy in which a content cost is calculated based on the number of occurrences of the value one (1) among cached data values;

[0018] Figures 3A to 3B This is an example based on some aspects Figure 1 A block diagram of a cache controller circuit for using a content-aware cache replacement policy in which a content cost is calculated based on the number of occurrences of a bit value zero (0) in cached data values;

[0019] Figures 4A to 4B This is an example based on some aspects Figure 1A block diagram of a cache controller circuit of the invention using a content-aware cache replacement policy in which a content cost is calculated based on the number of times a bit value of a recently evicted data value changes compared to a bit value of a cached data value;

[0020] 5A to 5D This is an example based on some aspects Figure 1 A flow chart of exemplary operations of a cache controller circuit for providing a content-aware cache replacement and insertion strategy; and

[0021] Figure 6 Examples may include Figure 1 A block diagram of an exemplary processor-based device of a processor-based device. DETAILED DESCRIPTION

[0022] With reference now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0023] Various aspects disclosed in the specific embodiments include providing content-aware cache replacement and insertion strategies in a processor-based device. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, the processor-based device provides a cache memory device and a cache controller circuit associated with the cache memory device. The cache controller circuit is configured to select cached data values ​​for eviction from the cache memory device based on the content cost of the cached data values, so that cached data values ​​with lower content costs are evicted earlier. As used herein, the "content cost" of a data value refers to a numerical value corresponding to the energy consumption of the processor-based device caused by the bit values ​​of multiple bits of the data value, such as the energy consumption when storing and / or transmitting the data value.

[0024] Thus, when the cache controller circuitry determines that an eviction is required from the cache memory device, the cache controller circuitry determines a content cost for each cached data value in a plurality of cached data values ​​in the cache memory device (e.g., cached data values ​​stored in a plurality of ways of a group of the cache memory device). Each content cost is determined based on a bit value of a plurality of bits of each corresponding cached data value. For example, in some aspects, each content cost may include a count of the number of occurrences of a specified bit value (e.g., a value of one (1) or a value of zero (0)) in the plurality of bit values ​​of the corresponding cached data value. Some aspects may provide that each content cost may include a count of the number of changes in each bit value in the plurality of bit values ​​of the most recently evicted data value compared to the bit value of the corresponding cached data value. The cache controller circuitry uses the content cost to identify the cached data value in the plurality of cached data values ​​that is associated with the lowest content cost as a target cached data value. The cache controller circuitry then evicts the target cached data value from the cache memory device. In this way, the cache controller circuitry implements a content-aware cache replacement policy that ensures that subsequent retransmission and / or restoring of evicted data values ​​will incur a lower energy cost, while retaining cached data values ​​that would incur a greater energy cost if retransmitted and / or restoring.

[0025] Some aspects may provide that the cache controller circuitry may receive a data value to be cached and may also determine a content cost for the data value. In some such aspects, before identifying a target cached data value, the cache controller circuitry may determine whether all of a plurality of content costs for the cached data values ​​have the same value (i.e., whether a particular cached data value cannot be transferred from system memory and / or stored in system memory with a lower energy cost than any other cached data value). If so, the cache controller circuitry may use an alternative cache replacement policy (e.g., as a non-limiting example, a "least recently used" cache replacement policy) to identify the target cached data value. According to some such examples, if the cache controller circuitry determines that not all of the plurality of content costs have the same value, the cache controller circuitry may further determine whether the content cost of the data value to be cached is lower than all of the plurality of content costs (i.e., whether the data value to be cached has a lower energy cost than any of the cached data values). If so, the cache controller circuitry may bypass caching of the data value.

[0026] In some aspects, cache controller circuitry may receive a cache hint based on a plurality of bit values ​​of a data value to be cached (e.g., received from a client device such as a neural signal processor (NSP), as a non-limiting example). The cache hint may include, for example, an indication that the data value is associated with a relatively high content cost or memory access latency, or a relatively low content cost or memory access latency, and thus, the data value should or should not be cached by the cache controller circuitry, respectively. In such aspects, the cache controller circuitry may then determine, based on the cache hint, whether to cache the data value based on the cache hint or to bypass caching for the data value.

[0027] In this regard, Figure 1 An exemplary processor-based device 100 is illustrated that provides a processor 102 for providing a content-aware cache replacement and insertion strategy. In some aspects, the processor 102 may include a central processing unit (CPU) having one or more processor cores, and in some exemplary aspects, may be one of a plurality of similarly configured processors (not shown) of the processor-based device 100. The processor 102 is communicatively coupled to an interconnect bus 104, which in some embodiments may include a plurality of processors not shown in the figure for clarity. Figure 1 Additional constituent elements shown in (eg, bus controller circuitry and / or arbitration circuitry as non-limiting examples).

[0028] The processor 102 is also communicatively coupled via the interconnect bus 104 to a memory controller 106, which controls access to and manages the flow of data to and from a system memory device 108. The system memory device 108 provides addressable memory for data storage by the processor-based device 100 and, thus, may include, as a non-limiting example, dynamic random access memory (DRAM). Figure 1 The processor 102 also includes a cache memory device 110 that may be used to cache local copies of frequently accessed data within the processor 102 for faster access. In some aspects, the cache memory device 110 may comprise, for example, a level 1 (L1) cache. Figure 1 The processor 102 in the example of FIG is also communicatively coupled to a cache memory device (in FIG. Figure 1Cache memory device 110 and cache memory device 112 together form a hierarchical cache structure used by processor-based device 100 to cache frequently accessed data for faster retrieval compared to retrieving data from system memory device 108.

[0029] like Figure 1 As shown, the cache memory device 110 is divided into a plurality of groups (in Figure 1 ) 114(0)-114(S), each group including multiple paths, such as paths (in Figure 1 16(0)-116(W) and 116'(0)-116'(W) of the groups 114(0)-114(S), and the cache memory device 110 is configured to support corresponding levels of associativity. Each way of the multiple ways 116(0)-116(W), 116'(0)-116'(W) of the groups 114(0)-114(S) is configured to store cached data values, such as cached data values ​​118(0)-118(W) of the ways 116(0)-116(W), that represent data that was earlier retrieved from the system memory device 108 or from a higher level cache such as the cache memory device 112. The cached data values ​​118(0)-118(W) may each comprise, for example, a cache line and may be associated with a tag (not shown) that stores information that enables the corresponding cache line to be mapped to a unique memory address. It will be understood that the cached data values ​​118(0)-118(W) of the cache memory device 110 may also be associated with other data elements, such as validity indicators and / or dirty data indicators, which are not shown in the figure for clarity. Figure 1 Shown in.

[0030] Figure 1 The processor-based device 100 may include any of known digital logic elements, semiconductor circuits, processing cores and / or memory structures, as well as other elements or combinations thereof. The embodiments described herein are not limited to any particular arrangement of elements, and the disclosed techniques may be readily extended to various structures and layouts on semiconductor sockets or packages. It will be understood that some embodiments of the processor-based device 100 may include more than Figure 1 For example, processor 102 may also include more or fewer memory devices, execution pipeline stages, controller circuits, buffers, and / or caches, which are shown for clarity. Figure 1 Omit.

[0031] As mentioned above, caches, such as cache memory device 110 and cache memory device 112, may be employed to minimize the impact of memory access latency experienced by processor 102 when performing memory access operations to system memory device 108 or higher-level caches, such as cache memory device 112. However, for some caches, the selection of a cache replacement policy may have little effect on the miss rate of the processor-based device 100 when using the cache. Furthermore, conventional cache replacement and insertion policies do not take into account other costs that may be associated with memory access requests. In some aspects, one such cost is the energy cost associated with the movement of data within processor 102 or between processor 102 and system memory device 108 and / or the storage of data in system memory device 108. For example, when transferring data, a device, such as a DRAM module, that employs an off-chip terminated interconnect may consume energy only when transferring a bit value of one (1) and consume no energy when transferring a bit value of zero (0). In contrast, devices such as system-on-chip (SoC) devices that employ on-chip unterminated interconnects may consume energy only when a bit value transitions from one value to another (i.e., from a value of zero (0) to a value of one (1), or vice versa). Similarly, some memory devices may consume more refresh energy when storing data values ​​that include more bit values ​​of one (1) than bit values ​​of zero (0).

[0032] Therefore, in this regard, the processor 102 provides a cache controller circuit 120 to provide a content-aware cache replacement and insertion strategy. Figure 1 In the example shown in FIG, cache controller circuit 120 is shown as a separate element from cache memory device 110. However, it will be understood that in some aspects, cache controller circuit 120 may be provided as an integral element of cache memory device 110, or vice versa. Cache controller circuit 120 is configured to employ a content cost-based ( Figure 1 A content-aware cache replacement policy is provided for selecting content costs 122(0)-122(W) of the cached data values, such as cached data values ​​118(0)-118(W), and for selecting one of the cached data values ​​118(0)-118(W) having the lowest content cost 122(0)-122(W) as a target cached data value to be evicted.

[0033] The content costs 122(0)-122(W) are determined by the cache controller circuitry 120 based on the bit values ​​of a plurality of bits (not shown) of each cached data value. The calculation of the content costs 122(0)-122(W) may vary from implementation to implementation depending on how the processor-based device 100 consumes energy when transmitting and / or storing each bit value. For example, in some aspects, each of the content costs 122(0)-122(W) may include a count of the number of occurrences of a specified bit value (e.g., a value of one (1) or a value of zero (0)) in the plurality of bit values ​​of the corresponding cached data value 118(0)-118(W). In some such aspects, the content costs 122(0)-122(W) may be compared to the content cost of the data value 126 received by the cache controller circuitry 120 to be cached (in Figure 1 (labeled as "data value content cost") 124 for comparison. Figures 2A to 2B and Figures 3A to 3B , discusses examples of determining content costs 122(0)-122(W) based on these aspects in more detail.

[0034] Some aspects may provide that the cache controller circuitry 120 is configured to track a recently evicted data value 128 representing a value of a cached data value that was recently evicted from the cache memory device 110. In such aspects, the content costs 122(0)-122(W) may include a count of the number of times each bit value of a plurality of bit values ​​(not shown) of the recently evicted data value 128 has changed compared to a corresponding bit value of the plurality of bit values ​​of each cached data value 118(0)-118(W). Figures 4A to 4B , discusses examples of determining content costs 122(0)-122(W) based on these aspects in more detail.

[0035] The cache controller circuitry 120 uses the content costs 122(0)-122(W) to identify a cached data value associated with a lowest content cost among the plurality of cached data values ​​118(0)-118(W) (e.g., cached data value 118(0) as a non-limiting example) as a target cached data value 118(0). The cache controller circuitry 120 then evicts the target cached data value 118(0) from the cache memory device 110. By evicting the target cached data value 118(0) having the lowest content cost among the content costs 122(0)-122(W), the cache controller circuitry 120 ensures that the processor-based device 100 will incur lower energy consumption when the target cached data value 118(0) is subsequently retransmitted and / or restored, while retaining cached data values ​​118(1)-118(W) that would incur a greater energy cost if retransmitted and / or restored.

[0036] As mentioned above, in some aspects, the cache controller circuitry 120 may receive a data value 126 to be cached and may determine a content cost 124 for the data value 126. In some such aspects, before identifying a target cached data value 118(0), the cache controller circuitry 120 may determine whether all of the plurality of content costs 122(0)-122(W) for the cached data values ​​118(0)-118(W) have the same value. If so, this indicates that none of the cached data values ​​118(0)-118(W) can be retrieved or transmitted with a lower energy cost than any of the other cached data values ​​118(0)-118(W). Thus, in such aspects, the cache controller circuitry 120 may use an alternative cache replacement policy (e.g., as a non-limiting example, a "least recently used" cache replacement policy) to identify the target cached data value. Some such examples may further provide that, if cache controller circuitry 120 determines that not all of content costs 122(0)-122(W) have the same value, cache controller circuitry 120 may determine whether content cost 124 of to-be-cached data value 126 is lower than all of content costs 122(0)-122(W). This indicates that to-be-cached data value 126 can be retrieved or transmitted at a lower energy cost than any of cached data values ​​118(0)-118(W). In this case, cache controller circuitry 120 may bypass caching of data value 126.

[0037] In accordance with some aspects, a client device (not shown) that is the source of the data value 126 received by the cache controller circuitry 120 may provide a cache hint 130 based on a plurality of bit values ​​of the data value 126. For example, in aspects where the client device is an NSP, the NSP may determine that the content of the data value 126 (e.g., a lookup table, neural network weights, or the like) is biased toward containing more particular data values ​​(e.g., more zeros (0) than ones (1), or vice versa). Accordingly, the client device may provide the cache hint 130 to the cache controller circuitry 120 to indicate that the data value 126 is associated with a relatively high content cost or memory access latency, or is associated with a relatively low content cost or memory access latency (and thus the data value 126 should or should not be cached by the cache controller circuitry 120, respectively). Based on the cache hint 130, in these aspects, the cache controller circuitry 120 may then determine whether to cache the data value 126 based on the cache hint 130 or to bypass caching of the data value 126.

[0038] As mentioned above, the content costs 122(0)-122(W) are determined based on the multiple bit values ​​of the cached data values ​​118(0)-118(W) and, in some aspects, can be compared to the content cost 124 of the data value 126 when providing a content-aware cache replacement policy. Figure 1 In the case where the cache controller circuit 120 uses a content-aware cache replacement policy in which the content costs 122(0)-122(W) are calculated based on the number of occurrences of the median value one (1) among the cached data values ​​118(0)-118(W), the present invention provides Figures 2A to 2B .exist Figure 2A In the example, the data value 126 will be represented by Figure 1 The cache controller circuit 120 of cache memory device 110 caches the cached data value 118(0)-118(3) in group 114(0) and thus caches one of cached data values ​​118(0)-118(3). Figure 1 18(3) will be identified as the target cached data values ​​to be evicted. To simplify the illustrated example, data value 126 and cached data values ​​118(0)-118(3) are each illustrated as comprising four (4) bits; however, it will be understood that some aspects may provide that data value 126 and cached data values ​​118(0)-118(3) comprise more than four (4) bits. Additionally, for clarity, the data values ​​126 and cached data values ​​118(0)-118(3) are each illustrated as comprising four (4) bits. Figures 2A to 2B Ways 116(0)-116(W) storing cached data values ​​118(0)-118(W) are omitted.

[0039] exist Figure 2A In the example of FIG. 1 , cache controller circuitry 120 determines content cost 124 for data value 126 based on bit values ​​200(0)-200(3) of data value 126. Cache controller circuitry 120 also determines content costs 122(0)-122(3) for corresponding cached data values ​​118(0)-118(3) based on corresponding bit values ​​202(0)-202(3), 204(0)-204(3), 206(0)-206(3), and 208(0)-208(3). Because the content-aware cache replacement policy applied in this example is based on the number of occurrences of bit value one (1), content cost 124 for data value 126 is determined to have a value of three (3), while content costs 122(0)-122(3) for cached data values ​​118(0)-118(3) are determined to have values ​​of two (2), one (1), four (4), and two (2), respectively. Cached data value 118(1) is therefore identified as having the lowest content cost 122(1), and cache controller circuitry 120 therefore identifies cached data value 118(1) as the target cached data value 118(1). Figure 2B As shown, cache controller circuitry 120 evicts the target cached data value 118(1) and installs data value 126 as the new cached data value 118(1).

[0040] Figures 3A to 3B Example Figure 1 The cache controller circuit 120 uses a content-aware cache replacement policy that is consistent with Figures 2A to 2B , but differs in that the content costs 122(0)-122(W) are calculated based on the number of occurrences of the bit value zero (0) in the cached data values ​​118(0)-118(W). Figures 3A to 3B As shown, the bit values ​​200(0)-200(3) of the data value to be cached 126 and the bit values ​​202(0)-202(3), 204(0)-204(3), 206(0)-206(3) and 208(0)-208(3) of the corresponding cached data values ​​118(0)-118(3) have Figure 2A. Since the content-aware cache replacement policy applied in this example is based on the number of occurrences of the bit value zero (0), the content cost 124 of the data value 126 is determined to have a value of one (1), while the content costs 122 (0) - 122 (3) of the cached data values ​​118 (0) - 118 (3) are determined to have values ​​of two (2), three (3), zero (0), and two (2), respectively. Therefore, the cache controller circuitry 120 in this example identifies the cached data value 118 (2) as having the lowest content cost 122 (2), and the cache controller circuitry 120 therefore identifies the cached data value 118 (2) as the target cached data value 118 (2). As Figure 3B As shown, cache controller circuitry 120 evicts the target cached data value 118(2) and installs data value 126 as the new cached data value 118(2).

[0041] Figures 4A to 4B Example Figure 1 The cache controller circuit 120 uses a content-aware cache replacement policy, where each of the content costs 122(0)-122(W) includes Figure 1 A count of the number of times that bit values ​​in the plurality of bit values ​​400(0)-400(3) of the most recently evicted data value 128 have changed compared to corresponding bit values ​​202(0)-202(3), 204(0)-204(3), 206(0)-206(3), and 208(0)-208(3) of the corresponding cached data values ​​118(0)-118(3). Figures 4A to 4B , the bit values ​​200(0)-200(3) of the data value to be cached 126 and the bit values ​​202(0)-202(3), 204(0)-204(3), 206(0)-206(3) and 208(0)-208(3) of the corresponding cached data values ​​118(0)-118(3) have Figure 2ATo calculate the content cost 122(0) of, for example, cached data value 118(0), bit values ​​400(0)-400(3) of recently evicted data value 128 are compared to bit values ​​202(0)-202(3), and the number of bit value changes between the corresponding bits is counted. Although bit value 400(0) is the same as bit value 202(0) (i.e., zero (0)) and bit value 400(1) is the same as bit value 202(1) (i.e., one (1)), bit value 400(2) and bit value 202(2), as well as bit value 400(3) and bit value 202(3), each represent a change in bit value (from one (1) to zero (0) and from zero (0) to one (1), respectively). Therefore, the content cost 122(0) of cached data value 118(0) is determined to be two (2). Similarly, content costs 122(1)-122(3) are determined to have values ​​of one (1), two (2), and two (2), respectively. Therefore, cache controller circuitry 120 in this example identifies cached data value 118(1) as having the lowest content cost 122(1), and cache controller circuitry 120 therefore identifies cached data value 118(1) as the target cached data value 118(1). Figure 4B As shown, cache controller circuitry 120 evicts the target cached data value 118(1) and installs data value 126 as the new cached data value 118(1).

[0042] To further describe Figure 1 The cache controller circuit 120 is used to provide content-aware cache replacement and insertion strategy operation, 5A to 5D A flowchart illustrating exemplary operation 500 is provided. For clarity, 5A to 5D When cited Figure 1 、 Figures 2A to 2B 、 Figures 3A to 3B and Figures 4A to 4B It will be appreciated that some aspects may provide that 5A to 5D Some of the operations shown may be performed in an order different from that illustrated herein and / or may be omitted. Figure 5A In some aspects, the exemplary operations 500 are performed from Figure 1 The processor 102 (eg, using Figure 1 The cache controller circuit 120) identifies a plurality of groups of cache memory devices for storing data values ​​(e.g., Figure 1 、 Figures 2A to 2B and Figures 3A to 3B The data value 126) is cached in a group (for example, Figure 114(0) of the plurality of groups 114(0)-114(S) of the cache memory device 110 (block 502). In such aspects, the cache controller circuit 120 may then identify the corresponding multiple ways (e.g., Figure 1 of the plurality of ways 116(0)-116(W)) (e.g., Figures 2A to 2B 、 Figures 3A to 3B and Figures 4A to 4B 118 ( 0 )- 118 ( 3 )) (block 504 ).

[0043] According to some aspects (e.g., aspects of calculating content cost based on the number of times the bit values ​​of the most recently evicted data value have changed compared to the bit values ​​of the cached data value), the cache controller circuit 120 may determine the most recently evicted data value, such as Figure 1 and Figures 4A to 4B (block 506). Some aspects may provide that the cache controller circuit 120 receives a data value to be cached, such as Figure 1 、 Figures 2A to 2B 、 Figures 3A to 3B and Figures 4A to 4B In some aspects, cache controller circuitry 120 may select a cache controller circuit 120 based on a plurality of bit values ​​of data value 126 (eg, Figures 2A to 2B 、 Figures 3A to 3B and Figures 4A to 4B Bit values ​​200(0)-200(3)) receive cache hints (e.g., Figure 1 Cache hint 130) (block 510). In such aspects, cache controller circuitry 120 may then determine whether to cache data value 126 based on cache hint 130 (block 512). If not, cache controller circuitry 120 will bypass caching of data value 126 (block 514). However, if cache controller circuitry 120 determines at decision block 512 that data value 126 is to be cached (or if cache controller circuitry 120 embodies aspects that do not use cache hint 130), then example operations 500 bypass caching of data value 126 at block 514. Figure 5B Continue at block 516 of .

[0044] Now see Figure 5B In some aspects, example operations 500 continue with cache controller circuitry 120 determining a content cost of data value 126 (eg, Figure 1 、 Figures 2A to 2B 、 Figures 3A to 3B and Figures 4A to 4BThe cache controller circuit 120 determines the content cost 124 of the cache memory device 110 based on the plurality of bit values ​​(e.g., Figures 2A to 2B 、 Figures 3A to 3B and Figures 4A to 4B The plurality of bit values ​​202(0)-202(3)) of the cached data values ​​118(0)-118(W) determine a plurality of content costs (eg, Figure 1 、 Figures 2A to 2B 、 Figures 3A to 3B and Figures 4A to 4B 122(0)-122(W)) (block 518). In some aspects, the operations of block 518 for determining the plurality of content costs 122(0)-122(W) may include: the plurality of content costs 122(0)-122(W) each including a count of the number of occurrences of a specified bit value in the plurality of bit values ​​202(0)-202(3) of the cached data values ​​in the plurality of cached data values ​​118(0)-118(W) (block 520). Some aspects may provide that the operations of block 518 for determining the plurality of content costs 122(0)-122(W) each including a count of the number of occurrences of a specified bit value in the plurality of bit values ​​202(0)-202(3) of the cached data values ​​in the plurality of cached data values ​​118(0)-118(W) (block 520). Figures 4A to 4B 400(0)-400(3)) is compared to a corresponding bit value in the plurality of bit values ​​202(0)-202(3) of the cached data values ​​118(0)-118(W) (block 522). In some aspects, the example operations 500 are then performed at Figure 5C Continue at block 524 of .

[0045] Now go to Figure 5C , the exemplary operations 500 continue by the cache controller circuitry 120 determining whether all of the plurality of content costs 122(0)-122(W) have the same value (block 524). If so, the cache controller circuitry 120 replaces a cached data value (e.g., Figure 1 、 Figures 2A to 2B 、 Figures 3A to 3B and Figures 4A to 4B122(W)) is identified as the target cached data value (block 526). However, if the cache controller circuitry 120 determines at decision block 524 that not all of the plurality of content costs 122(0)-122(W) have the same value, then in some aspects, the cache controller circuitry 120 may determine whether the content cost 124 of the data value 126 is lower than all of the plurality of content costs 122(0)-122(W) (block 528). If so, the cache controller circuitry 120 bypasses caching of the data value 126 (block 530). If the cache controller circuitry 120 determines at decision block 528 that the content cost 124 of the data value 126 is not lower than all of the plurality of content costs 122(0)-122(W), then the example operations 500 Figure 5D Continue at block 532 of .

[0046] Now continue to refer to Figure 5D , the exemplary operations 500 continue by the cache controller circuitry aligning the plurality of cached data values ​​118 ( 0 ) - 118 ( W ) with the lowest content cost (eg , Figure 1 、 Figures 2A to 2B 、 Figures 3A to 3B and Figures 4A to 4B 122(0)) associated with the cached data value (e.g., Figures 2A to 2B 、 Figures 3A to 3B and Figures 4A to 4B The cache controller circuit 120 identifies the target cached data value 118(0) as the target cached data value 118(0) (block 532). The cache controller circuit 120 then evicts the target cached data value 118(0) from the cache memory device 110 (block 534).

[0047] Providing content-aware cache replacement and insertion strategies in a processor-based device as disclosed in various aspects described herein can be provided in or integrated into any processor-based device. Non-limiting examples include: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a laptop computer, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyeglasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, a motor vehicle, a vehicle component, an avionics system, an unmanned aerial vehicle, and a multirotor aircraft.

[0048] In this regard, Figure 6 An example of a processor-based device 600 is illustrated, which may include Figure 1 The processor-based device 100 is shown. In this example, the processor-based device 600 includes a processor 602, which includes one or more central processing units (CPUs). Figure 6 The central processing unit (labeled as "CPU" in the figure) 604, which may also be referred to as a CPU core or processor core. The processor 602 may have a cache memory 606 coupled to the processor 602 for quickly accessing temporarily stored data. The processor 602 is coupled to a system bus 608 and may mutually couple the master devices and slave devices included in the processor-based device 600. As is well known, the processor 602 communicates with these other devices by exchanging address, control, and data information on the system bus 608. For example, the processor 602 may communicate a bus transaction request to a memory controller 610, which is an example of a slave device. Although in Figure 6 Although not illustrated, multiple system buses 608 may be provided, with each system bus 608 forming a different structure.

[0049] Other master devices and slave devices may be connected to the system bus 608. Figure 6As illustrated in , as examples, these devices may include a memory system 612 (which includes a memory controller 610 and a memory array 614), one or more input devices 616, one or more output devices 618, one or more network interface devices 620, and one or more display controllers 622. The input devices 616 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 618 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device 620 may be any device configured to allow data exchange to and from the network 624. The network 624 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), Bluetooth ™ Network and Internet. Network interface device 620 may be configured to support any type of communication protocol desired.

[0050] The processor 602 may also be configured to access a display controller 622 via the system bus 608 to control information transmitted to one or more displays 626. The display controller 622 transmits information to be displayed to the display 626 via one or more video processors 628, which process the information to be displayed into a format suitable for the display 626. The display controller 622 and / or the video processor 628 may include a GPU or be integrated into a GPU. The display 626 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0051] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. The memory disclosed herein can be a memory of any type and size and can be configured to store any type of information desired. In order to clearly illustrate this interchangeability, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choice, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as resulting in departure from the scope of this disclosure.

[0052] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative embodiment, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0053] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware and may reside, for example, in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. In an alternative embodiment, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative embodiment, the processor and storage medium may reside as discrete components in a remote station, a base station, or a server.

[0054] It is also noted that the operational steps described in any of the exemplary aspects herein are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. In addition, the operations described in a single operational step may actually be performed in a plurality of different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flow chart. Those skilled in the art will also understand that any of a variety of different technologies and techniques may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0055] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0056] Specific implementation examples are described in the following numbered clauses:

[0057] 1. A processor-based device, comprising:

[0058] a cache memory device; and

[0059] a cache controller circuit of the cache memory device, the cache controller circuit being configured to:

[0060] determining a plurality of content costs for each of a plurality of cached data values ​​in the cache memory device based on a plurality of bit values ​​of each of the plurality of cached data values;

[0061] identifying a cached data value associated with a lowest content cost among the plurality of cached data values ​​as a target cached data value based on the plurality of content costs; and

[0062] The target cached data value is evicted from the cache memory device.

[0063] 2. A processor-based device according to clause 1, wherein:

[0064] The cache memory device includes a plurality of groups, each group including a plurality of ways;

[0065] The cache controller circuit is further configured to:

[0066] identifying a set of the cache memory devices for caching a data value therein; and

[0067] The plurality of cached data values ​​stored in corresponding ways of the set are identified.

[0068] 3. A processor-based apparatus as recited in any one of clauses 1 to 2, wherein the plurality of content costs each comprises a count of the number of occurrences of a specified bit value in the plurality of bit values ​​of a cached data value in the plurality of cached data values.

[0069] 4. A processor-based device according to any of clauses 1 to 2, wherein:

[0070] The cache memory device is further configured to determine a most recently evicted data value; and

[0071] The plurality of content costs each include a count of the number of times each bit value of a plurality of bit values ​​of the most recently evicted data value changes compared to a corresponding bit value of the plurality of bit values ​​of the cached data value of the plurality of cached data values.

[0072] 5. A processor-based device according to any of clauses 1 to 4, wherein:

[0073] The cache controller circuit is further configured to:

[0074] determining whether all of the plurality of content costs have the same value; and

[0075] In response to determining that all of the plurality of content costs have the same value, identifying the cached data value of the plurality of cached data values ​​as the target cached data value using an alternative cache replacement policy; and

[0076] The cache controller circuitry is configured to identify the cached data value associated with the lowest content cost among the plurality of cached data values ​​as the target cached data value in response to determining that all of the plurality of content costs do not have the same value.

[0077] 6. A processor-based device according to any of clauses 1 to 5, wherein:

[0078] The cache controller circuit is further configured to:

[0079] receiving a data value to be cached;

[0080] determining a content cost of the data value;

[0081] determining whether the content cost of the data value is less than all of the plurality of content costs; and

[0082] In response to determining that the content cost of the data value is lower than all of the plurality of content costs, bypassing caching of the data value; and

[0083] The cache controller circuitry is configured to, in response to determining that the content cost of the data value is not less than all of the plurality of content costs, identify the cached data value among the plurality of cached data values ​​associated with the lowest content cost as the target cached data value.

[0084] 7. A processor-based device according to any of clauses 1 to 6, wherein:

[0085] The cache controller circuit is further configured to:

[0086] receiving a data value to be cached;

[0087] receiving a cache hint based on a plurality of bit values ​​of the data value;

[0088] determining whether to cache the data value based on the cache hint; and

[0089] In response to determining that the data value is not to be cached, bypassing caching of the data value; and

[0090] The cache controller circuitry is configured to, in response to determining that the data value is to be cached, identify the cached data value of the plurality of cached data values ​​associated with the lowest content cost as the target cached data value.

[0091] 8. A processor-based device according to any one of clauses 1 to 7, wherein the processor-based device is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a Session Initiation Protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

[0092] 9. A processor-based device, comprising:

[0093] means for determining a plurality of content costs for each of a plurality of cached data values ​​in a cache memory device based on a plurality of bit values ​​of each of the plurality of cached data values;

[0094] means for identifying, based on the plurality of content costs, a cached data value among the plurality of cached data values ​​associated with a lowest content cost as a target cached data value; and

[0095] Means for evicting the target cached data value from the cache memory device.

[0096] 10. A method for providing a content-aware cache replacement and insertion strategy, the method comprising:

[0097] determining, by a cache controller circuit, a plurality of content costs for each of a plurality of cached data values ​​in a cache memory device based on a plurality of bit values ​​of each cached data value;

[0098] identifying, by the cache controller circuitry, a cached data value associated with a lowest content cost among the plurality of cached data values ​​as a target cached data value based on the plurality of content costs; and

[0099] The target cached data value is evicted from the cache memory device by the cache controller circuitry.

[0100] 11. The method according to clause 10, further comprising:

[0101] identifying, by the cache controller circuitry, a set of the plurality of sets of the cache memory device for caching a data value therein; and

[0102] The plurality of cached data values ​​stored in corresponding ways of the group are identified by the cache controller circuitry.

[0103] 12. The method of any of clauses 10 to 11, wherein the plurality of content costs each comprises a count of the number of occurrences of a specified bit value in the plurality of bit values ​​of a cached data value in the plurality of cached data values.

[0104] 13. The method of any of clauses 10 to 11, further comprising determining, by the cache controller circuitry, a most recently evicted data value;

[0105] Wherein the plurality of content costs each comprise a count of the number of times each bit value of a plurality of bit values ​​of the most recently evicted data value changes compared to a corresponding bit value of the plurality of bit values ​​of the cached data value of the plurality of cached data values.

[0106] 14. The method of any of clauses 10 to 13, further comprising determining, by the cache controller circuitry, that all of the plurality of content costs do not have the same value;

[0107] wherein, in response to determining that all of the plurality of content costs do not have the same value, identifying the cached data value associated with the lowest content cost among the plurality of cached data values ​​as the target cached data value.

[0108] 15. The method according to any one of clauses 10 to 14, further comprising:

[0109] receiving, by the cache controller circuit, a data value to be cached;

[0110] determining, by the cache controller circuitry, a content cost for the data value; and

[0111] determining, by the cache controller circuitry, that the content cost of the data value is not less than all of the plurality of content costs; and

[0112] wherein, in response to determining that the content cost of the data value is not less than all of the plurality of content costs, identifying the cached data value associated with the lowest content cost among the plurality of cached data values ​​as the target cached data value.

[0113] 16. A method according to any one of clauses 10 to 15, wherein:

[0114] receiving, by the cache controller circuit, a data value to be cached from a client device;

[0115] receiving, by the cache controller circuitry from the client device, a cache hint based on a plurality of bit values ​​of the data value; and

[0116] determining, by the cache controller circuitry, to cache the data value based on the cache hint;

[0117] Wherein, in response to determining that the data value is to be cached, the cached data value associated with the lowest content cost among the plurality of cached data values ​​is identified as the target cached data value.

[0118] 17. A non-transitory computer-readable medium having stored thereon computer-executable instructions that, when executed, cause a processor to:

[0119] determining a plurality of content costs for each of a plurality of cached data values ​​in a cache memory device based on a plurality of bit values ​​of each of the plurality of cached data values;

[0120] identifying a cached data value associated with a lowest content cost among the plurality of cached data values ​​as a target cached data value based on the plurality of content costs; and

[0121] The target cached data value is evicted from the cache memory device.

[0122] 18. The non-transitory computer-readable medium of clause 17, wherein the plurality of content costs each comprise a count of the number of occurrences of a designated bit value in the plurality of bit values ​​of a cached data value in the plurality of cached data values.

[0123] 19. The non-transitory computer-readable medium of clause 17, wherein:

[0124] The computer-executable instructions further cause the processor to determine a most recently evicted data value; and

[0125] The plurality of content costs each include a count of the number of times each bit value of a plurality of bit values ​​of the most recently evicted data value changes compared to a corresponding bit value of the plurality of bit values ​​of the cached data value of the plurality of cached data values.

[0126] 20. The non-transitory computer-readable medium of any one of clauses 17 to 19, wherein the computer-executable instructions further cause the processor to:

[0127] determining whether all of the plurality of content costs have the same value; and

[0128] In response to determining that all of the plurality of content costs have the same value, a cached data value of the plurality of cached data values ​​is identified as a target cached data value using an alternative cache replacement policy.

Claims

1. A processor-based device, comprising: cache memory devices; and a cache controller circuit of the cache memory device, the cache controller circuit being configured to: determining a plurality of content costs for each of a plurality of cached data values ​​in the cache memory device based on a plurality of bit values ​​of each of the plurality of cached data values; identifying a cached data value associated with a lowest content cost among the plurality of cached data values ​​as a target cached data value based on the plurality of content costs; and The target cached data value is evicted from the cache memory device.

2. The processor-based device of claim 1 , wherein: The cache memory device includes a plurality of groups, each group including a plurality of ways; The cache controller circuit is further configured to: identifying a set of said cache memory devices for caching a data value therein; as well as The plurality of cached data values ​​stored in corresponding ways of the set are identified. 3 . The processor-based device of claim 1 , wherein the plurality of content costs each comprises a count of the number of occurrences of a specified bit value in the plurality of bit values ​​of a cached data value in the plurality of cached data values.

4. The processor-based device of claim 1 , wherein: The cache memory device is further configured to determine a most recently evicted data value; and The plurality of content costs each include a count of the number of times each bit value of a plurality of bit values ​​of the most recently evicted data value changes compared to a corresponding bit value of the plurality of bit values ​​of the cached data value of the plurality of cached data values.

5. The processor-based device of claim 1 , wherein: The cache controller circuit is further configured to: determining whether all of the plurality of content costs have the same value; and In response to determining that all of the plurality of content costs have the same value, identifying the cached data value of the plurality of cached data values ​​as the target cached data value using an alternative cache replacement policy; and The cache controller circuitry is configured to identify the cached data value associated with the lowest content cost among the plurality of cached data values ​​as the target cached data value in response to determining that all of the plurality of content costs do not have the same value.

6. The processor-based device of claim 1 , wherein: The cache controller circuit is further configured to: receiving a data value to be cached; determining a content cost of the data value; determining whether the content cost of the data value is less than all of the plurality of content costs; and In response to determining that the content cost of the data value is lower than all of the plurality of content costs, bypassing caching of the data value; and The cache controller circuitry is configured to, in response to determining that the content cost of the data value is not less than all of the plurality of content costs, identify the cached data value among the plurality of cached data values ​​associated with the lowest content cost as the target cached data value.

7. The processor-based device of claim 1 , wherein: The cache controller circuit is further configured to: receiving a data value to be cached; receiving a cache hint based on a plurality of bit values ​​of the data value; determining whether to cache the data value based on the cache hint; as well as In response to determining that the data value is not to be cached, bypassing caching of the data value; and The cache controller circuitry is configured to, in response to determining that the data value is to be cached, identify the cached data value of the plurality of cached data values ​​associated with the lowest content cost as the target cached data value.

8. The processor-based device of claim 1 , wherein the processor-based device is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a Session Initiation Protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

9. A processor-based device, comprising: means for determining a plurality of content costs for each of a plurality of cached data values ​​in a cache memory device based on a plurality of bit values ​​of each of the plurality of cached data values; means for identifying, based on the plurality of content costs, a cached data value among the plurality of cached data values ​​associated with a lowest content cost as a target cached data value; and Means for evicting the target cached data value from the cache memory device.

10. A method for providing a content-aware cache replacement and insertion strategy, the method comprising: determining, by a cache controller circuit, a plurality of content costs for each of a plurality of cached data values ​​in a cache memory device based on a plurality of bit values ​​of each cached data value; identifying, by the cache controller circuitry, a cached data value associated with a lowest content cost among the plurality of cached data values ​​as a target cached data value based on the plurality of content costs; and The target cached data value is evicted from the cache memory device by the cache controller circuitry.

11. The method according to claim 10, further comprising: identifying, by the cache controller circuitry, a group of the plurality of groups of the cache memory device for caching a data value therein; as well as The plurality of cached data values ​​stored in corresponding ways of the group are identified by the cache controller circuitry.

12. The method of claim 10, wherein the plurality of content costs each comprise a count of the number of occurrences of a designated bit value in the plurality of bit values ​​of a cached data value in the plurality of cached data values.

13. The method of claim 10, further comprising determining, by the cache controller circuitry, a most recently evicted data value; Wherein the plurality of content costs each comprise a count of the number of times each bit value of a plurality of bit values ​​of the most recently evicted data value changes compared to a corresponding bit value of the plurality of bit values ​​of the cached data value of the plurality of cached data values.

14. The method of claim 10, further comprising determining, by the cache controller circuitry, that all of the plurality of content costs do not have the same value; in, In response to determining that all of the plurality of content costs do not have the same value, the cached data value associated with the lowest content cost among the plurality of cached data values ​​is identified as the target cached data value.

15. The method according to claim 10, further comprising: receiving, by the cache controller circuit, a data value to be cached; determining, by the cache controller circuitry, a content cost of the data value; as well as determining, by the cache controller circuitry, that the content cost of the data value is not less than all of the plurality of content costs; and wherein, in response to determining that the content cost of the data value is not less than all of the plurality of content costs, identifying the cached data value associated with the lowest content cost among the plurality of cached data values ​​as the target cached data value.

16. The method of claim 10, wherein: receiving, by the cache controller circuit, a data value to be cached from a client device; receiving, by the cache controller circuitry from the client device, a cache hint based on a plurality of bit values ​​of the data value; as well as determining, by the cache controller circuitry, to cache the data value based on the cache hint; Wherein, in response to determining that the data value is to be cached, the cached data value associated with the lowest content cost among the plurality of cached data values ​​is identified as the target cached data value.

17. A non-transitory computer-readable medium having stored thereon computer-executable instructions that, when executed, cause a processor to: determining a plurality of content costs for each of a plurality of cached data values ​​in a cache memory device based on a plurality of bit values ​​of each of the plurality of cached data values; identifying a cached data value associated with a lowest content cost among the plurality of cached data values ​​as a target cached data value based on the plurality of content costs; and The target cached data value is evicted from the cache memory device. 18 . The non-transitory computer-readable medium of claim 17 , wherein the plurality of content costs each comprise a count of the number of occurrences of a designated bit value in the plurality of bit values ​​of a cached data value in the plurality of cached data values.

19. The non-transitory computer readable medium of claim 17, wherein: The computer-executable instructions further cause the processor to determine a most recently evicted data value; and The plurality of content costs each include a count of the number of times each bit value of a plurality of bit values ​​of the most recently evicted data value changes compared to a corresponding bit value of the plurality of bit values ​​of the cached data value of the plurality of cached data values.

20. The non-transitory computer-readable medium of claim 17, wherein the computer-executable instructions further cause the processor to: determining whether all of the plurality of content costs have the same value; and In response to determining that all of the plurality of content costs have the same value, a cached data value of the plurality of cached data values ​​is identified as a target cached data value using an alternative cache replacement policy.

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