Semiconductor substrate

Abstract

The present technology relates to a semiconductor substrate configured such that when two substrates are bonded to each other, bonding defects can be reduced. The semiconductor substrate includes: an insulating film; an electrode provided in the insulating film, the electrode being bonded to an electrode provided on another semiconductor substrate when the semiconductor substrate is bonded to the other semiconductor substrate; a barrier metal provided between the insulating film and the electrode; and a film disposed between the barrier metal and the electrode. The present technology can be applied to a device in which a plurality of semiconductor substrates are stacked, such as an imaging device.

Description

Technical Field

[0001] The present technology relates to a semiconductor substrate, for example, to a semiconductor substrate capable of more reliably bonding electrodes to each other when two substrates are bonded together. Background Art

[0002] In stacked image sensors, wafers are sometimes directly bonded together using hybrid bonding, in which wafers are electrically bonded to each other by bonding metal connection pads formed in a wiring layer (see, for example, Patent Document 1).

[0003] [Citation List]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. JP 2019-110260A Summary of the Invention

[0006] [Technical Issues]

[0007] The connection pads are then heat-treated after being overlapped. The metal forming the connection pads expands during the heat treatment, which prevents the contact between the connection pads from deteriorating. With the advancement of miniaturization, the size of such connection pads is getting smaller and smaller.

[0008] As the size of the connection pad decreases, the volume of the metal that makes up the connection pad also decreases. Furthermore, as the volume of the metal decreases, the amount of expansion caused by heat treatment also decreases. Even when the connection pad is miniaturized, it is desirable to ensure that the contact properties of the connection pad do not deteriorate.

[0009] In view of this situation, the present technology can ensure that the contact properties of the connection pads are not deteriorated.

[0010] [Solution to the problem]

[0011] The first semiconductor substrate of one aspect of the present technology is a semiconductor substrate comprising: an insulating film; an electrode arranged in the insulating film, and when the semiconductor substrate is bonded to another semiconductor substrate, the electrode is joined to an electrode arranged on the other semiconductor substrate; a barrier metal arranged between the insulating film and the electrode; and a film arranged between the barrier metal and the electrode.

[0012] The second semiconductor substrate of one aspect of the present technology is a semiconductor substrate comprising: an insulating film; an electrode arranged within the insulating film, wherein when the semiconductor substrate is bonded to another semiconductor substrate, the electrode is joined to an electrode arranged on the other semiconductor substrate; and a barrier metal arranged between the insulating film and the electrode, wherein the inclination of the barrier metal arranged on one side wall of the electrode is different from the inclination of the barrier metal arranged on the other side wall of the electrode.

[0013] A first semiconductor substrate in one aspect of the present technology includes: an electrode arranged in the insulating film, and when the semiconductor substrate is attached to another semiconductor substrate, the electrode is joined to an electrode arranged on the other semiconductor substrate; a barrier metal arranged between the insulating film and the electrode; and a film arranged between the barrier metal and the electrode.

[0014] A second semiconductor substrate according to one aspect of the present technology includes: an insulating film; an electrode disposed within the insulating film, wherein when the semiconductor substrate is bonded to another semiconductor substrate, the electrode is bonded to an electrode disposed on the other semiconductor substrate; and a barrier metal disposed between the insulating film and the electrode, wherein the inclination of the barrier metal disposed on one side wall of the electrode is different from the inclination of the barrier metal disposed on the other side wall of the electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 1 is a diagram showing the configuration of one embodiment of an imaging device to which the present technology is applied.

[0016] Figure 2 A diagram showing an example of a cross-sectional structure of a pixel.

[0017] Figure 3 This is a schematic diagram explaining the wiring connections.

[0018] Figure 4 A diagram showing a configuration example of a pixel according to Embodiment 1.

[0019] Figure 5 Graph illustrating adhesion strength.

[0020] Figure 6 Graph illustrating adhesion strength.

[0021] Figure 7 is a diagram illustrating the manufacture of a pixel according to Embodiment 1.

[0022] Figure 8 This is a diagram showing an example of the configuration of a pixel according to Implementation Option 2.

[0023] Figure 9is a diagram illustrating the manufacture of a pixel according to Embodiment 2.

[0024] Figure 10 This is a diagram showing an example of the configuration of a pixel according to Implementation Option 3.

[0025] Figure 11 3 is a diagram illustrating the manufacture of a pixel according to Embodiment 3.

[0026] Figure 12 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 4-1.

[0027] Figure 13 is a diagram illustrating the manufacture of a pixel according to Embodiment 4-1.

[0028] Figure 14 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 4-2.

[0029] Figure 15 is a diagram illustrating the manufacture of a pixel according to Embodiment 4-2.

[0030] Figure 16 This is a diagram showing an example of the structure of a pixel according to implementation scheme 5.

[0031] Figure 17 is a diagram illustrating the manufacture of a pixel according to Embodiment 5.

[0032] Figure 18 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 6.

[0033] Figure 19 is a diagram illustrating the manufacture of a pixel according to Embodiment 6.

[0034] Figure 20 This is a diagram showing an example of the structure of a pixel according to implementation scheme 7.

[0035] Figure 21 is a diagram illustrating the manufacture of a pixel according to Embodiment 7.

[0036] Figure 22 is a diagram illustrating the manufacture of a pixel according to Embodiment 7.

[0037] Figure 23 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 8.

[0038] Figure 24 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 8.

[0039] Figure 25 is a diagram illustrating the manufacture of a pixel according to Embodiment 8.

[0040] Figure 26is a diagram illustrating the manufacture of a pixel according to Embodiment 8.

[0041] Figure 27 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 9.

[0042] Figure 28 is a diagram illustrating the manufacture of a pixel according to Embodiment 9.

[0043] Figure 29 This is a diagram showing an example of the structure of a pixel according to implementation scheme 10.

[0044] Figure 30 This is a diagram showing an example of the structure of a pixel according to implementation scheme 10.

[0045] Figure 31 is a diagram illustrating the manufacture of a pixel according to Embodiment 10.

[0046] Figure 32 is a diagram illustrating the manufacture of a pixel according to Embodiment 10.

[0047] Figure 33 This is a diagram showing an example of the structure of a pixel according to implementation scheme 11.

[0048] Figure 34 is a diagram illustrating the manufacture of a pixel according to Embodiment 11.

[0049] Figure 35 is a schematic diagram illustrating the depression.

[0050] Figure 36 1 is a diagram showing a structure for suppressing dishing.

[0051] Figure 37 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 12.

[0052] Figure 38 is a diagram illustrating the manufacture of a pixel according to embodiment 12.

[0053] Figure 39 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 13.

[0054] Figure 40 is a diagram illustrating the manufacture of a pixel according to embodiment 13.

[0055] Figure 41 is a diagram illustrating the manufacture of a pixel according to embodiment 13.

[0056] Figure 42 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 13.

[0057] Figure 43This is a diagram showing an example of the configuration of a pixel according to implementation scheme 14.

[0058] Figure 44 This is a diagram illustrating the function of the expansion assisting membrane.

[0059] Figure 45 is a diagram illustrating the manufacture of a pixel according to embodiment 14.

[0060] Figure 46 This is a diagram showing an example of a cross-sectional structure of a pixel according to embodiment 15.

[0061] Figure 47 This is a diagram showing an example of a planar structure of a pixel according to implementation scheme 15.

[0062] Figure 48 This is a diagram illustrating the function of the expansion assisting membrane.

[0063] Figure 49 2 is a diagram showing another cross-sectional configuration example of a pixel according to embodiment 15.

[0064] Figure 50 2 is a diagram showing another cross-sectional configuration example of a pixel according to embodiment 15.

[0065] Figure 51 is a diagram illustrating the manufacture of a pixel according to embodiment 15.

[0066] Figure 52 is a diagram illustrating the manufacture of a pixel according to embodiment 15.

[0067] Figure 53 A diagram showing an example of a cross-sectional structure of a pixel according to embodiment 16.

[0068] Figure 54 This is a diagram showing an example of a planar structure of a pixel according to implementation scheme 16.

[0069] Figure 55 2 is a diagram showing another planar configuration example of a pixel according to embodiment 16.

[0070] Figure 56 is a diagram illustrating the manufacture of a pixel according to embodiment 16.

[0071] Figure 57 It is a diagram showing the orientation at the electrode bonding surface.

[0072] Figure 58 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 17.

[0073] Figure 59 It is a diagram showing the structure of the side wall and bottom surface of the electrode.

[0074] Figure 60 is a diagram illustrating the manufacture of a pixel according to Embodiment 17.

[0075] Figure 61 is a diagram showing another example of pixel manufacturing according to embodiment 17.

[0076] Figure 62 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 18.

[0077] Figure 63 It is a diagram illustrating the orientation direction of electrodes.

[0078] Figure 64 is a diagram illustrating the manufacture of a pixel according to embodiment 18.

[0079] Figure 65 is a diagram showing another example of pixel manufacturing according to embodiment 18.

[0080] Figure 66 is a diagram showing another example of pixel manufacturing according to embodiment 18.

[0081] Figure 67 This is a diagram showing an example of the configuration of a pixel according to implementation scheme 19.

[0082] Figure 68 is a diagram illustrating the manufacture of a pixel according to embodiment 19.

[0083] Figure 69 is a diagram illustrating the manufacture of a pixel according to embodiment 19.

[0084] Figure 70 This is a diagram showing in detail an example of the configuration of a pixel according to implementation scheme 19.

[0085] Figure 71 A diagram showing an example of a cross-sectional structure of a pixel according to embodiment 20.

[0086] Figure 72 is a diagram illustrating the manufacture of a pixel according to Embodiment 20.

[0087] Figure 73 A diagram showing an example of a cross-sectional structure of a pixel according to embodiment 20.

[0088] Figure 74 is a diagram illustrating the manufacture of a pixel according to Embodiment 20.

[0089] Figure 75 A diagram showing an example of a cross-sectional structure of a pixel according to embodiment 20.

[0090] Figure 76 is a diagram illustrating the manufacture of a pixel according to Embodiment 20.

[0091] Figure 77 A diagram showing an example of a cross-sectional structure of a pixel according to embodiment 20.

[0092] Figure 78 A diagram showing an example of a cross-sectional structure of a pixel according to embodiment 20.

[0093] Figure 79 A diagram showing an example of a cross-sectional structure of a pixel according to embodiment 21.

[0094] Figure 80 is a diagram showing the bonding of pixels according to embodiment 21.

[0095] Figure 81 is a diagram illustrating the manufacture of a pixel according to embodiment 21.

[0096] Figure 82 is a diagram illustrating the manufacture of a pixel according to embodiment 21.

[0097] Figure 83 is a diagram illustrating the manufacture of a pixel according to embodiment 21.

[0098] Figure 84 A diagram showing an example of a cross-sectional structure of a pixel according to embodiment 21.

[0099] Figure 85 is a diagram illustrating the manufacture of a pixel according to embodiment 21.

[0100] Figure 86 is a diagram illustrating the manufacture of a pixel according to embodiment 21.

[0101] Figure 87 It is a diagram illustrating the patterned shape.

[0102] Figure 88 A diagram showing an example of a cross-sectional structure of a pixel according to embodiment 22.

[0103] Figure 89 is a diagram showing the joining of pixels according to embodiment 22.

[0104] Figure 90 is a diagram illustrating the manufacture of a pixel according to embodiment 22.

[0105] Figure 91 is a diagram illustrating the manufacture of a pixel according to embodiment 22.

[0106] Figure 92 is a diagram illustrating the manufacture of a pixel according to embodiment 22.

[0107] Figure 93is a diagram illustrating the manufacture of a pixel according to embodiment 22.

[0108] Figure 94 A diagram showing an example of a cross-sectional structure of a pixel according to embodiment 22.

[0109] Figure 95 is a diagram illustrating the manufacture of a pixel according to embodiment 22.

[0110] Figure 96 is a diagram illustrating the manufacture of a pixel according to embodiment 22.

[0111] Figure 97 It is a diagram showing a configuration example of an electronic device.

[0112] Figure 98 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0113] Figure 99 : is a block diagram showing an example of the functional configuration of a camera head and a camera control unit (CCU).

[0114] Figure 100 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0115] Figure 101 1 and 2 are diagrams for assisting in explaining examples of installation positions of the vehicle exterior information detection unit and the imaging portion. DETAILED DESCRIPTION

[0116] Modes for carrying out the present technology (hereinafter referred to as embodiments) will be described below.

[0117] <Overall Configuration Example of Imaging Device>

[0118] Figure 1 : is a diagram showing the configuration of one embodiment of an imaging device to which the present technology is applied. Figure 1 , imaging device 1 is a three-dimensional semiconductor device composed of a first substrate 11 serving as a sensor substrate and a second substrate 21 serving as a circuit substrate attached to first substrate 11 so as to be stacked thereon. Imaging device 1 is configured as an image sensor, such as a complementary metal oxide semiconductor (CMOS) image sensor.

[0119] In the imaging device 1, a pixel region 13 is provided in a first substrate 11, in which a plurality of pixels 12 (each including a photoelectric conversion unit) are regularly arranged two-dimensionally. In the pixel region 13, a plurality of pixel drive lines 14 are provided in the row direction, and a plurality of vertical signal lines 15 are provided in the column direction, and one pixel 12 is provided so as to be connected to one pixel drive line 14 and one vertical signal line 15.

[0120] Each pixel 12 is provided with a photoelectric conversion unit, a floating diffusion (FD) region, and a pixel circuit composed of multiple pixel transistors. Note that multiple pixels 12 can share part of the pixel circuit. On the other hand, peripheral circuits such as a vertical drive circuit 22, a column signal processing circuit 23, a horizontal drive circuit 24, and a system control circuit 25 are provided in the second substrate 21.

[0121] <Example of Imaging Apparatus>

[0122] Figure 2 It shows Figure 1 FIG. 1 shows an example of a cross-sectional configuration of a pixel 12. The pixel 12 includes a first semiconductor substrate 30 and a second semiconductor substrate 40 bonded to the first semiconductor substrate 30. The first semiconductor substrate 30 includes, for example, a Si substrate 33 and a transistor 34 formed of a complementary metal oxide semiconductor on the Si substrate 33. Multiple wiring layers are stacked on the transistor 34, with the first wiring layer 31 formed at the position farthest from the substrate 33 (the uppermost layer). A diffusion prevention film 41 composed of, for example, SiCN, SiN, or the like is provided between the wiring layers.

[0123] A first electrode pad 54 made of, for example, Cu and a dummy electrode 55 made of, for example, Cu are provided in the first wiring layer 31. The first electrode pad 54 and the dummy electrode 55 are embedded in an interlayer insulating film 39 made of a low dielectric constant material such as organic quartz glass, SiO2, or the like, and are located on the same surface of the first electrode pad 54, the dummy electrode 55, and the interlayer insulating film 39 on the side opposite to the Si substrate 33. The first electrode pad 54 is connected to wiring in the wiring layer on the Si substrate 33 side through a via.

[0124] On the other hand, the second semiconductor substrate 40 includes a photoelectric conversion layer 35 that outputs an electrical signal (charge) according to the amount of received light, a color filter 36 arranged on the photoelectric conversion layer 35, and a microlens 37 arranged on the color filter 36. An insulating film 38 is formed on the photoelectric conversion layer 35 in a region other than the color filter 36. Each set of the photoelectric conversion layer 35, the color filter 36, and the microlens 37 forms one pixel.

[0125] The wiring layers are stacked on the surface of the photoelectric conversion layer 35 opposite the color filter 36, and the second wiring layer 32 is formed at the position farthest from the photoelectric conversion layer 35. A diffusion prevention film 42 composed of, for example, SiCN or SiN is formed between the wiring layers. The second wiring layer 32 is composed of an interlayer insulating film 43 made of a low-dielectric-constant material such as organic quartz glass or SiO2, a second electrode pad 57, and a dummy electrode 58. The second electrode pad 57 and the dummy electrode 58 are embedded in the interlayer insulating film 43 and are located in the same plane as the second electrode pad 57, the dummy electrode 58, and the surface of the interlayer insulating film 43 opposite the photoelectric conversion layer 35.

[0126] The photoelectric conversion layer 35 is composed of, for example, a photodiode, etc. The transistor 34 provided on the second semiconductor substrate is a so-called transfer transistor, a reset transistor, an amplifier transistor, etc., and is used to calculate the charge output from the photoelectric conversion layer 35 .

[0127] <Joints where pumping occurs>

[0128] Figure 3 1 is a cross-sectional view showing a state of a junction portion of electrodes during a pumping phenomenon when two substrates (eg, a first semiconductor substrate 30 and a second semiconductor substrate 40) are attached to each other. Figure 3 The bonding portion between the first electrode pad 54 and the second electrode pad 57 will be described.

[0129] like Figure 3 As shown in FIG. 1A , of the two substrates to be bonded, a stacked film 100-1 is formed on the upper substrate (second semiconductor substrate 40), in which an interlayer insulating film 101-1, a liner insulating film 102-1, and an interlayer insulating film 103-1 are stacked. An electrode 105-1 (e.g., corresponding to the first electrode pad 54) made of copper (Cu) is formed in the stacked film 100-1 as an electrode. A barrier metal 104-1 is formed between the stacked film 100-1 and the electrode 105-1.

[0130] As with the upper substrate, a stacked film 100-2 is formed on the lower substrate (first semiconductor substrate 30) in which interlayer insulating films 101-2 to 103-2 are stacked. Copper (Cu) serving as an electrode 105-2 (e.g., corresponding to the second electrode pad 57) is formed in the stacked film 100-2. A barrier metal 104-2 is formed between the stacked film 100-2 and the electrode 105-2.

[0131] Due to the recess, the electrode 105-1 is formed slightly recessed from the position of the bonding surface. Similarly, due to the recess, the electrode 105-2 is formed slightly recessed from the position of the bonding surface.

[0132] Figure 3 B shows the structure of the joint after the two substrates are attached to each other. Figure 3 When heat treatment is performed on the joint portion shown in B, the joint portion enters Figure 3 In other words, a pumping phenomenon occurs due to the heat treatment, and copper (Cu) serving as electrodes 105-1 and 105-2 in the stacked films 100-1 and 100-2 formed on the upper and lower substrates expands (110-1 and 110-2 in the figure).

[0133] Electrode 105-1 and electrode 105-2 are bonded using this pumping phenomenon. By utilizing the thermal expansion of electrodes 105, degradation of contact between electrodes 105 can be suppressed. On the other hand, as the size of electrodes 105 decreases with the miniaturization of pixel 12, the capacity of the metal constituting electrodes 105 also decreases. As the capacity of the metal decreases, the amount of expansion caused by heat treatment decreases, which can lead to bonding defects.

[0134] As electrodes 105 are miniaturized, the amount of concavity tends to increase. If the amount of concavity increases, the distance between electrodes 105 on two substrates increases when the substrates are bonded together. Therefore, even if electrodes 105 expand, the expansion will not compensate for this distance. Electrodes 105 will not contact each other, potentially leading to bonding defects.

[0135] An electrode structure that can suppress the occurrence of bonding defects will be described.

[0136] <Implementation Plan 1>

[0137] Figure 4 This is a diagram showing a configuration example of a pixel 12 a according to Embodiment 1 to which the present technology is applied. Figure 4 A single electrode constituting the pixel 12a is shown, and the following electrode (electrode pad) is shown, which is arranged on the bonding surface side where the first semiconductor substrate 30 and the second semiconductor substrate 40 are bonded, and is bonded using the above-mentioned pumping phenomenon to make the first semiconductor substrate 30 and the second semiconductor substrate 40 conductive.

[0138] Although an electrode is described here as an example, the present technology described below can be applied not only to an electrode having a conduction function but also to a joining member that lacks a conduction function but joins semiconductor substrates to each other.

[0139] As an example, an electrode provided in an imaging device 1 including a pixel 12 having a stacked structure in which a first semiconductor substrate 30 and a second semiconductor substrate 40 are bonded will be described below. Figure 2 However, the technology described below is not only applicable to devices that constitute such an imaging device 1, but can also be widely applied to devices having a stacked structure. The technology can also be applied to a single substrate to be stacked. In other words, the technology can be applied to electrodes provided in a semiconductor substrate before stacking.

[0140] like Figure 4 As shown, the electrode formed at the bonding portion is configured by forming an electrode 105 in a stacked film 100 in which an interlayer insulating film 101 , a liner insulating film 102 , and an interlayer insulating film 103 are stacked.

[0141] Figure 4The electrode 105 shown has a dual damascene shape and is configured with a connection hole 121 and a wiring hole 122. As described later, this technology can be applied to an electrode having a single damascene shape and can also be applied to a configuration having only a connection hole.

[0142] The barrier metal 104 and the expansion hindrance suppression film 131 are formed between the stacked film 100 and the electrode 105. More specifically, the barrier metal 104 and the expansion hindrance suppression film 131 are formed on the side surface of each of the connection hole 121 and the wiring hole 122 between the stacked film 100 and the electrode 105. The barrier metal 104 is formed on the bottom surface of each of the connection hole 121 and the wiring hole 122 between the stacked film 100 and the electrode 105.

[0143] The expansion hindrance suppression film 131 is a film formed of a material that does not hinder thermal expansion of the material constituting the electrode 105 during heat treatment.

[0144] For example, Figure 3 As shown, if only the barrier metal 104 is formed between the stacked film 100 and the electrode 105, the barrier metal 104 may hinder the expansion of the electrode 105, resulting in a reduction in the amount of expansion of the electrode 105. If the adhesion between the barrier metal 104 and the electrode 105 is high, the electrode 105 may be Figure 4 The expansion force in the upward direction may be suppressed and weakened by the barrier metal 104 , and the expansion may be insufficient.

[0145] However, the expansion retardation suppression film 131 is provided between the barrier metal 104 and the electrode 105, so the structure is such that the barrier metal 104 does not hinder the expansion of the electrode 105. Reducing the adhesion strength between the expansion retardation suppression film 131 and the electrode 105 can suppress the electrode 105 from Figure 4 The expansion force in the middle upward direction is suppressed and weakened by the expansion hindrance suppression film 131, so that sufficient expansion can be achieved.

[0146] For example, indium tin oxide (ITO), SiO 2 formed by plasma deposition, SiO formed by atomic layer deposition (ALD), or the like can be used as the expansion hindrance suppression film 131 .

[0147] For example, the adhesion strength between material A and material B can be determined as follows. Here, an example of calculating the adhesion strength by a method called 4-point bending (PB) will be given, and reference will be made to Figure 5 and Figure 6 Provide explanation.

[0148] like Figure 5As shown in Figure A, a sample substrate is prepared in which the material (evaluation material 162) serving as the expansion retardation suppression film 131 is formed on a Cu substrate 161. For example, a silicon substrate 162 is attached to the sample substrate on the material 162 side using epoxy adhesive. For example, the sample substrate is cut into a size of 8 mm x 40 mm. Using a cutter, a notch 164 is formed on the sample substrate side of the sample substrate laminated with the silicon substrate 162.

[0149] like Figure 5 As shown in Figure B, a sample substrate with notches 164 formed is placed in the measuring instrument and measurement begins. The sample substrate, with the evaluation material 162 facing downward, is supported by two fixed supports 166. Then, two blades 167 apply pressure from the top of the silicon substrate 162. The amount of movement of blades 167 and the repulsive force of blades 167 are measured.

[0150] Figure 6 A shows an example of the measurement result when such measurement is performed. Figure 6 In Figure A, the vertical axis represents repulsive force (N) and the horizontal axis represents movement (μm). Although specific values ​​are not given, initially, when measurement begins, the chip stretches, and after a while, cracks begin to form in the area where the notch is located. As blade 167 moves further, the interface fractures (stress relaxation), and then delamination occurs.

[0151] In this peeling state, even if the blade 167 moves, the repulsive force remains constant for a period of time. When the peeling is completed, the repulsive force increases as the blade 167 moves until the chip breaks. Using such measurement results, the adhesion strength (G value) is determined based on the following formula (1).

[0152] [Mathematical formula 1]

[0153]

[0154] In formula (1), E represents the physical property value of the epoxy resin, ν represents the physical property value of the silicon substrate 163, and P represents the repulsive force of the peeled portion obtained from the measurement results. b represents the width of the sample substrate, which is 8 mm in this case. h1 represents the thickness of the Cu substrate 161, h2 represents the thickness of the evaluation material 162, and l represents the distance from the end of the sample substrate to the support member 166, which is set to 11.4 mm, for example.

[0155] The evaluation material 162 having a G value (N / m) obtained by formula (1) not greater than a predetermined value can be used as the expansion hindrance suppression film 131. For example, when the evaluation material 162 formed on the Cu substrate 161 is SiO, the G value is 1 to 6 N / m.

[0156] Although Ti (titanium) or W (tungsten) can be used as the barrier metal 104, it has been confirmed that when titanium or tungsten is used as the evaluation material 162 and the G value is calculated after forming the Cu substrate 161, the G value is at least 25 N / m. It has also been confirmed that when the G value is calculated using a sample substrate in which titanium or tungsten is used instead of the Cu substrate 161 and SiO is formed on the titanium or tungsten, the G value is at least 25 N / m.

[0157] Based on this, for example, Figure 3 In the electrode shown, which is composed of the barrier metal 104 and the electrode 105, the adhesion strength between the barrier metal 104 and the electrode 105 is 25 N / m, which is a high adhesion strength. Therefore, when the copper (Cu) constituting the electrode 105 expands, the expansion force may be suppressed by the barrier metal 104.

[0158] On the other hand, Figure 4 As shown, when expansion-preventing film 131 is provided between barrier metal 104 and electrode 105, the adhesion strength between expansion-preventing film 131 and electrode 105 decreases. For example, when SiO is used as expansion-preventing film 131, the adhesion strength between expansion-preventing film 131 and electrode 105 (in this case, the adhesion strength between SiO and copper (Cu)) is low, namely, approximately 1 to 6 N / m. Therefore, when the copper (Cu) constituting electrode 105 expands, the expansion force is prevented from being suppressed by expansion-preventing film 131.

[0159] In this manner, the expansion retardation suppression film 131 is formed between the barrier metal 104 and the electrode 105 from a material having low adhesion strength with the material of the electrode 105, so that the electrode 105 can be allowed to expand without suppressing the expansion of the electrode 105 during thermal expansion. This in turn can suppress the occurrence of bonding defects.

[0160] Since the expansion-preventing film 131 is made of a material having a relatively low adhesion strength relative to the material of the electrode 105, a suitable combination of expansion-preventing film 131 is appropriately selected depending on the material of the electrode 105. Examples of materials for the electrode 105 include metals such as Cu, Ag, Au, Be, Al, Zn, Sn, Ni, Pb, Co, Ru, Mo, W, Ta, and Ti, as well as alloys primarily composed of Cu or Al, such as duralumin and bronze. The material of the expansion-preventing film 131 suitable for the material being used can be determined based on which of these materials is used as the electrode 105.

[0161] Here, an example has been described in which a material that reduces the adhesion strength with the electrode 105 is used as the expansion hindrance suppression film 131. However, a material having a low friction coefficient may also be used as the expansion hindrance suppression film 131.

[0162] Consider again Figure 3 The case shown is where only the barrier metal 104 is formed between the stacked film 100 and the electrode 105. Figure 3 In the structure of the electrode 105 shown in FIG. 1 , the barrier metal 104 can hinder the expansion of the electrode 105, and as a result, the expansion amount of the electrode 105 may be reduced. If the friction force of the barrier metal 104 relative to the electrode 105 is high, the electrode 105 Figure 4 The expansion force in the upward direction may be suppressed and weakened by the barrier metal 104 , and the expansion may be insufficient.

[0163] The expansion-blocking suppression film 131 is provided between the barrier metal 104 and the electrode 105, so that friction is less likely to occur between the expansion-blocking suppression film 131 and the electrode 105, thereby providing a structure in which the barrier metal 104 does not block the expansion of the electrode 105. This in turn suppresses the expansion of the electrode 105. Figure 4 The expansion force in the middle upward direction is suppressed and weakened by the expansion hindrance suppression film 131, so that sufficient expansion can be achieved.

[0164] For example, carbon (C), molybdenum disulfide (MoS 2 ), or the like can be used as the expansion hindrance suppression film 131 .

[0165] For example, tantalum (Ta) can be used as the barrier metal 104, but the friction coefficient of tantalum is approximately 0.58. In this case, a material with a friction coefficient of 0.58 or less can be used as the expansion retardation suppression film 131. For example, carbon (C) has a friction coefficient of approximately 0.10 to 0.15, which is less than 0.58, and is therefore suitable for use as the expansion retardation suppression film 131. For example, molybdenum disulfide (MoS2) has a friction coefficient of approximately 0.04, which is less than 0.58, and is therefore suitable for use as the expansion retardation suppression film 131.

[0166] In addition to carbon (C) and molybdenum disulfide (MoS2), tungsten disulfide (WS2), tungsten selenide (WSe2), hafnium sulfide (HfS2), boron nitride (BN), or materials such as graphite, graphene, fullerene, carbon nanotubes, diamond-like carbon, and diamond (which are compositions containing carbon as a main component) can also be used as the material of the expansion retardation suppression film 131. For example, a material having a static friction coefficient of 0.2 (μ) or less can be used as the material of the expansion retardation suppression film 131.

[0167] Reference Figure 4 When an upward expansion force occurs in the electrode 105 in the figure, the expansion-obstructing film 131 provided between the barrier metal 104 and the electrode 105 prevents the expansion-obstructing film 131 from suppressing the upward force. Therefore, the expansion of the electrode 105 is not hindered, and bonding with the electrode provided on the substrate to be bonded can be performed without any problems.

[0168] Because in Figure 4 In the illustrated configuration, the expansion-obstruction-suppressing film 131 is not formed on the bottom surface of the wiring hole 122 . Therefore, a non-conductive material other than a conductive material may be used as the material of the expansion-obstruction-suppressing film 131 .

[0169] <Manufacturing according to Embodiment 1>

[0170] Will refer to Figure 7 Description Figure 4 The pixel 12a is manufactured by forming the electrode 105 shown in FIG. Figure 7 The manufacture of a portion of the electrode 105 will be described.

[0171] In step S11, a substrate is prepared in which a stacked film 100 is formed in which an interlayer insulating film 101, a liner insulating film 102, and an interlayer insulating film 103 are stacked. The connection hole 121 and the wiring hole 122 are formed by etching the stacked film 100.

[0172] For example, in a photolithography step, a photoresist is applied to generate a resist pattern (patterning) for forming the wiring hole 122. An etching step is performed, and dry etching is performed using the resist pattern generated in the photolithography step as a mask, thereby forming the wiring hole 122. The connection hole 121 can be formed by repeating the same process.

[0173] In step S12 , the barrier metal 104 is formed by, for example, sputtering. The barrier metal 104 is formed on the side surfaces and bottom surfaces of the connection hole 121 and the wiring hole 122 , and also on the top surface of the interlayer insulating film 103 .

[0174] In step S13, an expansion-preventing film 131 is formed on the barrier metal 104. The expansion-preventing film 131 can also be formed by sputtering. If a material with low adhesion strength (such as an oxide film) is used as the expansion-preventing film 131, an oxide film is formed in step S13. If a material with a low friction coefficient (such as carbon) is used as the expansion-preventing film 131, a carbon film is formed in step S13.

[0175] In step S14, the expansion hindering suppressing film 131 is removed by an etch-back process. Since the expansion hindering suppressing film 131 is removed by the etch-back process, the expansion hindering suppressing film 131 on the interlayer insulating film 103, the expansion hindering suppressing film 131 on the bottom surface of the connection hole 121, and the expansion hindering suppressing film 131 on the bottom surface of the wiring hole 122 are removed. In other words, the expansion hindering suppressing film 131 in the area other than the expansion hindering suppressing film 131 formed on the side surface of the connection hole 121 and the side surface of the wiring hole 122 is removed.

[0176] In step S15, the material of the electrode 105, for example, copper (Cu), is embedded in the connection hole 121 and the wiring hole 122. The electrode 105 made of copper (Cu) is embedded in the connection hole 121 and the wiring hole 122 by Cu sputtering and then Cu plating.

[0177] In step S16 , the Cu is polished and planarized. This step removes excess Cu and the barrier metal 104 on the top surface of the interlayer insulating film 103 by chemical mechanical planarization (CMP).

[0178] Through the above steps, a Figure 4 The electrodes of the expansion hindrance suppression film 131 are shown.

[0179] While sputtering is used as an example for forming the barrier metal 104 and the expansion retardation suppression film 131, the film formation method is not limited to sputtering. For example, plasma enhanced CVD (PECVD), thermal CVD (TCVD) using heat, photo CVD (photo CVD) using light, metal CVD (MCVD), and metal organic CVD (MOCVD) are examples of chemical vapor deposition (CVD). Molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD) can also be used for film formation. These methods can also be appropriately applied in the following description.

[0180] <Implementation Plan 2>

[0181] Figure 8 This is a diagram showing a configuration example of a pixel 12b according to Embodiment 2 to which the present technology is applied. Figure 8 The pixel 12b according to Embodiment 2 is shown Figure 4 The same parts among the illustrated pixels 12 a according to Embodiment 1 are given the same reference numerals, and description thereof is appropriately omitted.

[0182] When compared Figure 8 The pixel 12b according to Embodiment 2 is shown Figure 4 In the illustrated pixel 12a according to Embodiment 1, the region where the expansion hindering suppression film 131b of the pixel 12b is formed is different from the region where the expansion hindering suppression film 131 of the pixel 12a is formed. Other points are the same.

[0183] Figure 8 The expansion hindrance suppressing film 131 b of the illustrated pixel 12 b is provided on the side surface of the connection hole 121 , but is not provided on the side surface of the wiring hole 122 . Figure 8The expansion hindrance suppression film 131b of the illustrated pixel 12b is also provided on a portion of the bottom surface of the connection hole 121. Note that the configuration may be such that the expansion hindrance suppression film 131b is not provided on the bottom surface of the connection hole 121.

[0184] This configuration can make it possible not to hinder the expansion of copper (Cu) in the connection hole 121 when copper (Cu) mainly in the connection hole 121 expands during heat treatment and joins to the other electrodes 105. Figure 8 The structure of the electrode 105 shown can be applied as such a structure.

[0185] exist Figure 8 In the illustrated configuration, the copper of electrode 105 within connection hole 121 contacts expansion-inhibiting film 131b. As in Embodiment 1, expansion-inhibiting film 131b is made of a material with low adhesive strength or a material with a low coefficient of friction. Therefore, expansion-inhibiting film 131b does not hinder the expansion of the copper of electrode 105 within connection hole 121 during heat treatment. Consequently, expansion of electrode 105 is not hindered, and bonding with an electrode provided on a substrate to be bonded can be achieved without any problems.

[0186] <Manufacturing according to Embodiment 2>

[0187] Will refer to Figure 9 Description Figure 8 The pixel 12a is manufactured by forming the electrode 105 shown in FIG. Figure 9 The manufacture of a portion of the electrode 105 will be described.

[0188] In step S21, a substrate having a laminated film 100 in which the barrier metal 104 and the expansion retardation suppression film 131b are formed is prepared. Figure 7 In the steps S11 , S12 , and S13 described above, the barrier metal 104 and the expansion hindrance suppression film 131 b are formed in the connection hole 121 and the wiring hole 122 .

[0189] In step S21 , for example, in a photolithography step, a photoresist is applied to create a resist pattern 201 that masks a region to be left as the expansion hindrance suppressing film 131 b (patterning).

[0190] In step S22 , an etching step is performed, and dry etching is performed using the resist pattern 201 as a mask, which removes the expansion hindering suppression film 131 b other than the side wall within the connection hole 121 and forms the expansion hindering suppression film 131 b on the side wall within the connection hole 121 .

[0191] As shown in the depiction of step S21, the resist 201 is applied to the side surfaces and a portion of the bottom surface of the connection hole 121, and a portion of the top surface of the laminated film 100. Therefore, as shown in the depiction of step S22, the expansion hindrance suppression film 131b is formed on the side surfaces and a portion of the bottom surface of the connection hole 121, and a portion of the top surface of the laminated film 100.

[0192] In step S23, the material of the electrode 105, such as copper (Cu), is buried in the connection hole 121 and the wiring hole 122. In step S24, the Cu is polished and flattened. Steps S23 and S24 are the same as steps S15 and S16 ( Figure 7 ) are basically the same.

[0193] Through the above steps, a Figure 8 The electrodes of the expansion hindrance suppression film 131b are shown.

[0194] <Implementation Plan 3>

[0195] Figure 10 This is a diagram showing a configuration example of a pixel 12 c according to Embodiment 3 to which the present technology is applied. Figure 10 The pixel 12c according to the embodiment 3 is shown Figure 4 The same parts among the illustrated pixels 12 a according to Embodiment 1 are given the same reference numerals, and description thereof is appropriately omitted.

[0196] although Figure 4 The pixel 12a according to the embodiment 1 shown has a dual mosaic structure, but Figure 10 The pixel 12c according to Embodiment 3 shown has a single mosaic structure.

[0197] like Figure 10 As shown, in the electrode formed in the joint portion, a connection hole 121c is provided in the insulating film 221, and a barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121c. An expansion retardation suppression film 131 is formed on the barrier metal 104 formed on the side surfaces of the connection hole 121c.

[0198] The expansion-hindering suppression film 131c is formed from a material that does not hinder the thermal expansion of the material constituting the electrode 105 during heat treatment. As in Embodiment 1, it is composed of a material having low adhesion strength or a material having a low coefficient of friction. Therefore, the expansion-hindering suppression film 131c does not hinder the expansion of the copper of the electrode 105 within the connection hole 121c during heat treatment. Therefore, the expansion of the electrode 105 is not hindered, and bonding with the electrode provided on the substrate to be bonded can be achieved without any problems.

[0199] <Manufacturing according to Embodiment 3>

[0200] Will refer to Figure 11 Description Figure 10 The pixel 12c is manufactured by the electrode 105 shown in FIG. Figure 11 The manufacture of a portion of the electrode 105 will be described.

[0201] In step S31, a semiconductor substrate is prepared with connection holes 121c formed in insulating film 221. Connection holes 121c are formed by etching the semiconductor substrate. For example, in a photolithography step, a photoresist is applied to create a resist pattern for forming connection holes 121c. Dry etching is performed using the created resist pattern as a mask to form connection holes 121c.

[0202] In step S32 , the barrier metal 104 is formed by, for example, sputtering. The barrier metal 104 is formed on the side surfaces and the bottom surface of the connection hole 121 c and also on the top surface of the insulating film 221 .

[0203] In step S33, an expansion-preventing film 131c is formed on the barrier metal 104. The expansion-preventing film 131c can also be formed by sputtering. If a material with low adhesion strength (such as an oxide film) is used as the expansion-preventing film 131c, an oxide film is formed in step S33. If a material with a low friction coefficient (such as carbon) is used as the expansion-preventing film 131c, a carbon film is formed in step S33.

[0204] In step S34, the excess expansion hindering suppressing film 131c is removed by an etch-back process. Since the expansion hindering suppressing film 131c is removed by the etch-back process, the expansion hindering suppressing film 131c on the interlayer insulating film 103 and the expansion hindering suppressing film 131c on the bottom surface of the connection hole 121c are removed. In other words, the expansion hindering suppressing film 131c in the area other than the expansion hindering suppressing film 131c formed on the side surface of the connection hole 121 is removed.

[0205] In step S35, the material of the electrode 105, for example, copper (Cu), is buried in the connection hole 121c. The electrode 105 made of copper (Cu) is buried in the connection hole 121c by Cu sputtering and then Cu plating.

[0206] In step S36 , the Cu is polished and planarized. This step removes excess Cu and the barrier metal 104 on the top surface of the insulating film 221 by chemical mechanical planarization (CMP).

[0207] Through the above steps, a Figure 10 The electrode of the expansion hindrance suppression film 131c is shown.

[0208] <Implementation Plan 4-1>

[0209] Figure 12 This is a diagram showing a configuration example of a pixel 12d according to Embodiment 4-1 to which the present technology is applied. Figure 12 The pixel 12d and the pixel 12d according to the embodiment 4-1 are shown Figure 4 The same parts among the illustrated pixels 12 a according to Embodiment 1 are given the same reference numerals, and description thereof is appropriately omitted.

[0210] When compared Figure 12 The pixel 12d and the pixel 12d according to the embodiment 4-1 are shown Figure 4 In the illustrated pixel 12a according to Embodiment 1, the region where the expansion hindering suppression film 131d of the pixel 12d is formed is different from the region where the expansion hindering suppression film 131 of the pixel 12a is formed. Other points are the same.

[0211] and Figure 4 The pixel 12a shown in accordance with Embodiment 1 is different. Figure 12 The expansion hindrance suppressing film 131 d of the illustrated pixel 12 d is provided on the bottom surface of the connection hole 121 and the bottom surface of the wiring hole 122 , but other points are the same. Figure 12 The expansion hindrance suppressing film 131 d of the illustrated pixel 12 d is provided on the side and bottom surfaces of the connection hole 121 and the side and bottom surfaces of the wiring hole 122 .

[0212] exist Figure 12 In the illustrated configuration, the expansion-blocking suppression film 131d is formed in the connection hole 121 and the wiring hole 122. The copper of the electrode 105 is in contact with the expansion-blocking suppression film 131d, but is not in contact with the barrier metal 104. As in the first embodiment, the expansion-blocking suppression film 131d is made of a material having low adhesion strength or a material having a low friction coefficient. However, when the expansion-blocking suppression film 131d is also formed on the bottom surface of the wiring hole 122, as in Figure 12 In the pixel 12d shown, a conductive material is used as the material of the expansion hindrance suppression film 131d.

[0213] Likewise, in Figure 12 In the illustrated configuration, the expansion-obstructing film 131d does not obstruct the expansion of copper of the electrode 105 during heat treatment. Therefore, the electrode 105 is not obstructed from expanding and can be joined to an electrode provided on a substrate to be bonded without any problems.

[0214] <Manufacturing according to Embodiment 4-1>

[0215] Will refer to Figure 13 Description Figure 12 The pixel 12d is manufactured by forming the electrode 105 shown in FIG. Figure 13The manufacture of a portion of the electrode 105 will be described.

[0216] In step S41, a substrate having a laminated film 100 in which the barrier metal 104 and the expansion retardation suppression film 131d are formed is prepared. Figure 7 In the steps S11 , S12 , and S13 described above, the barrier metal 104 and the expansion hindrance suppression film 131 d are formed in the connection hole 121 and the wiring hole 122 .

[0217] As shown in the depiction of step S41 , the expansion hindrance suppression film 131 d is formed on the side and bottom surfaces of the connection hole 121 , the side and bottom surfaces of the wiring hole 122 , and the top surface of the laminated film 100 .

[0218] In step S42, the material of the electrode 105, such as copper (Cu), is buried in the connection hole 121 and the wiring hole 122. In step S43, the Cu is polished and flattened. Steps S43 and S44 are the same as steps S15 and S16 ( Figure 7 ) is basically the same. By omitting Figure 7 The etch-back process performed in step S14 and polishing of Cu forms an electrode in which the expansion hindrance suppressing film 131d also exists on the bottom surface, as shown in FIG. Figure 12 shown.

[0219] Through the above steps, a Figure 12 The electrode of the expansion hindrance suppression film 131d is shown.

[0220] <Implementation Plan 4-2>

[0221] Figure 14 This is a diagram showing a configuration example of a pixel 12d according to Embodiment 4-2 to which the present technology is applied. Figure 14 The pixel 12d and the pixel 12d according to the embodiment 4-2 are shown Figure 12 The same parts among the illustrated pixels 12 d according to Embodiment 4-1 are given the same reference numerals, and description thereof is appropriately omitted.

[0222] Figure 14 The pixel 12d according to the embodiment 4-2 is shown with Figure 12 The pixel 12d according to the embodiment 4-1 shown is different in that a dummy electrode 108 is added to the pixel 12d. The other points are the same.

[0223] Figure 14 The pixel 12d shown includes an electrode 105 for conducting with other semiconductor substrates and a dummy electrode 108 that does not need to conduct with other semiconductor substrates. Figure 14 The electrode 105 shown arranged on the right side of the pixel 12d has the same Figure 12The electrodes 105 shown have the same structure, and their description will be omitted.

[0224] For example, when there are regions where electrodes 105 are located and regions where electrodes 105 are not located due to layout or other factors, dummy electrodes 108 are located in the regions where electrodes 105 are not located. Dummy electrodes 108 are located in regions where the bonding with other semiconductor substrates is weak, for example, to prevent a decrease in bonding strength between semiconductor substrates. Therefore, dummy electrodes 108 can be formed relatively larger than electrodes 105 that require conduction.

[0225] like Figure 14 As shown, dummy electrode 108, shown on the left side of the figure, is larger than electrode 105, shown on the right side of the figure. Making dummy electrode 108 larger also increases the amount of copper embedded in connection hole 123, thereby increasing the amount of expansion during heat treatment. In this case, the reduction in expansion associated with miniaturized electrode 105 is less likely to occur in dummy electrode 108, making it possible to omit expansion hindrance suppression film 131.

[0226] exist Figure 14 In the illustrated dummy electrode 108, only the barrier metal 107 is formed between the interlayer insulating film 103 and the dummy electrode 108, without forming the expansion hindrance suppression film 131. In this way, the electrodes including the dummy electrode 108 and the electrodes including the electrode 105 may have different configurations.

[0227] although Figure 14 While an example of combining Embodiment 4-2, in which dummy electrode 108 is provided, with Embodiment 4-1 is shown, Embodiment 4-2 can also be implemented in combination with Embodiments 1 to 3. In other words, the configuration of electrode 105 described in Embodiments 1 to 3 can be appropriately applied to the configuration of electrode 105. Embodiment 4-2 can also be combined with the embodiments described below.

[0228] <Manufacturing according to Embodiment 4-2>

[0229] Will refer to Figure 15 Description Figure 4 The pixel 12d is manufactured by forming the electrode 105 shown in FIG. Figure 15 The manufacture of part of the electrode 105 and the dummy electrode 108 will be described.

[0230] In step S51, a substrate is prepared in which a stacked film 100 is formed, in which an interlayer insulating film 101, a liner insulating film 102, and an interlayer insulating film 103 are stacked. The connection hole 121, the wiring hole 122, and the connection hole 123 are formed by etching the stacked film 100. For example, in a photolithography step, a photoresist is applied to generate a resist pattern for forming the connection hole 121, the wiring hole 122, and the connection hole 123, and dry etching is performed using the resist pattern as a mask to form the connection hole 121, the wiring hole 122, and the connection hole 123.

[0231] In step S52, the barrier metal 104 is formed by sputtering, for example. The barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121, the side and bottom surfaces of the wiring hole 122, and the side and bottom surfaces of the connection hole 123, and also on the top surface of the stacked film 100.

[0232] In step S53, an expansion-preventing film 131d is formed on the barrier metal 104. The expansion-preventing film 131d can also be formed by sputtering. If a material with low adhesion strength (such as an oxide film) is used as the expansion-preventing film 131, an oxide film is formed in step S53. If a material with a low friction coefficient (such as carbon) is used as the expansion-preventing film 131, a carbon film is formed in step S53.

[0233] In step S53, an expansion hindrance suppressing film 131d is formed on the side and bottom surfaces of the connection hole 121, the side and bottom surfaces of the wiring hole 122, the side and bottom surfaces of the connection hole 123, and the top surface of the laminate film 100. The expansion hindrance suppressing film 131d formed on the side and bottom surfaces of the connection hole 123 will be represented as an expansion hindrance suppressing film 131d'.

[0234] In step S54, the portion serving as the electrode 105, in this case, the connection hole 121 and the wiring hole 122, is filled (coated) with the resist 241. An etching step is performed, and dry etching is performed using the resist pattern generated in the photolithography step as a mask. This removes the expansion retardation suppression film 131d' formed in the connection hole 123 serving as the dummy electrode 108.

[0235] In step S55 , an ashing and washing process is performed to remove the resist 241 , and wet washing is performed.

[0236] In step S56, the material of the electrode 105, such as copper (Cu), is embedded in the connection hole 121 and the wiring hole 122. The material of the dummy electrode 108, such as copper (Cu), is also embedded in the connection hole 123. The copper (Cu) is embedded in the connection hole 121, the wiring hole 122, and the connection hole 123 by Cu sputtering and then copper plating.

[0237] In step S57, Cu is polished and planarized. In this step, excess Cu and the barrier metal 104 on the top surface of the stacked film 100 are removed by CMP.

[0238] Through the above steps, a Figure 14 The electrode 105 shown includes an expansion hindrance suppression film 131 and a pixel 12 d having a dummy electrode 108 that does not include the expansion hindrance suppression film 131 .

[0239] <Implementation Plan 5>

[0240] Figure 16 This is a diagram showing a configuration example of a pixel 12e according to Embodiment 5 to which the present technology is applied. Figure 16 The pixel 12e according to Embodiment 5 is shown as well as Figure 10 The pixel 12c according to the embodiment 3 is shown Figure 12 The same parts among the pixels 12 d according to Embodiment 4 are given the same reference numerals, and description thereof is appropriately omitted.

[0241] When compared Figure 16 The pixel 12e according to Embodiment 5 is shown Figure 10 In the pixel 12c according to the third embodiment shown, the single damascene structure is the same, but the expansion hindrance suppressing film 131e is also formed on the bottom surface of the connection hole 121e.

[0242] When compared Figure 16 The pixel 12e according to Embodiment 5 is shown Figure 12 In the case of the pixel 12d according to the fourth embodiment shown, Figure 12 The pixel 12d according to the fourth embodiment shown has a dual mosaic structure, and Figure 16 The pixel 12e according to Embodiment 5 shown has a single mosaic structure.

[0243] like Figure 16 As shown, in the electrode formed at the joint where the substrates are bonded together, a connection hole 121e is provided in the insulating film 221, and the barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121e. An expansion retardation suppression film 131e is formed on the barrier metal 104 formed on the side and bottom surfaces of the connection hole 121e.

[0244] The expansion hindrance suppression film 131e is a film formed of a material that does not hinder the thermal expansion of the material constituting the electrode 105 during the heat treatment, and is composed of a material having low adhesive strength or a material having a low friction coefficient as in Embodiment 1. However, when the expansion hindrance suppression film 131e is also formed on the bottom surface of the connection hole 121e, as in Figure 16In the pixel 12e shown, a conductive material is used as the material of the expansion hindrance suppression film 131e.

[0245] Likewise, in Figure 16 In the illustrated configuration, the expansion-inhibiting film 131e does not inhibit the expansion of copper of the electrode 105 within the connection hole 121e during heat treatment. Therefore, the electrode 105 is not inhibited from expanding and can be joined to an electrode provided on a substrate to be bonded without any problems.

[0246] <Manufacturing according to Embodiment 5>

[0247] Will refer to Figure 17 Description Figure 16 The pixel 12e is manufactured by forming the electrode 105 shown in FIG. Figure 17 The manufacture of a portion of the electrode 105 will be described.

[0248] In step S61, a semiconductor substrate is prepared in which a connection hole 121e is formed in the insulating film 221 and a barrier metal 104 and an expansion hindrance suppression film 131e are formed in the connection hole 121e. Figure 11 In steps S31, S32, and S33 described above, the barrier metal 104 and the expansion hindrance suppression film 131e are formed in the connection hole 121e.

[0249] As shown in the depiction of step S51 , the expansion hindrance suppression film 131 e is formed on the side and bottom surfaces of the connection hole 121 e and the top surface of the insulating film 221 .

[0250] In step S52, the material of the electrode 105, such as copper (Cu), is buried in the connection hole 121e. In step S53, the Cu is polished and flattened. Steps S53 and S54 are the same as steps S35 and S36 ( Figure 11 ) is basically the same. By omitting Figure 11 The etch-back process performed in step S34 and polishing of Cu forms the electrode 105 in which the expansion hindrance suppression film 131e also exists on the bottom surface of the connection hole 121e, as shown in FIG. Figure 16 shown.

[0251] Through the above steps, a Figure 16 The electrode of the expansion hindrance suppression film 131e is shown.

[0252] <Implementation Plan 6>

[0253] Figure 18 This is a diagram showing a configuration example of a pixel 12f according to Embodiment 6 to which the present technology is applied. Figure 16 The pixel 12f according to Embodiment 6 shown in FIG. Figure 4The same parts among the illustrated pixels 12 a according to Embodiment 1 are given the same reference numerals, and description thereof is appropriately omitted.

[0254] When compared Figure 18 The pixel 12f according to Embodiment 6 shown in FIG. Figure 4 While the pixel 12a according to the embodiment 1 is shown, the pixel 12f is different in that the electrode 105 is composed of an electrode 105f-1 and an electrode 105f-2 formed of different materials.

[0255] Figure 18 The electrode 105 of the pixel 12f shown is composed of an electrode 105f-1 and an electrode 105f-2. The electrode 105f-1 is formed of a first material, and the electrode 105f-2 is formed of a second material different from the first material. Figure 18 In the illustrated example, the electrode 105 f - 1 is an electrode formed in the connection hole 121 , and the electrode 105 f - 2 is an electrode formed in the wiring hole 122 .

[0256] The first material filling the connection hole 121 and forming the electrode 105f-1 is a material that easily expands thermally. A material having a large linear expansion coefficient can be used for the first material. The second material filling the wiring hole 122 and forming the electrode 105f-2 is a conductive material.

[0257] Zinc (Zn), aluminum (Al), tin (Sn), duralumin, bronze, or a combination thereof can be used as the first material. Copper (Cu) can be used as the second material. The linear expansion coefficient of copper (Cu) is 16.5. The linear expansion coefficient of zinc (Zn) is 30.2, aluminum (Al) is 23.1, tin (Sn) is 22.0, duralumin is 21.6, and bronze is 17.3. All of these values ​​are greater than the linear expansion coefficient of copper and can be used as the first material.

[0258] The barrier metal 104 and the expansion retardation suppression film 131f are formed on the side walls of the connection hole 121. The barrier metal 104 is formed on the bottom surface of the connection hole 121. The barrier metal 104 is formed on the side walls and bottom surface of the wiring hole 122.

[0259] Electrode 105f-1 formed in connection hole 121 is formed of the first material that is easily expanded, and expansion retardation suppression film 131f is formed to prevent its expansion from being hindered. Therefore, the amount of expansion of electrode 105f-1 formed in connection hole 121 can be increased, and electrode 105f-1 can be fully expanded.

[0260] When a necessary amount of expansion can be ensured by using the easily expandable first material as the electrode 105 f - 1 in the connection hole 121 , the expansion hindrance suppression film 131 f may be omitted.

[0261] exist Figure 18 In the illustrated configuration, the expansion retardation suppression film 131f is formed in the connection hole 121, and a first material having a large linear expansion coefficient is used for the electrode 105f-1 in the connection hole 121. The electrode 105f-1 is in contact with the expansion retardation suppression film 131f but is not in contact with the barrier metal 104. As in the first embodiment, the expansion retardation suppression film 131f is formed of a material having low adhesive strength or a material having a low friction coefficient.

[0262] Likewise, in Figure 18 In the illustrated configuration, the expansion-obstruction-suppressing film 131f does not obstruct the expansion of the electrode 105 during heat treatment. Therefore, the electrode 105 is not obstructed from expanding and can be joined to an electrode provided on a substrate to be bonded without any problems.

[0263] <Manufacturing according to Embodiment 6>

[0264] Will refer to Figure 19 and Figure 20 Description Figure 18 The pixel 12f is manufactured by the electrode 105 shown in FIG. Figure 19 and Figure 20 The manufacture of a portion of the electrode 105 will be described.

[0265] In step S71, a semiconductor substrate having an interlayer insulating film 101 formed therein is prepared. The wiring holes 122 are formed by etching the interlayer insulating film 101. For example, in a photolithography step, a photoresist is applied to generate a resist pattern in which the region where the wiring holes 122 are to be formed is open, and dry etching is performed using the resist pattern as a mask to form the wiring holes 122.

[0266] In step S72 , the barrier metal 104 is formed by, for example, sputtering. The barrier metal 104 is formed on the side surfaces and bottom surfaces of the wiring hole 122 and also on the top surface of the interlayer insulating film 101 .

[0267] In step S73, a second material, such as copper (Cu), is embedded in the wiring hole 122. The electrode 105f-2 composed of copper (Cu) is embedded in the wiring hole 122 by Cu sputtering and then Cu plating. The barrier metal 104 formed on the interlayer insulating film 101 is removed, and the liner insulating film 102 is formed.

[0268] In step S74 , the interlayer insulating film 103 is formed on the liner insulating film 102 formed on the interlayer insulating film 101 .

[0269] In step S75, the connection hole 121 is formed by etching the interlayer insulating film 103. For example, in a photolithography step, a photoresist is applied to generate a resist pattern in which the region where the connection hole 121 is to be formed is opened, and dry etching is performed using the resist pattern as a mask to form the connection hole 121.

[0270] In step S76 ( Figure 20 ), for example, by sputtering to form the barrier metal 104. The barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121 and also formed on the top surface of the interlayer insulating film 103.

[0271] In step S77, an expansion-preventing film 131f is formed on the barrier metal 104. The expansion-preventing film 131f can also be formed by sputtering. If a material with low adhesion strength (such as an oxide film) is used as the expansion-preventing film 131f, an oxide film is formed in step S77. If a material with a low friction coefficient (such as carbon) is used as the expansion-preventing film 131f, a carbon film is formed in step S77.

[0272] In step S78, the excess expansion hindering suppressing film 131f is removed by an etch-back process. Since the expansion hindering suppressing film 131f is removed by the etch-back process, the expansion hindering suppressing film 131f on the interlayer insulating film 103 and the expansion hindering suppressing film 131f on the bottom surface of the connection hole 121 are removed. In other words, the expansion hindering suppressing film 131f in the area other than the expansion hindering suppressing film 131f formed on the side surface of the connection hole 121 is removed.

[0273] In step S79, the material of the electrode 105f-1, for example, an alloy of copper (Cu) and tin (Sn), is buried in the connection hole 121. The electrode 105f-1 composed of the alloy (Cu-Sn) is buried in the connection hole 121 by alloy sputtering and then alloy plating.

[0274] In step S80, the alloy is polished and planarized. In this step, excess portions of the alloy and the barrier metal 104 on the top surface of the interlayer insulating film 103 are removed by CMP.

[0275] Through the above steps, we can form Figure 18 The electrodes shown are composed of different materials and include an expansion hindrance suppressing film 131f.

[0276] <Implementation Plan 7>

[0277] Figure 21 This is a diagram showing a configuration example of a pixel 12g according to Embodiment 7 to which the present technology is applied. Figure 21 The pixel 12g according to Embodiment 7 shown in FIG. Figure 18The same parts among the pixels 12f according to Embodiment 6 are given the same reference numerals, and description thereof is appropriately omitted.

[0278] When compared Figure 21 The pixel 12g according to Embodiment 7 shown in FIG. Figure 18 In the pixel 12f according to Embodiment 6 shown, the region where the expansion hindering suppression film 131g is formed in the pixel 12g is different from the region where the expansion hindering suppression film 131f is formed in the pixel 12f. Other points are the same.

[0279] and Figure 18 The pixel 12f according to the embodiment 6 shown is different. Figure 21 The expansion hindrance suppressing film 131 g of the illustrated pixel 12 g is also provided on the bottom surface of the connection hole 121 , but other points are the same. Figure 21 The expansion hindrance suppressing film 131 g of the illustrated pixel 12 g is provided on the side and bottom surfaces of the connection hole 121 .

[0280] exist Figure 21 In the illustrated configuration, an expansion-blocking suppression film 131g is formed within the connection hole 121, and a first material having a large linear expansion coefficient is used for the electrode 105g-1 within the connection hole 121. The electrode 105g-1 is in contact with the expansion-blocking suppression film 131g but is not in contact with the barrier metal 104. As in the first embodiment, the expansion-blocking suppression film 131g is formed of a material having low adhesive strength or a material having a low friction coefficient.

[0281] Likewise, in Figure 21 In the illustrated configuration, the expansion-obstructing film 131g does not obstruct the expansion of the electrode 105 during heat treatment. Therefore, the electrode 105 is not obstructed from expanding and can be joined to an electrode provided on a substrate to be bonded without any problems.

[0282] <Manufacturing according to Embodiment 7>

[0283] Will refer to Figure 22 Description Figure 21 The pixel 12g is manufactured by the electrode 105g shown in FIG. Figure 22 The production of a portion of the electrode 105g will be described.

[0284] In step S91, a substrate having a laminated film 100 in which a barrier metal 104 and an expansion retardation suppression film 131g are formed is prepared. Figure 19 and Figure 20In steps S71 to S77 described above, the connection hole 121 and the wiring hole 122 are formed in the stacked film 100, the barrier metal 104 is formed on the side surfaces thereof, and the electrode 105-2 is formed in the wiring hole 122. In addition, the expansion retardation suppression film 131g is formed on the side surfaces and bottom surface of the connection hole 121 and on the surface of the interlayer insulating film 101.

[0285] In step S92, the material of the electrode 105g-1, for example, an alloy of copper (Cu) and tin (Sn), is buried in the connection hole 121. The electrode 105g-1 composed of the alloy (Cu—Sn) is buried in the connection hole 121 by alloy sputtering and then alloy plating.

[0286] In step S93, the alloy is polished and planarized. In this step, excess portions of the alloy and the barrier metal 104 on the top surface of the interlayer insulating film 103 are removed by CMP.

[0287] When manufacturing Figure 21 The pixel 12g is shown, the Figure 20 The etching back process performed in step S78 is performed, and Cu is polished. By such a process, an electrode is formed in which the expansion hindrance suppression film 131g is also present on the bottom surface of the connection hole 121, as shown in FIG. Figure 21 shown.

[0288] Through the above steps, we can form Figure 21 The electrode 105 shown is composed of a different material and includes an expansion hindrance suppressing film 131g.

[0289] <Implementation Plan 8>

[0290] Figure 23 is a diagram showing a cross-sectional configuration example of a pixel 12h according to an eighth embodiment to which the present technology is applied. Figure 24 1 is a diagram showing an example of a planar structure of the pixel 12h. Figure 23 The pixel 12h and the pixel 12h according to the embodiment 8 are shown Figure 4 The same parts among the illustrated pixels 12 a according to Embodiment 1 are given the same reference numerals, and description thereof is appropriately omitted.

[0291] When compared Figure 23 The pixel 12h and the pixel 12h according to the embodiment 8 are shown Figure 4 While the pixel 12a according to the embodiment 1 is shown, the pixel 12h is different in that the pixel 12h has a configuration in which a via hole 261 is added to the pixel 12a. Other points are the same.

[0292] The via hole 261 is formed in Figure 23The via hole 261 is formed in the bottom surface of the connection hole 121 of the pixel 12h shown in FIG.

[0293] Reference Figure 24 In the example of the planar configuration shown, the connection hole 121 is formed in a square shape, and the wiring hole 122 is formed in a circular shape in the center of the connection hole 121. The via hole 261 is formed in the area inside the connection hole 121 and outside the wiring hole 122. The via hole 261 is formed in a small circular shape, and a plurality of via holes 261 are provided. Because the via hole 261 is circular in the plan view and square in the cross-sectional view ( Figure 23 ), so one via 261 is formed in a cylindrical shape. Although the via 261 will continue to be described as having a cylindrical shape as an example, other shapes, such as a prism, may also be used.

[0294] Reference Figure 23 In the cross-sectional configuration example shown, the barrier metal 104 is formed on the side and bottom surfaces of the via hole 261. In addition, the expansion retardation suppression film 131h is formed on the side surfaces of the via hole 261.

[0295] In the pixel 12 h , providing a plurality of via holes 261 increases the amount of copper (Cu) constituting the electrode 105 , for example, and thus can increase the amount of expansion.

[0296] Likewise, in Figure 23 In the illustrated configuration, electrode 105 is configured to contact expansion-inhibiting film 131h. As in Embodiment 1, expansion-inhibiting film 131h is made of a material with low adhesive strength or a material with a low coefficient of friction. Therefore, expansion-inhibiting film 131h does not hinder the expansion of the copper of electrode 105 within connection hole 121 during heat treatment. Consequently, electrode 105's expansion is not hindered, and it can be joined to an electrode provided on a substrate to be bonded without any problems.

[0297] <Manufacturing according to Embodiment 8>

[0298] Will refer to Figure 25 Description Figure 24 The pixel 12h is manufactured by the electrode 105 shown in FIG. Figure 25 The manufacture of a portion of the electrode 105 will be described.

[0299] In step S101, a substrate is prepared in which a stacked film 100 is formed, in which interlayer insulating film 101, liner insulating film 102, and interlayer insulating film 103 are stacked. Resist is applied to stacked film 100 to generate a resist pattern 281 in which a portion where via 261 is to be formed is opened.

[0300] although Figure 25The resist pattern 281 shown in the figure is shown as a pattern in which openings are arranged at equal intervals, but only openings need to be provided at both ends of the resist pattern 281 to form the vias 261, so a resist pattern 281 without an opening in the central portion of the resist pattern 281 can be generated.

[0301] In step S102 , dry etching is performed using the generated resist pattern 281 as a mask, and a groove 291 is formed in the interlayer insulating film 103 .

[0302] In step S103 , a resist pattern 282 is generated in which a region to be used as the connection hole 121 is opened.

[0303] In step S104, dry etching is performed using the generated resist pattern 282 as a mask, and the connection hole 121 is formed in the interlayer insulating film 103. In the bottom surface of the hole serving as the connection hole 121, a concave groove 292 is formed in the portion where the groove 291 is located.

[0304] In step S105, a resist is applied to cover the grooves 292 located at the positions where the via holes 261 are to remain. A resist 283 is also applied to the side surfaces of the connection holes 121 and the top surface of the laminate film 100. In step S105, a resist pattern 283 is generated in which the areas where the wiring holes 122 are to be formed are open.

[0305] In step S106 ( Figure 26 ), dry etching is performed using the generated resist pattern 283 as a mask to form a wiring hole 122 in the interlayer insulating film 101 of the stacked film 100.

[0306] In step S107, the barrier metal 104 is formed, for example, by sputtering. The barrier metal 104 is formed on the side surfaces and bottom surfaces of the connection hole 121 and the wiring hole 122, and also on the top surface of the interlayer insulating film 103. After the barrier metal 104 is formed, the expansion-preventing film 131h is formed on the barrier metal 104. The expansion-preventing film 131 can also be formed by sputtering. In step S107, the barrier metal 104 and the expansion-preventing film 131h are formed on the side surfaces and bottom surfaces of the via hole 261.

[0307] If a material with low adhesion strength (such as an oxide film) is used as the expansion hindrance suppression film 131h, an oxide film is formed in step S107. If a material with low friction coefficient (such as carbon) is used as the expansion hindrance suppression film 131h, a carbon film is formed in step S107.

[0308] In step S108, the expansion-blocking suppressing film 131h is removed by an etch-back process. Since the expansion-blocking suppressing film 131h is removed by the etch-back process, the expansion-blocking suppressing film 131h on the interlayer insulating film 103, the expansion-blocking suppressing film 131h on the bottom surface of the connection hole 121, the expansion-blocking suppressing film 131h on the bottom surface of the wiring hole 122, and the expansion-blocking suppressing film 131h on the bottom surface of the via 261 are also removed. In other words, the expansion-blocking suppressing film 131h is removed in areas other than the expansion-blocking suppressing film 131h formed on the side surfaces of the connection hole 121, the side surfaces of the wiring hole 122, and the side surfaces of the via 261.

[0309] In step S109, the material of the electrode 105, such as copper (Cu), is buried in the connection hole 121, the wiring hole 122, and the via 261. The electrode 105 composed of copper (Cu) is buried in the connection hole 121, the wiring hole 122, and the via 261 by Cu sputtering and then Cu plating.

[0310] In step S110 , the Cu is polished and planarized. In this step, excess Cu and the barrier metal 104 on the top surface of the interlayer insulating film 103 are removed by CMP.

[0311] Through the above steps, a Figure 24 The via hole 261 and the electrode of the expansion hindrance suppressing film 131h are shown.

[0312] <Implementation Plan 9>

[0313] Figure 27 This is a diagram showing a configuration example of a pixel 12i according to Embodiment 9 to which the present technology is applied. Figure 27 The pixel 12i according to embodiment 9 and Figure 24 The same parts among the illustrated pixels 12h according to Embodiment 8 are given the same reference numerals, and description thereof is appropriately omitted.

[0314] When compared Figure 27 The pixel 12i according to embodiment 9 and Figure 24 In the illustrated pixel 12h according to Embodiment 8, the region where the expansion hindering suppressing film 131i is formed in the pixel 12i is different from the region where the expansion hindering suppressing film 131h is formed in the pixel 12h. Other points are the same.

[0315] and Figure 24 The pixel 12h shown in accordance with Embodiment 8 is different. Figure 27 The expansion hindrance suppressing film 131 i of the illustrated pixel 12 i is provided on the bottom surface of the connection hole 121 , the bottom surface of the wiring hole 122 , and the bottom surface of the via hole 261 , but other points are the same. Figure 27The expansion hindrance suppressing film 131 i of the illustrated pixel 12 i is provided on the side and bottom surfaces of the connection hole 121 , the side and bottom surfaces of the wiring hole 122 , and the side and bottom surfaces of the via hole 261 .

[0316] exist Figure 27 In the illustrated configuration, the expansion-blocking suppression film 131i is formed in the connection hole 121, the wiring hole 122, and the via 261. The copper of the electrode 105 is in contact with the expansion-blocking suppression film 131i, but is not in contact with the barrier metal 104. As in the first embodiment and the like, the expansion-blocking suppression film 131i is made of a material having low adhesion strength or a material having a low friction coefficient. However, when the expansion-blocking suppression film 131i is also formed on the bottom surface of the wiring hole 122, as in Figure 27 In the pixel 12i shown, a conductive material is used as the material of the expansion hindrance suppression film 131i.

[0317] Likewise, in Figure 27 In the illustrated configuration, the expansion-obstruction-suppressing film 131i does not obstruct the expansion of copper of the electrode 105 during heat treatment. Therefore, the electrode 105 is not obstructed from expanding and can be joined to an electrode provided on a substrate to be bonded without any problems.

[0318] <Manufacturing according to Embodiment 9>

[0319] Will refer to Figure 28 Description Figure 27 The pixel 12i is manufactured by forming the electrode 105 shown in FIG. Figure 28 The manufacture of a portion of the electrode 105 will be described.

[0320] In step S121, a substrate having a laminated film 100 formed therein is prepared. In the steps before step S121, by performing reference Figure 25 and Figure 26 In the steps S101 to S107 described above, the barrier metal 104 and the expansion hindrance suppression film 131 i are formed in the connection hole 121 , the wiring hole 122 , and the via hole 261 .

[0321] In step S122, the material of the electrode 105, such as copper (Cu), is buried in the connection hole 121, the wiring hole 122 and the via 261. In step S123, the Cu is polished and flattened. Steps S122 and S123 are the same as steps S109 and S110 ( Figure 26 ) is basically the same. By omitting Figure 26 The etch-back process performed in step S108 and polishing of Cu forms an electrode in which the expansion hindrance suppression film 131i also exists on the bottom surfaces of the connection hole 121, the wiring hole 122 and the via hole 261, as shown in FIG. Figure 27 shown.

[0322] Through the above steps, a Figure 27 The via hole 261 and the electrode of the expansion hindrance suppression film 131i are shown.

[0323] <Implementation Plan 10>

[0324] Figure 29 is a diagram showing an example of a cross-sectional structure of a pixel 12j of embodiment 10 to which the present technology is applied, Figure 30 It is a diagram showing the planar structure of the pixel 12j. Figure 29 The pixel 12j according to the embodiment 10 is shown Figure 4 The same parts among the illustrated pixels 12 a according to Embodiment 1 are given the same reference numerals, and description thereof is appropriately omitted.

[0325] When compared Figure 29 The pixel 12j according to the embodiment 10 is shown Figure 4 While the pixel 12a according to the embodiment 1 is shown, the pixel 12j is different in that the pixel 12j has a configuration in which a groove 301 is added to the pixel 12a. Other points are the same.

[0326] Grooves 301 are formed in Figure 29 The trench 301 is formed in the bottom surface of the connection hole 121 of the pixel 12j shown in FIG.

[0327] Reference Figure 30 In the example of the planar configuration shown, the connection hole 121 is formed in a square shape, and the wiring hole 122 is formed in a circular shape in the center of the connection hole 121. The groove 301 is formed in a square shape in the area inside the connection hole 121 and outside the wiring hole 122 to surround the wiring hole 122. The groove 301 can be formed larger than the via hole 261 ( Figure 23 ) is deeper and has a rectangular shape with a predetermined width, such as Figure 30 shown.

[0328] Reference Figure 29 In the cross-sectional configuration example shown, the barrier metal 104 is formed on the side surfaces and bottom surface of the trench 301. In addition, the expansion retardation suppression film 131j is also formed on the side surfaces of the trench 301.

[0329] In the pixel 12j, provision of the groove 301 increases the amount of copper (Cu) constituting the electrode 105, for example, and thus the amount of expansion can be increased.

[0330] exist Figure 29In the illustrated configuration, electrode 105 is also configured to contact expansion-inhibiting film 131j. As in Embodiment 1 and other embodiments, expansion-inhibiting film 131j is formed from a material with low adhesive strength or a material with a low coefficient of friction. Therefore, expansion-inhibiting film 131j does not hinder the expansion of the copper of electrode 105 within connection hole 121 during heat treatment. Consequently, electrode 105's expansion is not hindered, and it can be bonded to the electrode provided on the substrate to be bonded without any problems.

[0331] <Manufacturing according to Embodiment 10>

[0332] Will refer to Figure 31 and Figure 32 Description Figure 30 The pixel 12j is manufactured by forming the electrode 105 shown in FIG. Figure 31 and Figure 32 The manufacture of a portion of the electrode 105 will be described.

[0333] In step S131, a substrate is prepared in which a stacked film 100 is formed in which interlayer insulating film 101, liner insulating film 102, and interlayer insulating film 103 are stacked. Resist is applied to stacked film 100 to produce a resist pattern 321 in which a portion where trench 301 is to be formed is opened.

[0334] In step S132 , dry etching is performed using the generated resist pattern 321 as a mask, and a groove 331 is formed in the stacked film 100 .

[0335] In step S133 , a resist pattern 322 is generated in which a region to be used as the connection hole 121 is opened.

[0336] In step S134, dry etching is performed using the generated resist pattern 322 as a mask, and the connection hole 121 is formed in the laminated film 100. In the bottom surface of the hole serving as the connection hole 121, a concave groove 332 is formed in the portion where the groove 331 is located.

[0337] In step S135 , a resist pattern 323 is generated in which a region where the wiring hole 122 is to be formed is opened.

[0338] In step S136 ( Figure 32 ), dry etching is performed using the generated resist pattern 322 as a mask to form a wiring hole 122 in the interlayer insulating film 101 of the stacked film 100.

[0339] In step S137, the barrier metal 104 is formed, for example, by sputtering. The barrier metal 104 is formed on the side surfaces and bottom surfaces of the connection hole 121 and the wiring hole 122, and also on the top surface of the interlayer insulating film 103. An expansion-preventing film 131j is also formed on the already formed barrier metal 104. The expansion-preventing film 131 can also be formed by sputtering. In step S137, the barrier metal 104 and the expansion-preventing film 131j are formed on the side surfaces and bottom surfaces of the trench 301.

[0340] If a material with low adhesion strength (such as an oxide film) is used as the expansion hindrance suppression film 131j, an oxide film is formed in step S137. If a material with low friction coefficient (such as carbon) is used as the expansion hindrance suppression film 131j, a carbon film is formed in step S137.

[0341] In step S138, the excess expansion-preventing film 131j is removed by an etch-back process. Since the expansion-preventing film 131j is removed by the etch-back process, the expansion-preventing film 131j on the surface of the interlayer insulating film 103, the expansion-preventing film 131j on the bottom surface of the connection hole 121, the expansion-preventing film 131j on the bottom surface of the wiring hole 122, and the expansion-preventing film 131j on the bottom surface of the trench 301 are removed. In other words, the expansion-preventing film 131j is removed from areas other than the expansion-preventing film 131j formed on the side surfaces of the connection hole 121, the side surfaces of the wiring hole 122, and the side surfaces of the trench 301.

[0342] In step S139, the material of the electrode 105, such as copper (Cu), is buried in the connection hole 121, the wiring hole 122, and the groove 301. The electrode 105 composed of copper (Cu) is buried in the connection hole 121, the wiring hole 122, and the groove 301 by Cu sputtering and then Cu plating.

[0343] In step S140, Cu is polished and planarized. In this step, excess Cu and the barrier metal 104 on the top surface of the interlayer insulating film 103 are removed by CMP.

[0344] Through the above steps, a Figure 30 The groove 301 and the electrode of the expansion hindrance suppression film 131j are shown.

[0345] <Implementation Plan 11>

[0346] Figure 33 This is a diagram showing a configuration example of a pixel 12k according to Embodiment 11 to which the present technology is applied. Figure 33 The pixel 12k and the pixel 12k according to the embodiment 11 are shown Figure 30The same parts among the pixels 12j according to the embodiment 10 are given the same reference numerals, and the description thereof is appropriately omitted.

[0347] When compared Figure 33 The pixel 12k and the pixel 12k according to the embodiment 11 are shown Figure 30 In the illustrated pixel 12j according to Embodiment 10, the region where the expansion hindering suppressing film 131k of the pixel 12k is formed is different from the region where the expansion hindering suppressing film 131j of the pixel 12j is formed. Other points are the same.

[0348] and Figure 30 The pixel 12j shown according to the embodiment 10 is different. Figure 33 The expansion hindrance suppressing film 131 k of the illustrated pixel 12 k is provided on the bottom surface of the connection hole 121 , the bottom surface of the wiring hole 122 , and the bottom surface of the groove 301 , but other points are the same. Figure 33 The expansion hindrance suppressing film 131 k of the illustrated pixel 12 k is provided on the side and bottom surfaces of the connection hole 121 , the side and bottom surfaces of the wiring hole 122 , and the side and bottom surfaces of the groove 301 .

[0349] exist Figure 33 In the illustrated configuration, the expansion-blocking suppression film 131k is formed in the connection hole 121, the wiring hole 122, and the groove 301. The copper of the electrode 105 is in contact with the expansion-blocking suppression film 131k, but is not in contact with the barrier metal 104. As in the first embodiment and the like, the expansion-blocking suppression film 131k is made of a material having low adhesion strength or a material having a low friction coefficient. However, when the expansion-blocking suppression film 131k is also formed on the bottom surface of the wiring hole 122, as in Figure 33 In the pixel 12k shown, a conductive material is used as the material of the expansion hindrance suppression film 131k.

[0350] Likewise, in Figure 33 In the illustrated configuration, the expansion-obstructing film 131k does not obstruct the expansion of copper of the electrode 105 during heat treatment. Therefore, the electrode 105 is not obstructed from expanding and can be joined to an electrode provided on a substrate to be bonded without any problems.

[0351] <Manufacturing according to Embodiment 11>

[0352] Will refer to Figure 34 Description Figure 33 The pixel 12j is manufactured by forming the electrode 105 shown in FIG. Figure 34 The manufacture of a portion of the electrode 105 will be described.

[0353] In step S151, a semiconductor substrate having a stacked film 100 formed therein, a barrier metal 104 and an expansion hindrance suppressing film 131j formed therein are prepared. Figure 31 and Figure 32 In steps S131 to S136 described above, the barrier metal 104 and the expansion hindrance suppression film 131 k are formed in the connection hole 121 , the wiring hole 122 , and the trench 301 .

[0354] In step S152, the material of the electrode 105, such as copper (Cu), is buried in the connection hole 121, the wiring hole 122 and the groove 301. In step S153, the Cu is polished and flattened. Steps S152 and S153 are the same as steps S139 and S140 ( Figure 32 ) is basically the same. By omitting Figure 32 The etch-back process performed in step S138 and polishing of Cu forms an electrode in which the expansion hindrance suppressing film 131k also exists on the bottom surface of the connection hole 121, the wiring hole 122 and the groove 301, as shown in FIG. Figure 33 shown.

[0355] Through the above steps, a Figure 33 The groove 301 and the electrode of the expansion hindrance suppressing film 131k are shown.

[0356] <Implementation Plan 12>

[0357] Will refer to Figure 35 This illustrates the trend that the amount of recess increases as the electrode 105 becomes smaller.

[0358] Figure 35 A represents an electrode 105' formed in a relatively large size (a portion to which the present technology is not applicable will be indicated by a dotted line or a double-dotted line), Figure 35 B represents a miniaturized electrode 105".

[0359] Reference Figure 35 In A, the center portion of the electrode 105 ′ is formed to position a, and both ends are formed to positions b that are deeper than position a. The region from position a to position b where the electrode 105 ′ is not formed is considered a recessed region 341 .

[0360] Reference Figure 35 In B, the central portion of the electrode 105 ″ is formed to a position c that is deeper than the position a. The region from the position a to the position c where the electrode 105 ″ is not formed is regarded as a recessed region 342 .

[0361] like Figure 35 As shown in FIG. 1A , when the size of the electrode 105 ′ is relatively large, the depression has an effect only on the end portion of the opening side of the electrode 105 ′. However, as shown in FIG. Figure 35As shown in FIG. 3B , for a miniaturized electrode 105 ″, the effect of the recess may extend to the entire open side of the electrode 105 ″. As the recessed area 342 of the electrode 105 ″ increases, that is, as the distance from position a to position c increases, when the semiconductor substrate is bonded to another semiconductor substrate and the electrodes 105 ″ are connected to each other, the electrode 105 ″ will not expand sufficiently, the electrodes 105 ″ will not contact each other, and a contact defect may occur.

[0362] One factor that causes the occurrence of the recessed regions 341 and 342 is the corrosion of the electrode 105' (hereinafter, when there is no need to distinguish between the electrode 105' and the electrode 105", the electrode 105' will be taken as an example). The corrosion of the electrode 105' will be referred to as Figure 36 Provide explanation.

[0363] The description will continue using an example in which the barrier metal 104' is formed of tantalum nitride (TaN) and the electrode 105' is formed of copper (Cu). Figure 35 As shown, when barrier metal 104' and electrode 105' are brought into contact, ie, when dissimilar metals are brought into contact, a current density difference between the adjacent metals may cause corrosion known as galvanic corrosion, thereby causing charge transfer.

[0364] Figure 36 A is a graph in which the vertical axis represents current density and the horizontal axis represents potential, and the graph represents the relationship between current density and the potential of a predetermined metal. Figure 36 A is a graphic of metals such as TaN, Cu, and nickel.

[0365] The potential of TaN is lower than that of Cu, so a current path 361 is generated for charge to be transferred from TaN to Cu. Figure 35 As shown, a current path 361 is formed between the barrier metal 104' formed of TaN and the electrode 105' formed of Cu, wherein charge is transferred from the barrier metal 104' to the electrode 105', resulting in the electrode 105' being charged. When the electrode 105' is charged, slurry stagnation occurs, thereby forming a recessed area 341.

[0366] This corrosion may occur in Figure 35 As a result, a large recessed region 342 may be formed throughout the entire Cu of the opening side of the miniaturized electrode 105″ shown in B. A structure in which the influence of corrosion is suppressed at least in the electrode 105 and such a recessed region 342 does not appear will be described below.

[0367] Reference Figure 36 B, a reaction film 381 is provided between the barrier metal 104 and the electrode 105 to reduce the influence of corrosion on the electrode 105. The reaction film 381 is a film formed of a metal having a higher potential than the electrode 105.

[0368] Reference Figure 36 A, by setting the reaction film 81 to a potential higher than that of Cu, for example, the reaction film 81 is formed of nickel, a current path 362 is generated in which charge is transferred from TaN to nickel. Figure 36 The current path 362 is generated from the barrier metal 104 to the reaction film 381. As a result, a recessed region 343 is generated in a portion of the region where the reaction film 381 and the barrier metal 104 are in contact.

[0369] Reference Figure 36 A, when comparing nickel and copper, nickel has a higher potential than copper, so no current path 363 is created for charge to transfer from nickel to copper. Figure 36 B, no current path 363 is generated from the reaction film 381 to the electrode 105.

[0370] By providing the reaction film 381 between the barrier metal 104 and the electrode 105 , the occurrence of dishing due to corrosion of the electrode 105 can be suppressed.

[0371] Figure 37 This is a diagram showing a configuration example of a pixel 12m according to Embodiment 12 to which the present technology is applied. Figure 37 The pixel 12m and the pixel 12m according to the embodiment 12 are shown Figure 12 The same parts among the illustrated pixels 12 d according to Embodiment 4-1 are given the same reference numerals, and description thereof is appropriately omitted.

[0372] like Figure 37 As shown, the electrode 105 is formed in the stacked film 100 in which the interlayer insulating film 101, the liner insulating film 102, and the interlayer insulating film 103 are stacked, thereby forming the electrode formed in the joint portion. The barrier metal 104 and the reaction film 381 are formed between the stacked film 100 and the electrode 105. More specifically, the barrier metal 104 and the reaction film 381 are formed on the side surfaces and bottom surfaces of the connection hole 121 and the wiring hole 122.

[0373] The reaction film 381 is formed of a material having a higher potential than the material constituting the electrode 105. For example, metals such as graphite, platinum, zirconium, titanium, silver, and nickel, or alloys containing these metals as main components can be used as the material of the reaction film 381.

[0374] Figure 37 The portion of the reaction film 381 located on the opening side (upper side in the figure) undergoes a reference Figure 36 The following illustrates the state in which the etched film 381 is etched and a recessed region 343 is formed. As seen from the top surface of the interlayer insulating film 103, the recessed region 343 exists at the position of the reaction film 381 and forms a recessed shape therein. Depending on the degree of the recess, the recessed region 343 may be large or small (or may not exist).

[0375] A structure in which the reaction film 381 is provided between the barrier metal 104 and the electrode 105 prevents the barrier metal 104 from corroding the electrode 105, thereby reducing the amount of dishing. Reducing the amount of dishing prevents insufficient expansion of the electrode 105, a lack of contact between the electrodes 105, and contact defects when the semiconductor substrate is bonded to another semiconductor substrate and the electrodes 105 are in contact with each other.

[0376] <Manufacturing according to Embodiment 12>

[0377] Will refer to Figure 38 Description Figure 37 The pixel 12m is manufactured by forming the electrode 105 shown in FIG. Figure 38 The manufacture of a portion of the electrode 105 will be described.

[0378] In step S161, a semiconductor substrate having a stacked film 100 formed therein, in which an interlayer insulating film 101, a liner insulating film 102, and an interlayer insulating film 103 are stacked, is prepared. The connection hole 121 and the wiring hole 122 are formed by etching the stacked film 100. For example, in a photolithography step, a photoresist is applied to generate a resist pattern for forming the connection hole 121, and dry etching is performed using the resist pattern as a mask to form the connection hole 121. The wiring hole 122 is formed through a similar step.

[0379] In step S162 , the barrier metal 104 is formed by, for example, sputtering. The barrier metal 104 is formed on the side surfaces and bottom surfaces of the connection hole 121 and the wiring hole 122 , and also on the top surface of the interlayer insulating film 103 .

[0380] In step S163, a reaction film 381 is formed on the barrier metal 104. The reaction film 381 can also be formed by sputtering. The reaction film 381 uses a material having a higher potential than that used for the barrier metal 104 and the electrode 105.

[0381] In step S164, the material of the electrode 105, for example, copper (Cu), is embedded in the connection hole 121 and the wiring hole 122. The electrode 105 made of copper (Cu) is embedded in the connection hole 121 and the wiring hole 122 by Cu sputtering and then Cu plating.

[0382] In step S165, Cu is polished and planarized. In this step, excess Cu and the barrier metal 104 and the reaction film 381 on the top surface of the interlayer insulating film 103 are removed by CMP.

[0383] Through the above steps, a Figure 37 The electrodes of the reaction membrane 381 are shown.

[0384] <Implementation Plan 13>

[0385] Figure 39 This is a diagram showing a configuration example of a pixel 12n according to Embodiment 13 to which the present technology is applied. Figure 39 The pixel 12n according to the embodiment 13 is shown Figure 37 The same parts among the pixels 12 m according to Embodiment 12 are given the same reference numerals, and description thereof is appropriately omitted.

[0386] When compared Figure 39 The pixel 12n according to the embodiment 13 is shown Figure 37 In the pixel 12m according to the embodiment 12 shown, the region where the reaction film 381n is formed in the pixel 12n is different from the region where the reaction film 381 is formed in the pixel 12m. Other points are the same.

[0387] Figure 39 The reaction film 381n of the illustrated pixel 12n is provided on a portion of the side surface of the connection hole 121. The reaction film 381n is formed on the side surface of the connection hole 121 at a predetermined depth from the side where the bonding surface is located.

[0388] The reaction film 381n is formed at a depth of, for example, at least 10 nm from the surface of the stacked film 100. The reaction film 381n is formed to a thickness of, for example, at least 5 nm. The reaction film 381n is formed to a film thickness and depth that allow the slurry to enter and react sufficiently, even if the reaction film 381n melts and forms a gap.

[0389] As reference Figure 35 and Figure 36 As mentioned above, the depression occurs on the side where the bonding surface of the electrode 105 is located, so Figure 39 The pixel 12n shown has a configuration in which the reaction film 381n is provided on the side of the bonding surface where a depression may occur. Even with this configuration, the reaction film 381n prevents the depression from reaching the electrode 105 and can be bonded to an electrode provided on another substrate to be bonded without any problems.

[0390] <Manufacturing according to Embodiment 13>

[0391] Will refer to Figure 40 and Figure 41 Description Figure 39 The pixel 12n is manufactured by forming the electrode 105 shown in FIG. Figure 40 and Figure 41 The manufacture of a portion of the electrode 105 will be described.

[0392] In step S171, a substrate is prepared in which the barrier metal 104 is formed on the stacked film 100 in which the interlayer insulating film 101, the liner insulating film 102, and the interlayer insulating film 103 are stacked. In step S172, a resist pattern 401 is formed. The resist pattern 401 is formed so that the side of the connection hole 121 where the reaction film 381n is to be formed is open.

[0393] In step S173, the resist pattern 401 is partially removed. The resist pattern 401 to be removed is the resist pattern 401 formed on the laminate film 100. In other words, the resist pattern is removed to leave the resist pattern 401 formed in the connection hole 121 and the wiring hole 122.

[0394] In step S174 , a reaction film 381 n is formed by, for example, sputtering. The reaction film 381 n is formed on the side surfaces of the opening of the connection hole 121 , the top surface of the resist pattern 401 , and the top surface of the interlayer insulating film 103 .

[0395] In step S175, a resist pattern 403 is formed. The resist pattern 403 is formed on the reaction film 381n formed in the process of step S174.

[0396] In step S176 ( Figure 41 ), in order to remove the reaction film 381n formed on the resist pattern 401, in which the resist pattern 403 is to be partially removed, the resist pattern 403 is removed in the region where the reaction film 381n formed on the resist pattern 401 is located.

[0397] In step S177, the reaction film 381n in the region of the opening of the resist pattern 403 is removed by an etch-back process. In step S178, the resist pattern 403 is removed.

[0398] In step S179, the material of the electrode 105, for example, copper (Cu), is embedded in the connection hole 121 and the wiring hole 122. The electrode 105 made of copper (Cu) is embedded in the connection hole 121 and the wiring hole 122 by Cu sputtering and then Cu plating.

[0399] In step S175, Cu is polished and planarized. In this step, the excess portion of Cu and the barrier metal 104 and the reaction film 381n on the top surface of the interlayer insulating film 103 are removed by CNP.

[0400] Through the above steps, a Figure 39 The electrodes of the reaction membrane 381n are shown.

[0401] as Figure 39When the reaction film 381n is provided in a portion of the connection hole 121 as in the illustrated pixel 12n, the expansion hindrance suppression film 131 may be provided in a portion where the reaction film 381n is not provided. Figure 42 An example of a pixel 12n' having such a configuration is shown.

[0402] The reaction film 381n is formed in a predetermined size on Figure 42 The illustrated pixel 12n' is formed on the side of the connection hole 121, on the side where the bonding surface is located. The expansion-hindering suppression film 131 is formed on the side of the connection hole 121 of the pixel 12n' in the area where the reaction film 381n is not formed, on the bottom surface of the connection hole 121, and on the side and bottom surfaces of the wiring hole 122. This configuration enables a configuration in which the amount of concavity is suppressed and the expansion of the electrode 105 is not hindered during heat treatment.

[0403] Embodiment 13 may be implemented in combination with any one or more of Embodiments 1 to 11.

[0404] <Implementation Plan 14>

[0405] Figure 43 This is a diagram showing a configuration example of a pixel 12p according to Embodiment 14 to which the present technology is applied.

[0406] exist Figure 43 In the illustrated pixel 12p, a connection hole 121 and a wiring hole 122 are formed in the insulating film 500. For example, copper (Cu) serving as the electrode 105 is buried in the connection hole 121 and the wiring hole 122.

[0407] An expansion assisting film 511 is formed around the wiring hole 122. The expansion assisting film 511 is configured to have a thickness substantially equal to the depth of the wiring hole 122. Although not shown, the electrode 105 within the wiring hole 122 is connected to an electrode in the wiring layer. The wiring hole 122 and the electrode 105 are formed in the central portion of the expansion assisting film 511 to facilitate connection to the wiring.

[0408] The barrier metal 104 is formed to surround the electrode 105 and the expansion assisting film 511. The barrier metal 104 is continuously formed between the electrode 105 and the insulating film 500 in the connection hole 121, between the expansion assisting film 511 and the insulating film 300, and on the bottom surface of the wiring hole 122.

[0409] like Figure 44 As shown, the expansion assisting film 511 pushes the electrode 105 toward the bonding surface side during the heat treatment to assist expansion.

[0410] like Figure 44As shown, during the heat treatment, the expansion assisting film 511 expands, and the electrode 105 on the expansion assisting film 511 is subjected to a force that moves it toward the bonding surface (upper side in the figure) due to the expansion of the expansion assisting film 511. The electrode 105 itself has a force that expands toward the bonding surface, and the force from the expansion assisting film 511 is added to this force. As a result, the expansion force of the electrode 105 is strengthened, allowing for seamless bonding with electrodes provided on other substrates to be bonded.

[0411] The expansion assisting film 511 is made of a material that thermally expands more readily than the electrode 105 to assist expansion of the electrode 105 during thermal expansion. A material having a high coefficient of thermal expansion is used for the expansion assisting film 511. When copper (Cu) is used for the electrode 105, a material having a higher coefficient of thermal expansion than copper is used for the expansion assisting film 511. Since the coefficient of thermal expansion of copper is 16.8 ppm / K, when copper is used for the electrode 105, for example, a material having a coefficient of thermal expansion of 16.8 ppm / K or higher is used as the material for the expansion assisting film 511.

[0412] For example, resin, metal, or insulating material is used as the material of the expansion assisting film 511. When resin is used as the material of the expansion assisting film 511, for example, polyimide, epoxy resin, fluororesin, or the like can be used.

[0413] When a metal is used as the material of the expansion assisting film 511, for example, aluminum, tin, zinc, lead, magnesium, solder, etc. can be used. When an insulating material is used as the material of the expansion assisting film 511, for example, lithium titanium oxide / lithium titanate (LTO), a low-k material (a material having a low dielectric constant k, a low-k material), etc. can be used.

[0414] Figure 43 An example is shown in which the surface of the bonding surface on the electrode 105 side of the pixel 12p is recessed from the surface of the insulating film 500 due to the recess. Figure 44 As shown above, even when the electrode 105 is recessed due to the concavity, during the heat treatment, the expansion of the electrode 105 is assisted by the expansion force of the expansion assisting film 511. Therefore, during bonding to another substrate, bonding with an electrode provided on another substrate to be bonded can be performed without any problem.

[0415] <Manufacturing according to Embodiment 14>

[0416] Will refer to Figure 45 Description Figure 43 The pixel 12p is manufactured by forming the electrode 105 shown in FIG. Figure 45 The manufacture of a portion of the electrode 105 will be described.

[0417] In step S191, a substrate having an insulating film 500 formed therein is prepared. In step S192, a groove 531 is formed in the insulating film 500 by etching. The groove 531 is a region where the electrode 105 and the expansion assisting film 511 are formed. For example, in a photolithography step, a photoresist is applied to generate a resist pattern for forming the groove 531, and dry etching is performed using the resist pattern as a mask to form the groove 531.

[0418] In step S193 , the barrier metal 104 is formed by, for example, sputtering. The barrier metal 104 is formed on the side and bottom surfaces of the groove 531 and the surface of the insulating film 500 .

[0419] In step S194, an expansion assisting film 511 is formed on the barrier metal 104 in the groove 531. Forming the expansion assisting film 511 in step S194 also forms a space corresponding to the connection hole 121.

[0420] In step S195, the expansion assisting film 511 is partially removed, which forms a region corresponding to the wiring hole 122. Similar to the process of step S191, for example, a resist pattern in which a portion serving as the wiring hole 122 is opened is generated, and dry etching is performed using the resist pattern as a mask to form the wiring hole 122.

[0421] In step S196, the material of the electrode 105, for example, copper (Cu), is embedded in the connection hole 121 and the wiring hole 122. The electrode 105 made of copper (Cu) is embedded in the connection hole 121 and the wiring hole 122 by Cu sputtering and then Cu plating.

[0422] In step S197, Cu is polished and planarized. In this step, excess Cu and the barrier metal 104 on the top surface of the insulating film 500 are removed by CMP.

[0423] Through the above steps, a Figure 43 The electrodes of the expansion auxiliary membrane 511 are shown.

[0424] <Implementation Plan 15>

[0425] Figure 46 is a diagram showing a cross-sectional configuration example of a pixel 12q according to Embodiment 14 to which the present technology is applied, Figure 47 1 is a diagram showing an example of a planar configuration of the pixel 12q. Figure 46 The pixel 12q according to embodiment 15 is shown Figure 43 The same parts among the pixels 12p according to Embodiment 14 are given the same reference numerals, and description thereof is appropriately omitted.

[0426] exist Figure 46In the illustrated pixel 12q, a connection hole 121 and a wiring hole 122 are formed in the insulating film 500. For example, copper (Cu) serving as the electrode 105 is buried in the connection hole 121 and the wiring hole 122. The barrier metal 104 is formed so as to surround the electrode 105. The barrier metal 104 is continuously formed on the side and bottom surfaces of the connection hole 121 and the side and bottom surfaces of the wiring hole 122.

[0427] The expansion assisting film 511p is formed around the wiring hole 122. The barrier metal 104 is formed between the electrode 105 in the wiring hole 122 and the expansion assisting film 511. The expansion assisting film 511p is surrounded by an oxide film 551. The oxide film 551 is formed between the expansion assisting film 511p and the insulating film 500.

[0428] exist Figure 46 In the illustrated configuration of the pixel 12 q , the expansion assisting film 511 q is formed in a layer below the electrode 105 in the connection hole 121 .

[0429] Reference Figure 47 In the example of the planar structure of the pixel 12q shown in FIG. 1 , the electrode 105 is formed in the center portion, and the expansion auxiliary film 511q is formed around the electrode 105. Figure 47 In the example shown, the electrode 105 is octagonal, that is, the connection hole 121 is formed in an octagon. The expansion auxiliary membrane 511q is formed in a quadrilateral. Although the example in which the electrode 105 is octagonal and the expansion auxiliary membrane 511q is quadrilateral is described here, other shapes can also be used.

[0430] The expansion assisting film 511 q is formed using the same resin, metal, or insulating material as that of the expansion assisting film 511 of the pixel 12 p according to Embodiment 14.

[0431] like Figure 48 As shown, the expansion assisting film 511q pushes the electrode 105 toward the bonding surface side during the heat treatment to assist expansion. Figure 48 As shown, during the heat treatment, the expansion assisting film 511q expands, and the barrier metal 104 and electrode 105 on the expansion assisting film 511q are subjected to a force that moves them toward the bonding surface (upper side in the figure) due to the expansion of the expansion assisting film 511q. The electrode 105 itself has a force that expands toward the bonding surface, and the force from the expansion assisting film 511q is added to this force. As a result, the expansion force of the electrode 105 is strengthened, and when bonding to another substrate, bonding with electrodes provided on the other substrate can be achieved without any problems.

[0432] Figure 46 An example is shown in which the surface of the bonding surface on the electrode 105 side of the pixel 12q is recessed from the surface of the insulating film 500 due to the recess. Figure 44As described above, even when the electrode 105 is recessed due to the recess, the expansion of the electrode 105 is assisted by the expansion force of the expansion assisting film 511q. Therefore, during bonding to another substrate, bonding with electrodes provided on the other substrate to be bonded can be performed without any problems.

[0433] Figure 49 1 shows another cross-sectional configuration example of the pixel 12q according to Embodiment 14. Figure 49 In the illustrated pixel 12q, the expansion assisting film 511 is composed of three layers. The expansion assisting film 511q of pixel 12q consists of an expansion assisting film 511-1, an interlayer film 512, and expansion assisting films 511-2. The expansion assisting films 511q-1 and 511q-2 can be made of the same material or different materials. The interlayer film 512 can be made of the same material as the insulating film 500.

[0434] Although the case where the expansion assisting film 511 is composed of three layers is described here as an example, the number of layers is not limited to three, and the expansion assisting film 511 may be composed of multiple layers.

[0435] When the electrodes 105 are arranged very close to each other, a configuration in which an expansion assisting film 511q is provided may be used, such as Figure 50 shown. Figure 50 The upper portion of FIG shows a cross-sectional configuration example of two adjacent electrodes 105 in the pixel 12q. Figure 50 The lower part shows a plane configuration example.

[0436] exist Figure 50 In the example of the expansion assisting film 511q shown, the expansion assisting film 511q is formed across the adjacent electrodes 105-1 and 105-2. The expansion assisting film 511q is formed in a region within a layer below the electrodes 105-1 and 105-2 and is located between the electrodes. Figure 50 In the example shown in the upper portion of FIG. 5 , the oxide film 551 surrounding the expansion assisting film 511 is formed on the left side of the lower layer of the electrode 105 - 1 and on the right side of the lower layer of the electrode 105 - 2 .

[0437] The expansion assisting film 511 q may be formed for each electrode 105 , or may be formed across a plurality of electrodes 105 .

[0438] <Manufacturing according to Embodiment 15>

[0439] Will refer to Figure 51 and Figure 52 Description Figure 46 The pixel 12q is manufactured by forming the electrode 105 shown in FIG. Figure 51 and Figure 52 The manufacture of a portion of the electrode 105 will be described.

[0440] In step S201 , a substrate having the insulating film 500 formed therein is prepared. In step S202 , a film serving as the expansion assisting film 511 q is formed on the insulating film 500 .

[0441] In step S203, the expansion assisting film 511q is removed from the region other than the region to be used as the expansion assisting film 511q. For example, a resist pattern is generated in which the region to be used as the expansion assisting film 511q is masked, and dry etching is performed using the resist pattern as a mask to form the expansion assisting film 511.

[0442] In step S204 , an oxide film 551 is formed. For example, SiN (silicon nitride) can be used as the oxide film 551. The oxide film 551 is formed on the top surface and side surfaces of the expansion assisting film 511q and the top surface of the insulating film 500.

[0443] In step S205, the excess oxide film 551 is removed. For example, the oxide film 551 formed on the top surface of the expansion assisting film 511q and the top surface of the insulating film 500 is removed by an etch-back process.

[0444] In step S206 ( Figure 52 ), an insulating film 500 is further formed. In step S206, an insulating film 500 is formed in a layer of a portion where the connection hole 121 is to be formed.

[0445] In step S207 , the connection hole 121 and the wiring hole 122 are formed by, for example, dry etching. The wiring hole 122 is formed by etching the expansion assisting film 511 q , and the connection hole 121 is formed by etching the insulating film 500 .

[0446] In step S208 , the barrier metal 104 is formed by sputtering, for example. The barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121 , the side and bottom surfaces of the wiring hole 122 , and the top surface of the insulating film 500 .

[0447] In step S209, the material of the electrode 105, for example, copper (Cu), is embedded in the connection hole 121 and the wiring hole 122. The electrode 105 made of copper (Cu) is embedded in the connection hole 121 and the wiring hole 122 by Cu sputtering and then Cu plating.

[0448] In step S210, the Cu is polished and planarized. In this step, excess Cu and the barrier metal 104 on the top surface of the insulating film 500 are removed by CMP. When recessing occurs, the top surface of the electrode 105 is located lower than the top surface of the insulating film 500, as shown in the depiction of step S210.

[0449] Through the above steps, a Figure 46The electrodes of the expansion auxiliary film 511q are shown.

[0450] <Implementation Plan 16>

[0451] Figure 53 is a diagram showing a cross-sectional configuration example of a pixel 12r according to Embodiment 14 to which the present technology is applied, Figure 54 A diagram showing an example of a planar structure of the pixel 12r. Figure 53 and Figure 54 The pixel 12r and the pixel 12r according to the embodiment 16 are shown Figure 46 and Figure 47 The same parts among the pixels 12q according to Embodiment 14 are given the same reference numerals, and description thereof is appropriately omitted.

[0452] and Figure 46 Compared to the pixel 12q shown in Figure 53 The pixel 12r shown in FIG2 is different from the pixel 12r in which the expansion auxiliary film 511r is formed. Other points are the same. Figure 53 The expansion assisting film 511 r of the illustrated pixel 12 r is provided around the wiring hole 122 and also provided in a portion around the connection hole 121 .

[0453] The barrier metal 104 is formed between the electrode 105 and the expansion assisting film 511 in the wiring hole 122. The barrier metal 104 is formed between the electrode 105 and the expansion assisting film 511 in the connection hole 121.

[0454] The expansion assisting film 511 r is surrounded by an oxide film 551 . The oxide film 551 r is formed between the expansion assisting film 511 r and the insulating film 500 .

[0455] exist Figure 53 In the illustrated pixel 12 r , an expansion assisting film 511 r made of a material having a high thermal expansion coefficient is provided below and around the electrode 105 of the connection hole 121 .

[0456] Reference Figure 54 In the example of the planar structure of the pixel 12r shown in FIG. 1 , the electrode 105 is formed in the center portion, and the expansion auxiliary film 511r is formed around the electrode 105. Figure 54 In the example shown, the electrode 105 is octagonal, that is, the connection hole 121 is formed in an octagon. The expansion auxiliary membrane 511r is formed in a quadrilateral. Although the example in which the electrode 105 is octagonal and the expansion auxiliary membrane 511r is quadrilateral is described here, other shapes can also be used.

[0457] The expansion assisting film 511 r is formed using the same resin, metal, or insulating material as that of the expansion assisting film 511 of the pixel 12 q according to Embodiment 14.

[0458] With reference Figure 48 As in the case of the pixel 12q described above, the expansion assisting film 511r serves as a film that pushes the electrode 105 upward toward the bonding surface side to assist expansion during the heat treatment. During the heat treatment, the force from the expansion assisting film 511r disposed below the connection hole 121 and the force from the expansion assisting film 511r disposed around the connection hole 121 act on the electrode 105. Figure 54 The electrode 105 of the pixel 12r shown. Therefore, the expansion force of the electrode 105 is strengthened, and when it is attached to another substrate, it can be bonded to the electrode provided on the other substrate to be attached without any problem.

[0459] Figure 53 An example is shown in which the surface of the bonding surface on the electrode 105 side of the pixel 12r is recessed from the surface of the insulating film 500 due to the recess. Even if the electrode 105 is recessed due to the recess, the expansion of the electrode 105 is assisted by the expansion force of the expansion assisting film 511r. Therefore, during bonding to another substrate, bonding with the electrode provided on the other substrate to be bonded can be achieved without any problems.

[0460] Figure 55 Another planar configuration example of the pixel 12r according to embodiment 14 is shown. Figure 55 The illustrated planar configuration example of the pixel 12 r is an example in which the expansion assisting film 511 r arranged in the lower layer of the electrode 105 is only partially provided in the connection hole 121 . Figure 55 The structure of the pixel 12r shown can also be applied to Figure 46 A pixel 12q according to embodiment 15 is shown.

[0461] Figure 55 The example shown in Figure A shows an example in which the expansion assisting film 511r provided in the lower layer of the electrode 105 is divided into two regions, namely, the expansion assisting film 511r-1 and the expansion assisting film 511r-2. The expansion assisting films 511r-1 and 511r-2 are provided above and below in the figure, respectively. The expansion assisting film 511r-1 and the expansion assisting film 511r-2 are separated by the insulating film 500.

[0462] Figure 55 The example shown in B is Figure 55 The same as shown in A is that the expansion auxiliary film 511r provided in the lower layer of the electrode 105 is divided into two regions, namely, the expansion auxiliary film 511r-1 and the expansion auxiliary film 511r-2. Figure 55 In the example shown in FIG. 1B , the expansion assisting film 511 r - 1 and the expansion assisting film 511 r - 2 are provided on the left and right sides of the figure, respectively. The expansion assisting film 511 r - 1 and the expansion assisting film 511 r - 2 are separated by an insulating film 500 .

[0463] exist Figure 55In the example shown in FIG. 3C , the expansion assisting film 511r provided in the lower layer of the electrode 105 is provided in a rectangular shape near the center of the electrode 105. Alternatively, the expansion assisting film 511r is not provided in the area directly below the electrode 105, but rather is provided at the end of the electrode 105. In this manner, a configuration in which the expansion assisting film 511r having a predetermined shape and size is provided only in the central area or at the end of the electrode 105 can also be used.

[0464] exist Figure 55 In the example shown in FIG. 5 , the expansion assisting film 511r provided in the lower layer of the electrode 105 is divided into four regions, namely, expansion assisting films 511r-1 to 511r-4. The expansion assisting films 511r-1 to 511r-4 are provided at the four corners of the electrode 105, respectively. The expansion assisting films 511r-1 to 511r-4 are separated by an insulating film 500.

[0465] When the expansion auxiliary film 511r is also provided around the electrode 105, Figure 53 As in the pixel 12r shown, the expansion auxiliary film 511 around the electrode 105 is also Figure 55 The shapes shown in A to D are formed.

[0466] The region, size, shape, etc. where the expansion assisting membrane 511 is provided are not limited to those described above, and the expansion assisting membrane 511 may be formed and arranged in a region, size, shape, etc. other than those described above.

[0467] <Manufacturing according to Embodiment 16>

[0468] Will refer to Figure 56 Description Figure 53 The pixel 12q is manufactured by forming the electrode 105 shown in FIG. Figure 56 The manufacture of a portion of the electrode 105 will be described.

[0469] In step S221, a substrate on which the insulating film 500 including the expansion assisting film 511r and the oxide film 551r is formed is prepared. Figure 51 Steps S201 to S205 are shown, and after these steps are completed, the substrate is prepared.

[0470] In step S222 , the connection hole 121 and the wiring hole 122 are formed by dry etching, for example. In step S222 , etching is performed using a mask in which a portion corresponding to the connection hole 121 is opened so that the expansion assisting film 511 r remains on the side surface of the connection hole 121 .

[0471] In step S223 , the barrier metal 104 is formed by sputtering, for example. The barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121 , the side and bottom surfaces of the wiring hole 122 , and the top surface of the insulating film 500 .

[0472] In step S224, the material of the electrode 105, for example, copper (Cu), is embedded in the connection hole 121 and the wiring hole 122. The electrode 105 made of copper (Cu) is embedded in the connection hole 121 and the wiring hole 122 by Cu sputtering and then Cu plating.

[0473] In step S225, the Cu is polished and planarized. In this step, excess Cu and the barrier metal 104 on the top surface of the insulating film 500 are removed by CMP. When recessing occurs, the top surface of the electrode 105 is located lower than the top surface of the insulating film 500, as shown in the depiction of step S210.

[0474] Through the above steps, a Figure 53 The electrodes of the expansion auxiliary membrane 511r are shown.

[0475] <Implementation Plan 17>

[0476] Hereinafter, description will be made on Embodiment 17. Embodiment 17 will describe a pixel 12 in which the electrode 105 is formed of copper (Cu) and a Cu (111) face is formed on the connection face side.

[0477] As described in the above embodiment, if the electrodes 105 are bonded to each other by utilizing thermal expansion when the substrate is attached to another substrate, the occurrence of contact defects and the like can be reduced by forming the electrodes 105 in a Cu (111) orientation.

[0478] Cu(111) has a high surface diffusion rate and can be directly bonded at low temperatures. Forming the electrode 105 in the Cu(111) orientation provides a high surface diffusion rate, which facilitates expansion during bonding and suppresses the occurrence of defects during bonding.

[0479] Will refer to Figure 57 When the electrode 105 is formed of copper (Cu), the orientation of copper in the electrode 105 is described. Figure 57 A is a diagram showing a cross-sectional configuration example of a pixel 12' before CMP (pixels 12 to which this technique is not applicable are primed) and illustrates the orientation of copper. As described in the above embodiment, the electrode 105 is formed by a buried wiring method using electric field assisted Cu plating.

[0480] When the electrode 105 is formed by the buried wiring method using electric field assisted Cu plating, Cu is formed in a random orientation. Therefore, even if a Cu (111) surface is successfully formed, as shown in FIG. Figure 57As shown in FIG. 1 , even if (111)-oriented Cu is formed in the central region of the electrode 105 ′ (hereinafter referred to as the (111) region 601 ), randomly oriented Cu is formed around the (111) region 601 (hereinafter referred to as the random region 602 ).

[0481] After CMP treatment, Figure 57 The pixel 12' shown in A becomes Figure 57 B, and when viewed in plan view, as Figure 56 As shown in C. The (111) region 601 is provided at the center of the electrode 105' on the bonding surface side of the pixel 12', and the random region 602 is provided around it.

[0482] When the electrode 105' is miniaturized, the (111) region 601 shrinks and the proportion of the (111) region 601 occupying the bonding surface decreases. In other words, the influence of the random region 602 on the bonding surface may increase, and bonding using the above-mentioned high surface diffusion rate may become difficult. Figure 57 As shown in A, it is difficult to control the direction of plating in a shape with a step (inclination). In addition, (111)-oriented twins (hereinafter appropriately represented as (111)nt-Cu) are grown by forming a surface perpendicular to the electroplating deposition surface. Therefore, in the buried wiring formation method with a step on the side, it is difficult to align the (111) surface parallel to the bonding surface.

[0483] Figure 58 A diagram showing a cross-sectional configuration example of a pixel 12s according to Embodiment 17 to which the present technology is applied.

[0484] exist Figure 58 In the pixel 12s shown, the electrode 105 is formed in the insulating film 500. The electrode 105 is formed of Cu, and the entire junction surface is a (111) region 601 in which Cu is aligned in the (111) orientation.

[0485] The sidewalls and bottom edge of the electrode 105 are as follows Figure 59 shown. Figure 59 A is Figure 58 105. FIG. 106 is an enlarged view of a region 631 of a side wall of the electrode 105. In the side wall region 631, the barrier metal 104, the Cu seed crystal 621, and the plating barrier film 622 are formed between the insulating film 500 and the electrode 105.

[0486] The Cu seed crystal 621 is a film provided when forming the electrode 105 when Cu is formed by sputtering and Cu plating. The Cu seed crystal 621 is a film integrated with the formed electrode 105 (Cu) when the electrode 105 is formed, and therefore does not originally exist in the formed electrode 105. Figure 60When the pixel 12s (electrode 105 ) is manufactured, the Cu seed crystal 621 remains and is formed on the side wall of the electrode 105 .

[0487] The plating barrier film 622 is formed between the Cu seed crystal 621 and the electrode 105 in the sidewall region 631 of the electrode 105. The plating barrier film 622 is a film that blocks the growth of Cu. Since the plating barrier film 622 is formed on the sidewall, the growth of Cu is blocked, and the Cu seed crystal 621 remains without being integrated with the electrode 105.

[0488] Since the plating barrier film 622 is formed on the side wall and the growth of Cu is hindered, the formation of Figure 57 The random regions 602 are shown in A and B. In other words, the (111) regions 601 can be formed without hindering the growth of Cu from the bottom surface.

[0489] Figure 59 B is Figure 58 FIG1 is an enlarged view of a region 632 on the bottom surface of the electrode 105 in FIG1. ​​In the bottom surface region 632, the barrier metal 104 is formed between the insulating film 500 and the electrode 105. Since the plating barrier film 622 is not formed on the bottom surface, the Cu seed crystal 621 formed on the bottom surface is integrated with the electrode 105 and does not remain.

[0490] Figure 58 The electrode 105 of the pixel 12s shown in FIG. 1 is constructed with a plating barrier film 622 disposed on the sidewalls, preventing the (111)nt-Cu film from growing from the sidewalls. This configuration also allows the (111)nt-Cu film to grow from the bottom surface toward the bonding surface. Consequently, the (111)nt-Cu film can be formed perpendicularly to the substrate (silicon substrate) on which the insulating film 500 is formed.

[0491] The plating barrier film 622 is formed using a material that has the function of inhibiting the growth of Cu. For example, an insulating film such as SiO2 or SiN or a metal such as Ta (tantalum) can be used as the plating barrier film 622. SiO2, Ta2O5, TiO2, SiN, SiCN, SiOF, etc. can be used as the plating barrier film 622.

[0492] according to Figure 58 The electrodes 105 shown, when the semiconductor substrate is attached to another semiconductor substrate and the electrodes 105 are connected to each other, can be connected to each other even at low temperatures, for example, below 300 degrees. For example, connecting the electrodes 105 at low temperatures can realize a stacked device using organic materials with a temperature limit below 400 degrees, such as the imaging device 1 ( Figure 1 and Figure 2 ).

[0493] Even when the electrodes 105 are miniaturized, it is possible to prevent the electrodes 105 from not contacting each other and causing contact defects, which makes it easier to improve the stability of connection, ensure a certain yield, and the like.

[0494] <Manufacturing according to Embodiment 17>

[0495] Will refer to Figure 60 Description Figure 58 The pixel 12s is manufactured by the electrode 105 shown in FIG. Figure 60 The manufacture of a portion of the electrode 105 will be described.

[0496] In step S251, a substrate is prepared in which a connection hole 121 is formed in the insulating film 500 and a barrier metal 104 is further formed. For example, a resist pattern is generated for forming the connection hole 121, and dry etching is performed using the resist pattern as a mask to form the connection hole 121. Then, the barrier metal 104 is formed by, for example, sputtering. The barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121 and on the top surface of the insulating film 500.

[0497] In step S252, a Cu seed crystal 621 is formed. For example, a barrier layer composed of Ti (titanium), Ta (tantalum), or a nitride thereof is formed. The barrier layer is formed to a thickness of approximately 5 to 50 nm in an Ar / N2 atmosphere using a method such as radio frequency (RF) sputtering. Then, a Cu seed crystal 621 is formed to a thickness of approximately 1 to 50 nm on the barrier layer using a method such as RF sputtering.

[0498] In step S253, a plating barrier film 622 is formed. The plating barrier film 622 is formed on the Cu seed crystal 621, the side and bottom surfaces of the connection hole 121, and the top surface of the insulating film 500. For example, the plating barrier film 622 is formed by forming a SiO2 or SiN film or a natural oxide film such as Ti or Ta using ALD or the like, and then making its surface non-conductive.

[0499] In step S254, the entire surface is etched back using dry etching to remove the plating barrier film 622 formed on the surface of the insulating film 500 and the bottom surface of the connection hole 121. Step S254 is performed to ensure that the plating barrier film 622 remains only in the area serving as the side wall of the electrode 105, that is, on the side surface of the connection hole 121.

[0500] In step S255, Cu serving as the electrode 105 is formed in the connection hole 121. For example, (111)nt-Cu is formed by electroplating. The electroplating is performed using the following plating solution, for example:

[0501] Copper sulfate bath, Cu 60g / L, H2SO4 60g / L, HCl 50ppm

[0502] Additives include accelerators (sulfur organic compounds) and inhibitors (non-ionic surfactants), etc.

[0503] The plating current condition of electroplating is 10mA / cm 2 ~50mA / cm 2 When plating is performed under these conditions, (111)nt-Cu can be formed on the Cu seed crystal 621.

[0504] As depicted in step S255, (111) nt-Cu grows from the bottom surface of the connection hole 121 where the Cu seed crystal 621 is exposed, and is formed within the connection hole 121. Furthermore, since the Cu seed crystal 621 is also exposed on the surface of the insulating film 500, the (111) nt-Cu grows and is formed from the surface of the insulating film 500. However, since the (111) nt-Cu does not grow from the sidewall where the plating barrier film 622 is located, the formation of a random region 602 having misaligned (111) nt-Cu on the bonding surface side can be suppressed.

[0505] In step S256 , excess Cu is removed. For example, Cu and the barrier metal 104 formed on the surface of the insulating film 500 are removed by CMP.

[0506] Through the above steps, a Figure 58 The electrode has a Cu(111) orientation.

[0507] <Other Examples of Manufacturing According to Embodiment 17>

[0508] Will refer to Figure 61 Description Figure 58 Another example of manufacturing a pixel 12s having the configuration of the electrode 105 shown.

[0509] In step S261, a substrate is prepared in which the connection hole 121 is formed in the insulating film 500, and further, the barrier metal 104, the Cu seed crystal 621 and the plating barrier film 622 are formed. In the steps before step S261, by performing steps S251 to S253 ( Figure 60 ), forming the barrier metal 104, the Cu seed crystal 621 and the plating barrier film 622.

[0510] If the plating barrier film 622 is formed of a metal such as Ti or Ta, step S262-2 is performed after the treatment in step S262-1. Step S262-2 is performed to make the surface of the plating barrier film 622 (in this case, the surface of the metal) non-conductive by oxygen (O2) plasma treatment or the like. Performing the treatment to make the surface non-conductive can improve the stability of subsequent steps.

[0511] After executing step S262-1, the process moves to step S262-2. If the plating barrier film 622 is formed of a material other than metal, such as an insulating film, after executing step S261, the process moves to step S262-2.

[0512] In step S262-2, a resist pattern 641 is generated in which a region serving as the connection hole 121 is opened. In step S263, dry etching is performed using the resist pattern 641 as a mask to remove the plating preventer film 622 formed on the bottom surface of the connection hole 121.

[0513] Executing step S263 ensures that the plating barrier film 622 remains in the region serving as the sidewall of the electrode 105, ie, on the side of the connection hole 121. At the time of executing step S263, the plating barrier film 622 formed on the surface of the insulating film 500 still remains.

[0514] In step S264, Cu serving as the electrode 105 is formed in the connection hole 121. The processing in step S264 is the same as that in step S255 ( Figure 60 ), for example, a process for forming (111) nt-Cu by electroplating. In step S264, since the plating barrier film 622 remains on the surface of the insulating film 500, (111) nt-Cu does not grow from the surface of the insulating film 500, and thus (111) nt-Cu is not formed on the insulating film 500.

[0515] In step S264, the reference step S255 ( Figure 60 ) is applicable to the conditions for forming (111)nt-Cu by applying the electric field assisted plating method described in the preceding text. However, in this case, the plating barrier film 622 is also formed on the insulating film 500, so it is necessary to reduce the plating current value and adjust it to an appropriate level according to the numerical aperture.

[0516] As described with reference to step S264, (111) nt-Cu grows from the bottom surface of the connection hole 121 in which the Cu seed crystal 621 is exposed, and is formed within the connection hole 121. However, since the plating barrier film 622 is formed on the surface of the insulating film 500, the (111) nt-Cu does not grow from the surface of the insulating film 500. However, since the (111) nt-Cu also does not grow from the side wall where the plating barrier film 622 is located, the generation of the random region 602 having the (111) nt-Cu having a misaligned orientation on the bonding surface side can be suppressed.

[0517] In step S265, the barrier metal 104 formed on the surface of the insulating film 500 is removed by, for example, CMP. At this time, if Cu remains on the surface of the insulating film 500, Cu is also removed.

[0518] Through the above steps, a Figure 58 The electrode has a Cu(111) orientation surface as shown.

[0519] <Implementation Plan 18>

[0520] Figure 62 A diagram showing a cross-sectional configuration example of a pixel 12t according to Embodiment 18 to which the present technology is applied. Figure 62 The pixel 12t and the pixel 12t according to embodiment 18 are shown Figure 58 The same parts among the pixels 12s according to Embodiment 17 are given the same reference numerals, and description thereof is appropriately omitted.

[0521] and Figure 58 Compared to the Pixel 12s shown in Figure 61 The pixel 12t shown in FIG. 1 is different in that the side wall shape of the connection hole 121 is different and no plating inhibitor film 622 is formed. The other points are the same.

[0522] exist Figure 62 In the illustrated pixel 12t, a connection hole 121 is formed in the insulating film 500, and an electrode 105 is formed in the connection hole 121. The connection hole 121 is formed in an inverted tapered shape. The connection hole 121 is formed so that its width on the connection surface side (the upper side in the figure) is smaller than the width on the bottom surface side (the lower side in the figure) of the connection hole 121. The barrier metal 104 is formed on the sidewalls and bottom surface of the connection hole 121.

[0523] Figure 63 The diagram shows the orientation of Cu formed in connection hole 121. Because the sidewalls of connection hole 121 are formed to slope downward in the diagram, the (111) nt-Cu formed from the sidewalls grows in a downwardly sloping direction. Meanwhile, the (111) nt-Cu growing from the bottom surface of connection hole 121 grows upward, that is, toward the connection surface.

[0524] Since the (111) nt-Cu grown from the sidewall grows in a downward direction and the (111) nt-Cu grown from the bottom surface grows in an upward direction, the influence of the (111) nt-Cu grown from the sidewall on the (111) nt-Cu grown from the bottom surface can be reduced. By growing the (111) nt-Cu in this manner, the electrode 105 within the connection hole 121 can be constructed so that the (111) region 601 occupies most of the connection surface side, even if the random region 602 is formed near the sidewall of the connection hole 121, as shown in FIG. Figure 62 shown.

[0525] according to Figure 62 When the semiconductor substrate is bonded to another semiconductor substrate and the electrodes 105 are connected to each other, the electrodes 105 can be connected to each other even at low temperatures, for example, below 300 degrees Celsius. For example, connecting the electrodes 105 at low temperatures makes it possible to realize a stacked device using organic materials with a temperature limit of below 400 degrees Celsius.

[0526] Even when the electrodes 105 are miniaturized, it is possible to prevent the electrodes 105 from not contacting each other and causing contact defects, which makes it easier to improve the stability of connection, ensure a certain yield, and the like.

[0527] Cu on the sidewall of the pad (connection hole 121) with poor seed coverage can be protected and defects occurring during plating can be reduced. Aligning the crystal orientation in the electrode 105 can reduce crystal interfaces and improve electromigration resistance.

[0528] <Manufacturing according to Embodiment 18>

[0529] Will refer to Figure 64 Description Figure 62 The pixel 12t is manufactured by the electrode 105 shown in FIG. Figure 64 The manufacture of a portion of the electrode 105 will be described.

[0530] In step S271, a substrate having the insulating film 500 formed therein is prepared, and etching is performed to form the connection hole 121. For example, a resist pattern 661 is generated in which a region serving as the connection hole 121 is opened, and dry etching is performed using the resist pattern 661 as a mask to form the connection hole 121.

[0531] In step S271, a plasma film 663 formed of SiO2 or SiN is formed by plasma chemical vapor deposition (CVD). The plasma film 663 is formed on the sidewalls and bottom surface of the connection hole 121 and on the surface of the insulating film 500. As shown in the depiction of step S271, the plasma film 663 formed on the sidewalls of the connection hole 121 has an inverted tapered shape.

[0532] By forming the plasma film 663 from the same material as the insulating film 500, the plasma film 663 and the insulating film 500 can be integrally formed. However, even if the plasma film 663 is formed from a different material from the insulating film 500, the plasma film 663 can be used to form the inversely tapered sidewalls of the insulating film 500.

[0533] In step S273, etching is performed to remove the plasma film 663 formed on the bottom surface of the connection hole 121. The plasma film 663 formed on the surface of the insulating film 500 is processed to be thinner or removed.

[0534] The plasma film 663 formed on the bottom surface of the connection hole 121 may be left, and the etch-back process in step S273 may be omitted.

[0535] In step S274, a barrier metal 104 and a Cu seed crystal 621 are formed. The barrier metal 104 is formed, for example, by sputtering, and is formed on the side surfaces (on the plasma film 663) and bottom surface of the connection hole 121 and the top surface of the insulating film 500 (on the top surface of the plasma film 663).

[0536] The Cu seed crystal 621 can be obtained by referring to step S252 ( Figure 60 The Cu seed crystal 621 is formed on the barrier metal 104, in this case, on the side and bottom surfaces of the connection hole 121 and the top surface of the insulating film 500.

[0537] In step S275, Cu serving as the electrode 105 is formed in the connection hole 121. The processing in step S275 is the same as that in step S255 ( Figure 60 ) is the same as in the process of forming (111) nt-Cu by electroplating. In step S275, (111) nt-Cu is also formed on the surface of the insulating film 500.

[0538] In step S276 , the (111) nt-Cu and the barrier metal 104 formed on the surface of the insulating film 500 are removed by, for example, CMP.

[0539] Through the above steps, a Figure 62 The electrode has a Cu(111) orientation surface as shown.

[0540] <Other Examples of Manufacturing According to Embodiment 18>

[0541] Will refer to Figure 65 Another example of a manufacturing process for forming the sidewall of the connection hole 121 in the inverse tapered shape will be described.

[0542] In step S281, a substrate having an insulating film 500 formed therein is prepared, and etching is performed to form the connection hole 121, and the sidewall of the connection hole 121 is formed into an inverted tapered shape. For example, a resist pattern 681 is generated in which a region smaller than the region serving as the connection hole 121 is opened, and etching is performed using the resist pattern 681 as a mask.

[0543] This etching process is performed by combining isotropic etching conditions. Isotropic etching can also form the sidewalls of the connection holes 121 into an inverted tapered shape because the film directly below the resist can be removed.

[0544] In the process of step S281, the connection hole 121 having the side wall of the reverse tapered shape is formed. After the process of step S281 is completed, steps S272 to S276 are executed (execution of the same Figure 64 By performing processes such as forming and removing the barrier metal 104 and the Cu seed crystal 621, forming and removing the (111)nt-Cu film, etc., a Figure 62 Electrode 105 of pixel 12t is shown.

[0545] <Other Examples of Manufacturing According to Embodiment 18>

[0546] The plasma film 663 is formed to have the same function as the plating barrier film 622. That is, as the material of the plasma film 663, the plasma film 663 can be formed using the same material as the plating barrier film 622. In this case, the plasma film 663 having an inverted tapered shape is formed on the side wall of the connection hole 121. Providing the plasma film 663 (plating barrier film 622) having such an inverted tapered shape makes it easier to grow the (111)nt-Cu film in the desired direction, in this case, toward the connection surface side.

[0547] Will refer to Figure 66 The production of the pixel 12 t having the plating inhibitor film 622 having an inverted tapered shape will be described.

[0548] In step S291, a substrate having the insulating film 500 formed therein is prepared, and etching is performed to form the connection hole 121. For example, a resist pattern 701 in which a region serving as the connection hole 121 is open is generated, and dry etching is performed using the resist pattern 701 as a mask to form the connection hole 121.

[0549] In step S292, the barrier metal 104 and the Cu seed crystal 621 are formed. The barrier metal 104 and the Cu seed crystal 621 can be formed by, for example, sputtering. The Cu seed crystal 621 can be formed by the same method as in step S252 ( Figure 60 ) is formed by the same process as described above.

[0550] In step S293, plasma SiO2 (P-SiO) is formed to a thickness of, for example, approximately 100 nm to 200 nm. Plasma SiO2 functions as the plating barrier film 622 and is formed of a material that can be used as the plating barrier film 622. Although SiO2 is used as an example here, other materials can also be used.

[0551] In step S294 , the plating barrier film 622 formed on the surface of the insulating film 500 and the bottom surface of the connection hole 121 is removed by an etch-back process.

[0552] When the plating barrier film 622 is formed on the side wall of the connection hole 121 by such a process, and when the plating barrier film 622 is formed on the side wall by such a process, the plating barrier film 622 having a tapered shape can be obtained, as shown in FIG. Figure 66 The shape of the plating barrier film 622 can be adjusted by adjusting the conditions used when forming the plasma SiO 2 in step S293, the conditions used in the etch-back process in step S294, and the like.

[0553] After step S294, by executing steps S255 and S256 ( Figure 60 ) treatment, Cu with a (111) surface can be formed as the electrode 105.

[0554] <Implementation Plan 19>

[0555] Figure 67 This is a diagram showing an example of the cross-sectional structure of a pixel 12u according to Embodiment 19 to which the present technology is applied.

[0556] Although the above embodiment is described with reference to the electrode 105 as an example, Figure 67 As shown, there is also a region where a plurality of electrodes 105 are provided. Figure 67 An example is shown in which the electrodes 105-1 to 105-6 are arranged side by side in the insulating film 500. The electrodes 105-1 to 105-6 are formed of copper (Cu), and are configured such that the (111) plane is located in the joint portion.

[0557] For example, the above-described embodiment 17 or 18 may be applied to each electrode 105 so that each electrode 105 is formed by a process of controlling the growth of a (111)nt-Cu film. However, each electrode 105 may also be formed by the following process.

[0558] Will refer to Figure 68 and Figure 69 The fabrication of a pixel 12u having an electrode 105, wherein the Cu(111) surface is disposed on the bonding surface side, as shown in FIG. Figure 67 shown.

[0559] In step S311, electrodes 105A and 105B are formed within insulating film 500. Electrode 105A is a single large electrode formed in the region where electrodes 105-1, 105-2, and 105-3 are formed. Similarly, electrode 105B is a single large electrode formed in the region where electrodes 105-4, 105-5, and 105-6 are formed. In this example, the size of electrodes A (B) is larger than the combined size of the three electrodes 105.

[0560] The electrodes 105A and 105B are formed of Cu with a uniform plane orientation (111). If the size is above 100, the electrode 105 can be formed of Cu with uniform plane orientation (111). The electrodes 105A and 105B are formed, for example, with The electrode 105 is formed with the above dimensions and is formed by growing Cu having a uniform plane orientation (111). Since similar steps (processing) are performed for the electrode 105A and the electrode 105B, the description will continue using the electrode 105A as an example.

[0561] In step S311, a substrate having insulating film 500 formed therein is prepared, and a groove having approximately the same size as electrode 105A is formed at the position where electrode 105A is to be formed by etching. For example, in a photolithography step, a photoresist is applied to generate a resist pattern for forming the groove, and dry etching is performed using the resist pattern as a mask to form the groove.

[0562] For example, the barrier metal 104A is formed by sputtering in a groove formed at a location where the electrode 105A is to be formed. The barrier metal 104A formed in areas other than the side and bottom surfaces of the groove is removed by a process such as an etch-back process. Then, within the groove where the barrier metal 104A is formed, Cu is grown on the (111) surface by using a Cu plating process, thereby forming Cu having a (111) plane orientation.

[0563] In step S312, electrode 105A is segmented. Electrode 105A is segmented into electrode 105-1, electrode 105-2, and electrode 105-3. For example, electrode 105A is segmented (reduced) to a desired size by a photolithography process, a dry etching process, or the like. A resist pattern 721 is generated in which the positions corresponding to the segmentation are opened, and etching is performed using resist pattern 721 as a mask to form grooves at the segmentation positions.

[0564] Grooves 731-1 and 731-2 are formed in electrode 105A, and grooves 731-3 and 731-4 are formed in electrode 105B. The formation of grooves 731-1 and 731-2 divides electrode 105A into electrodes 105-1, 105-2, and 105-3. The formation of grooves 731-3 and 731-4 divides electrode 105B into electrodes 105-4, 105-5, and 105-6.

[0565] By adjusting the shape of the resist pattern 721, etching conditions, etc., the shape of the groove 731 can be made into a desired shape. Figure 68 In the example shown, the groove 731 is formed in a tapered shape. The groove 731 is formed in a tapered shape in which the side surfaces are not vertical but inclined.

[0566] The groove 731 is formed at a depth that separates the barrier metal 104. When the barrier metal 104 is processed, the insulating film 500 is also processed, and as a result, a concave portion may be formed in the insulating film 500.

[0567] The barrier metal 104A is divided into the barrier metal 104A-1, the barrier metal 104A-2, and the barrier metal 104A-3 by forming the groove 731. The barrier metal 104B is divided into the barrier metal 104B-1, the barrier metal 104B-2, and the barrier metal 104B-3 by forming the groove 731. After performing processing such as removing the resist pattern 721, the process moves to step S313.

[0568] In step S313, barrier metal 104C is formed. In step S312, groove 731 is formed to divide electrode 105A, and Cu is exposed on the sidewalls of the divided portion. For example, referring to the figure depicting step S312, due to the formation of groove 731-1, electrode 105-1 is in a state where barrier metal 104A is not present on the sidewall on the right side of the figure. Electrode 105-2 is in a state where barrier metal 104A is not present on both the left and right sidewalls of the figure.

[0569] In step S313, a process of forming the barrier metal 104 on the sidewalls of the electrode 105 without the barrier metal 104 is performed. In step S313, the barrier metal 104C is formed on the surface of the electrode 105 and on the sidewalls and bottom surface of the groove 731.

[0570] In step S314 ( Figure 69 ), the barrier metal 104C formed on the surface of the electrode 105 and the bottom surface of the groove 731 is removed by a process such as dry etching. Figure 69In step S314, by removing the excess barrier metal 104C, the electrode 105-1 is in a state where the barrier metal 104A-1 is formed on the side wall and bottom surface on the left side of the figure, and the barrier metal 104C-1 is formed on the side wall on the right side of the figure.

[0571] The electrode 105-2 is in a state where the barrier metal 104A-2 is formed on the bottom surface, the barrier metal 104C-2 is formed on the side wall on the left side of the figure, and the barrier metal 104C-3 is formed on the side wall on the right side of the figure. The electrode 105-3 is in a state where the barrier metal 104A-3 is formed on the bottom surface and the right side surface, and the barrier metal 104C-4 is formed on the side wall on the left side of the figure.

[0572] Electrode 105-4 is in a state where barrier metal 104B-1 is formed on the bottom surface and the left side surface, and barrier metal 104C-5 is formed on the right side wall in the figure. Electrode 105-5 is in a state where barrier metal 104B-2 is formed on the bottom surface, barrier metal 104C-6 is formed on the left side wall in the figure, and barrier metal 104C-7 is formed on the right side wall in the figure. Electrode 105-6 is in a state where barrier metal 104B-3 is formed on the bottom surface and the right side surface, and barrier metal 104C-8 is formed on the left side wall in the figure.

[0573] The barrier metal 104C remaining on the sidewall of the electrode 105 is formed into a recess in the insulating film 500. For example, the barrier metal 104C-1 formed on the left side of the electrode 105-1 is formed at the location of the recess in the insulating film 500. The barrier metal 104A-1 is formed on the bottom surface of the electrode 105-1, but the barrier metal 104C-1 is formed deeper than the barrier metal 104A-1. Other barrier metals 104C are also formed at the location of the recess in the insulating film 500.

[0574] When barrier metal 104C is removed, portions of barrier metals 104A and 104C formed at both ends of the outermost surface of electrode 105 are also removed, and the corresponding portions assume the shape of recesses. For example, the upper side of barrier metal 104C-1 formed on the left side of electrode 105-1 (the outermost surface of electrode 105-1) is formed to a position lower than (deeper than) the outermost surface of electrode 105-1. This portion forms a recess relative to the outermost surface of electrode 105-1.

[0575] The other barrier metals 104A and 104C are also formed at positions lower than the outermost surface of the electrode 105 and at positions that are recessed relative to the outermost surface of the electrode 105 .

[0576] In step S315, an insulating film 723 is formed. The insulating film 723 is formed to fill the groove 731 between the electrodes 105. The insulating film 723 is formed of the same material as the insulating film 500 and can be integrated with the insulating film 500 after formation. Alternatively, the insulating film 723 can be formed of a material different from that of the insulating film 500. For example, a material having better film forming properties than the insulating film 500 can be used as the insulating film 723.

[0577] In step S316, the insulating film 723 is subjected to CMP to expose the surface of the electrode 105 and flatten the bonding surface. Because the outermost surface of the electrode 105 and the barrier metal 104 are at different heights, the CMP of the insulating film 723 only requires consideration of the selectivity between the insulating film 723 and Cu. Polishing of the barrier metal 104 is unnecessary, thus reducing the amount of dishing in the Cu produced by CMP. This reduction in dishing reduces contact defects in the bond between the electrodes 105 when the substrate is bonded to another substrate.

[0578] Because the top surface of electrode 105 and barrier metal 104 are at different heights, or in other words, because barrier metal 104 has a recess as described above, insulating film 723 remains in the recess. Insulating film 723-1 is formed in the recess of barrier metal 104A-1 between electrode 105-1. Insulating film 723-2 is formed between electrode 105-2 and electrode 105-3. A portion of insulating film 723-2 is formed in the recess of barrier metal 104C-1 formed on the sidewall of electrode 105-1, while the remaining portion is formed in the recess of barrier metal 104C-2 formed on the sidewall of electrode 105-2.

[0579] The insulating film 723-3 is formed between the electrodes 105-2 and 105-3. A portion of the insulating film 723-3 is formed in a recess of the barrier metal 104C-3 formed on the sidewall of the electrode 105-2, and the remaining portion is formed in a recess of the barrier metal 104C-4 formed on the sidewall of the electrode 105-3. The insulating film 723-4 is formed in a recess of the barrier metal 104A-3 on the electrode 105-3.

[0580] The insulating film 723-5 is formed in the recess of the barrier metal 104B-1 on the electrode 105-4. The insulating film 723-6 is formed between the electrode 105-4 and the electrode 105-5. A portion of the insulating film 723-6 is formed in the recess of the barrier metal 104C-5 formed on the sidewall of the electrode 105-4, and the remaining portion is formed in the recess of the barrier metal 104C-6 formed on the sidewall of the electrode 105-5.

[0581] An insulating film 723-7 is formed between the electrode 105-5 and the electrode 105-6. A portion of the insulating film 723-7 is formed in a recess of the barrier metal 104C-7 formed on the sidewall of the electrode 105-5, and the remaining portion is formed in a recess of the barrier metal 104C-8 formed on the sidewall of the electrode 105-6. The insulating film 723-8 is formed in a recess of the barrier metal 104B-3 on the electrode 105-6.

[0582] The electrode 105 at the junction of the pixel 12 u has the configuration shown in the description of step S316 . Figure 70 1 to 105 - 3 formed by dividing the electrode 105A are shown in FIG, and the configuration of the electrode 105 at the junction of the pixel 12 u will be described in more detail.

[0583] If by reference Figure 68 and Figure 69 The described process forms the electrode 105 at the junction of the pixel 12 u , and the orientation of the barrier metal 104 formed on the sidewall of one electrode 105 will be different.

[0584] Electrode 105-1 includes a vertical barrier metal 104A-1 on the left side of the figure and a barrier metal 104C-1 on the right side of the figure that tilts from the upper left to the lower right. Electrode 105-2 includes a barrier metal 104C-2 on the left side of the figure that tilts from the upper right to the lower left, and a barrier metal 104C-4 on the right side of the figure that tilts from the upper left to the lower right.

[0585] The electrode 105-3 includes a vertical barrier metal 104A-3 on the right side of the figure and a barrier metal 104C-4 on the left side of the figure that is tilted from the upper right to the lower left. In this way, when focusing on one electrode 105, the barrier metals 104 provided on the sidewalls of the electrode 105 are formed with different tilts and different directions.

[0586] The thickness of the barrier metal 104A and the thickness of the barrier metal 104C may be the same or different. When the thicknesses are different, for example, the barrier metal 104A-1 and the barrier metal 104C-1 having different thicknesses are formed on the sidewall of the electrode 105-1.

[0587] When focusing on one electrode 105, the length of the joint surface side and the length of the bottom surface side of the electrode 105 are different. For example, in electrode 105-1, the length of the joint surface side is shorter than the length of the bottom surface side. Similarly, in electrode 105-2, the length of the joint surface side is shorter than the length of the bottom surface side. In this way, the length of the joint surface side of the electrode 105 is shorter than the length of the bottom surface side.

[0588] The insulating film 723 is formed at the end portion on the bonding surface side of the barrier metal 104. For example, the insulating film 723-1 is formed at the end portion on the bonding surface side of the barrier metal 104A-1 provided on the side wall of the electrode 105-1, and the insulating film 723-2 is formed at the end portion on the bonding surface side of the barrier metal 104C-1.

[0589] The ends of the barrier metal 104 on the bonding surface side and the opposite side are located deeper than the barrier metal 104 on the bottom side of the electrode 105. For example, the end of the barrier metal 104C-1 provided on the side wall of the electrode 105-1 is located deeper than the barrier metal 104A-1 on the bottom side of the electrode 105-1. The ends of the barrier metal 104C-2 and the end of the barrier metal 104C-3 provided on the side wall of the electrode 105-2 are located deeper than the barrier metal 104A-2 on the bottom side of the electrode 105-2.

[0590] In other words, the barrier metal 104 on one or both sidewalls of the electrode 105 is formed to a position deeper than the barrier metal 104 on the bottom side of the electrode 105 .

[0591] If the insulating film 500 and the insulating film 723 are formed of different materials during manufacturing, the insulating film 723 formed between the electrodes 105 and the insulating film 500 formed around the electrodes 105 will have different film properties. Different film properties mean different materials themselves, different types of films (film species), etc.

[0592] When the electrode pattern is formed by forming a large electrode 105 and then dividing (mineralizing) the large electrode 105 , the electrode 105 will have such a configuration feature.

[0593] By forming a large electrode 105 and then dividing (mineralizing) the large electrode 105, the electrode 105 can be composed of Cu having a plane orientation of (111). Because Cu having a plane orientation of (111) has a high thermal expansion coefficient even at low temperatures, when the semiconductor substrate is bonded to another semiconductor substrate and the electrodes 105 are connected to each other, the electrodes 105 can be connected to each other even at low temperatures, such as below 300 degrees Celsius. For example, connecting the electrodes 105 at low temperatures makes it possible to realize a stacked device using organic materials with a temperature limit of below 400 degrees Celsius.

[0594] Even when the electrodes 105 are miniaturized, it is possible to prevent the electrodes 105 from not contacting each other and causing contact defects, which can improve the stability of connection, ensure a certain yield, and the like.

[0595] Of course, the above-mentioned embodiments 1 to 19 can be implemented individually or in combination with each other.

[0596] The above embodiments 1 to 19 describe examples of application to the imaging device 1 having a stacked structure in which a plurality of semiconductor substrates are stacked. However, the present technology can be widely applied to semiconductor substrates including electrodes having the configuration of the above-described electrode 105 .

[0597] <Implementation Plan 20-1>

[0598] Figure 71 This is a diagram showing a configuration example of a pixel 12v according to embodiment 20-1 to which the present technology is applied. Figure 71 The pixel 12v and the pixel 12v according to the embodiment 20-1 are shown Figure 4 The same parts among the illustrated pixels 12 a according to Embodiment 1 are given the same reference numerals, and description thereof is appropriately omitted.

[0599] Figure 71 A single electrode constituting the pixel 12v is shown, and the following electrode (electrode pad) is shown, which is arranged on the bonding surface side where the first semiconductor substrate 30 and the second semiconductor substrate 40 are bonded, and is bonded using the above-mentioned pumping phenomenon to make the first semiconductor substrate 30 and the second semiconductor substrate 40 conductive.

[0600] like Figure 71 As shown, the electrode formed at the bonding portion is configured by forming an electrode 105 in a stacked film 100 in which an interlayer insulating film 101 , a liner insulating film 102 , and an interlayer insulating film 103 are stacked.

[0601] Figure 71 The electrode 105 shown has a dual damascene shape and is configured with a connection hole 121 and a wiring hole 122. As described later, this technology can be applied to an electrode having a single damascene shape and can also be applied to a configuration having only a connection hole.

[0602] The barrier metal 104 and the liner film 801 or the air layer 802 are formed between the stacked film 100 and the electrode 105. More specifically, the barrier metal 104 and the liner film 801 are formed between the stacked film 100 and the electrode 105 on the side of the wiring hole 122. The barrier metal 104 and the air layer 802 are formed between the stacked film 100 and the electrode 105 on the side of the connection hole 121.

[0603] The air layer 802 is a film provided so as not to hinder thermal expansion of the material constituting the electrode 105 during heat treatment.

[0604] For example, Figure 3As shown, if only the barrier metal 104 is formed between the stacked film 100 and the electrode 105, the barrier metal 104 may hinder the expansion of the electrode 105, resulting in a reduction in the amount of expansion of the electrode 105. If the adhesion between the barrier metal 104 and the electrode 105 is high, the electrode 105 may be Figure 71 The expansion force in the upward direction may be suppressed and weakened by the barrier metal 104 , and the expansion may be insufficient.

[0605] The air layer 802 is provided between the barrier metal 104 and the electrode 105, so that the barrier metal 104 does not hinder the expansion of the electrode 105. The provision of the air layer 802 reduces (eliminates) the adhesion strength between the barrier metal 104 and the electrode 105, which suppresses the expansion of the electrode 105. Figure 71 The occurrence of a situation where the expansion force in the upward direction is suppressed and weakened by the cushion film 801. This ensures that sufficient expansion can be achieved.

[0606] The air layer 802 is formed by the galvanic effect, as will be described later. Figure 72 Although the liner film 801 is formed in the region where the air layer 802 exists during the manufacturing process, the liner film 801 is corroded by the galvanic effect and becomes the air layer 802. In order to utilize the galvanic effect, a material having an intermediate electronegativity, that is, between the electronegativity of the material of the electrode 105 and the electronegativity of the material of the barrier metal 104, is used for the liner film 801.

[0607] For example, Cu (copper) is used as the material of the electrode 105. For example, Ta (tantalum), TaN (tantalum nitride), Ti (titanium), TiN (titanium nitride), etc. are used as the material of the barrier metal 104. When such a material is used, a material having an electronegativity between that of Cu and that of the material of the barrier metal 104 is used as the liner film 801.

[0608] For example, Al (aluminum), V (vanadium), Mn (manganese), Co (cobalt), Ni (nickel), Mo (molybdenum), Ru (ruthenium), or the like can be used as the liner film 801 .

[0609] <Manufacturing according to embodiment 20-1>

[0610] Will refer to Figure 72 Description Figure 71 The pixel 12v is manufactured by the electrode 105 shown in FIG. Figure 72 The manufacture of a portion of the electrode 105 will be described.

[0611] In step S311, a substrate is prepared in which a stacked film 100 is formed in which an interlayer insulating film 101, a liner insulating film 102, and an interlayer insulating film 103 are stacked. The connection hole 121 and the wiring hole 122 are formed by etching the stacked film 100.

[0612] For example, in a photolithography step, a photoresist is applied to generate a resist pattern (patterning) for forming the wiring hole 122. An etching step is performed, and dry etching is performed using the resist pattern generated in the photolithography step as a mask, thereby forming the wiring hole 122. The connection hole 121 can be formed by repeating the same process.

[0613] In step S312 , the barrier metal 104 is formed by, for example, sputtering. The barrier metal 104 is formed on the side surfaces and bottom surfaces of the connection hole 121 and the wiring hole 122 , and also on the top surface of the interlayer insulating film 103 .

[0614] In step S313, a liner film 801 is formed on the barrier metal 104. The liner film 801 can also be formed by sputtering.

[0615] In step S314, the material of the electrode 105, for example, copper (Cu), is embedded in the connection hole 121 and the wiring hole 122. The electrode 105 made of copper (Cu) is embedded in the connection hole 121 and the wiring hole 122 by Cu sputtering and then Cu plating.

[0616] In step S315, Cu is polished and planarized. This step removes excess Cu and the barrier metal 104 and liner film 801 on the top surface of the interlayer insulating film 103 by chemical mechanical planarization (CMP). When the Cu is polished in step S315, an air layer 802 is formed by self-alignment.

[0617] Through the above steps, a Figure 71 The electrodes are shown with an air layer 802. The air layer 802 can be formed by self-alignment and thus can be formed by a cost-effective process.

[0618] <Implementation Plan 20-2>

[0619] Figure 73 This is a diagram showing a configuration example of a pixel 12v according to Embodiment 20-2 to which the present technology is applied. Figure 73 The pixel 12v and the pixel 12v according to the embodiment 20-2 are shown Figure 71 The same parts among the pixels 12 w according to the embodiment 20 - 1 are given the same reference numerals, and description thereof is appropriately omitted.

[0620] like Figure 73 As shown, the pixel 12v according to the embodiment 20-2 is Figure 71 The pixel 12v according to the embodiment 20-1 shown is different in that a dummy electrode 108 is added. Other points are the same.

[0621] Figure 73 The pixel 12 v shown includes an electrode 105 for conducting with other semiconductor substrates and a dummy electrode 108 that does not need to conduct with other semiconductor substrates. Figure 73 The electrode 105 shown as being formed on the right side of the pixel 12v has Figure 71 The electrodes 105 shown have the same structure, and their description will be omitted.

[0622] For example, when there are regions where electrodes 105 are located and regions where electrodes 105 are not located due to layout or other factors, dummy electrodes 108 are located in the regions where electrodes 105 are not located. Dummy electrodes 108 are located in regions where the connection to other semiconductor substrates is weak, for example, to prevent a decrease in adhesion strength between semiconductor substrates. Therefore, dummy electrodes 108 can be formed relatively larger than electrodes 105 that require conduction.

[0623] like Figure 73 As shown, dummy electrode 108 shown on the left side of the figure is larger than electrode 105 shown on the right side of the figure. Making dummy electrode 108 larger also increases the amount of copper embedded in connection hole 123, thereby increasing the amount of expansion during heat treatment. In this case, the reduction in expansion associated with miniaturized electrode 105 is less likely to occur in dummy electrode 108, making it possible to omit air layer 802.

[0624] exist Figure 73 In the dummy electrode 108 shown, only the barrier metal 107 is formed between the interlayer insulating film 103 and the dummy electrode 108, without forming the liner film 801, the air layer 802, etc. In this way, the electrodes including the dummy electrode 108 and the electrodes including the electrode 105 can also have different configurations.

[0625] <Manufacturing according to embodiment 20-2>

[0626] Will refer to Figure 74 Description Figure 73 The pixel 12v is manufactured by the electrode 105 shown in FIG. Figure 74 The manufacture of part of the electrode 105 and the dummy electrode 108 will be described.

[0627] In step S321, a substrate is prepared in which a stacked film 100 is formed, in which an interlayer insulating film 101, a liner insulating film 102, and an interlayer insulating film 103 are stacked. The connection hole 121, the wiring hole 122, and the connection hole 123 are formed by etching the stacked film 100. For example, in a photolithography step, a photoresist is applied to generate a resist pattern for forming the connection hole 121, the wiring hole 122, and the connection hole 123, and dry etching is performed using the resist pattern as a mask to form the connection hole 121, the wiring hole 122, and the connection hole 123.

[0628] In step S322, the barrier metal 104 is formed by sputtering, for example. The barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121, the side and bottom surfaces of the wiring hole 122, and the side and bottom surfaces of the connection hole 123, and also on the top surface of the stacked film 100.

[0629] In step S323, a liner film 801 is formed on the barrier metal 104. The liner film 801 can also be formed by sputtering. In step S323, the liner film 801 is formed on the side and bottom surfaces of the connection hole 121, the side and bottom surfaces of the wiring hole 122, the side and bottom surfaces of the connection hole 123, and the top surface of the stacked film 100. The liner film 801 formed on the side and bottom surfaces of the connection hole 123 will be referred to as a liner film 801'.

[0630] In step S324, the portion serving as the electrode 105, in this case, the connection hole 121 and the wiring hole 122, is filled (coated) with the resist 241. An etching step is performed, and dry etching is performed using the resist pattern generated in the photolithography step as a mask, thereby removing the liner film 801' formed in the connection hole 123 serving as the dummy electrode 108.

[0631] In step S325 , an ashing and washing process is performed to remove the resist 241 , and wet washing is performed.

[0632] In step S326, the material of the electrode 105, such as copper (Cu), is embedded in the connection hole 121 and the wiring hole 122. The material of the dummy electrode 108, such as copper (Cu), is also embedded in the connection hole 123. The copper (Cu) is embedded in the connection hole 121, the wiring hole 122, and the connection hole 123 by Cu sputtering and then Cu plating.

[0633] In step S327, Cu is polished and planarized. In this step, excess Cu and the barrier metal 104 on the top surface of the stacked film 100 are removed by CMP. In step S327, an air layer 802 is formed.

[0634] Through the above steps, a Figure 73 The electrode 105 with the air layer 802 is shown, and the pixel 12v has a dummy electrode 108 that does not include the air layer 802.

[0635] <Implementation Plan 20-3>

[0636] Figure 75 1 is a diagram showing a configuration example of a pixel 12v' according to Embodiment 20-3 to which the present technology is applied. Figure 75 The pixel 12v' and the pixel 12v' according to the embodiment 20-3 are shown Figure 71The same parts among the pixels 12 v according to the embodiment 20-1 are given the same reference numerals, and description thereof is appropriately omitted.

[0637] Figure 71 The pixel 12v according to the embodiment 20-1 shown has a dual mosaic structure, and Figure 75 The pixel 12v' according to the embodiment 20-3 is shown to have a single mosaic structure.

[0638] like Figure 75 As shown, in the electrode formed at the joint portion, a connection hole 121' is provided in the insulating film 221, and a barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121'. An air layer 802' is formed between the barrier metal 104 formed on the side of the connection hole 121' and the electrode 105.

[0639] Air layer 802' is provided as a film that does not hinder the thermal expansion of the material constituting electrode 105 during heat treatment. Therefore, air layer 802' does not hinder the expansion of the copper of electrode 105 within connection hole 121' during heat treatment. Therefore, the expansion of electrode 105 is not hindered, and bonding with the electrode provided on the substrate to be bonded can be performed without any problems.

[0640] <Manufacturing according to embodiment 20-3>

[0641] Will refer to Figure 76 Description Figure 75 The manufacturing of the pixel 12v' having the electrode 105 shown is referred to as Figure 76 The manufacture of a portion of the electrode 105 will be described.

[0642] In step S331, a semiconductor substrate is prepared with connection holes 121' formed in insulating film 221. Connection holes 121' are formed by etching the semiconductor substrate. For example, in a photolithography step, photoresist is applied to create a resist pattern for forming connection holes 121'. Dry etching is performed using the created resist pattern as a mask, thereby forming connection holes 121'.

[0643] In step S332 , the barrier metal 104 is formed by, for example, sputtering. The barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121 ′ and also on the top surface of the insulating film 221 .

[0644] In step S333, a liner film 801' is formed on the barrier metal 104. The liner film 801' can also be formed by sputtering.

[0645] In step S334, the material of the electrode 105, for example, copper (Cu), is buried in the connection hole 121'. The electrode 105 made of copper (Cu) is buried in the connection hole 121' by Cu sputtering and then Cu plating.

[0646] In step S335, the Cu is polished and planarized. In this step, excess Cu, the barrier metal 104 on the top surface of the insulating film 221, and the liner film 801' are removed by CMP. In this step, the liner film 801' formed on the side of the connection hole 121' is etched, thereby forming an air layer 802'.

[0647] Through the above steps, a Figure 75 The electrodes of the air layer 802' are shown.

[0648] <Implementation Plan 20-4>

[0649] Figure 77 1 is a diagram showing a configuration example of a pixel 12v" according to embodiment 20-4 to which the present technology is applied. Figure 77 The pixel 12v" according to the embodiment 20-4 is shown Figure 71 The same parts among the pixels 12 v according to the embodiment 20-1 are given the same reference numerals, and description thereof is appropriately omitted.

[0650] When compared Figure 77 The pixel 12v" according to the embodiment 20-4 is shown Figure 71 The pixel 12v according to the embodiment 20-1 is shown in FIG. 1 , but the pixel 12v is different in that the electrode 105 is composed of an electrode 105v-1 and an electrode 105v-2 formed of different materials.

[0651] Figure 77 The electrode 105 of the pixel 12v" shown in FIG. 1 is composed of an electrode 105v-1 and an electrode 105v-2. The electrode 105v-1 is formed of a first material, and the electrode 105v-2 is formed of a second material different from the first material. Figure 77 In the illustrated example, the electrode 105 v - 1 is an electrode formed in the connection hole 121 , and the electrode 105 v - 2 is an electrode formed in the wiring hole 122 .

[0652] The barrier metal 104 and the air layer 802 are formed on the sidewalls of the connection hole 121. The barrier metal 104 and the liner film 801 are formed on the bottom surface of the connection hole 121. The barrier metal 104 is formed on the sidewalls and bottom surface of the wiring hole 122.

[0653] The electrode 105v-1 formed in the connection hole 121 is formed of a first material that is easily expanded (e.g., Cu), and an air layer 802 is formed to prevent its expansion from being hindered. Therefore, the amount of expansion of the electrode 105v-1 formed in the connection hole 121 can be increased, and the electrode 105v-1 can be fully expanded. For example, Co can be used as the second material constituting the electrode 105v-2.

[0654] Likewise, in Figure 77 In the illustrated configuration, the expansion of the electrode 105 is not hindered, and the electrode 105 can be joined to the electrode provided on the substrate to be bonded without any problem.

[0655] <Implementation Plan 20-5>

[0656] Figure 78 A is a diagram showing a cross-sectional configuration example of a pixel 12v'' according to Embodiment 20-5 to which the present technology is applied, Figure 78 B is a diagram showing the planar structure of the pixel 12v''. Figure 78 The pixel 12v'' and Figure 71 The same parts among the pixels 12 v according to the embodiment 20-1 are given the same reference numerals, and description thereof is appropriately omitted.

[0657] When compared Figure 78 The pixel 12v'' and Figure 71 The pixel 12v according to the embodiment 20-1 shown has a different configuration in that a groove 301 is added to the pixel 12v. Other points are the same.

[0658] Grooves 301 are formed in Figure 78 The trench 301 is formed in the bottom surface of the connection hole 121 of the pixel 12 v ″ shown. The trench 301 is formed in a region corresponding to the difference between the bottom surface of the connection hole 121 and the surface of the wiring hole 122 on the connection hole 121 side.

[0659] Reference Figure 78 In the planar configuration example shown in FIG. 1B , the connection hole 121 is formed in a square shape, and the wiring hole 122 is formed in a circular shape in the center of the connection hole 121. The groove 301 is formed in a square shape in the area inside the connection hole 121 and outside the wiring hole 122 to surround the wiring hole 122.

[0660] Reference Figure 78 In the cross-sectional configuration example shown in FIG. 1A , the barrier metal 104 is formed on the side and bottom surfaces of the trench 301. Furthermore, a liner film 801 is also formed on the side surfaces of the trench 301. As in Embodiments 20-1 to 20-4, an air layer 802 is formed on the side surfaces of the connection hole 121.

[0661] In the pixel 12v''', providing the groove 301 increases the amount of copper (Cu) constituting the electrode 105, for example, and thus the amount of expansion can be increased.

[0662] exist Figure 78 In the illustrated configuration, electrode 105 is also configured to be in contact with air layer 802. This configuration with air layer 802 prevents the expansion of copper in electrode 105 within connection hole 121 during heat treatment from being hindered, allowing for easy bonding with electrodes provided on the substrate to be bonded.

[0663] <Implementation Plan 21-1>

[0664] Figure 79 This is a diagram showing a configuration example of a pixel 12w according to Embodiment 21-1 to which the present technology is applied. Figure 79 A single electrode constituting the pixel 12 w is shown, and an electrode (electrode pad) provided on the bonding surface side where the first semiconductor substrate 30 and the second semiconductor substrate 40 are bonded to conduct the first semiconductor substrate 30 and the second semiconductor substrate 40 to each other is shown.

[0665] like Figure 79 As shown, the electrode 105 is formed in the insulating film 221 to form an electrode formed in the joint portion.

[0666] Figure 79 The electrode 105 shown has a shape based on a single damascene process and is configured to have a connection hole 121. Note that the present technology can be applied to an electrode having a shape based on a dual damascene process and can also be applied to a configuration having a connection hole and a wiring hole.

[0667] like Figure 79 As shown, in the electrode formed at the joint portion, a connection hole 121 is provided in the insulating film 221, and the barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121. Carbon nanotubes 851 are formed on the joint surface side of the electrode 105. Before joining with another semiconductor substrate, the carbon nanotubes 851 are formed to a position higher than the joint surface of the insulating film 221.

[0668] Figure 80 A shows that when the first semiconductor substrate 30 and the second semiconductor substrate 40 (including Figure 79 FIGURE 1 illustrates the state of one electrode when electrodes 105-1 and 105-2 are bonded. The first semiconductor substrate 30, located on the upper side, and the second semiconductor substrate 40, located on the lower side, are bonded with a slight offset. The first semiconductor substrate 30 and the second semiconductor substrate 40 are electrically connected by connecting the carbon nanotubes 851-1 formed on the electrode 105-1 of the first semiconductor substrate 30 with the carbon nanotubes 851-2 formed on the electrode 105-2 of the second semiconductor substrate 40.

[0669] Figure 80 B is shown in Figure 80 FIG. 1 is a diagram showing a state of a pixel before being joined in the joined state shown in A in FIG. 1 , with a portion thereof being magnified. Pixel 12w-1 is joined to pixel 12w-2 shifted to the right in the figure. Figure 80 The carbon nanotube 851-1 within the dotted circle in FIG. B is a portion that is bonded to the insulating film 221 of the pixel 12w-2. Figure 80 As shown in FIG. 3 , the carbon nanotubes 851-1 at the offset position are broken during bonding and thus do not hinder bonding of the first semiconductor substrate 30 and the second semiconductor substrate 40. However, the carbon nanotubes 851 at positions other than the offset position are bonded to each other, so that the first semiconductor substrate 30 and the second semiconductor substrate 40 can be more reliably electrically bonded.

[0670] although Figure 80 The case where the carbon nanotubes 851 are formed in the electrodes 105 of both the first semiconductor substrate 30 and the second semiconductor substrate 40 is shown, but forming the carbon nanotubes 851 in only one electrode and directly bonding the electrode to the other electrode 105 (Cu) also falls within the scope of the present technology.

[0671] <First Example of Manufacturing According to Embodiment 21>

[0672] Will refer to Figure 81 Description Figure 79 A first example of manufacturing a pixel 12w having the structure of the electrode 105 shown is shown. Figure 81 The manufacture of a portion of the electrode 105 will be described.

[0673] In step S411, a semiconductor substrate is prepared, wherein a connection hole 121 is formed in the insulating film 221, a barrier metal 104 is formed in the connection hole 121, and copper (Cu) is buried therein as part of the electrode 105. The copper is buried at a position lower than the joint surface of the insulating film 221.

[0674] In step S412, a catalyst metal 852 is formed by sputtering, for example. The catalyst metal 852 is a material for forming the carbon nanotubes 851. The catalyst metal 852 is formed on the side surfaces of the connection hole 121, the top surface of the electrode 105, and the top surface of the insulating film 221.

[0675] For example, Ti (titanium), Ni (nickel), Ru (ruthenium), Mo (molybdenum), Co (cobalt), Fe (iron), etc. can be used as catalyst metal 852. Catalyst metal 852 can be a single layer composed of these metals or a multilayer layer composed of two or more metals. Catalyst metal 852 can also be a mixture of these metals. If catalyst metal 852 is a multilayer or mixture, the top layer is preferably a Co (cobalt) layer.

[0676] In step S413, the catalyst metal 852 is polished and planarized. In this step, the catalyst metal 852 on the top surface of the insulating film 221 is removed by CMP.

[0677] In step S414, plasma activation is performed. For example, N2 gas is used for the plasma activation. In step S415, carbon nanotubes 851 are formed by chemical vapor deposition (CVD) using, for example, CH4 or C2H6.

[0678] Then, by performing cleaning as shown in step S416, a Figure 79 The carbon nanotube 851 electrode is shown.

[0679] <Second Example of Manufacturing According to Embodiment 21>

[0680] Will refer to Figure 82 Description Figure 79 The electrode 105 is shown as a second example of the fabrication of a pixel 12w.

[0681] In step S421, a semiconductor substrate is prepared in which a connection hole 121 is formed in the insulating film 221, a barrier metal 104 is formed in the connection hole 121 and on the insulating film 221, and copper (Cu) as a part of the electrode 105 is buried therein. Figure 81 In step S411 described above, the semiconductor substrate after polishing the barrier metal 104 has been prepared, and thus the semiconductor substrate is in a state where the barrier metal 104 is not formed on the insulating film 221. Figure 82 In step S421 described above, the semiconductor substrate has already been prepared before the barrier metal 104 is polished, and thus the barrier metal 104 is located on the insulating film 221 in the semiconductor substrate.

[0682] In step S422 , the catalyst metal 852 is formed by, for example, sputtering. The catalyst metal 852 is formed on the side surfaces of the connection hole 121 , on the top surface of the electrode 105 , and on the barrier metal 104 of the insulating film 221 .

[0683] In step S423, the catalyst metal 852 and the barrier metal 104 are polished and planarized. In this step, the catalyst metal 852 and the barrier metal 104 on the top surface of the insulating film 221 are removed by CMP.

[0684] In step S424, plasma activation treatment is performed using, for example, N2 gas. In step S425, carbon nanotubes 851 are formed by CVD using, for example, CH4 or C2H6.

[0685] Then, by performing cleaning as shown in step S426, a Figure 79 The carbon nanotube 851 electrode is shown.

[0686] <Third Example of Manufacturing According to Embodiment 21>

[0687] Will refer to Figure 83 Description Figure 79 The third example of manufacturing the pixel 12w is shown as the structure of the electrode 105. Figure 83 A third example of manufacturing described with reference to Figure 82 The process of the second example of manufacturing described is the same except that when, for example, Fe (iron) is used for the catalyst metal 852 , the carbon nanotubes 851 are formed under the catalyst metal 852 .

[0688] In step S431 , a semiconductor substrate is prepared in which a connection hole 121 is formed in the insulating film 221 , a barrier metal 104 is formed in the connection hole 121 and on the insulating film 221 , and copper (Cu) as a part of the electrode 105 is buried therein.

[0689] In step S432, a catalyst metal 852 is formed by sputtering, for example. The catalyst metal 852 is formed on the side surfaces of the connection hole 121, the top surface of the electrode 105, and the barrier metal 104 of the insulating film 221. For example, Fe (iron) is used as the catalyst metal 852.

[0690] In step S433 , the catalyst metal 852 and the barrier metal 104 on the top surface of the insulating film 221 are removed by CMP.

[0691] In step S434, plasma activation treatment using, for example, N2 gas is performed. In step S435, carbon nanotubes 851 are formed by CVD using, for example, CH4 or C2H6. The carbon nanotubes 851 grow and form between the catalyst metal 852 and the electrode 105.

[0692] Then, by performing cleaning as shown in step S436 , an electrode in which the carbon nanotubes 851 are formed on the lower side of the catalyst metal 852 can be formed.

[0693] <Implementation Plan 21-2>

[0694] Figure 84 1 is a diagram showing a configuration example of a pixel 12w' according to Embodiment 21-2 to which the present technology is applied. Figure 84 The pixel 12w' and the pixel 12w' according to the embodiment 21-2 are shown Figure 79 The same parts among the pixels 12w according to the embodiment 21-1 are given the same reference numerals, and description thereof is appropriately omitted.

[0695] Figure 84 The pixel 12w' according to the embodiment 21-2 shown is Figure 79 The pixel 12w according to the embodiment 21-1 shown is different in that a dummy electrode 108 is added and the pixel is formed in a dual damascene structure. Other points are the same.

[0696] like Figure 84 As shown, the electrode formed at the bonding portion is configured by forming an electrode 105 in a stacked film 100 in which an interlayer insulating film 101 , a liner insulating film 102 , and an interlayer insulating film 103 are stacked.

[0697] Figure 84 The electrode 105 shown has a shape based on a dual damascene process and is configured to have a connection hole 121 and a wiring hole 122. A barrier metal 104 is formed between the stacked film 100 and the electrode 105. The electrode 105 is filled with Cu to a position lower than the joint surface of the stacked film 100, and the carbon nanotubes 851 are formed on the top surface.

[0698] Figure 84 The illustrated pixel 12w includes an electrode 105 for conducting with another semiconductor substrate and a dummy electrode 108 that does not require conducting with the other semiconductor substrate. For example, when there are areas where the electrode 105 is configured and areas where the electrode 105 is not configured due to layout or other factors, the dummy electrode 108 is configured in the area where the electrode 105 is not configured. For example, the dummy electrode 108 is configured in an area where the bonding with the other semiconductor substrate is weak so that the adhesion strength between the semiconductor substrates is not reduced. Therefore, the dummy electrode 108 can be formed to be relatively larger than the electrode 105 that needs to be conducted.

[0699] exist Figure 84 In the illustrated dummy electrode 108, only the barrier metal 107 is formed between the interlayer insulating film 103 and the dummy electrode 108, and no carbon nanotubes 851 are formed. In this way, the electrodes including the dummy electrode 108 and the electrodes including the electrode 105 may have different configurations.

[0700] <Manufacturing according to embodiment 21-2>

[0701] Will refer to Figure 85 Description Figure 84 The electrode 105 is shown in the fabrication of the pixel 12w'.

[0702] In step S441, a semiconductor substrate is prepared in which connection holes 121 and wiring holes 122 are formed in the stacked film 100. Barrier metal 104 is formed in the connection holes 121, in the wiring holes 122, and on the stacked film 100, and copper (Cu) serving as a portion of the electrode 105 is embedded therein. Connection holes 123 serving as dummy electrodes 108 are also formed in the semiconductor substrate, and barrier metal 107 is formed in the connection holes 123, and copper (Cu) serving as the dummy electrodes 08 is embedded therein.

[0703] In step S442 , the catalyst metal 852 is formed by sputtering, for example. The catalyst metal 852 is formed on the side surfaces of the connection hole 121 , the top surface of the electrode 105 , the top surface of the dummy electrode 108 , and the barrier metal 104 of the stacked film 100 .

[0704] In step S443, the catalyst metal 852 and the barrier metal 104 are polished and planarized. In this step, the catalyst metal 852 and the barrier metal 104 formed on the top surface of the stacked film 100 and the top surface of the dummy electrode 108 are removed by CMP.

[0705] In step S444, plasma activation treatment is performed using, for example, N2 gas. In step S445, carbon nanotubes 851 are formed on the electrode 105 by CVD using, for example, CH4 or C2H6.

[0706] Then, by performing cleaning as shown in step S446 , the electrode 105 in which the carbon nanotubes 851 are formed on the catalyst metal 852 and the dummy electrode 108 can be formed.

[0707] <Adjusting the Density of Carbon Nanotubes>

[0708] The density of the carbon nanotubes 851 will be adjusted. Figure 86 By following the process shown and patterning the catalyst metal 852 , the density of the carbon nanotubes 851 can be adjusted to a desired density.

[0709] Will use reference Figure 81 The manufacturing process of the electrode of the pixel 12w according to the embodiment 21-1 is continued as an example. Figure 81 The state in which the catalyst metal 852 is formed on the electrode 105 in step S413 is Figure 86 The state in step S451. Figure 86), when the catalyst metal 852 is formed on the electrode 105, the catalyst metal 852 (eg, Ti (titanium)) is patterned in step S452.

[0710] Figure 87 Examples of patterned shapes are shown. Figure 87 FIG. 8 shows the shape of the catalyst metal 852 after patterning, and is a plan view of the catalyst metal 852 when viewed from above. Figure 87 As shown in FIG. 8A , the catalyst metal 852 may be patterned into a stripe shape. The density of the formed carbon nanotubes 851 may be adjusted by adjusting the width of the stripes, the number of stripes, and the like.

[0711] like Figure 87 As shown in FIG. 8B , the catalyst metal 852 may be patterned into a lattice shape. The density of the formed carbon nanotubes 851 may be adjusted by adjusting the thickness of the lattice lines, the number of lines, and the like.

[0712] like Figure 87 As shown in FIG. C, the catalyst metal 852 can be patterned into a circular pattern (hexagonal lattice). The density of the formed carbon nanotubes 851 can be adjusted by adjusting the size of each circle, the number of circles, etc.

[0713] like Figure 87 The catalyst metal 852 may be patterned into concentric circles as shown in FIG. The density of the formed carbon nanotubes 851 may be adjusted by adjusting the thickness of the wire constituting one concentric circle, the number of circles, and the like.

[0714] <Implementation Plan 22-1>

[0715] Figure 88 This is a diagram showing a configuration example of a pixel 12x according to Embodiment 22-1 to which the present technology is applied. Figure 88 A single electrode constituting the pixel 12 x is shown, and an electrode (electrode pad) provided on the bonding surface side where the first semiconductor substrate 30 and the second semiconductor substrate 40 are bonded to conduct the first semiconductor substrate 30 and the second semiconductor substrate 40 to each other is shown.

[0716] like Figure 88 As shown, the electrode 105 is formed in the insulating film 221 to form an electrode formed in the joint portion.

[0717] Figure 88 The electrode 105 shown has a shape based on a single damascene process and is configured with a connection hole 121. Note that this technology can be applied to electrodes having a shape based on a dual damascene process, and can also be applied to a configuration having both a connection hole and a wiring hole. This technology can also be applied to a structure having a dummy electrode.

[0718] like Figure 88 As shown, in the electrode formed at the joint portion, a connection hole 121 is provided in the insulating film 221, and the barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121. A porous metal 881 is formed on the joint surface side of the electrode 105. The porous metal 881 is formed to a position higher than the joint surface of the insulating film 221.

[0719] Figure 89 A shows that when the first semiconductor substrate 30 and the second semiconductor substrate 40 (including Figure 88 FIG. 1 shows a state where one electrode is bonded to another electrode 105. The first semiconductor substrate 30, located on the upper side, and the second semiconductor substrate 40, located on the lower side, are bonded in an unshifted state. By bonding the porous metal 881-1 formed on the electrode 105-1 of the first semiconductor substrate 30 to the porous metal 881-2 formed on the electrode 105-2 of the second semiconductor substrate 40, the first semiconductor substrate 30 and the second semiconductor substrate 40 are electrically connected. The porous metal 881 can collapse during the bonding process to strengthen the bond between the porous metals 881.

[0720] Figure 89 The bonding state shown in B is a state in which the first semiconductor substrate 30 located on the upper side and the second semiconductor substrate 40 located on the lower side are bonded with a slight offset. The first semiconductor substrate 30 and the second semiconductor substrate 40 are electrically connected by bonding the overlapping portions of the porous metal 881-1 formed on the electrode 105-1 of the first semiconductor substrate 30 and the porous metal 881-2 formed on the electrode 105-2 of the second semiconductor substrate 40.

[0721] although Figure 89 The case where the porous metal 881 is formed in the electrodes 105 of both the first semiconductor substrate 30 and the second semiconductor substrate 40 is shown, but forming the porous metal 881 in only one electrode and directly bonding the electrode to the other electrode 105 (Cu) also falls within the scope of the present technology.

[0722] <First Example of Manufacturing According to Embodiment 22-1>

[0723] Will refer to Figure 90 Description Figure 88 A first example of manufacturing a pixel 12x having the structure of the electrode 105 shown is shown. Figure 90 The manufacture of a portion of the electrode 105 will be described.

[0724] In step S511, connection holes 121 are formed in insulating film 221. In step S512, barrier metal 104 is formed in connection holes 121, and copper (Cu) serving as electrode 105 is embedded therein. Barrier metal 104 and copper are also formed on the joint surface of insulating film 221. Although the description will continue assuming that copper is used as the electrode material, other materials may also be used. Since porous metal 881 is formed in a subsequent step, a porous material may be used as the material for electrode 105.

[0725] In step S513, the electrode 105 and the barrier metal 104 are polished and planarized. In this step, the electrode 105 (copper) and the barrier metal 104 on the top surface of the insulating film 221 are removed by CMP.

[0726] In step S514, an insulating film 221' is formed on the electrode 105 and the insulating film 221. The insulating film 221' uses the same material as the insulating film 221 and is a portion to be used as the insulating film 221. For example, SiO2, SiON, SiCN, or the like is used for the insulating film 221 and the insulating film 221' formed by CVD, ALD, or the like.

[0727] In step S515, the connection hole 121' is formed. The insulating film 221' is processed to form a portion serving as the connection hole 121, that is, a portion where the porous metal 881 is formed.

[0728] In step S516, barrier metal 104 and alloy 882 are formed. In step S516, barrier metal 104 is formed on the sidewalls of connection hole 121' formed in step S515. Barrier metal 104 and alloy 882 are formed on electrode 105 (copper), on the side surfaces of connection hole 121', and on insulating film 221. For example, an alloy of Cu and Zn is used as alloy 882.

[0729] In step S517, the alloy 882 and the barrier metal 104 on the top surface of the insulating film 221 are removed by CMP. In this step, the alloy 882 formed on the electrode 105 is processed to be convex and extends to a position higher than the bonding surface of the insulating film 221.

[0730] In step S518, porous metal 881 is formed. For example, if an alloy of Cu and Zn is used for alloy 882, pores are formed by etching Zn. For example, porous metal 881 is formed by etching in a copper sulfate plating solution using an azole additive.

[0731] Here, the pores (porous metal 881) will be described. The porosity of the porous metal is about 10% to 50%, and the depth of the porous portion (the length from the highest point of the porous metal 881 to the Cu) is about several nm to several tens of nm.

[0732] The porous metal is formed into a convex shape, as shown in the depiction of step S518. Due to the convex shape, the porous metal can collapse during the bonding process, thereby reliably connecting to other porous metals or electrodes. Therefore, it is preferred that the porous metal 881 has a strength that satisfies the following relationship:

[0733] Yield stress (platform stress) during compression < stress applied during bonding

[0734] Through the above steps, a Figure 88 The porous metal 881 electrode is shown.

[0735] <First Example of Manufacturing According to Embodiment 22-1>

[0736] Will refer to Figure 91 Description Figure 88 A second example of fabrication of a pixel 12x is shown with the configuration of the electrode 105 .

[0737] In step S521, a semiconductor substrate is prepared by performing steps S511 to S514 ( Figure 90 ) forms a connection hole 121'.

[0738] In step S522, the barrier metal 104 and the porous metal 881 are formed. The porous metal 881 is formed by electrochemical etching (Cu-Zn→Zn) in hydrochloric acid.

[0739] In step S523, the porous metal 881 and the barrier metal 104 on the top surface of the insulating film 221 are removed by CMP. In this step, the porous metal 881 formed on the electrode 105 is processed to be convex and extends to a position higher than the bonding surface of the insulating film 221.

[0740] Through the above steps, a Figure 88 The porous metal 881 electrode is shown.

[0741] <Third Example of Manufacturing According to Embodiment 22-1>

[0742] Will refer to Figure 92 Description Figure 88 A third example of fabrication of a pixel 12x is shown with the configuration of the electrode 105 .

[0743] In step S531 , a semiconductor substrate is prepared in which the connection hole 121 is formed in the insulating film 221 .

[0744] In step S532, the barrier metal 104 is formed in the connection hole 121, and copper (Cu) serving as the electrode 105 is buried therein. In this step, the barrier metal 104 and copper are also formed on the bonding surface of the insulating film 221.

[0745] In step S533, the electrode 105 and the barrier metal 104 on the top surface of the insulating film 221 are removed by CMP. The copper (electrode 105) buried in the connection hole 121 in this step has a concave shape due to the concavity.

[0746] In step S534, a porous metal 881 is formed. The porous metal 881 is formed by performing electroless plating (Cu—Ni—P) on Cu used as the electrode 105, for example.

[0747] Through the above steps, a Figure 88 The porous metal 881 electrode is shown.

[0748] <Fourth Example of Manufacturing According to Embodiment 22-1>

[0749] Will refer to Figure 93 Description Figure 88 A fourth example of the fabrication of a pixel 12x is shown with the configuration of the electrode 105 .

[0750] In step S541, a semiconductor substrate is prepared, wherein the semiconductor substrate is prepared by performing steps S531 to S533 ( Figure 92 ) to form an electrode 105 having a concave shape.

[0751] In step S542, a metal 885 is formed (by plating) on ​​the electrode 105. For example, Ag is used as the metal 885, and Ag is formed by chemical plating.

[0752] In step S543, porous metal 881 is formed. For example, with respect to Ag formed on electrode 105, atmospheric pressure plasma in which H2 is diluted with He or Ar is generated, and the Ag surface is modified to form pores.

[0753] Through the above steps, a Figure 88 The porous metal 881 electrode is shown.

[0754] <Implementation Plan 22-2>

[0755] Figure 94 2 is a diagram showing a configuration example of a pixel 12x' according to Embodiment 22-2 to which the present technology is applied. Figure 94 The pixel 12x' and the pixel 12x' according to the embodiment 22-2 are shown Figure 88The same parts among the pixels 12x according to the embodiment 22-1 are given the same reference numerals, and description thereof is appropriately omitted.

[0756] Figure 94 The electrode formed in the pixel 12x' shown in A is configured by forming a porous metal 881 as the electrode 105 in the insulating film 221. In the electrode formed in the joint portion, the connection hole 121 is provided in the insulating film 221, and the barrier metal 104 is formed on the side and bottom surfaces of the connection hole 121. The porous metal 881 is formed at the portion where the electrode 105 is formed in Embodiment 22-1, and the porous metal 881 serves as the electrode.

[0757] Figure 94 The electrode formed in the pixel 12x' shown in FIG. B is configured by forming a porous metal 881 as the electrode 105 in the insulating film 221 and forming an insulating film 887 between the laminated film 100 and the porous metal 881. The insulating film 887 is provided to suppress film formation from the sidewalls of the connection hole 121 and to improve the embedding property of the porous metal 881.

[0758] <Manufacturing according to embodiment 22-2>

[0759] Will refer to Figure 95 Description Figure 94 The pixel 12x' is manufactured by the electrode 105 shown in FIG. Figure 95 The fabrication of a portion of porous metal 881 used as an electrode is described.

[0760] In step S551, the connection hole 121 is formed in the insulating film 221. In step S552, the barrier metal 104 is formed in the connection hole 121, and an alloy 882 serving as the porous metal 881 is embedded (formed) therein. As the alloy 882, for example, an alloy of Cu and Zn is used.

[0761] In step S553, the alloy 882 and the barrier metal 104 on the top surface of the insulating film 221 are removed by CMP. In this step, the alloy 882 is processed to be convex and extends to a position higher than the bonding surface of the insulating film 221.

[0762] In step S554, porous metal 881 is formed. For example, if an alloy of Cu and Zn is used for alloy 882, pores are formed by etching the Zn. For example, porous metal 881 is formed by etching in a copper sulfate plating solution using an azole additive. The porous metal is formed by electrochemical etching (Cu-Zn→Zn) in hydrochloric acid.

[0763] As in Embodiment 22-1, the porous metal 881 has a porosity of about 10% to 50%. The depth of the porous portion (the length from the highest point of the porous metal 881 to the insulating film 221) is about several hundred nm, which is at least the depth of the connection hole 121.

[0764] The porous metal 881 is formed into a convex shape, as shown in the depiction of step S554. Due to the convex shape, the porous metal can collapse during the bonding process, thereby reliably connecting to other porous metals or electrodes. Therefore, it is preferred that the porous metal 881 has a strength that satisfies the following relationship:

[0765] Yield stress (platform stress) during compression < stress applied during bonding

[0766] Through the above steps, a Figure 94 A shows the porous metal electrode 881.

[0767] <Manufacturing according to embodiment 22-2>

[0768] Will refer to Figure 96 Description Figure 94 The manufacturing of the pixel 12x' composed of the porous metal 881 shown in B will refer to Figure 96 The manufacture of a portion of porous metal 881 is described.

[0769] In step S561, the connection hole 121 is formed in the insulating film 221. In step S562, the barrier metal 104 is formed on the interface between the connection hole 121 and the insulating film 221. In step S563, the insulating film 887 is formed on the barrier metal 104.

[0770] In step S564, the barrier metal 104 and the insulating film 887 are polished and planarized. In this step, the barrier metal 104 and the insulating film 887 on the top surface of the insulating film 221 are removed by CMP.

[0771] In step S565, an alloy 882 serving as the porous metal 881 is embedded (formed) therein. As the alloy 882, for example, an alloy of Cu and Zn is used.

[0772] In step S566, the alloy 882 on the top surface of the insulating film 221 is removed by CMP. In this step, the alloy 882 is processed to be convex and extends to a position higher than the bonding surface of the insulating film 221.

[0773] In step S567, porous metal 881 is formed. For example, if an alloy of Cu and Zn is used for alloy 882, pores are formed by etching Zn. The processing in step S567 can be performed as a similar process to step S554 ( Figure 95 ) steps to execute.

[0774] Through the above steps, a Figure 94 B shows the porous metal electrode 881.

[0775] <Application examples of electronic equipment>

[0776] This technology is widely applicable to electronic devices that use image sensors in their imaging units (photoelectric conversion units), including imaging devices such as digital cameras and video cameras, mobile terminal devices with imaging functions, and copiers that use image sensors in their image reading units. Image sensors can be formed as a single chip or as a module with imaging functions, in which the imaging unit and signal processing unit or optical system are packaged together.

[0777] Figure 97 This is a block diagram showing a configuration example of an imaging device used as an electronic device to which the present technology is applied.

[0778] Figure 97 The image sensor 1000 in FIG. 1 includes an optical unit 1001 composed of a lens group and the like, an imaging element (imaging device) 1002, and a digital signal processor (DSP) circuit 1003 serving as a camera signal processing circuit. The image sensor 1000 also includes a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to one another via a bus 1009.

[0779] The optical unit 1001 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 1002. The imaging element 1002 converts the amount of incident light that forms an image on the imaging surface through the optical unit 1001 into an electrical signal on a pixel basis and outputs the electrical signal as a pixel signal.

[0780] The display unit 1005 includes a thin display such as a liquid crystal display (LCD) or an organic electroluminescence (EL) display, and displays a moving image or a still image captured by the imaging element 1002. The recording unit 1006 records the moving image or the still image captured by the imaging element 1002 in a recording medium such as a hard disk or a semiconductor memory.

[0781] The operation unit 1007 issues operation commands for various functions of the image sensor 1000 in response to user operations. The power supply unit 1008 supplies various types of power used as operation power sources for the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007 to these units as appropriate.

[0782] The image sensor 1 including the pixels 12 according to the embodiments 1 to 19 can be applied to Figure 97 A portion of the imaging device is shown.

[0783] <Application examples of endoscopic surgery systems>

[0784] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0785] Figure 98 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0786] exist Figure 98 , a state is shown in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy instrument 11112, a support arm device 11120 on which the endoscope 11100 is supported, and a cart 11200 on which various instruments used for endoscopic surgery are mounted.

[0787] Endoscope 11100 includes a lens barrel 11101 having an area of ​​a predetermined length from its distal end to be inserted into a body cavity of a patient 11132, and a camera 11102 connected to the proximal end of lens barrel 11101. In the example shown in the drawings, endoscope 11100 including a hard scope including rigid lens barrel 11101 is shown. However, endoscope 11100 may also include a soft scope including flexible lens barrel 11101.

[0788] The lens barrel 11101 has an opening at its distal end into which the objective lens is fitted. A light source device 11203 is connected to the endoscope 11100 so that light generated by the light source device 11203 is guided to the distal end of the lens barrel via a light guide extending inside the lens barrel 11101 and irradiated toward an observation object in the body cavity of the patient 11132 via the objective lens. Note that the endoscope 11100 may be a straight-view endoscope, or may be an oblique endoscope or a side-view endoscope.

[0789] The camera head 11102 is equipped with an optical system and an imaging element. Light reflected from the observation object (observation light) is focused onto the imaging element through the optical system. The imaging element performs photoelectric conversion on the observation light to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0790] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), and the like, and comprehensively controls the operations of the endoscope 11100 and the display device 11202. In addition, for example, the CCU 11201 receives an image signal from the camera 11102 and performs various types of image processing such as development processing (demosaic processing) to display an image based on the image signal.

[0791] The display device 11202 displays thereon an image based on an image signal on which image processing has been performed by the CCU 11201 under the control of the CCU 11201 .

[0792] For example, the light source device 11203 includes a light source such as a light emitting diode (LED), and supplies irradiation light used when imaging a surgical area to the endoscope 11100 .

[0793] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various types of information or instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (such as the type of irradiation light, magnification, and focal length) of the endoscope 11100.

[0794] The treatment instrument control device 11205 controls the driving of the energy device 11112 for purposes such as cauterization or incision of tissue and sealing of blood vessels. The pneumoperitoneum device 11206 injects gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to inflate the cavity, ensuring the field of view of the endoscope 11100 and ensuring the operator's working space. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats, such as text, images, and graphics.

[0795] Note that, for example, the irradiation light supplied to the light source device 11203 of the endoscope 11100 when photographing the surgical area may include a white light source such as an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance adjustment of the captured image can be performed by the light source device 11203. In addition, in this case, if the laser light from each RGB laser light source is emitted onto the observed object in a time-division manner and the drive of the imaging element of the camera 11102 is controlled in synchronization with the emission timing. Images corresponding to the RGB colors can be captured in a time-division manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0796] Furthermore, the light source device 11203 can be controlled so that the intensity of the light to be output is changed between each predetermined timing. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity to acquire and synthesize images in a time-division manner, it is possible to generate a high dynamic range image without underexposed shadows or overexposed highlights.

[0797] In addition, the light source device 11203 can supply light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by using the wavelength dependence of light absorption in body tissue to emit light having a narrow band compared to the irradiation light (i.e., white light) during ordinary observation, narrow-band observation (narrow-band imaging) is performed to capture predetermined tissues such as blood vessels on the surface of the mucosa with high contrast. In addition, in special light observation, fluorescence observation is performed to obtain an image by fluorescence generated by emitting excitation light. In fluorescence observation, for example, it is possible to irradiate body tissue with excitation light to observe fluorescence from the body tissue (autofluorescence observation), or it is possible to locally inject a reagent such as indocyanine green (ICG) into the body tissue and emit excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 can supply narrow-band light and / or excitation light suitable for the above-mentioned special light observation.

[0798] Figure 99 It shows Figure 98 A block diagram showing an example of the functional configuration of the camera 11102 and the CCU 11201 is shown.

[0799] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 for communication with each other.

[0800] The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light received from the distal end of the lens barrel 11101 is guided to the camera 11102 and incident on the lens unit 11401. The lens unit 11401 includes a combination of multiple lenses including a zoom lens and a focus lens.

[0801] The number of imaging elements included in the imaging unit 11402 can be one (single-board type) or multiple (multi-board type). When the imaging unit 11402 is constructed as a multi-board type, for example, image signals corresponding to each RGB are generated by the imaging element, and a color image can be obtained by synthesizing the image signals. Alternatively, the imaging unit 11402 can also be constructed to have a pair of imaging elements for acquiring image signals for the right eye and the left eye for three-dimensional (3D) display. If a 3D display is performed, the operator 11131 can more accurately grasp the depth of the body tissue in the surgical site. Note that when the imaging unit 11402 is constructed as a multi-board type, a plurality of lens units 11401 are provided corresponding to the respective imaging elements.

[0802] In addition, the imaging portion 11402 does not necessarily have to be provided on the camera head 11102. For example, the imaging portion 11402 may be provided just behind the objective lens inside the lens barrel 11101.

[0803] The driving section 11403 includes an actuator and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control section 11405. Therefore, the magnification and focus of the image captured by the imaging section 11402 can be appropriately adjusted.

[0804] The communication section 11404 includes a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication section 11404 transmits the image signal acquired from the imaging section 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0805] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. The control signal includes information related to imaging conditions, for example, information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and / or information specifying the magnification and focus of the captured image.

[0806] Note that imaging conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user or may be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are incorporated into the endoscope 11100.

[0807] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 via the communication unit 11404 .

[0808] The communication section 11411 includes a communication device for transmitting and receiving various types of information to and from the camera 11102. The communication section 11411 receives an image signal transmitted from the camera 11102 via the transmission cable 11400.

[0809] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0810] The image processing unit 11412 performs various types of image processing on the image signal in the RAW data format transmitted from the camera 11102 .

[0811] The control unit 11413 performs various types of control related to imaging of the surgical area, etc., performed by the endoscope 11100 and display of captured images obtained by imaging the surgical area, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera 11102 .

[0812] Furthermore, the control unit 11413 controls the display device 11202 to display a captured image of the surgical area, etc., based on the image signal processed by the image processing unit 11412. In this case, the control unit 11413 can use various image recognition technologies to identify various objects within the captured image. For example, the control unit 11413 can detect the edge shape and / or color of objects within the captured image to identify surgical instruments such as forceps, specific living body parts, bleeding, and fog when using the energy device 11112. When controlling the display device 11202 to display the captured image, the control unit 11413 can use the recognition results to cause the display device 11202 to display various types of surgical support information superimposed on the image of the surgical area. When this superimposed surgical support information is displayed and presented to the operator 11131, the burden on the operator 11131 can be reduced, allowing the operator 11131 to perform the surgery reliably.

[0813] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable for both electrical signals and optical communication.

[0814] Here, in the example shown in the drawing, communication is performed by wired communication using the transmission cable 11400, but communication between the camera 11102 and the CCU 11201 may be performed by wireless communication.

[0815] <Application examples for mobile objects>

[0816] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device to be installed on any type of mobile object such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, robot, etc.

[0817] Figure 100 This is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology according to the embodiment of the present disclosure can be applied.

[0818] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 100 In the illustrated example, vehicle control system 12000 includes a drive system control unit 12010, a main body system control unit 12020, an external vehicle information detection unit 12030, an internal vehicle information detection unit 12040, and an integrated control unit 12050. Furthermore, as functional components of integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0819] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates the vehicle's drive force, a drive force transmission mechanism that transmits the drive force to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates braking force for the vehicle.

[0820] The main system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the main system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, instead of pressing buttons, radio waves or signals from various switches transmitted from a portable device can be input to the main system control unit 12020. The main system control unit 12020 receives the input of radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0821] The vehicle exterior information detection unit 12030 detects information related to the exterior of the vehicle, including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can detect objects such as people, cars, obstacles, signs, and text on the road, or measure the distance to such objects.

[0822] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as information related to the measured distance. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0823] The in-vehicle information detection unit 12040 detects information related to the vehicle interior. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's condition. For example, the driver state detection unit 12041 includes a camera that captures an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or determine whether the driver has fallen asleep while sitting.

[0824] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on information related to the interior and exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output control instructions to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation, following driving based on a following distance, speed maintenance driving, collision warning, lane departure warning, and the like.

[0825] In addition, the microcomputer 12051 can coordinate control by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, so as to achieve automatic driving in which the vehicle travels autonomously without relying on the driver's operation.

[0826] In addition, the microcomputer 12051 can output control instructions to the main system control unit 12020 based on information related to the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlights based on the positions of the preceding vehicle or oncoming vehicles detected by the exterior information detection unit 12030 to perform coordinated control to achieve glare prevention, such as switching the high beam to the low beam.

[0827] The sound / image output unit 12052 transmits at least one of a sound and an image output signal to an output device capable of visually or auditorily notifying a vehicle occupant or information outside the vehicle. Figure 100 In the example of FIG, as output devices, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0828] Figure 101 This is a diagram showing an example of the installation position of the imaging unit 12031.

[0829] exist Figure 101 , the imaging unit 12031 includes imaging units 12101 , 12102 , 12103 , 12104 and 12105 .

[0830] Imaging units 12101, 12102, 12103, 12104, and 12105 are located, for example, at the front of the vehicle, in the sideview mirrors, rear bumper, and rear doors, as well as on the upper side of the windshield inside the vehicle. Imaging unit 12101 located in the front of the vehicle and imaging unit 12105 located on the upper side of the windshield inside the vehicle primarily capture images of the front of the vehicle 12100. Imaging units 12102 and 12103 located in the sideview mirrors primarily capture images of the sides of the vehicle 12100. Imaging unit 12104 located in the rear bumper or rear door primarily captures images of the rear of the vehicle 12100. Imaging unit 12105 located on the upper side of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0831] By the way, Figure 101Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, located at the front of the vehicle. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located at the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, located at the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 can be obtained.

[0832] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0833] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 can determine the distance to each 3D object within imaging ranges 12111-12114 and the temporal change in that distance (relative speed to vehicle 12100), thereby extracting the 3D object located on the travel path of vehicle 12100, particularly the closest 3D object, traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher), as the leading vehicle. Furthermore, microcomputer 12051 can set a predetermined distance between vehicles in front of the leading vehicle and perform automatic braking control (including tracking stop control) and automatic acceleration control (including tracking start control). This enables coordinated control such as autonomous driving, which allows the vehicle to travel autonomously without relying on driver input.

[0834] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 can classify 3D object data into data for two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other objects, extract the classified 3D object data, and use the extracted 3D object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as those that are visually recognizable by the driver of vehicle 12100 and those that are difficult for the driver to visually recognize. Microcomputer 12051 then determines a collision risk, indicating the degree of risk of collision with each obstacle. When the collision risk is equal to or greater than a set value and the possibility of a collision exists, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 and display unit 12062 or initiates forced deceleration or evasive steering via drive system control unit 12010. Microcomputer 12051 can assist in driving to avoid collisions.

[0835] At least one of the imaging units 12101-12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101-12104. For example, pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101-12104, which are infrared cameras, and performing pattern matching on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101-12104 and thus identifies the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to display a quadrilateral outline superimposed on the identified pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon indicating the pedestrian at a desired location.

[0836] The system used here refers to an entire apparatus composed of a plurality of apparatuses.

[0837] The effects described herein are merely examples and are not intended to be limiting, and other effects may also be achieved.

[0838] The embodiment of the present technology is not limited to the above-described embodiment, and various changes can be made within the scope of the present technology without departing from the basic spirit of the present technology.

[0839] The present technology can also be configured as follows.

[0840] (1) A semiconductor substrate comprising:

[0841] Insulating film;

[0842] an electrode provided in the insulating film, wherein when the semiconductor substrate is attached to another semiconductor substrate, the electrode is bonded to an electrode provided on the other semiconductor substrate;

[0843] A barrier metal provided between the insulating film and the electrode; and

[0844] A film provided between the barrier metal and the electrode.

[0845] (2) The semiconductor substrate according to (1),

[0846] Here, a first adhesion strength when a first material constituting the electrode and a second material constituting the film adhere to each other is smaller than a second adhesion strength when the first material and a third material constituting the barrier metal adhere to each other.

[0847] (3) The semiconductor substrate according to (2),

[0848] The first material is copper, and the second material is any one of indium tin oxide (ITO), SiO2 formed by plasma deposition, or SiO formed by atomic layer deposition (ALD).

[0849] (4) The semiconductor substrate according to (1),

[0850] The material constituting the film has a friction coefficient smaller than that of the material constituting the electrode.

[0851] (5) The semiconductor substrate according to (4),

[0852] The film is any one of carbon, molybdenum disulfide, tungsten disulfide, tungsten selenide, hafnium sulfide, boron nitride or a composition with carbon as the main component, and the composition includes graphite, graphene, fullerene, carbon nanotube, diamond-like carbon or diamond.

[0853] (6) The semiconductor substrate according to (4),

[0854] The friction coefficient of the film is less than 0.2 (μ).

[0855] (7) The semiconductor substrate according to (1),

[0856] Here, the material constituting the film has a higher potential than the material constituting the electrode.

[0857] (8) The semiconductor substrate according to (7),

[0858] The material constituting the film is any one of graphite, platinum, zirconium, titanium, silver, nickel, or alloys containing the same as main components.

[0859] (9) The semiconductor substrate according to (1),

[0860] The film is formed of a material having a thermal expansion coefficient greater than that of a material forming the electrode.

[0861] (10) The semiconductor substrate according to (9),

[0862] The material constituting the film is any one of resin, metal or insulating material.

[0863] (11) The semiconductor substrate according to (9),

[0864] The material constituting the film is any one of polyimide, epoxy resin, fluororesin, aluminum, tin, zinc, lead, magnesium, solder, lithium titanium oxide (LTO), or low-k material.

[0865] (12) The semiconductor substrate according to (1),

[0866] The film is provided on the side wall of the electrode and is formed of a material that hinders the growth of the copper plating layer.

[0867] (13) The semiconductor substrate according to (12),

[0868] The material constituting the film is any one of SiO2, Ta2O5, TiO2, SiN, SiCN or SiOF.

[0869] (14) The semiconductor substrate according to (12),

[0870] Wherein, the side wall of the electrode is formed in an inverted cone shape.

[0871] (15) The semiconductor substrate according to any one of (1) to (14),

[0872] The material constituting the electrode is copper and at least the outermost surface of the electrode is a (111) surface.

[0873] (16) The semiconductor substrate according to any one of (1) to (15),

[0874] The membrane is arranged on a side surface of the electrode.

[0875] (17) The semiconductor substrate according to any one of (1) to (15),

[0876] Wherein, the membrane is arranged on the side surface and the bottom surface of the electrode.

[0877] (18) A semiconductor substrate comprising:

[0878] Insulating film;

[0879] an electrode provided in the insulating film, wherein when the semiconductor substrate is attached to another semiconductor substrate, the electrode is bonded to an electrode provided on the other semiconductor substrate;

[0880] a barrier metal disposed between the insulating film and the electrode;

[0881] The inclination of the barrier metal disposed on one side wall of the electrode is different from the inclination of the barrier metal disposed on the other side walls of the electrode.

[0882] (19) The semiconductor substrate according to (18),

[0883] The material constituting the electrode is copper and at least the outermost surface of the electrode is a (111) surface.

[0884] [Reference Signs List]

[0885] 1 Imaging device

[0886] 11. First substrate

[0887] 12 pixels

[0888] 13-pixel area

[0889] 14 pixel drive lines

[0890] 15 vertical signal lines

[0891] 21 Second substrate

[0892] 22 Vertical drive circuit

[0893] 23 columns of signal processing circuits

[0894] 24 Horizontal drive circuit

[0895] 25 System control circuit

[0896] 30 first semiconductor substrate

[0897] 31 First wiring layer

[0898] 32 Second wiring layer

[0899] 33 Si substrate

[0900] 34 transistors

[0901] 35 Photoelectric conversion layer

[0902] 36 Color Filters

[0903] 37 Microlenses

[0904] 38 Insulation film

[0905] 39 interlayer insulating film

[0906] 40 second semiconductor substrate

[0907] 41 Diffusion prevention film

[0908] 42 Diffusion prevention film

[0909] 43 interlayer insulating film

[0910] 54 first electrode pad

[0911] 55 dummy electrode

[0912] 57 second electrode pad

[0913] 58 dummy electrodes

[0914] 81 reaction membrane

[0915] 100 laminated film

[0916] 101 interlayer insulating film

[0917] 102 pad insulation film

[0918] 103 interlayer insulating film

[0919] 104 Barrier Metal

[0920] 105 electrodes

[0921] 107 Barrier Metal

[0922] 108 dummy electrodes

[0923] 121 connection hole

[0924] 122 wiring holes

[0925] 123 connection hole

[0926] 131 Expansion Barrier Suppression Film

[0927] 221 Insulation Film

[0928] 261 vias

[0929] 301 Groove

[0930] 381 reaction membrane

[0931] 500 Insulation Film

[0932] 511 expansion auxiliary film

[0933] 512 interlayer film

[0934] 551 oxide film

[0935] 601(111) area

[0936] 602 Random Area

[0937] 621 Cu seed crystal

[0938] 622 Coated barrier film

[0939] 631 sidewall area

[0940] 641, 661 resist pattern

[0941] 663 Plasma Film

[0942] 723 Insulation Film

Claims

1. A semiconductor substrate, comprising: Insulating film; an electrode provided in the insulating film, wherein when the semiconductor substrate is attached to another semiconductor substrate, the electrode is bonded to an electrode provided on the other semiconductor substrate; a barrier metal disposed between the insulating film and the electrode; and A film provided between the barrier metal and the electrode.

2. The semiconductor substrate according to claim 1, in, A first adhesion strength when a first material constituting the electrode and a second material constituting the film adhere is smaller than a second adhesion strength when the first material and a third material constituting the barrier metal adhere.

3. The semiconductor substrate according to claim 2, in, The first material is copper, and the second material is any one of indium tin oxide (ITO), SiO 2 formed by plasma deposition, or SiO formed by atomic layer deposition (ALD).

4. The semiconductor substrate according to claim 1, in, The material constituting the film is a material having a friction coefficient smaller than that of the material constituting the electrode.

5. The semiconductor substrate according to claim 4, in, The film is any one of carbon, molybdenum disulfide, tungsten disulfide, tungsten selenide, hafnium sulfide, boron nitride, or a composition with carbon as a main component, and the composition includes graphite, graphene, fullerene, carbon nanotube, diamond-like carbon, or diamond. The semiconductor substrate according to claim 4 . in, The friction coefficient of the film is 0.2 (μ) or less.

7. The semiconductor substrate according to claim 1, in, The material constituting the film is a material having a higher potential than that of the material constituting the electrode.

8. The semiconductor substrate according to claim 7, in, The material constituting the film is any one of graphite, platinum, zirconium, titanium, silver, nickel, or an alloy containing these as main components.

9. The semiconductor substrate according to claim 1, in, The material constituting the film is a material having a thermal expansion coefficient greater than that of the material constituting the electrode.

10. The semiconductor substrate according to claim 9, in, The material constituting the film is any one of resin, metal, and insulating material.

11. The semiconductor substrate according to claim 9, in, The material constituting the film is any one of polyimide, epoxy resin, fluororesin, aluminum, tin, zinc, lead, magnesium, solder, lithium titanium oxide (LTO), or a low-k material.

12. The semiconductor substrate according to claim 1, in, The film is provided on a side wall of the electrode and is formed of a material that hinders growth of a plating layer of the copper.

13. The semiconductor substrate according to claim 12, in, The material constituting the film is any one of SiO2, Ta2O5, TiO2, SiN, SiCN or SiOF.

14. The semiconductor substrate according to claim 12, in, The sidewall of the electrode is formed in an inverted tapered shape.

15. The semiconductor substrate according to claim 1, in, The material constituting the electrode is copper and at least the outermost surface of the electrode is a (111) surface.

16. The semiconductor substrate according to claim 1, in, The membrane is disposed on a side of the electrode.

17. The semiconductor substrate according to claim 1, in, The membrane is provided on the side surfaces and the bottom surface of the electrode.

18. A semiconductor substrate, comprising: Insulating film; an electrode provided in the insulating film, wherein when the semiconductor substrate is attached to another semiconductor substrate, the electrode is bonded to an electrode provided on the other semiconductor substrate; a barrier metal disposed between the insulating film and the electrode; The inclination of the barrier metal disposed on one side wall of the electrode is different from the inclination of the barrier metal disposed on the other side walls of the electrode.

19. The semiconductor substrate according to claim 18, in, The material constituting the electrode is copper and at least the outermost surface of the electrode is a (111) surface.

Images