Semiconductor element having bonding layer with functional and non-functional conductive pads

Abstract

A semiconductor element is disclosed having an interconnect bonding layer with a functional metal contact pad and a non-functional metal contact pad surrounded by a dielectric material in the interconnect bonding layer. A functional metal contact pad is exposed to the bonding surface and connected to the buried metal layer. The non-functional metal contact pads are distributed in areas where no functional metal contact pads or fewer functional metal contact pads are present, and are exposed to the bonding surface, and terminate at a partial depth of the functional metal contact pads. Each of the functional metal contact pad and the non-functional metal contact pad is formed by a single damascene process involving an etch step.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit under 35 U.S.C. § 119(e)(1) of U.S. Provisional Application No. 63 / 477,551, filed December 28, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The field relates to microelectronics having functional and non-functional conductive (eg, metal) pads in a bonding layer. Background Art

[0004] Over the past few decades, the semiconductor industry has experienced tremendous growth as engineers have developed chips with smaller and smaller transistors integrated onto them, just as Moore's Law correctly predicted. However, the industry is realizing that efforts to reduce the size of transistors on silicon chips are approaching physical limits. At the same time, consumer electronics, including computers and smartphones, continue to become increasingly complex, requiring the efficient use of large numbers of transistors. One way to increase three-dimensional (3D) integration is to stack chips or wafers on top of each other to form 3D integrated structures. Direct hybrid bonding enables higher density interconnections between stacked components. However, direct bonding between semiconductor components utilizes planarized bonding surfaces that have tight flatness tolerances, which can pose challenges. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The detailed description will now be described with reference to the following figures, which are provided by way of example and not limitation.

[0006] Figure 1 is a schematic cross-sectional view of a semiconductor component having at least one functional metal pad and at least one dummy metal pad embedded in a bonding layer, wherein the at least one functional metal pad is formed by a dual damascene process.

[0007] Figure 2 is a schematic cross-sectional view illustrating an embodiment of a semiconductor component having at least one functional metal pad and at least one dummy metal pad embedded in a bonding layer, wherein each of the at least one functional metal pad and the at least one dummy metal pad is formed by a single damascene process.

[0008] Figure 3is a schematic cross-sectional view of another embodiment of the present disclosure illustrating a semiconductor element having at least one functional metal pad and at least one dummy metal pad embedded in a bonding layer, wherein each of the at least one functional metal pad and the at least one dummy metal pad is formed by a single damascene process.

[0009] Figures 4-10 The diagram shows the preparation Figure 3 Schematic cross-sectional view of an example process of embedding functional metal pads and dummy metal pads in a bonding layer as shown in FIG.

[0010] Figure 11A and Figure 11B is a schematic cross-sectional view illustrating an example conductive pad fabricated by employing a dual damascene process.

[0011] Figure 11C and Figure 11D is a schematic cross-sectional view illustrating an example conductive pad fabricated by employing a single damascene process according to various embodiments disclosed herein.

[0012] Figure 12-13 The diagram shows the preparation Figure 2 An example process schematic cross-sectional view of functional metal pads and dummy metal pads embedded in a bonding layer is shown in FIG.

[0013] Figure 14 is a schematic cross-sectional view of two microelectronic elements configured to be bonded together.

[0014] Figure 15 is included Figure 14 Schematic cross-sectional view of a bonding structure of two microelectronic components bonded together. DETAILED DESCRIPTION

[0015] When forming a bonding layer above a semiconductor element, the conductive contact pads are embedded in a non-conductive layer (e.g., a dielectric layer). A chemical mechanical process (CMP) is performed to remove excess material from the dielectric layer, thereby flattening the surface. The semiconductor can be prepared to be directly bonded to another semiconductor element or device without an intermediate adhesive. Due to the thermal expansion mismatch between the metal and dielectric material used, thin film processes may generate stress in the bonding layer, such as metal traces under tension and dielectric materials under compression. Such stress may cause deformation and / or warping in semiconductor elements (e.g., device dies or chips, wafers, or passive devices). Therefore, there is a continuing need to reduce stress in the bonding layer and deformation of semiconductor elements.

[0016] To reduce stress and deformation in the bonding layer caused by thermal expansion mismatches between the metal and dielectric materials, in various embodiments, electrically non-functional (or dummy) metal pads can be embedded within the non-conductive dielectric material of the bonding layer in areas with few or no functional metal pads. This can be done to achieve a more uniform distribution of the metal pads (including both functional and non-functional metal pads) within the dielectric material. A thermal expansion mismatch between two mixed materials can result in one material being under tension and the other under compression. The thermal expansion coefficient of metals (e.g., copper) is typically greater than that of dielectric materials (e.g., silicon oxide). Therefore, during deposition or annealing processes (or other processes using high temperatures), when a semiconductor component cools from a high temperature, the metal contracts more than the dielectric. Because the two materials are placed side by side, the metal may be under tension while the dielectric may be under compression. However, if the two materials are evenly distributed relative to each other, the expansion of one material can be absorbed or offset by the contraction of the other. This can reduce or control both tensile and compressive stresses. Therefore, distributing the metal pads uniformly or nearly uniformly in the dielectric material helps to relieve stress caused by thermal expansion mismatch and reduce deformation.

[0017] In various embodiments, electrically non-functional or dummy metal pads in an interconnect layer or bonding layer can be shallower than electrically functional or active pads. If the non-functional metal pads extend to a greater depth (e.g., the same depth as the functional pads), the dummy pads may short-circuit buried metal traces in the interconnect layer below the dummy pads.

[0018] Conventionally, functional metal pads in a dielectric layer may be formed by a dual damascene process. Figure 1 1 shows a schematic cross-sectional view of a semiconductor component 100 having a device layer or device portion 102 and an interconnect structure 103 provided on the device layer (also referred to herein as the device portion) 102. As explained herein, in various embodiments, the interconnect structure 103 may include a plurality of non-conductive layers (e.g., Figure 1The first dielectric layer 104 and the second dielectric layer 106 may be formed of the same material or different materials. Although the interconnect structure 103 includes two dielectric layers 104 and 106, in other embodiments, more or fewer dielectric layers may be provided. The metal layer 108 is buried in the second dielectric layer 104 and is connected to the circuit device 101 patterned or otherwise provided in the device layer 102 through vias 105 or other conductors (e.g., other traces and / or vias). One end of the plurality of vias 110 is connected to the metal layer 108 (e.g., a trace) and the other end is connected to the functional metal pad 112 in the second dielectric layer 106. The plurality of vias 110 may be made of copper, tungsten, or polysilicon. Functional metal pads 112 may be exposed at a surface 116 of dielectric material 106. Non-functional or dummy metal pads 114 are also exposed at surface 116 of dielectric material 106 and extend into a partial depth of dielectric material 106 and terminate before reaching the underlying interconnect metal layer 108. Non-functional metal pads 114 are distributed in areas where there are no functional metal pads 112 or where there are fewer functional metal pads 112.

[0019] A dual damascene process can be used to Figure 1 Functional metal pads 112 and vias 110 are formed in the dielectric layer 106 in the second dielectric layer 106. The dual damascene process can be performed by a two-step etching method (e.g., a via-first process to form narrower holes 110a in the second dielectric layer 106; followed by a trench formation process to form trenches 112a that are wider than those holes. In the via-first method, holes 110a with finer pitch and higher aspect ratio extend through the second dielectric material 106, such as Figure 1 , as a hole for via 110. This process is generally more challenging than the subsequent trench formation process. The more expensive mask used for patterning makes the dual damascene process more complicated than the single damascene process. On the other hand, the trench process is used to form metal contact pads with larger sizes, such as Figure 1 As shown in FIG, for example, electrically functional or active pads 112 and electrically inactive or non-functional pads 114 (also referred to herein as dummy pads) are formed. Thus, the trench formation process is typically simpler than the via formation process. Another disadvantage of utilizing narrower via structures 110 is that they are typically associated with higher resistance due to their smaller cross-sectional dimensions.

[0020] Figure 1 One characteristic of the dual damascene process shown in FIG is that the functional contact pad 112 and the via hole 110 have two-step discontinuous sidewall structures due to the two-step etching process. Figure 1 As shown in FIG, the corners 118 and 120 between the functional pad 112 portion and the via 110 portion reveal this. In actual practice, these corners may not be as Figure 1 However, the stepped or cornered connection between the via 110 and the functional pad 112 is a sidewall discontinuity that results in a jagged and / or incomplete sidewall.

[0021] Therefore, there is a motivation to replace the relatively complex dual damascene process using expensive masks with a simpler fabrication process. The single damascene process can reduce process costs and simplify fabrication. Figure 2 is a schematic cross-sectional view of an example embodiment of the present disclosure. Figure 2 , an interconnect structure or layer 203 is placed on a microelectronic device layer or device portion 202. The interconnect structure 203 includes a second non-conductive or dielectric layer 206, which forms or includes a bonding layer for the semiconductor element 200, and a first non-conductive or dielectric layer 204 having a conductive layer or bottom layer interconnect 208 buried therein. The conductive layer 208 may be an interconnect metal layer for further connection to external devices or components. The device layer 202 may include a semiconductor device portion patterned with a device (e.g., Figure 2 ). In other embodiments, device layer 202 may include portions of an interposer or other electronic device, with or without active devices. Device layer 202 may include wafers, integrated device dies or chips (e.g., complementary metal oxide semiconductor (CMOS) chips), passive devices, and the like.

[0022] Conductive (e.g., metal) layer 208 can be buried or embedded in dielectric layer 204 near device layer 202. In some embodiments, interconnect metal layer 208 can be the outermost layer of device layer 202. For example, metal layer 208 can be formed in a dielectric layer provided above the semiconductor portion of device layer 202 during a back-end-of-line (BEOL) process. In some embodiments, metal layer 208 can be a redistribution layer (RDL) provided before depositing second dielectric layer 206. In some embodiments, metal layer 208 can be in electrical communication with one or more devices in device layer 202. For example, it can be electrically connected to active circuit devices 201 in device layer 202 through vias 205. At least one functional or active metal pad 212 and at least one non-functional metal pad 214 can be partially embedded in second dielectric layer 206. Functional or active metal pad 212 extends from top surface 216 through at least a portion of second dielectric layer 206 to connect to (e.g., contact) buried metal layer 208, while non-functional metal pad 214 extends from top surface 216 and terminates at a shallower location than functional metal pad 212. Metal contact pads 212, 214 can take different cross-sectional shapes and sizes, e.g., width or diameter as viewed from top surface 216, e.g., squares, triangles, circles, polygons, etc. of different sizes. In some embodiments, functional metal pad 212 can have the same first shape and the same first size, while non-functional metal pad 214 can have the same second shape and the same second size. In some embodiments, functional metal pad 212 and non-functional metal pad 214 can have the same shape and the same size. In other embodiments, functional metal pad 212 and non-functional metal pad 214 can have different shapes and / or different sizes. As Figure 2 As can be seen in FIG, the depth D of the non-functional metal pad 214 2a than the depth D of the functional metal pad 212 2b As such, the non-functional pad 214 terminates above the buried metal layer 208 and is not in contact with or electrically connected to the buried metal layer 208. In this manner, the non-functional metal pad 214 does not short-circuit the metal traces of the conductive metal layer 208. Thus, in various embodiments, the non-functional pad 214 (as well as the functional pad 212) can be placed vertically above the conductive metal layer 208, with the functional pad connected to the metal layer 208 and the non-functional pad 214 not connected to the metal layer 208.

[0023] Thus, in various embodiments disclosed herein, the functional conductive pads 212 can be electrically connected to an electrically functional component of the semiconductor element 200, such as a trace (e.g., buried metal layer 208), which in turn is connected to a device (e.g., circuit arrangement 201) or any other suitable electrically functional component (e.g., an interconnect in an interposer, a passive device, or any other suitable functional component). The dummy pads or non-functional pads 214 can be electrically inactive, such that the dummy pads or electrically non-functional pads 214 are electrically isolated within the semiconductor element 200 (e.g., the dummy pads 214 are not electrically connected to a functional component or circuit in the semiconductor element 200). As described herein in conjunction with Figure 14-15 As explained, the functional pad 212 and the non-functional pad 214 may be directly bonded to opposing conductive features (eg, opposing pads or opposing exposed vias) on the second semiconductor element (see Figure 14-15 ). In some embodiments, the functional pad 212 can be directly bonded to the relative functional pad. In some embodiments, the specific function of the functional pad is disabled, and the functional pad 212 can be directly bonded to the relative non-functional pad. In some embodiments, the non-functional pad or dummy pad 214 can be directly bonded to the relative non-functional pad or dummy pad. In some embodiments, if the specific function of the relative functional pad is disabled, the non-functional pad or dummy pad 214 can be directly bonded to the relative functional pad.

[0024] and Figure 1 Compared to the structure of semiconductor element 100 in FIG. 1 , the functional metal pad or active metal pad 212 and the non-functional metal pad 214 can be formed by a single damascene process. As such, the functional metal pad 212 may not have separate or distinct via portions, and may be characterized by a continuous sidewall or an integrated sidewall. Due to the etching process, the sidewalls of the functional metal pad 212 may form an angle with the vertical reference line, but the angle may be small. The sidewalls of the illustrated embodiment do not have abrupt discontinuities or corners (such as Figure 1 The corners 118 and 120 are formed by the dual damascene process. The single damascene process is used in the production of Figure 2 An important advantage of the functional metal pad 212 is that it is easier to produce than the dual damascene process. Figure 1 The functional metal pads 112 and the connected vias 110 are simpler to produce. Figure 2 The functional metal pad 212 does not use Figure 1 More expensive or complex masks are used in the structures. Figure 2 Another advantage of the functional metal pad 212 in the embodiment is that the resistance is lower due to the thicker cross-sectional dimensions of the metal pad and thus the Figure 1Compared with the performance of the semiconductor device 100, the performance of the semiconductor device 200 is better. Figure 2 The thickness D of the bonding contact pad 212 2b (and the thickness D of the dummy pad 214 2a ) can be formed to be larger than Figure 1 The contact pad 112 in is thicker because the contact pad 212 is not connected to the bottom layer via, but extends through the thickness of the bonding layer 206. Figure 2 The thickness of the bonding layer 216 and the thickness of the contact pad 212 are 2b Similarly, for the same reason, the thickness of the bonding layer 216 can be formed thicker than Figure 1 The bonding layer 106 in the embodiment is thinner: the bonding layer 106 can be formed thick enough to embed both the contact pad 112 and the bottom layer via 110. Figure 1 Compared to the case in FIG. 1 , the thinner bonding layer 206 and the thicker contact pad 212 can ensure that stress in the second dielectric layer or bonding layer 206 (which may cause deformation and warping of the semiconductor element 200) can be reduced and better controlled. Figure 1 Compared with the process of the device, since the pad 212 is thicker, it is used Figure 2 The annealing process of the hybrid direct bonding of the device can be performed at a lower annealing temperature. As the stress in the second dielectric layer 206 is reduced, the warpage of the semiconductor device is also reduced, which can reduce the risk of void formation at the bonding interface, thereby improving the direct bonding quality.

[0025] Figure 3 Another example embodiment of the present disclosure is depicted in , which uses a single damascene process to build functional metal pads and non-functional metal pads in a bonding layer. Figure 3 , a schematic cross-sectional view of a semiconductor component 300 is shown, which includes a device layer or device portion 302 and a first dielectric layer 304 disposed on the device layer 302. An interconnect conductive layer or bottom interconnect 308 is embedded in the first dielectric layer 304. A second non-conductive layer or dielectric layer or bonding layer 306 can be deposited on the first non-conductive layer or dielectric layer 304. The second dielectric layer 306 and the conductive pads 312 and 314 can serve as bonding structures for the semiconductor component 300. A functional metal pad or active metal pad 312 extends from a top surface 316 through the second dielectric layer 306 and is connected to the interconnect conductive layer or metal layer 308 buried in the first dielectric layer 304. Figure 2Like the semiconductor component 200 shown in FIG, a non-functional metal pad or dummy metal pad 314 extends from the top surface 316 through the second dielectric layer 306, but terminates above the buried conductive layer 308 in the second dielectric layer 306. The functional conductive pad 312 and the non-functional conductive pad 314 can be made of the same material as the buried conductive layer 308. Alternatively, the pads 312 and 314 can be made of different materials. For example, in some embodiments, the buried conductive layer 308 can include aluminum, while the pads 312 and 314 can include copper, or vice versa. As described with respect to FIG. Figure 2 As described with respect to element 200 in FIG. 3 , pads 312 and 314 may have different arrangements of shapes and sizes when viewed from top surface 316 , such as squares, triangles, circles, polygons, etc. of various sizes. For example, in the same embodiment, active metal pad 312 may have one shape and one size, while dummy metal pad 314 may have another shape and another size. In some embodiments, active metal pad 312 and dummy metal pad 314 may have various shapes and various sizes. Figure 3 As can be seen in FIG, the depth D of the dummy metal pad 314 3a Shallower than the depth D of the active metal pad 212 3b In addition, Figure 2 Like the semiconductor element 200 in FIG. 1 , the active metal pads 312 and 314 may be formed by a single damascene process, which may be more complex than the process used to form the active metal pads 312 and 314. Figure 1 The process of the semiconductor element 100 is simpler.

[0026] and Figure 2 In contrast, more than one functional contact pad 312 may be formed to connect to each buried metal trace 308. Each of the plurality of contact pads 312 may be more than one functional contact pad 312. Figure 2 The single contact pad 212 connected to each buried metal trace 208 is thinner. However, this redundancy can improve the quality and reliability of the functional contact pad 312. Figure 3 As shown in FIG, the dummy pads 314 may have different widths. Figure 2 The width of each dummy pad 314 may be related to the density of the functional pads 312 surrounding it. In some embodiments, the positioning and different widths of metal pads 312 and 314 may allow for a substantially uniform distribution of metal pads 312 and 314 in second dielectric layer 306, thereby minimizing stress in dielectric layer 306, as described with respect to FIG. Figure 2 Reducing stress in the interconnect structure or layer 303 can reduce warping of the dielectric layer 306 and the semiconductor 300 .

[0027] Figures 4-10 is a diagram for forming Figure 3 Schematic cross-sectional view of a method of manufacturing a semiconductor component 300. Figure 4 In the embodiment of the present invention, device layer 302 of semiconductor element 300 may include a carrier or substrate, such as a die, wafer, interposer, etc. Device layer 302 may have circuitry 301 disposed therein and be covered by a first dielectric layer 304. A conductive (e.g., metal) layer 308 is embedded in first dielectric layer 304, connected to circuitry 301 in device layer 302 through vias 305. Embedded metal layer 308 may be covered by a non-conductive layer (e.g., a portion of dielectric layer 304 or another dielectric layer disposed above layer 304, such as a passivation layer). The non-conductive layer (e.g., a portion of layer 304) may be etched to expose metal traces 308a connected to devices or circuitry 301 in device layer 302. In other embodiments, traces 308a may be part of an interposer and may not be directly connected to the devices. In some embodiments, first dielectric layer 304 and metal layer 308 may be fabricated as part of microelectronic device fabrication (e.g., wafer fabrication). In this case, a passivation layer may be applied above the wafer surface for protection, and only certain metal traces may be exposed for external connections. Figure 4 The semiconductor component 300 in FIG. 1 includes a device layer 302 and a first dielectric layer 304 having an embedded metal 308 . The semiconductor component 300 may include a complementary metal oxide semiconductor (CMOS) device.

[0028] like Figure 5 As shown in FIG, a second dielectric layer 306 (which may serve as part of a bonding layer) may be deposited on Figure 4 3. The second dielectric layer 306 is formed above the top surface of the semiconductor element 300 shown in FIG. 3, covering the first dielectric material 304 and the exposed metal trace 308a. The second dielectric layer 306 may include an inorganic dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like.

[0029] exist Figure 6 In the embodiment, the first photoresist layer 320 may be coated on Figure 5 306. The photoresist layer 320 is then exposed to radiation of a specific wavelength projected through a mask for patterning. After development, a first opening 322 can be formed in the first photoresist layer 320 to expose the second dielectric layer 306 below. The semiconductor element 300 is then exposed to an etching process so that a first cavity or opening 324 can be formed through the first opening 322 on the first photoresist layer 320 (a functional metal pad in the second dielectric layer 306 will be provided in the first cavity or opening 324). The cavity 324 can stop at the buried metal layer 308, as shown in FIG. Figure 7The first photoresist layer 320 may be stripped to expose the second dielectric layer 306 having the etched first cavity 324 therein, as shown in the schematic cross-sectional view of FIG. Figure 7 As shown in .

[0030] refer to Figure 8 , a second photoresist layer 326 is coated on the top surface of the second dielectric layer 306 and patterned. However, for the second photoresist layer 326, the second openings 328 patterned in the photoresist layer 326 are located in areas where there are no first cavities 324 for functional metal contact pads. In other embodiments, the second openings 328 can be staggered with the first cavities 324 in the second dielectric layer 306, depending on the density of the first cavities 324 in that area. Generally speaking, when the distribution of the first cavities 324 in the second dielectric layer 306 is uneven, areas with sparser first cavities 324 can have more second openings 328. As described for Figure 7 As described above, the second dielectric layer 306 can be etched through the second opening 328 to create a second cavity or opening 330 for a non-functional metal pad or a dummy metal pad, as shown in FIG. Figure 9 . However, the second cavity 330 can be partially etched through the second dielectric layer 306 to terminate at a position vertically above the buried conductive layer 308. Alternatively, the second cavity 330 can be etched in any suitable manner (e.g., with the same type or a different type of etching process as for the first cavity 324). The depth of the second cavity 330 can be controlled by timing the etching or by etching a stop layer (e.g., a silicon nitride layer). In some embodiments, the depth of the second cavity 330 in the second dielectric layer 306 can be etched as deep as possible but not completely through the second dielectric layer 306 (e.g., so that it is not in contact with the conductive layer 308 and is placed vertically above the conductive layer 308). In some embodiments, the second dielectric layer 306 can be formed thinner so that the ratio of the depth of the second cavity 330 to the thickness of the second dielectric layer 306 (e.g., Figure 3 As shown in 3a / D 3b ) can be, for example, greater than 50%, 65% or 85%. When the cavities 324 and 330 are filled with metal (e.g., copper) in a subsequent step, the deeper non-functional metal pads are better for relieving stress and reducing deformation. After the second etching process, the second photoresist layer 326 is stripped to expose the top surface of the second dielectric layer 306 and the first cavity 324 and the second cavity 330 formed therein, as shown in FIG. Figure 9 As shown in .

[0031] As explained herein, multiple (e.g., two) etching steps may be performed to separate Figure 3The dual damascene process also uses two etching steps, for example, to form a functional metal pad 312 and a non-functional metal pad 314 in the semiconductor device 300. Figure 1 However, in the dual damascene process, the Figure 1 The mask positions of the two etching steps for creating via 110 and functional metal pad 112 are overlapping. In other words, the second cavity created by the second etching step (for forming the trench for functional pad 112) is located on top of the first cavity created by the first etching step (for forming via 110). Figure 4-Figure 8 In the disclosed and discussed embodiments, the first cavity 324 created by the first etching step and the second cavity 330 created by the second etching step are located at different lateral locations. There is no lateral overlap between the first cavity and the second cavity. Therefore, each of the first cavity 324 and the second cavity 330 can be created by a single etching step (e.g., a single damascene process). Therefore, the disclosed embodiments are different from those used to form Figure 1 The structural approach is significantly different.

[0032] For example, one difference between a dual damascene process and a single damascene process is illustrated by the sidewall profile of the hole or opening formed by the corresponding etching process, as described above in conjunction with Figure 1 and Figure 2 discussed. Figures 11A-11B Further illustration of the combination Figure 1 The conductive features form the sidewalls of the structure, and Figure 11C-11D Illustration of the combination Figure 2 and Figure 3 The sidewall and pad structures are formed. Figure 11A In FIG, the conductive feature 410 includes a via portion 412 located below a conductive pad portion 414, the via portion 412 and the conductive pad portion 414 are connected together and embedded in a non-conductive dielectric material 416. Such a conductive feature 410 can be formed by a dual damascene process. Figure 11AAs can be seen in the figure, the size of the via 412 is significantly narrower than the conductive pad 414. Specifically, the left sidewall 420 is divided into two vertical segments (i.e., upper segment 420a and lower segment 420b) and a horizontal segment 426. The three line segments are connected by two corners 422 and 424, which can be approximately perpendicular or formed at another angle, thereby creating an edge or abrupt change in direction between adjacent faces of the segments 420a, 420b, and 426. As discussed above, the separation and disjointed structure of the upper pad portion 414 and the lower via portion 412 is caused by the use of the dual damascene process used to produce the conductive feature 410. The sidewall segments 420b and 430b at the lower via portion 412 and the sidewall segments 430a and 430b at the upper pad portion 414 can be vertical or nearly vertical. This nearly vertical structure can be formed by certain etching processes, such as reactive ion etching (RIE). In other embodiments, the conductive features may be formed by other etching methods, such as wet etching and other dry etching methods.

[0033] Figure 11B The conductive features 450 shown in FIG. Figure 11B The structures shown in are generally similar to those shown in , except that one or more of the sidewalls can be angled or curved, and segments of the sidewalls can be angled at non-perpendicular angles. The conductive feature 450 can be formed by any suitable etching technique, including, for example, a wet etching method. The conductive feature 450 embedded in the dielectric material 456 includes a smaller via portion 452 and a larger conductive pad portion 454 connected together. Due to the etching method, the sidewalls 460 and sidewalls 470 of the conductive feature 450 can be slightly tilted, thereby forming a smaller angle with a vertical reference line or plane. The tilted etching may be due to the upper portion of the etch channel being exposed to the etchant for a longer period of time than the lower portion. Similar to Figure 11A 4. As shown in FIG. 4 , conductive feature 410 having vertical sidewalls is shown in FIG. 4 , the size of the via portion 452 of conductive feature 450 is significantly narrower than the conductive pad portion 454. Due to the smaller angle of inclination, there is a clear separation or discontinuity between via 452 and pad 454. Similarly, sawtooth wall 460 is characterized by having two inclined segments 460a and 460b connected by two corners 462 and 464, and a horizontal segment 466. Sawtooth wall 470 has two inclined segments 470a and 470b connected by two corners 472 and 474, and a horizontal segment 476. In practice, corners 422, 424, 432, 434, 462, 464, 472, and 474 may not be as Figure 11A and Figure 11B4. The conductive feature 450 may be sharp as shown in FIG. 4 and may include a radius, but the radius should be very small compared to the size of the sidewall segments. The sharp corner structure between the upper pad portion 454 and the lower via portion 452 is due to the dual damascene process used to produce the conductive feature 450.

[0034] On the other hand, the conductive features formed by the single damascene process described herein do not have the jagged or discontinuously angled sidewalls that are characteristic of conductive features formed by the dual damascene process, as described above with respect to FIG. Figure 11A and Figure 11B Discussed. Figure 11C In FIG. 5 , the conductive feature 510 is formed in the opening in the dielectric material 516 by a single damascene process, which may employ a reactive ion etching (RIE) method or other suitable technique. Figure 11C In FIG. 5 , the sidewalls 520 and 530 of the conductive feature 510 can be vertical or substantially vertical. These structures are integral and continuous or have no corners, such as Figure 11A and Figure 11B The steps or discontinuities separating the upper and lower portions are shown in FIG. Figure 11D In FIG, a conductive feature 550 formed by a single damascene process is embedded in an opening in a dielectric material 556 with integral and continuous or corner-free sidewalls 560 and 570. Figure 11C Compared to the vertical sidewalls 520 and 530 in FIG, sidewalls 560 and sidewalls 570 can be inclined, slightly angled from a vertical reference line or plane. Inclined sidewalls 560 and 570 can be formed by a wet etching method (or any other suitable material removal technique) that is used to create the trench to form conductive feature 550. In some embodiments, the inclined sidewalls can have a certain degree of curvature, but can still be continuous so that the sidewalls do not include corners. In summary, compared to FIG. Figure 11A and Figure 11B Compared to the conductive features 410 and 450 formed by the dual damascene process shown in FIG. Figure 11C and Figure 11D The conductive features 510 and 550 shown in FIG. 5 are formed by a single damascene process and can be formed in a simpler manner.

[0035] Back to Figure 9 After forming the first cavity 324 for the functional metal pad or active metal pad 312 and the second cavity 330 for the non-functional metal pad 314, as shown in FIG. Figure 9As shown in FIG, a conductive material 332 (e.g., a metal material such as copper) may be deposited (e.g., plated) to fill the first cavity 324 and the second cavity 330, such that a functional conductive pad 312 is formed in the first cavity 324 and a non-functional conductive pad 314 is formed in the second cavity 330, as shown in FIG. Figure 10 In some embodiments, Figure 10 Before the metal filling process, a barrier layer and a metal seed layer may be deposited to cover the entire surface of the semiconductor 300, including Figure 9 The cavity shown in .

[0036] After the metal filling process, a planarization step (eg, CMP) is applied to remove excess metal material, thereby forming a smooth top surface 316 of the second dielectric layer 306, as shown in FIG. Figure 3 . The planarization process may include removing portions of any barrier layer between the metal material and the second dielectric layer 306, and may even remove portions of the second dielectric layer 306. The smooth top surface 316 of the second dielectric layer 306 may be configured for bonding (e.g., direct hybrid bonding) to another semiconductor element or microelectronic device. As explained below, in various embodiments, additional processes (such as activation and / or termination processes) may be performed to prepare the top surface 316 for direct bonding.

[0037] like Figure 3 As shown in , since the cross-sectional dimensions of functional metal pad 312 may be constrained by the dimensions of metal trace 308, functional metal pad 312 and non-functional metal pad 314 may have different cross-sectional dimensions. The density of metal pads 312 and metal pads 314 in second dielectric layer 306 may be defined in a variety of ways: for example, area density, which is the ratio of the area of ​​exposed metal pads 312 and 314 to the total area of ​​top surface 316 as viewed from a direction perpendicular to top surface 316; and volume density, which is the ratio of the volume of metal pads 312 and 314 in second dielectric layer 306 to the total volume of second dielectric layer 306 including the metal pads. If the sidewalls of metal pads 312 and 314 are formed to be nearly vertical, the area density may be close to the volume density when the depth of the non-functional metal pad is similar to the depth of the functional metal pad. Return to see Figure 3, viewed from a direction perpendicular to the top surface 316 of the semiconductor element 300, the pad area density of the metal pads 312 and the metal pads 314 can be designed to be uniform or approximately uniform across the entire surface 316 to effectively control the stress generated by direct bonding. In some embodiments, when an area of ​​the surface 316 does not have functional metal pads 312, the non-functional metal pads 314 can be positioned to match the pad density of the area with functional metal pads 312. In some embodiments, when an area of ​​the surface 316 has a lower pad density than other areas, non-functional metal pads 314 can be added to the area so that the pad density in the area is approximately the same as the pad density in other areas (or their size is otherwise adjusted to balance stress). In some embodiments, the pad area density on the surface 316 can be controlled by adjusting the size or cross-sectional dimensions of the non-functional metal pads 314. For example, smaller non-functional metal pads 314 may be positioned in areas with more functional metal pads 312 , while larger non-functional metal pads 314 may be positioned in areas with fewer functional metal pads 312 .

[0038] like Figure 3 As shown in FIG, non-functional metal pad 314 located at the central region can be wider than non-functional metal pad 314 located at the peripheral region disposed about the central region. This arrangement can be used to balance the size difference of functional metal pad 312 when viewed in a direction perpendicular to top surface 316. In addition, by forming non-functional metal pad 314 deeper but not reaching the underlying metal layer 308 or by forming a bonding layer, the ratio D of the depth of non-functional metal pad 314 to the depth of functional metal pad 312 can be made greater. 3a / D 3b Because the stress in dielectric layer 306 is reduced and deformation of semiconductor component 300 is minimized due to the positioning of non-functional metal pad 314 , surface 316 of semiconductor 300 can be bonded to another component with reduced risk of bond voids at the interface.

[0039] Now see Figure 12 and Figure 13 , illustrating the manufacturing process through a schematic cross-sectional view Figure 2 The manufacturing process of the semiconductor element 200 shown in FIG. Figure 12 , semiconductor device 200 at this stage includes a second dielectric layer 206 formed on a first dielectric layer 204, with a metal layer 208 embedded in the first dielectric layer 204. First dielectric layer 204 is positioned over device portion 202, which has circuitry 201 embedded therein. In this embodiment, second dielectric material layer 206 may be deposited over the metal layer after metal layer 208 is formed. Figure 12 A first cavity 224 is shown formed in the second dielectric layer 206 for the functional metal pad, for example by patterning and etching, similar to the process described with respect to FIG. Figure 6 and Figure 7 The process is described for the semiconductor device 300. Figure 13 In the embodiment, a second cavity 230 is formed in the second dielectric layer 206 for the non-functional metal pad, for example by patterning and etching, similar to the embodiment of FIG. Figure 8 and Figure 9 The process described for the semiconductor device 300. Thus, a two-step single damascene etching process is followed to form the first cavity 224 and the second cavity 230, which is similar to the one used to form the Figure 1 The dual damascene process of the semiconductor element 100 in FIG. 1 is significantly different. When the cavities 224 and 230 are filled with a conductive material (such as metal) and planarized, similar to Figure 10 The process for the semiconductor element 300 can form Figure 2 . As viewed from a direction perpendicular to the top surface 216, the functional metal pads 212 and the non-functional metal pads 214 can be evenly or substantially evenly distributed to minimize stress in the dielectric layer 206. In addition, by forming the non-functional metal pads 214 deeper but not reaching the underlying metal layer 208, or by forming the bonding layer (including at least a portion of the dielectric layer 206) thinner to reduce stress and deformation in the dielectric layer 206, the ratio of the depth of the non-functional metal pads 214 to the depth of the functional metal pads 212 can be made (as shown in FIG. Figure 2 As shown in the figure, it is D 2a / D 2b )higher.

[0040] Various embodiments disclosed herein relate to direct bonding structures, in which two or more elements can be directly bonded to each other without an intermediate adhesive. Such processes and structures are referred to herein as "direct bonding" processes or "directly bonded" structures. Direct bonding can involve the bonding of one material on one element to a material on another element (also referred to herein as "uniform" direct bonding), where the materials on different elements do not need to be the same, without the need for conventional adhesives. Direct bonding can also involve the bonding of multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0041] In some embodiments (not shown), each bonding layer has a single material. In these uniform direct bonding processes, only one material is directly bonded to each component. Example uniform direct bonding processes include those provided by Adeia, Inc. in San Jose, California. Technology. The materials of the relative bonding layers on different elements may be the same or different and may include elemental materials or compound materials. For example, in some embodiments, the non-conductive bonding layer may be blanket deposited over the base substrate portion without being patterned with conductive features (e.g., without the need for pads). In other embodiments, the bonding layers may be patterned on one or both elements and may be the same or different from each other, but one material from each element is directly bonded across the surface of the element (or across the surface of the smaller element if the elements are of different sizes) in the absence of an adhesive. In another embodiment of uniform direct bonding, one or both of the non-conductive bonding layers may include one or more conductive features, but the conductive features do not participate in the bonding. For example, in some embodiments, the relative non-conductive bonding layers may be uniformly directly bonded to each other, and after bonding, a through-substrate via (TSV) may then be formed through one element to provide electrical connectivity to another element.

[0042] In various embodiments, bonding layers 808a and / or 808b may include a non-conductive material, such as a dielectric material or an undoped semiconductor material (such as undoped silicon), which may include a native oxide. Dielectric bonding surfaces or materials suitable for direct bonding include, but are not limited to, inorganic dielectric materials (such as silicon oxide, silicon nitride, or silicon oxynitride), or may include carbon (such as silicon carbide, silicon carbonitride, low-K dielectric materials, SiCOH dielectric materials, silicon carbonitride, or diamond-like carbon or materials including a diamond surface). Despite including carbon, such carbon-containing ceramic materials may still be considered inorganic materials. In some embodiments, the dielectric material at the bonding surface does not include a polymeric material, such as an epoxy resin (e.g., an epoxy adhesive, a cured epoxy resin, or an epoxy composite material, such as FR-4 material), a resin, or a molding material.

[0043] In other embodiments, the bonding layer can include a conductive material, such as a deposited conductive oxide material, e.g., indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63 / 524,564, filed on June 30, 2023, the entire contents of which are incorporated herein by reference to provide examples of conductive bonding layers that do not require shorting contacts across an interface.

[0044] In direct bonding, the first element and the second element can be directly bonded to each other without an adhesive, which is different from a deposition process, and the interface produced is structurally different compared to the interface produced by deposition. In one application, the width of the first element in the bonded structure is similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure is different from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. In addition, different from the interface below the deposited layer, the interface between the direct bonded structure can include a defective area in which there is a nanoscale void (nanovoid). Nanovoids may be formed due to the activation (e.g., exposure to plasma, as explained below) of one or both of the bonding surfaces.

[0045] Compared to the bulk of the bonding layer, the bonding interface between the non-conductive bonding surfaces may include a higher concentration of material due to activation and / or the final chemical treatment process. For example, in an embodiment in which activation is performed using nitrogen plasma, a nitrogen concentration peak may be formed at the bonding interface. In some embodiments, the nitrogen concentration peak may be detected using secondary ion mass spectrometry (SIMS) technology. In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding surface to a nitrogen-containing plasma) may replace the OH groups of the hydrolyzed (OH-terminated) surface with NH2 molecules, thereby producing a nitrogen-terminated surface. In an embodiment in which activation is performed using oxygen plasma, an oxygen concentration peak may be formed at the bonding interface between the non-conductive bonding surfaces. In some embodiments, the bonding interface may include silicon oxynitride, silicon carbon oxynitride, or silicon carbonitride. Direct bonding may include covalent bonds, which are stronger than van der Waals bonds. The bonding layer may also include a polished surface that is flattened to a high degree of smoothness.

[0046] In direct bonding process (such as uniform direct bonding and hybrid bonding), two elements are bonded together without the need for an intermediate adhesive. In the indirect bonding process utilizing adhesive, an intermediate material is usually applied to one or two elements to realize the physical connection between elements. For example, in some processes based on adhesive, a flowable adhesive (for example, an organic adhesive (such as epoxy resin)) (which may include conductive filling materials) may be applied to one or two elements, and solidified to form physical (rather than chemical or covalent) connection between the elements. Common organic adhesives lack strong chemical bonds or covalent bonds with any element. In such processes, such as by reheating or removing flux, the connection between the elements is weaker and / or easily reversed.

[0047] In contrast, direct bonding processes connect two elements by forming a strong chemical bond (e.g., covalent bond) between relative non-conductive materials. For example, in a direct bonding process between non-conductive materials, one or both non-conductive surfaces of two elements are planarized and chemically prepared (e.g., activated and / or terminated) so that when the elements come into contact, a strong chemical bond (e.g., covalent bond) is formed, which has a strength higher than that of van der Waals forces or hydrogen bonds. In some embodiments (e.g., between relative dielectric surfaces, such as between relative silicon oxide surfaces), upon contact, chemical bonds can form spontaneously at room temperature. In some embodiments, the chemical bonds between relative non-conductive materials can be enhanced after the elements are annealed.

[0048] As noted above, hybrid bonding is a direct bonding in which the non-conductive features of the elements being bonded are bonded directly to the non-conductive features, and the conductive features are bonded directly to the conductive features. The non-conductive bonding materials and interfaces can be as described above, while conductive bonding can be formed as, for example, direct metal-to-metal connections. In conventional metal bonding processes, a fusible metal alloy (e.g., solder) can be provided between the conductors of the two elements, heated to melt the alloy, and then cooled to form a connection between the two elements. The resulting bonding often exhibits a sharp interface with the conductors from the two elements and is easily reversed by reheating. In contrast, the direct metal bonding employed in hybrid bonding does not require melting or an intermediate fusible metal alloy, and can produce strong mechanical and electrical connections, typically exhibiting interdiffusion of bonded conductive features and grain growth across the bond interface between the elements, even without the higher temperatures and pressures of thermocompression bonding.

[0049] Figure 14 and Figure 15 Schematically illustrates cross-sectional side views of a first element 802 and a second element 804 before and after a process of forming a direct bond structure, more specifically a hybrid bond structure, respectively, according to some embodiments. Figure 15 , a bonded structure 800 includes a first component 802 and a second component 804 that are directly bonded to each other at a bonding interface 818 without an intermediate adhesive. A conductive feature 806a of the first component 802 can be electrically connected to a corresponding conductive feature 806b of the second component 804. In the illustrated hybrid bonded structure 800, the conductive feature 806a is directly bonded to the corresponding conductive feature 806b without an intermediate solder or conductive adhesive.

[0050] The conductive features 806a and 806b of the illustrated embodiment are respectively embedded in the first bonding layer 808a of the first element 802 and the second bonding layer 808b of the second element 804 and can be considered as part thereof. The field regions of the bonding layers 808a and 808b extend between the conductive features 806a and 806b and partially or completely surround the conductive features 806a and 806b. The bonding layers 808a and 808b can include a non-conductive material layer suitable for direct bonding as described above, and the field regions are directly bonded to each other without the need for an adhesive. The non-conductive bonding layers 808a and 808b can be placed on the respective front sides 814a and 814b of the base substrate portions 810a and 810b.

[0051] The first element 802 and the second element 804 may include microelectronic elements, such as semiconductor elements, including, for example, integrated device dies, wafers, passive devices, discrete active devices (such as power switches, MEMS, etc.). In some embodiments, the base substrate portion may include device portions, such as bulk semiconductor (e.g., silicon) portions of the elements 802 and 804, and back-end-of-line (BEOL) interconnect layers located above such semiconductor portions. Bonding layers 808a, 808b may be provided during device fabrication as part of such BEOL layers, as part of a redistribution layer (RDL), or as a specific bonding layer added to an existing device, with bond pads extending from underlying contacts. Active devices and / or circuitry may be patterned and / or otherwise placed in or on the base substrate portions 810a, 810b and may be in electrical communication with at least some of the conductive features 806a, 806b. Active devices and / or circuitry may be placed on or near the front sides 814a, 814b of the base substrate portion 810a, 810b, and / or at or near the back sides 816a, 816b of the base substrate portions 810a, 810b. In other embodiments, the base substrate portions 810a and 810b may not include active circuitry, but may include dummy substrates, passive interposers, passive optical elements (e.g., glass substrates, gratings, lenses), etc. Bonding layers 808a and 808b are shown as being provided on the front sides of the elements, but similar bonding layers may also be provided on the back sides of the elements in addition or in lieu thereof.

[0052] In some embodiments, the base substrate portions 810a and 810b can have significantly different coefficients of thermal expansion (CTE), and a bonding element including such different base substrate portions can form a heterogeneous bonding structure. The CTE difference between the base substrate portions 810a and 810b, and in particular the CTE difference between the bulk semiconductor (typically single crystal) portions of the base substrate portions 810a and 810b, can be greater than 5 ppm / °C or greater than 10 ppm / °C. For example, the CTE difference between the base substrate portions 810a and 810b can be in the range of 5 ppm / °C to 100 ppm / °C, 5 ppm / °C to 40 ppm / °C, 10 ppm / °C to 100 ppm / °C, or 10 ppm / °C to 40 ppm / °C.

[0053] In some embodiments, one of the base substrate portions 810a, 810b may include an optoelectronic single crystal material, including a perovskite material, which may be used for optical piezoelectric or thermoelectric applications, while the other of the base substrate portions 810a, 810b may include a more conventional substrate material. For example, one of the base substrate portions 810a, 810b may include lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), while the other of the base substrate portions 810a, 810b may include silicon (Si), quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the base substrate portions 810a, 810b may include a III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), while the other of the base substrate portions 810a, 810b may include a non-III-V semiconductor material, such as silicon (Si), or may include other materials with similar CTEs, such as quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the base substrate portions 810a, 810b includes a semiconductor material, while the other of the base substrate portions 810a, 810b includes an encapsulation material (such as a glass, organic, or ceramic substrate).

[0054] In some arrangements, the first element 802 may include a singulated element, such as a singulated integrated device die. In other arrangements, the first element 802 may include a carrier or substrate (e.g., a semiconductor wafer) that includes multiple (e.g., dozens, hundreds, or more) device regions that form multiple integrated device dies when singulated, but in other embodiments, such a carrier may be a packaging substrate or a passive or active interposer. Similarly, the second element 804 may include a singulated element, such as a singulated integrated device die. In other arrangements, the second element 804 may include a carrier or substrate (e.g., a semiconductor wafer). Therefore, the embodiments disclosed herein may be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers may be directly bonded to each other (e.g., direct hybrid bonding) and singulated using a suitable singulation process. After singulation, side edges of the singulated structure (e.g., side edges of two bonded elements) can be substantially flush (substantially aligned xy dimensions), and / or edges of the bonding interfaces of the bonded elements and the singulated elements can coexist and can include markings indicating a common singulation process used for the bonded structure (e.g., saw marks if a saw singulation process is used).

[0055] Although only two elements 802 and 804 are shown in the figure, any suitable number of elements can be stacked in the bonding structure 800. For example, a third element (not shown) can be stacked on the second element 804, a fourth element (not shown) can be stacked on the third element, and so on. In this embodiment, through-substrate vias (TSVs) can be formed to provide vertical electrical connectivity between the vertically stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to each other along the first element 802. In some embodiments, the laterally stacked additional elements can be smaller than the second element. In some embodiments, the bonding structure can be encapsulated with an insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon carbide, etc.). One or more insulating layers can be provided above the bonding structure. For example, in some embodiments, a first insulating layer can be conformally deposited above the bonding structure, and a second insulating layer (which can include the same or different material as the first insulating layer) can be provided above the first insulating layer.

[0056] To achieve direct bonding between the bonding layers 808a, 808b, the bonding layers 808a, 808b may be prepared for direct bonding. The non-conductive bonding surfaces 812a, 812b at the upper or outer surfaces of the bonding layers 808a, 808b may be prepared for direct bonding by polishing (e.g., by chemical mechanical polishing (CMP)). The roughness of the polished bonding surfaces 812a, 812b may be less than For example, the roughness of the bonding surfaces 812a and 812b may be about arrive arrive or arrive The polishing can also be adjusted to recess the conductive features 806a, 806b relative to the field regions of the bonding layers 808a, 808b.

[0057] Preparing for direct bonding may also include cleaning one or both of the bonding surfaces 812a, 812b and exposing them to a plasma and / or etchant to activate at least one of the surfaces 812a, 812b. In some embodiments, one or both of the surfaces 812a, 812b may be terminated with a substance after or during activation (e.g., during the plasma and / or etching process). Without being limited by theory, in some embodiments, the activation process may be performed to break chemical bonds at the bonding surfaces 812a, 812b, while the termination process may provide additional chemicals at the bonding surfaces 812a, 812b that alter the chemical bonds and / or increase the bonding energy during direct bonding. In some embodiments, activation and termination are performed in the same step, e.g., using a plasma to activate and terminate the surfaces 812a, 812b. In other embodiments, one or both of the bonding surfaces 812a, 812b may be terminated in a separate process to provide additional substances for direct bonding. In various embodiments, the termination substance may include nitrogen. For example, in some embodiments, the bonding surfaces 812a, 812b can be exposed to a nitrogen-containing plasma. Depending on the material of the bonding surfaces 812a, 812b, other termination substances may be suitable for improving the bonding energy. In addition, in some embodiments, the bonding surfaces 812a, 812b can be exposed to fluorine. For example, there may be one or more fluorine concentration peaks at or near the bonding interface 818 between the first element 802 and the second element 804. Typically, the fluorine concentration peak occurs at the interface between the material layers. Additional examples of activation and / or termination treatments can be found in the following documents: U.S. Patent No. 9,391,143, column 5, line 55 to column 7, line 3; column 8, line 52 to column 9, line 45; column 10, lines 24-36; column 11, lines 24-32, lines 42-47, lines 52-55, and lines 60-64; column 12, lines 3-14, lines 31-33 and lines 55-67; ​​column 14, lines 38-40 and 44-50; and column 12, lines 46-61 of No. 10,434,749, the teachings of which regarding activation and termination are incorporated herein by reference.

[0058] Thus, in the direct bond structure 800, the bonding interface 818 between the two non-conductive materials (e.g., bonding layers 808a, 808b) may include a very smooth interface and have a high nitrogen (or other termination species) content and / or a fluorine concentration peak at the bonding interface 818. In some embodiments, various types of inspection techniques (such as SIMS techniques) may be used to detect the nitrogen and / or fluorine concentration peaks. After the activation process, the polished bonding surfaces 812a and 812b may be slightly rough (e.g., about arrive arrive or possibly rougher). In some embodiments, activation and / or termination can produce a slightly smoother surface prior to bonding, such as plasma treatment that preferentially etches high points on the bonding surface.

[0059] Non-conductive bonding layers 808a and 808b can be bonded directly to each other without an adhesive. In some embodiments, elements 802 and 804 are bonded together at room temperature without applying a voltage or applying an external pressure or force that exceeds that required to initiate contact between the two elements 802 and 804. Contact alone can result in direct bonding (e.g., covalent dielectric bonding) between the non-conductive surfaces of bonding layers 808a and 808b. Subsequent annealing of bonded structure 800 can result in direct bonding of conductive features 806a and 806b.

[0060] In some embodiments, prior to direct bonding, the conductive features 806a and 806b are recessed relative to the surrounding field region such that after dielectric bonding and prior to annealing, the total gap between the opposing contacts is less than 15 nm, or less than 10 nm. Due to process variations, the depth of the recess of the conductive features 806a and 806b may vary from component to component, so the gap may represent the maximum gap or average gap between corresponding conductive features 806a and 806b of the two coupled components (before annealing). After annealing, the conductive features 806a and 806b may expand and contact each other, forming a metal-to-metal direct bond.

[0061] During annealing, the conductive features 806a, 806b (e.g., metal material) may expand, while the direct bond between the non-conductive material surrounding the bonding layer 808a, 808b may prevent the components from separating, so that the thermal expansion increases the internal contact pressure between the opposing conductive features. Annealing may also cause metal grains to grow across the bonding interface, so that grains from one component migrate at least partially across the bonding interface into the other component, and vice versa. Therefore, in some hybrid bonding embodiments, the opposing conductive materials can be joined without being heated above the melting temperature of the conductive materials, so that the bond can be formed at a lower annealing temperature than soldering or thermocompression bonding.

[0062] In various embodiments, the conductive features 806a, 806b may include discrete pads, contacts, electrodes, or traces at least partially embedded in the non-conductive field region of the bonding layer 808a, 808b. In some embodiments, the conductive features 806a, 806b may include exposed contact surfaces of TSVs (e.g., through-silicon vias).

[0063] As noted above, in some embodiments, Figure 14 In elements 802, 804, prior to direct bonding, portions of the corresponding conductive features 806a and 806b can be recessed below the non-conductive bonding surfaces 812a and 812b, for example, by less than 30nm, less than 20nm, less than 15nm, or less than 10nm, such as within a range of 2nm to 20nm, or within a range of 4nm to 10nm. Due to process variations, both the dielectric thickness and the conductor recess depth can vary from element to element. Thus, the above recess depth ranges can apply to individual conductive features 806a, 806b, or to the average depth of the recess relative to the local non-conductive field region. Even for individual conductive features 806a, 806b, the vertical recess can vary across the feature and, therefore, can be measured at or near the lateral middle or center of the cavity in which a given conductive feature 806a, 806b is formed, or can be measured at the side of the cavity.

[0064] Advantageously, hybrid bonding technology (such as direct bond interconnects available from Adeia, Inc. of San Jose, California) is used. technology) can enable high density connections (eg, small or fine pitch for a regular array) between the conductive features 806a, 806b across the direct bonding interface 818.

[0065] In some embodiments, the pitch p of the conductive features 806a and 806b (such as conductive traces embedded in the bonding surface of one of the bonding elements) can be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or even less than 1 μm. For some applications, the ratio of the pitch of the conductive features 806a and 806b to one of the lateral dimensions (e.g., diameter) of the bonding pad is less than 20, or less than 10, or less than 5, or less than 3, and sometimes desirably less than 2. In various embodiments, the conductive features 806a and 806b and / or the traces can comprise copper or a copper alloy, although other metals (such as nickel, aluminum, or alloys thereof) may also be suitable. The conductive features disclosed herein, such as the conductive features 806a and 806b, can comprise fine-grained metal (e.g., fine-grained copper). Furthermore, its major lateral dimension (eg, pad diameter) may also be smaller, such as in the range of about 0.25 μm to 30 μm, in the range of about 0.25 μm to 5 μm, or in the range of about 0.5 μm to 5 μm.

[0066] For hybrid bonded elements 802 and 804 as shown, the orientations of one or more conductive features 806a and 806b from the opposing elements can be opposite to each other. As is known in the art, conductive features can generally be formed with adjacent vertical sidewalls, particularly when directional reactive ion etching (RIE) is used in a damascene process to define the conductor sidewalls, either directly by etching the conductive material or indirectly by etching a surrounding insulator. However, the conductor sidewalls may exhibit some slight taper, where the conductor becomes narrower as it moves away from the surface initially exposed to the etching. The taper is even more pronounced when the conductive sidewalls are defined directly or indirectly by isotropic wet or dry etching. In the illustrated embodiment, at least one conductive feature 806b (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 808b of the upper element 804 can taper or narrow upward away from the bonding surface 812b. In contrast, at least one conductive feature 806a (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 808a of the lower component 802 can taper or narrow downwardly away from the bonding surface 812a. Similarly, any bonding layer (not shown) on the backside 816a, 816b of the components 802, 804 can taper or narrow from the backside with an opposite tapered orientation relative to the frontside conductive features 806a, 806b of the same component.

[0067] As described above, during the annealing phase of the hybrid bond, the conductive features 806a, 806b can expand and contact each other to form a direct metal-to-metal bond. In some embodiments, the materials of the conductive features 806a, 806b of the opposing elements 802, 804 can diffuse into each other during the annealing process. In some embodiments, metal grains grow into each other across the bonding interface 818. In some embodiments, the metal is copper or includes copper, which may have grains oriented along 111 crystal planes to improve copper diffusion across the bonding interface 818. In some embodiments, the conductive features 806a and 806b may include a nano-twinned copper grain structure, which may help merge the conductive features during annealing. There is essentially no gap between the non-conductive bonding layer 808a and 808b at or near the bonded conductive features 806a and 806b. In some embodiments, a barrier layer (e.g., which may include copper) may be provided below the conductive features 806a and 806b and / or laterally surround the conductive features 806a and 806b. However, in other embodiments, there may be no barrier layer below the conductive features 806a and 806b.

[0068] Example

[0069] In various embodiments, the present disclosure relates to a device comprising: an interconnect structure having an upper surface prepared for direct bonding; a first contact pad extending to a first depth below the upper surface; and a second contact pad extending to a second depth below the upper surface, wherein the second depth is less than the first depth.

[0070] In one aspect of the present disclosure, the first contact pad comprises an active pad electrically connected to the underlying interconnect. In addition, the first contact pad is directly connected to the underlying interconnect without an intermediate via.

[0071] In another aspect of the present disclosure, the second contact pad comprises a dummy pad that is not electrically connected to the underlying interconnect.

[0072] In another aspect of the present disclosure, the first contact pad and the second contact pad are made of metal. In addition, the first contact pad and the second contact pad are made of copper.

[0073] In another aspect of the present disclosure, the first contact pad is placed in an opening having continuous sidewalls. Alternatively, the first contact pad is placed in an opening having sidewalls without corners. The first contact pad is formed by a single damascene process.

[0074] In another aspect of the present disclosure, the first pads and the second pads are substantially evenly distributed on the upper surface of the interconnect structure. Alternatively, the first pads and the second pads are substantially evenly distributed in the interconnect structure.

[0075] In another aspect of the present disclosure, the ratio of the second depth to the first depth is greater than 50%. Alternatively, the ratio of the second depth to the first depth is greater than 85%.

[0076] In another aspect of the disclosure, an interconnect structure includes a first dielectric layer including an upper surface, a first contact pad and a second contact pad extending to the first dielectric layer.

[0077] In another aspect of the present disclosure, the bottom layer interconnect is a redistribution layer (RDL) trace. Additionally, the bottom layer interconnect is an outermost metal layer of the microelectronic device.

[0078] In another aspect of the present disclosure, the device further comprises a device layer disposed on the interconnect structure, wherein the device layer comprises circuitry electrically connected to the underlying interconnect.

[0079] In yet another aspect of the present disclosure, the device layer includes a complementary metal oxide semiconductor (CMOS) device.

[0080] In some embodiments, the present disclosure is a bonding structure comprising the above-described device and a second element, the second element comprising a second dielectric layer and a third contact pad at least partially embedded in the second dielectric layer, wherein the first dielectric layer is directly bonded to the second dielectric layer without an adhesive, and the first contact pad is directly bonded to the third contact pad without an adhesive.

[0081] In some embodiments, the present disclosure is a device comprising: an interconnect structure having a surface prepared for direct bonding; and a plurality of pads embedded in the interconnect structure, the plurality of pads comprising a first plurality of active pads and a second plurality of dummy pads, the thickness of the dummy pads being less than the thickness of the active pads.

[0082] In one aspect of the present disclosure, each of the first plurality of active pads is electrically connected to an underlying interconnect. Additionally, each of the first plurality of active pads is directly connected to the underlying interconnect without an intervening via.

[0083] In another aspect of the disclosure, each of the second plurality of dummy pads is not electrically connected to an underlying interconnect.

[0084] In another aspect of the present disclosure, the first plurality of active pads are formed by a single damascene process.

[0085] In another aspect of the present disclosure, the plurality of pads are made of metal. In addition, the plurality of pads are made of copper.

[0086] In another aspect of the present disclosure, each active pad has a unitary sidewall. Alternatively, each active pad has a sidewall without corners.

[0087] In another aspect of the present disclosure, the first plurality of active pads and the second plurality of dummy pads are substantially uniformly distributed on a surface of the interconnect structure. Alternatively, the first plurality of active pads and the second plurality of dummy pads are substantially uniformly distributed in the interconnect structure.

[0088] In another aspect of the present disclosure, a surface of an interconnect structure includes: a first region having a first area density of active pads and dummy pads, the active pads and dummy pads having a first cross-sectional size; and a second region having a second area density of active pads and dummy pads, the active pads and dummy pads having a second cross-sectional size, wherein the first area density is greater than the second area density, and the second cross-sectional size is greater than the first cross-sectional size.

[0089] In yet another aspect of the present disclosure, a ratio of the thickness of the dummy pad to the thickness of the active pad is greater than 50%. In addition, a ratio of the depth is greater than 85%.

[0090] In some embodiments, the present disclosure is a device comprising: a device portion comprising a circuit device; an interconnect layer disposed on the device portion and having an upper bonding surface, the upper bonding surface being prepared for direct hybrid bonding to a second component, the interconnect layer comprising: one or more non-conductive layers, on the device portion, the one or more non-conductive layers having a first cavity and a second cavity formed therein; a buried conductive layer electrically connected to the circuit device and embedded in the one or more non-conductive layers at a first depth below the upper bonding surface; an electrically functional conductive pad disposed in the first cavity and extending from the upper bonding surface through at least a portion of the one or more non-conductive layers to connect to the buried conductive layer, the first cavity being defined by continuous sidewalls of the one or more non-conductive layers extending from the upper bonding surface; and an electrically non-functional conductive pad disposed in the second cavity and extending from the upper bonding surface through at least a portion of the one or more non-conductive layers, the electrically non-functional conductive pad terminating at a second depth less than the first depth.

[0091] In some embodiments, the present disclosure is a method of preparing a semiconductor component, comprising forming at least one first cavity in an interconnect layer of the semiconductor component, the at least one first cavity extending from an upper surface of the interconnect layer to a buried conductive layer of the semiconductor component; forming at least one second cavity in the interconnect layer, the at least one second cavity laterally spaced apart from the at least one first cavity, the at least one second cavity extending from the upper surface of the interconnect layer and terminating at a depth of a dielectric layer above the buried conductive layer; providing conductive material in the first cavity and the second cavity; and preparing the upper surface of the interconnect layer for direct hybrid bonding to another component.

[0092] In one aspect of the present disclosure, the method further includes planarizing the upper surface by removing excess metal material outside the interconnect layer to form a bonding surface.

[0093] In another aspect of the present disclosure, the conductive material is metal. Furthermore, the conductive material is copper.

[0094] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise," "comprising," "include," "including," and the like are to be interpreted in an inclusive sense and not in an exclusive or exhaustive sense; that is, in the sense of "including but not limited to." The word "coupled," as generally used herein, means that two or more elements may be directly connected or may be connected by way of one or more intermediate elements. Similarly, the word "connected," as generally used herein, means that two or more elements may be directly connected or may be connected by way of one or more intermediate elements. Additionally, the words "herein," "above," "below," and the like, and words of similar meaning, when used in this application, shall refer to the entire application and not to any particular portion of this application. In addition, as used herein, when a first element is described as being "on" or "over" a second element, the first element may be directly on or above the second element so that the first and second elements are in direct contact, or the first element may be indirectly on or above the second element so that one or more elements are interposed between the first and second elements. Where the context permits, words used in the above specific embodiments in the singular or plural may also include the plural or singular, respectively. The word "or" refers to a list of two or more items, and the word encompasses all of the following interpretations of the word: any one of the items in the list, all of the items in the list, and any combination of the items in the list.

[0095] Furthermore, conditional language used herein, such as “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as,” and the like, unless expressly stated otherwise or understood otherwise from the context, is generally intended to convey that some embodiments include certain features, elements, and / or states, while other embodiments do not. Thus, such conditional language is generally not intended to imply that a feature, element, and / or state is in any way essential to one or more embodiments.

[0096] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein can be embodied in various other forms; in addition, various omissions, replacements, and changes can be made to the form of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although the boxes are presented in a given arrangement, alternative embodiments can utilize different components and / or circuit topologies to perform similar functionality, and some boxes can be deleted, moved, added, subdivided, combined, and / or modified. Each of the boxes can be implemented in a variety of different ways. Any suitable combination of the elements and actions of the various embodiments described above can be combined to provide additional embodiments. The attached claims and their equivalents are intended to cover various forms or modifications that fall within the scope and spirit of the present disclosure.

Claims

1. A device comprising: an interconnect structure having an upper surface prepared for direct bonding; a first contact pad extending to a first depth below the upper surface; as well as A second contact pad extends to a second depth below the upper surface, the second depth being less than the first depth. 2 . The device of claim 1 , wherein the first contact pad comprises an active pad electrically connected to an underlying interconnect. 3 . The device of claim 2 , wherein the first contact pad is directly connected to the underlying interconnect without an intervening via. 4 . The device of claim 2 , wherein the second contact pad comprises a dummy pad that is not electrically connected to the underlying interconnect. The device according to claim 1 , wherein the first contact pad and the second contact pad are made of metal. The device of claim 5 , wherein the first contact pad and the second contact pad are made of copper. The device of claim 1 , wherein the first contact pad is positioned in an opening having continuous sidewalls. 8 . The device of claim 1 , wherein the first contact pad is placed in an opening having sidewalls without corners. 9 . The device of claim 1 , wherein the first contact pad is formed by a single damascene process. 10 . The device of claim 1 , wherein the first pads and the second pads are substantially evenly distributed on the upper surface of the interconnect structure.

11. The device of claim 1, wherein the first pads and the second pads are substantially evenly distributed in the interconnect structure. 12 . The device of claim 1 , wherein a ratio of the second depth to the first depth is greater than 50%. The device of claim 12 , wherein a ratio of the second depth to the first depth is greater than 85%.

14. The device of claim 1, wherein the interconnect structure comprises a first dielectric layer including the upper surface, the first contact pad extending into the first dielectric layer, and the second contact pad.

15. A bonding structure comprising the device of claim 14 and a second component, the second component comprising a second dielectric layer and a third contact pad at least partially embedded in the second dielectric layer, wherein the first dielectric layer is directly bonded to the second dielectric layer without an adhesive, and the first contact pad is directly bonded to the third contact pad without an adhesive.

16. The device of claim 2, wherein the bottom layer interconnect is a redistribution layer (RDL) trace.

17. The device of claim 2, wherein the bottom layer interconnect is an outermost metal layer of a microelectronic device.

18. The device according to claim 2, further comprising: a device layer disposed on the interconnect structure; as well as The device layer includes circuitry electrically connected to the underlying interconnect.

19. The device of claim 18, wherein the device layer comprises a complementary metal oxide semiconductor (CMOS) device.

20. A device comprising: an interconnect structure having a surface prepared for direct bonding; as well as a plurality of pads embedded in the interconnect structure, the plurality of pads comprising: a first plurality of active pads; as well as A second plurality of dummy pads are provided, the dummy pads having a thickness less than that of the active pads.

21. The device of claim 20, wherein each of the first plurality of active pads is electrically connected to an underlying interconnect.

22. The device of claim 21, wherein each of the first plurality of active pads is directly connected to the underlying interconnect without an intervening via.

23. The device of claim 22, wherein each of the second plurality of dummy pads is not electrically connected to the underlying interconnect. The device of claim 22 , wherein the first plurality of active pads are formed by a single damascene process. The device according to claim 20 , wherein the plurality of pads are made of metal.

26. The device of claim 20, wherein the plurality of pads are made of copper.

27. The device of claim 20, wherein each active pad has integral sidewalls.

28. The device of claim 20, wherein each active pad has a sidewall without corners.

29. The device of claim 20, wherein the first plurality of active pads and the second plurality of dummy pads are substantially evenly distributed on the surface of the interconnect structure.

30. The device of claim 20, wherein the first plurality of active pads and the second plurality of dummy pads are substantially evenly distributed in the interconnect structure.

31. The device of claim 20, wherein the first plurality of active pads comprises more than one cross-sectional dimension.

32. The device of claim 20, wherein the second plurality of dummy pads comprises more than one cross-sectional dimension.

33. The device of claim 20, wherein the surface of the interconnect structure comprises: a first region having a first area density of active pads and dummy pads, the active pads and dummy pads having a first cross-sectional size; and a second region having a second area density of active pads and dummy pads having a second cross-sectional size, wherein the first area density is greater than the second area density, and the second cross-sectional size is greater than the first cross-sectional size.

34. The device of claim 20, wherein a ratio of a thickness of the dummy pad to a thickness of the active pad is greater than 50%. The device of claim 34 , wherein the ratio of the depth is greater than 85%.

36. The device of claim 20, wherein the interconnect structure comprises a first dielectric layer including the surface, the first plurality of active pads, and the second plurality of dummy pads extending into the first dielectric layer.

37. A bonding structure comprising the device of claim 36 and a second component, the second component comprising a second dielectric layer and a third plurality of contact pads at least partially embedded in the second dielectric layer, wherein the first dielectric layer is directly bonded to the second dielectric layer without an adhesive, and at least a portion of the first plurality of active pads is directly bonded to at least a portion of the third plurality of contact pads without an adhesive.

38. The device of claim 21, wherein the bottom layer interconnect is a redistribution layer (RDL) trace.

39. The device of claim 38, wherein each direct active pad to RDL trace direct connection comprises more than one active pad.

40. The device of claim 21, wherein the bottom layer interconnect is an outermost metal layer of a microelectronic device.

41. The device of claim 21 , further comprising: a device layer disposed together with the interconnect structure; as well as The device layer includes circuitry electrically connected to the underlying interconnect.

42. The device of claim 41, wherein the device layer comprises a complementary metal oxide semiconductor (CMOS) device.

43. A device comprising: a device portion, the device portion including a circuit device; an interconnect layer disposed on the device portion and having an upper bonding surface prepared for direct hybrid bonding to a second component, the interconnect layer comprising: one or more non-conductive layers on the device portion, the one or more non-conductive layers having a first cavity and a second cavity formed therein; a buried conductive layer electrically connected to the circuitry and embedded in the one or more non-conductive layers at a first depth below the upper bonding surface; an electrically functional conductive pad positioned in the first cavity and extending from the upper bonding surface through at least a portion of the one or more non-conductive layers to connect to the buried conductive layer, the first cavity being defined by continuous sidewalls of the one or more non-conductive layers extending from the upper bonding surface; and An electrically non-functional conductive pad is positioned in the second cavity and extends from the upper bonding surface through at least a portion of the one or more non-conductive layers, the electrically non-functional conductive pad terminating at a second depth less than the first depth.

44. The device of claim 43, wherein the electrically functional conductive pad is directly connected to the buried conductive layer without an intervening via.

45. The device of claim 43, wherein the electrically functional conductive pad and the electrically non-functional conductive pad are made of metal.

46. ​​The device of claim 45, wherein the electrically functional conductive pad and the electrically non-functional conductive pad are made of copper.

47. The device of claim 43, wherein the electrically functional conductive pad has integral sidewalls.

48. The device of claim 43, wherein the electrically functional conductive pad has sidewalls without corners.

49. The device of claim 43, wherein each of the first cavity and the second cavity is formed by a single damascene process.

50. The device of claim 43, wherein the functional conductive pads and the non-functional conductive pads are substantially evenly distributed on the upper bonding surface.

51. The device of claim 43, wherein the functional conductive pads and the non-functional conductive pads are substantially evenly distributed in the interconnect layer.

52. The device of claim 43, wherein a ratio of the second depth to the first depth is greater than 50%.

53. The device of claim 52, wherein a ratio of the second depth to the first depth is greater than 85%.

54. The device of claim 43, wherein the interconnect structure comprises: A first dielectric layer includes the upper surface, the first contact pad and the second contact pad extending into the first dielectric layer.

55. A bonding structure comprising a device according to claim 43 and a second element, the second element comprising a second non-conductive layer and a third conductive pad at least partially embedded in the second non-conductive layer, wherein the one or more non-conductive layers are directly bonded to the second non-conductive layer without an adhesive, and the electrically functional conductive pad is directly bonded to the third conductive pad without an adhesive.

56. The device of claim 43, wherein the buried conductive layer is a redistribution layer (RDL) trace.

57. The device of claim 43, wherein the buried conductive layer is an outermost metal layer of a microelectronic device.

58. The device of claim 43, wherein the device portion comprises a complementary metal oxide semiconductor (CMOS) device.

59. A method of manufacturing a semiconductor device, comprising: forming at least one first cavity in an interconnect layer of the semiconductor element, the at least one first cavity extending from an upper surface of the interconnect layer to a buried conductive layer of the semiconductor element; forming at least one second cavity in the interconnect layer, the at least one second cavity being laterally spaced apart from the at least one first cavity, the at least one second cavity extending from the upper surface of the interconnect layer and terminating at a depth of the dielectric layer above the buried conductive layer; providing a conductive material in the first cavity and the second cavity; as well as The upper surface of the interconnect layer is prepared for direct hybrid bonding to another component.

60. The method of claim 59, further comprising: The upper surface is planarized by removing excess metal material outside the interconnect layer to form a bonding surface.

61. The method of claim 59, wherein the conductive material is a metal.

62. The method of claim 61, wherein the conductive material is copper.

63. The method of claim 59, further comprising hybrid bonding the upper surface of the interconnect layer directly to the other component.

64. The method of claim 59, wherein forming at least one first cavity comprises forming the at least one first cavity by a single damascene process.

65. The method of claim 59, wherein forming at least one second cavity comprises forming the at least one second cavity by a single damascene process.

66. The method of claim 59, wherein the at least one first cavity has sidewalls without corners.

67. The method of claim 59, wherein the at least one first cavity has a continuous sidewall.

68. The method of claim 60, wherein the conductive material provided in the at least one first cavity and the at least one second cavity is substantially uniformly distributed on the bonding surface.

69. The method of claim 60, wherein the conductive material provided in the at least one first cavity and the at least one cavity is substantially uniformly distributed in the interconnect layer.

70. The method of claim 60, wherein a ratio of a depth of the second cavity to a depth of the first cavity is greater than 50%.

71. The method of claim 70, wherein a ratio of a depth of the second cavity to a depth of the first cavity is greater than 70%.

72. The method of claim 59, wherein the buried conductive layer is a redistribution layer (RDL) trace.

73. The method of claim 59, wherein the buried conductive layer is an outermost metal layer of a microelectronic device.

74. The method of claim 59, wherein the semiconductor element comprises a CMOS device.

75. A process for forming a bonding layer on a semiconductor component, the semiconductor having an outermost metal layer, the outermost metal layer having at least one metal trace, the process comprising: depositing a dielectric layer on the metallization layer, the dielectric layer having a top surface; patterning the top surface of the dielectric layer in a first region; etching the dielectric layer to create at least one first cavity, the at least one first cavity reaching the at least one metal trace of the metallization layer; patterning the top surface of the dielectric layer in a second region; etching the dielectric layer to create at least one second cavity extending partially through the dielectric layer and terminating above the metallization layer; as well as The first cavity and the second cavity are filled with metal.

76. The process of claim 75, further comprising planarizing the semiconductor element by removing excess metal material over the dielectric layer to form a bonding surface.

77. The process of claim 76, further comprising hybrid bonding the semiconductor element directly to another semiconductor element.

78. The process of claim 76, wherein the metal filled in the at least one first cavity and the at least one second cavity is substantially uniformly distributed on the bonding surface.

79. The process of claim 76, wherein the metal filled in the at least one first cavity and the at least one cavity is substantially uniformly distributed in the interconnect layer.

80. The process of claim 75, wherein the metal is copper.

81. The process of claim 75, wherein the depth of the second cavity is greater than 50% of the depth of the first cavity.

82. The process of claim 75, wherein the depth of the second cavity is greater than 85% of the depth of the first cavity.

83. The process of claim 75, wherein the metallization layer is a redistribution layer (RDL) trace.

84. The process of claim 83 wherein each first cavity connected to an RDL trace comprises more than one cavity.

85. The process of claim 75, wherein the semiconductor element comprises a CMOS device.

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