Power conversion apparatus

Abstract

The disclosed embodiments include methods, apparatuses, integrated circuits, and circuit boards for power conversion with reduced parasitic effects. The apparatus includes an integrated circuit for power conversion. The integrated circuit includes a plurality of power transistors and a plurality of metal regions coupled to the power transistors. A first portion of the metal region is coupled to a source region of the power transistor. A second portion of the metal region is coupled to a drain region of the power transistor. The first portion and the second portion have at least one of a substantially equal number of metal regions, a substantially equal resistance, or an equilibrium distribution of metal regions.

Description

[0001] Priority claim

[0002] This disclosure claims priority to U.S. patent application Ser. No. 18 / 053,973, filed on November 9, 2022, entitled “METHODS, APPARATUSES, INTEGRATED CIRCUITS, AND CIRCUIT BOARDS FOR POWER CONVERSION WITH REDUCED PARASITICS” (Attorney Docket No. 15794.0047-00000), the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates to power conversion, and more particularly, to methods, apparatus, integrated circuits, and printed circuit boards for power conversion with reduced parasitic losses. Background Art

[0004] Many electronic products, particularly mobile computing and / or communication products and components (e.g., laptops, ultrabooks, tablets, LCD and LED displays) require multiple voltage levels. For example, a power amplifier for a radio frequency transmitter may require a relatively high voltage (e.g., 12 volts (V) or greater), while logic circuitry may require a low voltage level (e.g., 1V to 2V). Some other circuitry may require an intermediate voltage level (e.g., 5V to 10V). Power converters are typically used to generate lower or higher voltages from a common power source (e.g., a battery) to meet the power requirements of different components in an electronic product. Summary of the Invention

[0005] Embodiments of the present disclosure may provide methods, devices, integrated circuits, and circuit boards for power conversion with reduced parasitic effects.

[0006] These embodiments include an apparatus for power conversion. The apparatus includes an integrated circuit for power conversion. The integrated circuit includes a plurality of power transistors and a plurality of metal regions coupled to the power transistors. A first portion of the metal regions is coupled to a source region of the power transistor. A second portion of the metal regions is coupled to a drain region of the power transistor. The first portion and the second portion have at least one of a substantially equal number of metal regions, substantially equal resistance, or a balanced distribution of the metal regions.

[0007] These embodiments also include a power transistor for power conversion. The power transistor includes multiple active areas, multiple terminals, and multiple conductive paths. Each terminal is electrically coupled to at least one of the active areas via at least one of the conductive paths. Each conductive path includes one or more transversely oriented metal conductors and one or more vertically oriented metal conductors. In most of the conductive paths, the sum of the lengths of the one or more vertically oriented metal conductors exceeds the sum of the lengths of the one or more transversely oriented metal conductors.

[0008] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram of an exemplary apparatus for power conversion according to an embodiment of the present disclosure.

[0010] Figure 2A is a top view of an exemplary apparatus for power conversion according to an embodiment of the present disclosure.

[0011] Figure 2B According to the embodiment of the present disclosure Figure 2A A diagram of an exemplary integrated circuit for power conversion in FIG.

[0012] Figure 2C According to the embodiment of the present disclosure Figure 2B A diagram of exemplary input and output terminals of an exemplary integrated circuit in FIG.

[0013] Figure 2D According to the embodiment of the present disclosure Figure 1 Another top view of an exemplary apparatus for power conversion in FIG.

[0014] Figure 2E According to the embodiment of the present disclosure Figure 1 A cross-sectional view of an exemplary device for power conversion in FIG.

[0015] Figure 2F According to the embodiment of the present disclosure Figure 2E A cross-sectional view of an exemplary integrated circuit and circuit board for power conversion in FIG.

[0016] Figure 3A is a cross-sectional view of another exemplary circuit board and integrated circuit for power conversion according to an embodiment of the present disclosure.

[0017] Figure 3B is a cross-sectional view of an exemplary apparatus for power conversion according to an embodiment of the present disclosure.

[0018] Figure 4 is a block diagram of an exemplary integrated circuit for power conversion according to an embodiment of the present disclosure.

[0019] Figure 5A is a cross-sectional view of an exemplary integrated circuit for power conversion according to an embodiment of the present disclosure.

[0020] Figure 5B is a perspective view of a metal region of an exemplary integrated circuit for power conversion according to an embodiment of the present disclosure.

[0021] Figure 6A is a top view of a redistribution layer (RDL) region and an active area of ​​an exemplary integrated circuit for power conversion, according to some embodiments.

[0022] Figure 6B is a top view of an RDL region, a gate region, and an active region of an exemplary integrated circuit for power conversion according to some embodiments.

[0023] Figure 7A is a top view of a metal 4 (M4) region and active areas of an exemplary integrated circuit for power conversion, according to some embodiments.

[0024] Figure 7B is a top view of four M4 regions and six active regions of an exemplary integrated circuit for power conversion according to some embodiments.

[0025] Figure 7C is a top view of the M4 region, a via between metal layers 4 and 3 (V43 via), and an active area of ​​an exemplary integrated circuit for power conversion, according to some embodiments.

[0026] Figure 7D is a top view of five M4 regions, V43 vias, and six active areas of an exemplary integrated circuit for power conversion according to some embodiments.

[0027] Figure 8A is a top view of a metal 3 (M3) region and active areas of an exemplary integrated circuit for power conversion, according to some embodiments.

[0028] Figure 8B is a top view of eight M3 regions and two active regions of an exemplary integrated circuit for power conversion according to some embodiments.

[0029] Figure 8C is a top view of four M4 regions and eight M3 regions of an exemplary integrated circuit for power conversion according to some embodiments.

[0030] Figure 8D is a top view of a via (V32 via) between metal layers 3 and 2 and an active area of ​​an exemplary integrated circuit for power conversion, according to some embodiments.

[0031] Figure 8E is a top view of eight M3 regions, V32 vias, and two active regions of an exemplary integrated circuit for power conversion according to some embodiments.

[0032] Figure 9A is a top view of a metal 2 (M2) region and active areas of an exemplary integrated circuit for power conversion, according to some embodiments.

[0033] Figure 9B is a top view of the M2 region and six active regions of an exemplary integrated circuit for power conversion according to some embodiments.

[0034] Figure 9C is a top view of the M3 region and the M2 region of an exemplary integrated circuit for power conversion according to some embodiments.

[0035] Figure 10A is a top view of a metal 1 (M1) region and active areas of an exemplary integrated circuit for power conversion, according to some embodiments.

[0036] Figure 10B is a top view of the M1 region and active area of ​​an exemplary integrated circuit for power conversion according to some embodiments.

[0037] Figure 10C is a top view of the M1 region and a portion of the active area of ​​an exemplary integrated circuit for power conversion according to some embodiments.

[0038] 10D is a top view of the M1 region, a via between metal layers 2 and 1 (V21 via), and a portion of the active area of ​​an exemplary integrated circuit for power conversion, according to some embodiments.

[0039] Figure 11 is a top view of two M2 regions, multiple gate regions, and a portion of an active area of ​​an exemplary integrated circuit for power conversion according to some embodiments.

[0040] Figure 12 The embodiment according to the present disclosure is shown Figure 1 An exemplary configuration mode of an exemplary apparatus for power conversion in FIG.

[0041] Figure 13 According to the embodiment of the present disclosure Figure 1 A circuit diagram of an exemplary apparatus for power conversion in FIG. DETAILED DESCRIPTION

[0042] The following disclosure provides many different exemplary embodiments or examples for realizing the different features of the provided subject matter. Specific simplified examples of components and arrangements are described below to illustrate the present disclosure. Of course, these are merely examples and are not intended to be restrictive. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0043] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples in this specification, including examples of any term discussed herein, is illustrative only and in no way limits the scope and meaning of the present disclosure or the scope and meaning of any exemplified term. Likewise, the present disclosure is not limited to the various embodiments given in this specification.

[0044] Although the terms "first", "second", etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, without departing from the scope of the embodiment, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumeration items.

[0045] For ease of description, spatially relative terms such as "below," "beneath," "below," "above," "upper," and the like may be used herein to describe one element or a characteristic relationship to another element or feature as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0046] In this disclosure, the term “coupled” may also be referred to as “electrically coupled,” and the term “connected” may be referred to as “electrically connected.” “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

[0047] A power converter may receive, deliver, or operate at high currents in one or more of the current paths. Power delivery paths and operation at high currents may be susceptible to parasitic losses that negatively impact performance. Parasitic losses can be described as I 2The product of I and R, where "I" is the current and "R" is the resistance. As current increases, power losses become more significant. For example, the power delivery path and high currents of some buck converters can reduce their power conversion efficiency due to parasitic losses. Additional constraints can further exacerbate undesirable parasitic losses. For example, die space may be limited, forcing signals to fan out on the printed circuit board (PCB) and be routed as needed.

[0048] The disclosed embodiments may include designs that reduce the inductor requirements of a buck converter. For example, an embodiment may place a charge pump converter between the input power and the buck converter. Because this arrangement reduces the inductor requirements of the buck converter, it may allow embodiments to use chip inductors for the buck converter even at relatively high input voltages (e.g., 12 volts (V)). For example, the charge pump converter may step down the input voltage before it is provided to the buck converter. Allowing the buck converter to operate using a stepped-down voltage may reduce the demand on its associated inductor, allowing a smaller chip inductor to be used in place of a larger inductor that takes up additional space.

[0049] The disclosed embodiments can include additional benefits. As an example, the disclosed embodiments can utilize inductors to bring the converter's power nodes to the edge, which can free up peripheral space on the PCB. This mechanism for routing power can reduce the number of layers on the PCB or module used to route all signals.

[0050] As another example, the disclosed embodiments can position the output terminals of a buck converter in a manner that allows the use of coupled inductors. Disclosed embodiments can position the buck converter output terminals adjacent to each other along the same edge of the converter, rather than routing power radially and placing the output terminals diametrically opposite each other to reduce parasitic effects. For example, by placing four voltage output terminals at the four corners of a circuit layout, a radial design can limit the feasibility of connecting the output terminals to increase the output amperage supply. The disclosed embodiments can address this issue by placing the output terminals adjacent to each other and routing the current vertically. Placing the output terminals nearby allows two or more output terminals to be connected to more easily supply additional current to the load. Placing the output nodes of the buck converter adjacent on the same side of the device can also advantageously allow the use of coupled inductors. For example, in the case of multiple voltage output terminals from a buck converter on the same die, two or more output terminals can be connected to the same coupled inductor. This arrangement may not be feasible when the inductor connection locations are radially dispersed. Furthermore, using coupled inductors can reduce the overall inductor size requirement, thereby providing the additional advantage of space saving.

[0051] While embodiments of the present disclosure can address these challenges and provide these benefits, the problems and features described are intended to be exemplary and not to limit the claims or scope of the present disclosure. Indeed, the disclosed embodiments can address challenges and provide benefits not explicitly recited.

[0052] Figure 1 is a diagram of an exemplary apparatus 100 for power conversion according to the disclosed embodiments. Figure 1 As shown in FIG, apparatus 100 may include an integrated circuit 110, a circuit board 120, and inductors 131, 132, 133, and 134. Integrated circuit 110 may include power conversion circuitry and may be coupled to circuit board 120 for power conversion. Circuit board 120 may include circuitry (not shown) for fanning out signals from integrated circuit 110. Inductors 131, 132, 133, and 134 may be coupled to circuit board 120 and electrically connected to integrated circuit 110 to form a circuit as shown in FIG. Figure 1 The four buck converters shown in BUCK 1, BUCK 2, BUCK 3 and BUCK 4 can convert the input power V IN Converted into output power V OUT-1 、V OUT-2 、V OUT-3 and V OUT-4 .

[0053] Inductors 131, 132, 133, and 134 can be chip inductors that can be characterized as small packages and can be used in various applications including power conversion and high-frequency circuit systems. Chip inductors can be inductors that adopt a chip form factor for integrated circuits used in electronic devices. Chip inductors can be used in power converters, RF transceivers, computers, and other electronic devices. Example chip inductors can include a ferrite core with wire windings, or can have multiple layers of wire. Chip inductors can provide benefits in converting voltages and can be used to form filter circuits and resonant circuits. As compared to conventional discrete inductors, chip inductors can be more compact and can weigh less.

[0054] like Figure 1 As shown in FIG, the integrated circuit 110 may include a circuit for inputting a voltage V IN A charge pump converter is used to step down the voltage. The charge pump converter can be placed at the input voltage V IN The charge pump converter can be connected to the four step-down converters BUCK 1, BUCK 2, BUCK 3 and BUCK4. IN (For example, 12V) is supplied to the buck converters BUCK 1, BUCK 2, BUCK 3 and BUCK 4 before the input voltage VIN The stepped-down voltage can reduce the demand on inductors 131, 132, 133, and 134. In some embodiments, inductors 131, 132, 133, and 134 can therefore be implemented as chip inductors rather than larger inductors that take up additional space.

[0055] During power conversion, current can flow through the plurality of conductive lines ( Figure 1 131, 132, 133, and 134. As described below, the conductive traces may extend perpendicular to the surface of circuit board 120. Thus, current may flow perpendicular to the surface of circuit board 120, and thus perpendicular to circuits on circuit board 120, such as circuits for fanning out signals. This may result in low parasitic effects, such as parasitic capacitors and parasitic inductors, from those circuits on circuit board 120. Apparatus 100 may convert power with low parasitic effects and provide efficient power conversion.

[0056] In some embodiments, the integrated circuit 110 of the apparatus 100 may include a charge pump converter ( Figure 1 The integrated circuit 110 may further include at least two buck converters (eg, buck converters BUCK 1, BUCK 2, BUCK 3, and BUCK 4). Figure 1 ) of the buck converter circuit system. At least two of the inductors 131, 132, 133, and 134 may include chip inductors. At least two buck converters (eg, BUCK 1 and BUCK 2 ( Figure 1 )) can be achieved through conductive lines (eg, conductive lines 121a and 121b ( Figure 2F )) are connected to at least two chip inductors (eg, inductors 131 and 132 ( Figure 1 )) in the corresponding chip inductor.

[0057] Figure 2A According to the disclosed embodiment Figure 1 A top view of an exemplary apparatus 100 for power conversion is shown in FIG. Figure 2A As shown in FIG, the apparatus 100 may include the apparatus 100 as described above with reference to FIG. Figure 1 The depicted coupled integrated circuit 110, circuit board 120, and inductors 131, 132, 133, and 134. Inductors 131, 132, 133, and 134 can each have a value of 330 nanohenries (nH). In some embodiments, inductors 131, 132, 133, and 134 can each have a value of 100 nH, 200 nH, 470 nH, or other values.

[0058] The integrated circuit 110 may be packaged by, for example, a ball grid array (BGA) package and may include a plurality of conductor balls for inputting and outputting signals. Among these conductor balls, the integrated circuit 110 may include a first plurality of conductor balls LX1 ( Figure 2B ), a second plurality of conductor balls LX2 ( Figure 2B ), a third plurality of conductor balls LX3 ( Figure 2B ), and a fourth plurality of conductor balls LX4 ( Figure 2B That is, the conductor balls LX1 , LX2 , LX3 , and LX4 may be output terminals of the integrated circuit 110 , which are used to output current to the conductors 131 , 132 , 133 , and 134 through the conductive lines of the circuit board 120 .

[0059] exist Figure 2A , regions LX1, LX2, LX3, and LX4 may indicate that the conductor balls LX1, LX2, LX3, and LX4 of the integrated circuit 110 may be within these regions. In other words, the output terminals of the integrated circuit 110 (e.g., the conductor balls LX1, LX2, LX3, and LX4) may be below the inductors 131, 132, 133, and 134. Therefore, at least a portion of the integrated circuit 110 (including the conductor balls LX1, LX2, LX3, and LX4) and the internal circuits connected thereto may be below the inductors 131, 132, 133, and 134.

[0060] like Figure 2A As shown in FIG, output terminals for outputting current (eg, conductor balls LX1, LX2, LX3, and LX4) may be within the right half of the integrated circuit 110. The integrated circuit 110 may also include a plurality of conductor balls V for receiving input power. IN Conductor sphere V IN is the input terminal of the integrated circuit 110 and can be Figure 2A In some embodiments, the output terminal for outputting current may be in the left half, upper half, or lower half of the integrated circuit 110. The conductive ball may be in the right half, lower half, or upper half of the integrated circuit 110, respectively.

[0061] In some embodiments, the conductive traces may be located on a common edge of the circuit board. Figure 2AAs shown in , the output terminals for outputting current (e.g., conductor balls LX1, LX2, LX3, and LX4) can be arranged into several lines along the ball grid array. When the integrated circuit 110 is mounted to the circuit board 120, the output terminals for outputting current can be mounted on the edge of the circuit board 120 for easy connection to the inductors 131, 132, 133, and 134. In these embodiments, the conductive lines can be on the edge of the circuit board 120.

[0062] Figure 2B According to the disclosed embodiment Figure 2A FIG. 1 is a diagram of an exemplary integrated circuit 110 for power conversion. Figure 2B As shown in FIG, the integrated circuit 110 may include a plurality of conductive balls V IN , multiple conductor balls CB1, multiple conductor balls VX, multiple conductor balls P2, multiple conductor balls GND, multiple conductor balls P1, multiple conductor balls CB2, conductor balls LX1, LX2, LX3 and LX4 and multiple conductor balls I / O. Figure 2B In the embodiment, the conductor balls without reference numerals may be used for the same functions as the conductor balls with the same reference numerals. These conductor balls are input terminals and output terminals of the integrated circuit 110 and may be coupled to peripheral circuits for power conversion, such as Figure 13 As shown in .

[0063] exist Figure 2B In FIG, the conductor balls LX1, LX2, LX3, and LX4, as well as VX, corresponding to the four buck converters are also shown by the dashed blocks BUCK 1, BUCK 2, BUCK 3, and BUCK 4. The conductor balls LX1 and VX within the dashed block BUCK 1 can be used for buck converter BUCK 1. The conductor balls LX2 and VX within the dashed block BUCK 2 can be used for buck converter BUCK 2. The conductor balls LX3 and VX within the dashed block BUCK 3 can be used for buck converter BUCK 3. The conductor balls LX4 and VX within the dashed block BUCK 4 can be used for buck converter BUCK 4.

[0064] like Figure 2B As shown in FIG, output terminals for outputting current (including conductor balls LX1, LX2, LX3, and LX4) may be arranged in those portions within the dotted-line blocks BUCK 1, BUCK 2, BUCK 3, and BUCK 4. These portions of the integrated circuit 110 may be located within the inductors 131, 132, 133, and 134 ( Figure 2A or Figure 2D ) below.

[0065] On the other hand, Figure 2BAs shown in FIG, output terminals for outputting current (including conductor balls LX1, LX2, LX3, and LX4) can be placed adjacently along the same edge of integrated circuit 110. This can allow two or more of the output terminals to be connected to more easily supply additional current to a load. Having the output terminals (including conductor balls LX1, LX2, LX3, and LX4) adjacent on the same side of integrated circuit 110 and / or device 100 can also advantageously allow coupled inductors to be used in different configurations, as described below with reference to FIG. Figure 12 shown.

[0066] Figure 2C According to the disclosed embodiment Figure 2B FIG. 1 is a diagram illustrating exemplary input and output terminals of an exemplary integrated circuit 110 for power conversion. Figure 2C As shown in FIG, the input terminals and output terminals of the integrated circuit 110 may include conductive balls V IN , conductor ball CB1, conductor ball VX, conductor ball P2, conductor ball GND, conductor ball P1, conductor ball CB2, conductor balls LX1, LX2, LX3 and LX4 and conductor ball I / O. Figure 2C , those conductor balls without reference numerals can be used for the same purpose as those conductor balls with reference numerals having the same pattern.

[0067] Figure 2D According to the disclosed embodiment Figure 1 Another top view of an exemplary apparatus 100 for power conversion in FIG. Figure 2D As shown in FIG, the apparatus 100 may include the apparatus 100 as described above with reference to FIG. Figure 1 The integrated circuit 110, the circuit board 120, and the inductors 131, 132, 133, and 134 are described as being coupled. The inductors 131, 132, 133, and 134 can share an inductor core 135 and thus can be coupled together as a coupled inductor. The inductors 131, 132, 133, and 134 can be coupled for various configurations, as described below with reference to Figure 12 A coupled inductor has two or more windings on a common core. Coupled inductors function in DC-DC converters by transferring energy from one winding to the other through the common core. By coupling two or more inductors, a power converter can efficiently provide a desired output voltage and / or current.

[0068] like Figure 2D As shown in , at least a portion of integrated circuit 110 may be below inductors 131 , 132 , 133 , and 134 .

[0069] Figure 2E According to the disclosed embodiment Figure 1 FIG. 1 is a cross-sectional view CC' of an exemplary device 100. Figure 2E As shown in FIG, an apparatus 100 for power conversion may include an integrated circuit 110, a circuit board 120, and an inductor 130. The inductor 130 may include inductors 131, 132, 133, and 134.

[0070] The integrated circuit 110 is part of the power converter and can be mounted to the circuit board 120. The integrated circuit 110 can be coupled to a plurality of conductive lines ( Figure 2F ), to convert multiple vertical currents I VTC is transmitted to the inductor 130. Figure 2E As shown in the figure, the vertical current I VTC It can be vertical to the surface 121 of the circuit board 120, for example. In one example, the vertical current I VTC It can be 4A, 8A or 16A.

[0071] The circuit board 120 may include surfaces 121 and 122, metal layers M1, M2, M3, and M4, and a plurality of conductive traces between the metal layers M1 and M2 and between the metal layers M3 and M4. The surfaces 121 and 122 are two sides of the circuit board 120. The conductive traces between the metal layers M1 and M2 ( Figure 2F ) may extend in a direction perpendicular to the surface 121 of the circuit board 120. The inductor 130 may be mounted on the surface 121 of the circuit board 120 and may be electrically coupled to the integrated circuit 110 through a conductive trace between the metal layers M1 and M2. Figure 2E As shown in , at least a portion of the integrated circuit 110 may be below the inductor 130 .

[0072] As mentioned above, the vertical current I VTC It can be vertical to, for example, the surface 121 of the circuit board 120. The device 100 can receive, generate, and operate using high currents. Power delivery and operation at high currents can be susceptible to parasitic losses that reduce the power conversion efficiency of the buck converters BUCK 1, BUCK 2, BUCK 3, and BUCK 4. In addition, the size of the integrated circuit 110 can be small, such as compared to an inductor, thereby forcing the signal to fan out on the circuit board 120 and be routed as needed. This can exacerbate parasitic effects on the device 100. Vertical current I VTC The arrangement can reduce such negative parasitic effects. By reducing parasitic effects, the device 100 can efficiently convert power. In some embodiments, a vertical current I is used between the integrated circuit 110 and the inductor 130. VTCIt can also facilitate adjacent placement of output terminals (including conductor balls LX1, LX2, LX3, and LX4). Adjacent placement of output terminals can allow coupled inductors to be used in different configurations of device 100 for power conversion. It can also allow the use of chip inductors, thereby reducing the size of device 100.

[0073] Figure 2F According to the disclosed embodiment Figure 2E A cross-sectional view of an exemplary integrated circuit 110 and a circuit board 120 is shown in FIG. Figure 2F As shown in FIG, the circuit board 120 may include a plurality of conductive lines 121a, 121b, 121c, and 121d from the metal layer M2 to the metal layer M1. Conductor balls LX1, LX2, LX3, and LX4 ( Figure 2B or Figure 2C )—that is, the output terminal of the integrated circuit 110—can be directly coupled to the conductive lines 121a, 121b, 121c, and 121d to transfer the vertical current I VTC Output to conductor 130 ( Figure 2E ).like Figure 2F As shown in FIG, the conductive lines 121a, 121b, 121c, and 121d may extend directly from the conductor balls LX1, LX2, LX3, and LX4 in a direction perpendicular to the surface 121 and extend to the inductor 130 ( Figure 2E ).

[0074] like Figure 2E and Figure 2F As shown in FIG, the integrated circuit 110 may be embedded inside the circuit board 120. The circuit board 120 has layers D1, D2, and D3. Layer D2 may be between layers D1 and D3. The integrated circuit 110 may be mounted in layer D2.

[0075] like Figure 2F As shown in FIG, circuit board 120 may have metal layers M1 and M2. Conductive traces 121a, 121b, 121c, and 121d may be coupled between metal layers M1 and M2. Integrated circuit 110 may be coupled to conductive traces 121a, 121b, 121c, and 121d in metal layer M2.

[0076] exist Figure 2F In the embodiment, the circuit board 120 may include a first plurality of terminals 121a-M1, 121b-M1, 121c-M1, and 121d-M1 on the surface 121. The terminals 121a-M1, 121b-M1, 121c-M1, and 121d-M1 may be coupled to first ends of the conductive traces 121a, 121b, 121c, and 121d, and may be coupled to the inductor 130 ( Figure 2E). The circuit board 120 may also include a second plurality of terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2, which are coupled to the other ends of the conductive lines 121a, 121b, 121c, and 121d in the metal layer M2. The terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 may be coupled to the integrated circuit 110 for power conversion. Figure 2F As shown in FIG, the terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 may be below the terminals 121a-M1, 121b-M1, 121c-M1, and 121d-M1.

[0077] like Figure 2F As shown in FIG, conductive traces 121a, 121b, 121c, and 121d may extend directly from terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 in a direction perpendicular to surface 121 and to terminals 121a-M1, 121b-M1, 121c-M1, and 121d-M1. Terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 may be inside circuit board 120 in metal layer M2.

[0078] As shown above, the circuit board 120 has layers D1, D2, and D3. Layer D2 may be between layers D1 and D3. Terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 may be on the side of layer D2.

[0079] like Figure 2F As shown in FIG, conductive lines 121a, 121b, 121c, and 121d may be coupled between metal layers M1 and M2. Terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 may be in metal layer M2. Conductive lines 121a, 121b, 121c, and 121d may be configured to conduct vertical current I VTC The vertical current I is transmitted from the terminals 121a-M2, 121b-M2, 121c-M2 and 121d-M2 to the terminals 121a-M1, 121b-M1, 121c-M1 and 121d-M1. VTC The flow may be in a direction perpendicular to the surface 121 of the circuit board 120 .

[0080] Figure 3A FIG is a cross-sectional view of another exemplary circuit board 140 and integrated circuit 110 for power conversion according to the disclosed embodiments. Figure 3AAs shown in FIG, the circuit board 140 may include surfaces 141 and 142, metal layers M1 and M2, and a plurality of conductive traces 141a, 141b, 141c, and 141d. The integrated circuit 110 may be mounted on the surface 142. The conductive traces 141a, 141b, 141c, and 141d may have the same Figure 2F Conductive traces 141a, 141b, 141c, and 141d may couple the integrated circuit 110 mounted on surface 142 with a conductor (e.g., inductor 130) mounted on surface 141. Figure 2E ))between.

[0081] like Figure 3A As shown in FIG, the circuit board 140 may include a first plurality of terminals 141a-M1, 141b-M1, 141c-M1, and 141d-M1 on the surface 141. The terminals 141a-M1, 141b-M1, 141c-M1, and 141d-M1 may be in the metal layer M1 and coupled to the first ends of the conductive lines 141a, 141b, 141c, and 141d. The terminals 141a-M1, 141b-M1, 141c-M1, and 141d-M1 may be used to couple to an inductor (e.g., the inductor 130) on the surface 141. Figure 2E )). The circuit board 120 may also include a second plurality of terminals 141a-M2, 141b-M2, 141c-M2, and 141d-M2 in the metal layer M2. The terminals 141a-M2, 141b-M2, 141c-M2, and 141d-M2 may be coupled to the other ends of the conductive lines 141a, 141b, 141c, and 141d. The terminals 141a-M2, 141b-M2, 141c-M2, and 141d-M2 may be on the surface 142 and coupled to the integrated circuit 110. Figure 3A As shown in FIG, terminals 141a-M2, 141b-M2, 141c-M2, and 141d-M2 may be below terminals 141a-M1, 141b-M1, 141c-M1, and 141d-M1.

[0082] The conductive lines 141a, 141b, 141c and 141d may be configured to transfer the vertical current I VTC The vertical current I is transmitted from the terminals 141a-M2, 141b-M2, 141c-M2 and 141d-M2 on the surface 142 to the terminals 141a-M1, 141b-M1, 141c-M1 and 141d-M1 on the surface 141. VTC The current may flow in a direction perpendicular to the surfaces 141 and 142 and then flow to the inductor (eg, the inductor 130 ( Figure 2E )).

[0083] Figure 3B is a cross-sectional view of an exemplary apparatus 200 for power conversion according to an embodiment of the present disclosure. Figure 3B As shown in FIG, the apparatus 200 may include an integrated circuit 110 ( Figure 3A )、PCB 140( Figure 3A ), molded component 220 and molded power inductor 230. Integrated circuit 110 can be as described above with reference to Figure 3A The described embodiment is mounted on a circuit board 140 and operates. The conductive trace 141 of the circuit board 140 may include conductive traces 141a, 141b, 141c, and 141d ( Figure 3A ) and may be configured to transfer vertical current from the integrated circuit 110 to the molded power inductor 230. The molded component 220 may include a Figure 13 The capacitors and resistors in the molded capacitors and / or molded resistors.

[0084] Figure 4 is a block diagram of an exemplary integrated circuit 110 for power conversion according to the disclosed embodiments. Figure 4 As shown in FIG, the integrated circuit 110 may include a conversion circuit 112 and a controller 114. The controller 114 may include circuitry configured to control a plurality of switches in the conversion circuit 112 for power conversion in various configurations, as described below with reference to FIG. Figure 12 described.

[0085] Figure 5A is a cross-sectional view of an exemplary integrated circuit 110 for power conversion according to the disclosed embodiments. Figure 5A As shown in FIG, the integrated circuit 110 may include: a substrate; an active region (AR) in the AR layer; a plurality of six metal 1 (M1) regions in the M1 layer; three metal 2 (M2) regions 201, 202, and 203 in the M2 layer; six metal 3 (M3) regions in the M3 layer; three metal 4 (M4) regions 401, 402, and 403 in the M4 layer; six vias (V1 vias) between the six M1 regions and the active region; six vias (V21 vias) between the M2 region and the M1 region; six vias (V32 vias) between the M3 region and the M2 region; and six vias (V43 vias) between the M4 region and the M3 region. The AR region includes a plurality of power transistors.

[0086] When the integrated circuit 110 inputs power V IN ( Figure 1 ) is converted to V OUT-1 、V OUT-2 、V OUT-3 and V OUT-4When the controller 114 of the integrated circuit 110 is configured to generate a horizontal current i between the transistors AR-LAT and from the transistor to, for example, the circuit board 120 ( Figure 2F ) of terminals 121a-M2, 121b-M2, 121c-M2 and 121d-M2 ( Figure 2F ) of the vertical current i VTC To operate the transistor. Figure 5A As shown in the figure, the vertical current i VTC The vertical current i VTC Can be used as vertical current I VTC ( Figure 2F ) flows through terminals 121a-M2, 121b-M2, 121c-M2 and 121d-M2, and enters conductive lines 121a, 121b, 121c and 121d ( Figure 2F ).

[0087] like Figure 5A As shown in FIG, the power transistor in the active area is in the AR layer. The M4 region, M3 region, M2 region, and M1 region are arranged in a stacked manner, coupled together by V43 vias, V32 vias, V21 vias, and V1 vias, and coupled to the source region and drain region of the power transistor in the active area. The stacked M4 region, M3 region, M2 region, and M1 region, as well as the V43 vias, V32 vias, V21 vias, and V1 vias are vertically oriented metal conductors that are configured to provide multiple conductive paths for vertical current i VTC Within the integrated circuit 110, current flows between the power transistors in the AR layer and the M4 regions 401, 402, and 403 in the M4 layer. Figure 5A As shown in FIG, there are six vertical currents i flowing along the Z axis between the AR layer and the M4 layer. VTC-1 to i VTC-6 .

[0088] As compared to the M3 layer, the M2 layer, the M1 layer, and the AR layer, the M4 layer is above the AR layer and is considered an upper layer within the integrated circuit 110. In some embodiments, as compared to the M2 layer, the M1 layer, and the AR layer, the M3 layer is above the AR layer and is considered an upper layer within the integrated circuit 110. In some embodiments, the integrated circuit 110 may further include an RDL region in an RDL layer above the M4 layer. The RDL region is coupled to the M4 region 402 through a via (VR4 via) between the RDL layer and the M4 layer and extends in the Y-axis direction to redistribute current. The integrated circuit 110 may include a via coupled to the RDL ( Figure 5A ) of multiple terminals (for example, Figure 2CVX, LX1, LX2, LX3 and LX4 in the .

[0089] like Figure 5A As shown in FIG, many areas of the M4 region, the M3 region, the M2 region, and the M1 region are also laterally oriented metal conductors configured to provide multiple conductive paths for lateral current i LAT For example, in the M2 layer there are three lateral currents i M2-LAT-1 to i M2-LAT-3 , and there are two lateral currents i flowing along the X-axis in the M4 layer M4-LAT-1 and i M4-LAT-2 There are two transverse currents i flowing along the Y axis in the M3 layer. M3-LAT-1 and i M3-LAT-2 . Transverse current i M2-LAT The X-axis direction and the transverse current i M3-LAT The Y-axis direction is perpendicular to the vertical current i VTC (including vertical current i VTC-1 to i VTC-6 ) in the Z-axis direction.

[0090] Thus, integrated circuit 110 may include multiple conductive paths electrically coupled between terminals coupled to the RDL and power transistors in the AR layer. Each terminal may be electrically coupled to at least one of the power transistors via at least one of the conductive paths. Each conductive path includes one or more laterally oriented metal conductors and one or more vertically oriented metal conductors. In a majority of the conductive paths of integrated circuit 110, the sum of the lengths of the one or more vertically oriented metal conductors exceeds the sum of the lengths of the one or more laterally oriented metal conductors.

[0091] like Figure 5AAs shown in FIG, M4 regions 401, 402, and 403 are thicker than M3 regions. Therefore, M4 regions 401, 402, and 403 have a lower resistance than M3 regions. M3 regions are thicker than M2 regions 201, 202, and 203. Therefore, M3 regions have a lower resistance than M2 regions 201, 202, and 203. M2 regions 201, 202, and 203 are thicker than M1 regions. In other words, the metal regions in the upper layer have a lower resistance than the metal regions in the lower layer. M4 regions 401, 402, and 403, the six M3 regions, M2 regions 201, 202, and 203, and the six M1 regions may be laterally oriented metal conductors in integrated circuit 110. In other words, in integrated circuit 110, the resistance of each laterally oriented metal conductor in the M2 layer is lower than the resistance of each laterally oriented metal conductor in the M1 layer. The resistance of each laterally oriented metal conductor in the M3 layer is lower than the resistance of each laterally oriented metal conductor in the M2 layer. The resistance of each laterally-oriented metal conductor in the M4 layer is less than the resistance of each laterally-oriented metal conductor in the M3 layer.

[0092] In some embodiments, integrated circuit 110 may include an M4 region, an M3 region, an M2 region, and an M1 region as laterally oriented metal conductors for conductive paths. Specifically, the laterally oriented metal conductors of integrated circuit 110 may include an M1 metal conductor in the M1 layer above the power transistor and an M2 metal conductor in the second metal layer above the first metal layer. The laterally oriented metal conductors may also include an M3 metal conductor in the M3 layer above the second metal layer and an M4 metal conductor in the M4 layer above the M3 layer. The width of the M1 metal conductor is smaller than the width of the M2 metal conductor. The width of the M2 metal conductor is smaller than the width of the M3 metal conductor. The width of the M3 metal conductor is smaller than the width of the M4 metal conductor.

[0093] Therefore, when two conductive paths are available through the upper and lower regions, lateral current flow is more likely to occur and flow through the upper metal region rather than the lower region. VTC-1 to i VTC-6 The total amount can be 0.5 milliamperes (mA). M4-LAT-1 、i M4-LAT-2 、i M3-LAT-1 、i M3-LAT-2 and i M2-LAT-1 to i M2-LAT-3 The total amount can be 0.1mA. VTC The total amount (0.5mA) is greater than the transverse current i M4-LAT 、i M3-LAT and i M2-LAT total amount (0.1mA).

[0094] Integrated circuit 110 also includes conductor balls LX1, LX2, LX3, and LX4 ( Figure 2A ) as an output terminal coupled to a conductive path ( Figure 5A The conductor balls LX1, LX2, LX3 and LX4 of the integrated circuit 110 are configured to be stacked via the RDL region ( Figure 5A ) The vertical current i VTC (For example, Figure 5A The vertical current i VTC-3 and i VTC-4 ) is output to at least a portion of the inductors 131, 132, 133, and 134 ( Figure 2A ).

[0095] For example, the M4 regions 401, 402, and 403 may have a thickness (length along the Z-axis direction) of 35 micrometers (μm). The M4 regions 401, 402, and 403 may also have a width (W M4 ), that is, W M4 =35 μm. The six M3 regions may have a thickness of 17 μm. The M3 regions may also have a width (W M3 ), that is, W M3 =17 μm. The M2 regions 201, 202, and 203 may have a thickness of 8 μm. The M2 regions 201, 202, and 203 may also have a width (W M2 ), that is, W M2 =8 μm. The M1 region may have a thickness of 0.5 μm. The M1 region may also have a width (W M1 ), that is, W M1 =0.5μm.

[0096] exist Figure 5A In the example, the M1 region is coupled to the source regions S2, S3, and S4 and the drain regions D1, D2, and D3 in the AR region of the power transistor. Source region S2 and drain region D2 form one of the power transistors. Source region S3 and drain region D3 also form one of the power transistors. The active region also includes a source region S1 (not shown) and drain region D1 for forming one of the power transistors. The active region also includes a drain region D4 (not shown) and source region S4 for forming one of the power transistors.

[0097] like Figure 5AAs shown in FIG, three M4 regions 401, 402, and 403 are in the M4 layer, which is higher than the M3 layer, M2 layer, M1 layer, and AR layer of the integrated circuit 110. Three M2 regions 201, 202, and 203 are in the M2 layer, which is below the M4 layer and above the AR layer. The M4 regions 401, 402, and 403 (35 μm) are thicker and wider than the M2 regions 201, 202, and 203 (8 μm). Therefore, the M4 regions 401, 402, and 403 have a lower resistance than the M2 regions 201, 202, and 203, and are configured to allow more current to flow than the M2 regions 201, 202, and 203 allow current to flow. That is, the lateral current i flowing through the M4 region 401 is greater than the M2 region 201. M4-LAT-1 is greater than the lateral current i flowing through the M2 region 201 M2-LAT-1 The lateral current i flowing through the M4 region 403 M4-LAT-2 is greater than the lateral current i flowing through the M2 region 203 M2-LAT-3 As described above, M4 regions 401, 402, and 403, as well as M2 regions 201, 202, and 203, are transversely oriented metal conductors. That is, the current flowing in each transversely oriented M4 metal conductor in the M4 layer can exceed the current flowing in each transversely oriented M2 conductor in the M2 layer. The current flowing in each transversely oriented M4 metal conductor in the M4 layer can also exceed the current flowing in each transversely oriented M3 conductor in the M3 layer. The current flowing in each transversely oriented M2 metal conductor in the M2 layer can also exceed the current flowing in each transversely oriented M1 conductor in the M1 layer.

[0098] In some embodiments, the two lateral currents i flowing in the M4 layer M4-LAT-1 and i M4-LAT-2 The total amount is greater than the two transverse currents i flowing in the M2 layer M2-LAT-1 and i M2-LAT-3 The total amount of the lateral current i flowing through the M2 region 202 M2-L4T-2 May be small because the vertical current i VTC-3 and i VTC-4 Directly from the AR region to the M4 region 402 is formed. The two conductive paths directly from the drain region D2 to the M4 region 402 and directly from the source region S3 to the M4 region 402 have a higher conductivity than that from the AR region (S3 or D2) through the formation of i M2-LAT-2 The conductive path from the M2 region 202 to the M4 region 402 has a lower resistance.

[0099] like Figure 5AAs shown in FIG, a conductive path P23-M2 exists between the source region S3 of the third transistor and the terminal coupled to the RDL. The conductive path P23-M2 starts from the source region S3 of the third transistor and is coupled to the terminal (not shown) of the RDL via the M2 region 202 in the M2 layer. The conductive path P23-M2 includes: a first plurality of vertically oriented metal conductors (including a portion of the stacked V1, M1, V21, and M2); a laterally oriented metal conductor on the M2 region 202; and a second plurality of vertically oriented metal conductors (including a stacked portion of M2, V32, M3, V43, M4, and VR4). The sum of the lengths of the first plurality of vertically oriented metal conductors and the second plurality of vertically oriented metal conductors exceeds the length of the laterally oriented metal conductors.

[0100] like Figure 5A As shown in , the integrated circuit 110 includes a first plurality of metal regions coupled to the source region of the power transistor. The integrated circuit 110 also includes a second plurality of metal regions coupled to the drain region of the power transistor. The first plurality of metal regions and the second plurality of metal regions have at least one of a substantially equal number of metal regions, a substantially equal resistance, or a balanced distribution of metal regions. That is, the number of M4 regions, M3 regions, M2 regions, and M1 regions coupled to the source region of the power transistor is substantially equal to the number of M4 regions, M3 regions, M2 regions, and M1 regions coupled to the drain region of the power transistor. The first plurality of stacked metal regions forming a first conductive path from the source region to the first M4 region have a substantially equal resistance to the second plurality of stacked metal regions forming a second conductive path from the drain region to the second M4 region. The first M4 region and the second M4 region may be the same M4 region or different M4 regions.

[0101] In some embodiments, the integrated circuit 110 includes multiple active regions. Each of the active regions is similar to Figure 5A One or more RDL regions, M4 regions, M3 regions, and M2 regions may span one or more active regions.

[0102] Figure 5B FIG is a perspective view of a metal region of an integrated circuit 110 for power conversion according to an embodiment of the present disclosure. Figure 5B As shown in FIG, the integrated circuit 110 includes two M4 regions, two M3 regions, two M2 regions, two M1 regions, and a substrate having an active region. The active region includes a plurality of power transistors (not shown). The integrated circuit 110 has a cross metal conductor orientation. The two M4 regions have a width W M4 =35μm and extends along the X-axis direction. The two M3 regions have a width W M3=17μm and extends along the Y-axis direction. The two M2 regions have a width W M2 =8μm and extends along the X-axis direction. The two M1 regions have a width W M1 =0.5 μm and extends along the Y-axis direction.

[0103] In some embodiments, an exemplary integrated circuit for power conversion may include multiple metal regions. The multiple metal regions may include multiple first metal regions in a first layer. The first metal regions may have a first width. The multiple metal regions may also include multiple second metal regions in a second layer. The second metal regions may have a second width. The second layer may be above the first layer. The second width is greater than the first width.

[0104] For example, Figure 5A and Figure 5B The integrated circuit 110 may include a plurality of M4 regions, M3 regions, M2 regions, and M1 regions. That is, the metal region of the integrated circuit 110 has an M2 region in the M2 layer. The M2 region has a width W M2 =8μm. The metal region of the integrated circuit 110 also has an M3 region in the M3 layer. The M3 region has a width W M3 =17 μm. The M3 layer is above the M2 layer. The width of the M3 region (17 μm) is greater than the width of the M2 region (8 μm). The width of the M3 region (17 μm) is approximately twice the width of the M2 region (8 μm).

[0105] In some embodiments, the plurality of metal regions of the exemplary integrated circuit for power conversion may further include a plurality of third metal regions in a third layer. The third metal regions have a third width. The third layer is above the second layer. The third width is greater than the second width.

[0106] For example, Figure 5A and Figure 5B The metal region of the integrated circuit 110 in the embodiment further includes an M4 region in the M4 layer. The M4 region has a width W M4 =35μm. The M4 layer is above the M3 layer. The width of the M4 region (35μm) is greater than the width of the M3 region (17μm). The width of the M4 region (35μm) is approximately twice the width of the M3 region (17μm).

[0107] In some embodiments, the plurality of metal regions of the exemplary integrated circuit for power conversion may further include a plurality of fourth metal regions in a fourth layer. The fourth layer is below the first layer and has a fourth width. A first portion of the fourth metal region is coupled to a source region of a power transistor. A second portion of the fourth metal region is coupled to a drain region of the power transistor. The fourth width is significantly smaller than the first width.

[0108] For example, Figure 5A and Figure 5B The metal region of the integrated circuit 110 in FIG. 1 also has an M1 region in the M1 layer. The M1 layer is below the M2 layer and has a width W M1 =0.5μm. The width of the M1 region (0.5μm) is significantly smaller than the width of the M2 region (8μm). Figure 5A As shown in FIG, three of the six M1 regions are coupled to the source region of the power transistor. The other three of the six M1 regions are coupled to the drain region of the power transistor.

[0109] In some embodiments, an exemplary integrated circuit for power conversion may have an M4 region, an M3 region, and an M2 region in layers M4, M3, and M2. The width of the M3 region may be 90% of the width of the M4 region. The width of the M2 region may be 90% of the width of the M3 region.

[0110] In some embodiments, an exemplary integrated circuit for power conversion may have an M4 region, an M3 region, and an M2 region in layers M4, M3, and M2. The width of the M3 region may be 80% of the width of the M4 region. The width of the M2 region may be 80% of the width of the M3 region.

[0111] In some embodiments, an exemplary integrated circuit for power conversion may have an M4 region, an M3 region, and an M2 region in layers M4, M3, and M2. The width of the M3 region may be 70% of the width of the M4 region. The width of the M2 region may be 70% of the width of the M3 region.

[0112] In some embodiments, an exemplary integrated circuit for power conversion may have an M4 region, an M3 region, and an M2 region in layers M4, M3, and M2. The width of the M3 region may be 60% of the width of the M4 region. The width of the M2 region may be 60% of the width of the M3 region.

[0113] In some embodiments, an exemplary integrated circuit for power conversion may have an M4 region, an M3 region, and an M2 region in layers M4, M3, and M2. The width of the M3 region may be 50% of the width of the M4 region. The width of the M2 region may be 50% of the width of the M3 region.

[0114] In some embodiments, an exemplary integrated circuit for power conversion may have an M4 region, an M3 region, and an M2 region in layers M4, M3, and M2. The width of the M3 region may be 40% of the width of the M4 region. The width of the M2 region may be 40% of the width of the M3 region.

[0115] In some embodiments, an exemplary integrated circuit for power conversion may have an M4 region, an M3 region, and an M2 region in layers M4, M3, and M2. The width of the M3 region may be 30% of the width of the M4 region. The width of the M2 region may be 30% of the width of the M3 region.

[0116] In some embodiments, an exemplary integrated circuit for power conversion may have an M4 region, an M3 region, and an M2 region in layers M4, M3, and M2. The width of the M3 region may be 20% of the width of the M4 region. The width of the M2 region may be 20% of the width of the M3 region.

[0117] In some embodiments, an exemplary integrated circuit for power conversion may have an M4 region, an M3 region, and an M2 region in layers M4, M3, and M2. The width of the M3 region may be 10% of the width of the M4 region. The width of the M2 region may be 10% of the width of the M3 region.

[0118] In some embodiments, an exemplary integrated circuit for power conversion may include an M4 region, an M3 region, and an M2 region in layers M4, M3, and M2. The width of the M3 region may be between 90% and 10% of the width of the M4 region. The width of the M2 region may be between 90% and 10% of the width of the M3 region.

[0119] In some embodiments, an exemplary integrated circuit for power conversion may be mounted on a circuit board having a plurality of conductive traces extending in a first direction perpendicular to a surface of the circuit board. The exemplary integrated circuit may include a plurality of metal regions. The plurality of metal regions of the exemplary integrated circuit may include a plurality of first metal regions extending in a second direction in a first layer of the exemplary integrated circuit. The plurality of metal regions of the exemplary integrated circuit may also include a plurality of second metal regions extending in a third direction in a second layer of the exemplary integrated circuit. The second layer is above the first layer. The third direction is perpendicular to the second direction.

[0120] For example, the integrated circuit 110 is mounted to Figure 2F Circuit board 120 or Figure 3A The circuit board 140 in the circuit board 120 ( Figure 2F ) includes conductive traces 121a, 121b, 121c, and 121d extending in the Z-axis direction perpendicular to the surface of the circuit board 120. The circuit board 140 ( Figure 3A ) includes conductive traces 141a, 141b, 141c, and 141d extending in a Z-axis direction perpendicular to the surface of the circuit board 140. The integrated circuit 110 ( Figure 2F or Figure 3A) may include multiple M4 regions, M3 regions, M2 regions and M1 regions ( Figure 5A That is, the integrated circuit 110 may include M2 ​​regions 201, 202, and 203 extending along the X-axis direction in the M2 layer of the integrated circuit 110 ( Figure 5A The integrated circuit 110 may further include an M3 layer in the integrated circuit 110 along the Y-axis direction ( Figure 5B ) six M3 regions ( Figure 5A ). The M3 layer is above the M2 layer. The Y-axis direction is perpendicular to the X-axis direction.

[0121] In some embodiments, the exemplary integrated circuit for power conversion further includes a plurality of third metal regions extending along the second direction in the third layer. The third layer is above the second layer. For example, the integrated circuit 110 ( Figure 5A ) may further include M4 regions 401, 402, and 403 extending along the X-axis direction in the M4 layer of the integrated circuit 110 ( Figure 5A ). The M4 layer is above the M3 layer.

[0122] In some embodiments, an exemplary integrated circuit for power conversion may include a plurality of power transistors. The power transistors have a plurality of gate regions extending along a third direction. The exemplary integrated circuit may further include a plurality of fourth metal regions extending along the third direction in a fourth layer. The fourth layer is above the third layer. The fourth metal regions extend along the same third direction as the gate regions. For example, integrated circuit 110 ( Figure 5A ) may include multiple power transistors. The power transistor includes multiple gate regions such as Figure 5A The gate regions G2 and G3 may extend along the Y-axis direction. Figure 5A ) may also include a plurality of RDL regions ( Figure 5A and Figure 6A The RDL layer is above the M4 layer. The RDL metal region and the gate region extend along the same Y-axis direction.

[0123] Figure 6A FIG is a top view of an RDL region and an active region of an integrated circuit 110 for power conversion according to some embodiments. Figure 6A As shown in , the integrated circuit 110 may include three RDL regions in the RDL layer and multiple active regions in the AR layer. The three RDL regions may extend along the Y-axis direction. The three RDL regions may be formed above all active regions and may be configured to redistribute vertical current from any one of the active regions (i.e., any one of the power transistors) to the appropriate output terminal of the integrated circuit 110.

[0124] Figure 6BAccording to some embodiments Figure 6A FIG. 1 is a top view of a portion of the RDL region and gate region above the active region of the integrated circuit 100. Figure 6A and Figure 6B As shown in FIG, the RDL region of the integrated circuit 110 may extend along the Y axis ( Figure 6A ). The integrated circuit 110 may include multiple gate regions above the active region. The gate regions may extend along the Y-axis region. That is, the RDL region and the gate region may extend along the same Y-axis direction in the integrated circuit 110.

[0125] In some embodiments, an exemplary integrated circuit for power conversion includes a plurality of RDL regions extending in the same direction as a plurality of gate regions above a plurality of active regions in the exemplary integrated circuit. Figure 6A As shown in FIG, the three RDL regions of the integrated circuit 110 may extend along the Y-axis direction. The integrated circuit 110 may also include a plurality of gate regions above each of the active regions, the plurality of gate regions being similar to Figure 6B The gate regions above the active regions shown in FIG. The gate regions above each of the active regions may also extend along the Y-axis direction. Therefore, the integrated circuit 110 may include three RDL regions extending along the same Y-axis direction as the multiple gate regions above the active regions.

[0126] Figure 7A FIG is a top view of the M4 region and active area of ​​the integrated circuit 110 for power conversion according to some embodiments. Figure 7A As shown in , the integrated circuit 110 may include multiple M4 regions and multiple active regions. The M4 region may extend along the X-axis direction. Figure 7A As shown in , multiple M4 regions of integrated circuit 110 can be formed over all active regions and can be configured to receive vertical current from all active regions (ie, any of the power transistors) or deliver vertical current to any of the active regions.

[0127] Figure 7B FIG is a top view of four M4 regions and six active regions of an exemplary integrated circuit for power conversion according to some embodiments. Figure 7B As shown in FIG, four M4 regions may be formed above six active regions. The M4 region may have a width W M4 As an example, the width W M4 It can be 35μm, that is, W M4=35 μm. In some embodiments, the M4 region of the integrated circuit 110 can be any size feasible for the technology node if it is wider and / or thicker than the M3, M2, and M1 regions below it. In some embodiments, the M4 region of the integrated circuit 110 can be any size feasible for the technology node if it has a lower resistance than the M3, M2, and M1 regions below it.

[0128] Figure 7C FIG. 1 is a top view of the M4 region, the V43 via between the M4 layer and the M3 layer, and the active area of ​​the integrated circuit 110 for power conversion according to some embodiments. Figure 7C As shown in , the integrated circuit 110 may include V43 vias formed in a balanced distribution over multiple active areas (ie, power transistors) of the integrated circuit 110 .

[0129] Figure 7D FIG. 1 is a top view of five M4 regions, V43 vias, and six active regions of an integrated circuit 110 for power conversion according to some embodiments. Figure 7D As shown in , sixty V43 vias may be formed in a balanced distribution under five M4 regions and over six active regions (ie, power transistors) of the integrated circuit 110 .

[0130] Figure 8A FIG is a top view of the M3 region and active area of ​​the integrated circuit 110 for power conversion according to some embodiments. Figure 8A As shown in , the integrated circuit 110 may include multiple M3 regions and multiple active regions. The M3 region may extend along the Y-axis direction. Figure 8A As shown in FIG, multiple M3 regions of integrated circuit 110 may be formed over all active regions and may be configured to receive vertical current from all active regions (ie, any of the power transistors) or deliver vertical current to any of the active regions.

[0131] Figure 8B FIG is a top view of eight M3 regions and two active regions of an integrated circuit 110 for power conversion according to some embodiments. Figure 8B As shown in FIG, eight M3 regions can be formed above two active regions. The M3 region can have a width W M3 As an example, the width W M4 It can be 17μm, that is, W M3 =17μm.

[0132] Figure 8CFIG is a top view of four M4 regions and eight M3 regions of an integrated circuit 100 for power conversion according to some embodiments. Figure 8C As shown in , four M4 regions can extend along the X-axis direction. Eight M3 regions can extend along the Y-axis direction. That is, the M3 regions can extend in a direction perpendicular to the direction in which the M4 regions can extend. Figure 8C As shown in FIG, the M4 region may have a width W M4 As an example, the width W M4 It can be 35μm, that is, W M4 =35μm. The M3 region may have a width W M3 Width W M4 It can be 17μm, that is, W M3 =17 μm. The width of the M3 region may be about 50% of the width of the M4 region. The width of the M4 region may be about twice the width of the M3 region, that is, W M4 =2×W M3 .

[0133] In some embodiments, the M3 region of the integrated circuit 110 can have any size feasible for the technology node, as long as the M3 region is thinner and / or less thick than those M4 regions above the M3 region, and thicker than those M2 and M1 regions below the M3 region. Figure 5A or Figure 5B ) wide and / or thick. In some embodiments, the M3 region of the integrated circuit 110 can have any size feasible for the technology node, as long as the M3 region has a higher resistance than those M4 regions above the M3 region and has a lower resistance than those M2 and M1 regions below the M3 region ( Figure 5A or Figure 5B )A lower resistance is sufficient.

[0134] Figure 8D FIG. 1 is a top view of a V32 via and an active area between the M3 layer and the M2 layer of an integrated circuit 110 for power conversion according to some embodiments. Figure 8D As shown in , the integrated circuit 110 may include V32 vias formed in a balanced distribution over multiple active areas (ie, power transistors) of the integrated circuit 110 .

[0135] Figure 8E is a top view of eight M3 regions, V32 vias, and two active regions of an exemplary integrated circuit for power conversion according to some embodiments. Figure 8E As shown in , twenty-four V32 vias may be formed in a balanced distribution below eight M3 regions above each active region (ie, power transistor) of the integrated circuit 110. Four additional V32 vias may be formed at the four corners of the active region.

[0136] In some embodiments, the exemplary integrated circuit for power conversion further includes a plurality of first vias coupled between the first metal region and the second metal region, and a plurality of second vias coupled between the second metal region and the third metal region. The first vias have a balanced distribution over the power transistor, and the second vias have a balanced distribution over the power transistor.

[0137] For example, Figure 7C and Figure 7D As shown in FIG, the integrated circuit 110 may include a plurality of V43 vias (V43) coupled between the M4 region and the M3 region. Figure 5A ). Multiple V43 vias can have a balanced distribution over multiple active areas (ie, power transistors) of the integrated circuit 110. Figure 8D and Figure 8E As shown in FIG, the integrated circuit 110 may further include a plurality of V32 vias (V32) coupled between the M3 region and the M2 region. Figure 5A ). The plurality of V32 vias may have a balanced distribution across the plurality of active areas (ie, power transistors) of the integrated circuit 110 .

[0138] Figure 9A is a top view of the M2 region and active area of ​​the integrated circuit 110 for power conversion according to some embodiments.

[0139] like Figure 9A As shown in , the integrated circuit 110 may include a plurality of M2 regions and a plurality of active regions. The M2 regions may extend along the X-axis direction. Figure 9A As shown in , multiple M2 regions of integrated circuit 110 can be formed over all active regions and can be configured to receive vertical current from all active regions (ie, any of the power transistors) or deliver vertical current to any of the active regions.

[0140] Figure 9B FIG is a top view of sixteen M2 regions and six active regions of an integrated circuit 110 for power conversion according to some embodiments. Figure 9B As shown in FIG, the M2 region may be formed over the six active regions. The M2 region may have a width W M2 As an example, the width W M2 It can be 8μm, that is, W M2=8 μm. In some embodiments, the M2 region of the integrated circuit 110 can be any size feasible for the technology node, as long as the M2 region is wider and / or thicker than the M1 regions below the M2 region. In some embodiments, the M2 region of the integrated circuit 110 can be any size feasible for the technology node, as long as the M2 region has a greater resistance than the M4 and M3 regions above the M2 region.

[0141] Figure 9C is a top view of the M3 region and the M2 region of an exemplary integrated circuit for power conversion according to some embodiments.

[0142] like Figure 9C As shown in , eight M3 regions can extend along the Y-axis direction. Sixteen M2 regions can extend along the X-axis direction. That is, the M2 regions can extend in a direction perpendicular to the direction in which the M3 regions can extend. Figure 9C As shown in FIG, the M3 region may have a width W M3 Width W M4 It can be, for example, 17 μm, that is, W M3 =17 μm. The M2 region may have a width W M2 Width W M2 It can be 8μm, that is, W M2 =8μm. The width of the M2 region may be about 50% of the width of the M3 region. The width of the M3 region may be about twice the width of the M2 region, that is, W M3 =2×W M2 .

[0143] In some embodiments, the M2 region of the integrated circuit 110 can have any size feasible for the technology node, as long as the M2 region is thinner and / or less thick than those M3 regions above the M2 region and thicker than those M1 regions below the M2 region ( Figure 5A or Figure 5B In some embodiments, the M2 region of the integrated circuit 110 can have any size feasible for the technology node, as long as the M2 region has a higher resistance than those of the M4 region and the M3 region above the M2 region.

[0144] Figure 10A FIG is a top view of the M1 region and active area of ​​the integrated circuit 110 for power conversion according to some embodiments. Figure 10A As shown in , the integrated circuit 110 may include a plurality of M1 regions and a plurality of active regions. The M1 region may extend along the Y-axis direction. Figure 10AAs shown in , multiple M1 regions of integrated circuit 110 may be formed over all active areas and may be configured to receive vertical current from or deliver vertical current to source and drain regions of power transistors in the active areas.

[0145] Figure 10B FIG is a top view of the M1 region and active area of ​​the integrated circuit 110 for power conversion according to some embodiments. Figure 10B As shown in FIG, the integrated circuit 110 may include a plurality of M1 regions formed above each active region. The M1 region may have a width W M1 Width W M1 It can be, for example, 0.5 μm, that is, W M1 =0.5 μm. The M2 region above the M1 region may have a width W M2 Width W M2 It can be 8μm, that is, W M2 =8μm. The width of the M1 region may be 6.25% of the width of the M2 region, that is, W M1 =0.0625×W M2 The width of the M1 region is significantly smaller than the width of those M2 regions above the M1 region.

[0146] In some embodiments, the width of the M1 region can be 5% to 20% of the width of the M2 region. The width of the M1 region is considered to be significantly smaller than the width of those M2 regions above the M1 region.

[0147] Figure 10C FIG is a top view of the M1 region and a portion of the active area of ​​the integrated circuit 110 for power conversion according to some embodiments. Figure 10C As shown in FIG, multiple M1 regions may extend the active area along the Y-axis direction.

[0148] 10D is a top view of the M1 region, the V21 vias between the M2 layer and the M1 layer, and a portion of the active area of ​​the integrated circuit 110 for power conversion according to some embodiments. As shown in FIG10D , the integrated circuit 110 may include V21 vias formed in a balanced distribution above a portion of the active area (i.e., the power transistor) of the integrated circuit 110. Although only a portion of the active area is shown in FIG10D , the other portions of the active area are the same as shown. That is, the integrated circuit 110 may include V21 vias formed in a balanced distribution above the active area (i.e., the power transistor) of the integrated circuit 110. The integrated circuit 110 may include V21 vias formed in a balanced distribution above all of the multiple active areas of the integrated circuit 110.

[0149] Figure 11FIG is a top view of two M2 regions, multiple gate regions, and a portion of an active region of an integrated circuit 110 for power conversion according to some embodiments. Figure 11 As shown in , the integrated circuit 110 may include multiple gate regions formed above a portion of the active region. The gate region may extend along the Y-axis direction. The two M2 regions may extend along the X-axis direction. Figure 11 As shown in , both ends of the gate region can be coupled to two M2 regions respectively. Both M2 regions can be configured to transfer current to or from the gate region. Therefore, current transfer can be fast and efficient. Figure 11 The two M2 regions in can be Figure 9B The upper and lower two of the eight M2 regions above the active region in the transistor. The other six of the eight M2 regions above the active region can be coupled to the source region or the drain region of the power transistor.

[0150] In some embodiments, the integrated circuit 110 may include a plurality of power transistors for power conversion. One or more of the power transistors may each include a plurality of active areas, a plurality of terminals, and a plurality of conductive paths. Each terminal may be electrically coupled to at least one of the active areas via at least one of the conductive paths. Each conductive path may include one or more transversely oriented metal conductors and one or more vertically oriented metal conductors. In most of the conductive paths, the sum of the lengths of the one or more vertically oriented metal conductors may exceed the sum of the lengths of the one or more transversely oriented metal conductors.

[0151] For example, the power transistor of the integrated circuit 110 may include six active regions ( Figure 9B Each of the six active regions may include a plurality of transistors including a gate region, a source region, and a drain region ( Figure 11 ).like Figure 11 As shown in , all gate regions can be coupled together via the M2 region. All source regions can be coupled together. All drain regions can also be coupled together. In other words, multiple transistors in the active region can be connected in parallel to form an equivalent transistor with doubled power handling capability. The equivalent transistors of the six active regions can be further connected in parallel to form a power transistor with high power handling capability.

[0152] The power transistor may also include a transistor coupled to the M4 region ( Figure 7B ) of multiple terminals. The power transistor may also include multiple conductive paths such as conductive path P23-M2 ( Figure 5AEach terminal can be electrically coupled to at least one of the six active regions via at least one of the conductive paths. Each conductive path can include one or more laterally oriented metal conductors (e.g., Figure 5A conductive path P23-M2 on the M2 region 202 in the embodiment of the present invention) and one or more vertically oriented metal conductors (e.g., Figure 5A In the embodiment of the present invention, the sum of the lengths of the one or more vertically oriented metal conductors may exceed the sum of the lengths of the one or more laterally oriented metal conductors in the conductive path P23-M2.

[0153] In some embodiments, the laterally oriented metal conductors may include a first metal conductor in a first metal layer above the active region and a second metal conductor in a second metal layer above the first metal layer. The width of the first metal conductor may be less than the width of the second metal conductor. For example, the laterally oriented metal conductors of a power transistor may include M2 ​​regions 201, 202, and 203 in an M2 layer above the active region ( Figure 5A The laterally oriented metal conductor of the power transistor may further include M4 regions 401, 402, and 403 in the M4 layer above the M2 layer. The width of the M2 regions 201, 202, and 203 may be 8 μm. The width of the M4 regions 401, 402, and 403 may be 35 μm. The width of the M2 regions 201, 202, and 203 (8 μm) is smaller than the width of the M4 regions 401, 402, and 403 (35 μm).

[0154] In some embodiments, in a power transistor, the current flowing in each laterally-oriented metal conductor in the second metal layer exceeds the current flowing in each laterally-oriented metal conductor in the first metal layer. For example, the current flowing in each laterally-oriented M4 region in the M4 layer may be 0.3 mA. The current flowing in each laterally-oriented M2 region in the M2 layer may be 0.1 mA. The current flowing in each M4 region (0.3 mA) exceeds the current flowing in each M2 region (0.1 mA).

[0155] In some embodiments, in a power transistor, the resistance of each laterally oriented metal conductor in the second metal layer is less than the resistance of each laterally oriented metal conductor in the first metal layer. For example, the M4 regions 401, 402, and 403 ( Figure 5A ) than the M2 regions 201, 202 and 203 in the M4 layer ( Figure 5A Therefore, the resistance of each of the M4 regions 401, 402, and 403 is smaller than the resistance of each of the M2 regions 201, 202, and 203.

[0156] Figure 12 Shown according to the disclosed embodiment Figure 1 An exemplary configuration of the apparatus 100 for power conversion is shown in FIG. Figure 12 As shown in FIG, the device 100 can have configurations 1, 2, 3, 4, and 5 for outputting power. The controller 114 ( Figure 4 ) can be configured to: determine one of configurations 1, 2, 3, 4, and 5; and couple inductors 131, 132, 133, and 134 based on the determined configuration. Figure 2D As shown in , inductors 131 , 132 , 133 , and 134 may share an inductor core 135 and may be coupled together based on the determined configuration.

[0157] In configuration 1, the controller 114 may be configured to determine the inductors 131, 132, 133, and 134 to be respectively OUT-1 、V OUT-2 、V OUT-3 and V OUT-4 Output current of 4 amperes (A). In configuration 2, the controller 114 can be configured to determine whether the inductors 132 and 133 can be based on the output power V OUT-2 and V OUT-3 The controller 114 can also be configured to determine the inductors 131 and 134 from the output power V OUT-1 and V OUT-4 Output current of 4A. In configuration 3, the controller 114 can be configured to determine whether the inductors 131 and 132 can be used based on the output power V OUT-1 and V OUT-2 The controller 114 can also be configured to determine whether the inductors 133 and 134 can be connected based on the output power V OUT-3 and V OUT-4 Coupled together to output 8A of current.

[0158] In configuration 4, the controller 114 may be configured to determine whether the inductors 131, 132, and 133 can be used based on the output power V OUT-1 、V OUT-2 and V OUT-3 The controller 114 can also be configured to determine the inductor 134 from the output power V OUT-4 Output current of 4A. In configuration 5, the controller 114 can be configured to determine whether the inductors 131, 132, 133 and 134 can be based on the output power V OUT-1 、V OUT-2 、V OUT-3 and V OUT-4Coupled together to output 16A of current.

[0159] When the controller 114 determines one of configurations 1, 2, 3, 4, and 5, the inductors 131, 132, 133, and 134 may be coupled as described above and configured to fan out multiple voltage outputs such as the converted voltages at currents of 4A, 8A, 12A, and 16A, as described with reference to FIG. Figure 12 shown.

[0160] Figure 13 According to some embodiments Figure 1 A circuit diagram of an exemplary apparatus 100 for power conversion is shown in FIG. Figure 13 As shown in FIG, the apparatus 100 may include: an integrated circuit 110; inductors 131, 132, 133, and 134; and a plurality of peripheral circuits such as capacitors and resistors, which are coupled to the integrated circuit 110 and the inductors 131, 132, 133, and 134 or between the integrated circuit 110 and the inductors 131, 132, 133, and 134. The peripheral circuits may be implemented on a circuit board 120 ( Figure 1 ). The apparatus 100 may be configured based on configurations 1, 2, 3, 4, and 5 ( Figure 12 )Convert input power V IN .

[0161] In the foregoing description, embodiments have been described with reference to many specific details, which may vary from implementation to implementation. Certain adjustments and modifications may be made to the described embodiments. Based on consideration of the description and practice of the disclosure disclosed herein, other embodiments may be apparent to those skilled in the art. The order of the steps shown in the accompanying drawings is intended to be for illustrative purposes only and is not intended to be limited to any particular order of steps. Therefore, it will be understood by those skilled in the art that these steps may be performed in different orders when implementing the same method.

[0162] It should be understood that certain features of the specification that are described in the context of separate embodiments for the sake of clarity may also be provided in combination in a single embodiment. Conversely, various features of the specification that are described in the context of a single embodiment for the sake of brevity may also be provided individually or in any suitable subcombination or as appropriate in any other described embodiment of the specification. Certain features described in the context of various embodiments should not be considered essential features of those embodiments, unless the embodiment is inoperable without those elements.

[0163] The following terms may be used to further describe the implementation:

[0164] 1. A device for power conversion, comprising:

[0165] An integrated circuit for power conversion, the integrated circuit comprising:

[0166] a plurality of power transistors; and

[0167] a plurality of metal regions coupled to the plurality of power transistors, wherein:

[0168] A first portion of the metal region is coupled to source regions of the plurality of power transistors;

[0169] The second portion of the metal regions is coupled to drain regions of the plurality of power transistors; and the first portion and the second portion have at least one of a substantially equal number of metal regions, a substantially equal resistance, or a balanced distribution of the metal regions.

[0170] 2. The device according to clause 1, wherein the integrated circuit is mounted on a circuit board comprising a surface and a plurality of conductive lines extending in a direction perpendicular to the surface, the integrated circuit being coupled to the conductive lines.

[0171] 3. The apparatus of clause 2, wherein the integrated circuit is coupled to an inductor mounted on the surface of the circuit board via at least one of the conductive lines, at least a portion of the integrated circuit being beneath the inductor.

[0172] 4. The device according to clauses 1 to 3, wherein the plurality of metal regions comprises:

[0173] a plurality of first metal regions in the first layer, the first metal regions having a first width; and

[0174] a plurality of second metal regions in a second layer, the second metal regions having a second width, the second layer being above the first layer,

[0175] The second width is greater than the first width.

[0176] 5. The device of clause 4, wherein the second width is twice the first width.

[0177] 6. The device of clause 4, wherein the plurality of metal regions further comprises:

[0178] a plurality of third metal regions in a third layer, the third metal regions having a third width, the third layer being above the second layer,

[0179] The third width is greater than the second width.

[0180] 7. The device of clause 6, wherein the third width is twice the second width.

[0181] 8. The apparatus of clause 6, wherein the plurality of metal regions further comprises:

[0182] a plurality of fourth metal regions in a fourth layer, the fourth layer being below the first layer and having a fourth width, wherein:

[0183] a first portion of the fourth metal region coupled to source regions of the plurality of power transistors;

[0184] A second portion of the fourth metal region is coupled to drain regions of the plurality of power transistors; and

[0185] The fourth width is significantly smaller than the first width.

[0186] 9. The device of clauses 1 to 8, wherein the direction is a first direction, wherein the plurality of metal regions comprises:

[0187] a plurality of first metal regions extending in the second direction in the first layer; and

[0188] a plurality of second metal regions extending along a third direction in a second layer, the second layer being above the first layer,

[0189] The third direction is perpendicular to the second direction.

[0190] 10. The apparatus of clause 9, wherein the plurality of metal regions further comprises:

[0191] A plurality of third metal regions extend along the second direction in a third layer, the third layer being above the second layer.

[0192] 11. The apparatus of clause 10, wherein the plurality of power transistors comprises:

[0193] a plurality of gate regions extending along a third direction,

[0194] Two ends of the gate regions of the plurality of power transistors are coupled to a portion of the first metal region.

[0195] 12. The apparatus of clause 11, wherein the integrated circuit further comprises:

[0196] a plurality of fourth metal regions extending along a third direction in a fourth layer, the fourth layer being above the third layer,

[0197] The fourth metal region and the gate region extend along the same third direction.

[0198] 13. The apparatus of clause 11, wherein the integrated circuit further comprises:

[0199] a plurality of first vias coupled between the first metal region and the second metal region; and

[0200] a plurality of second vias coupled between the second metal region and the third metal region, wherein:

[0201] The first vias have a balanced distribution over the plurality of power transistors; and

[0202] The second vias have a balanced distribution on the plurality of power transistors.

[0203] 14. The apparatus of clause 3, wherein the inductor is connected to the buck converter circuitry within the integrated circuit via a conductive line.

[0204] 15. The apparatus of clause 3, wherein the inductor is connected to the integrated circuit via a plurality of conductive lines.

[0205] 16. The apparatus of clause 3, wherein the inductor is a coupled inductor.

[0206] 17. The apparatus of clause 3, wherein the inductor is a chip inductor.

[0207] 18. An apparatus according to clause 3, wherein:

[0208] The integrated circuit includes charge pump circuitry and buck converter circuitry; and

[0209] Buck converter circuitry is connected to the inductor via at least one of the conductive lines.

[0210] 19. An apparatus according to clause 3, wherein:

[0211] The integrated circuit includes charge pump circuitry for two or more charge pumps and buck converter circuitry for at least two buck converters;

[0212] The inductor includes at least two chip inductors; and

[0213] The at least two buck converters are respectively connected to corresponding ones of the at least two chip inductors through corresponding ones of the conductive lines.

[0214] 20. The apparatus according to clause 2, wherein:

[0215] The conductive traces are located on a common edge of the circuit board.

[0216] 21. The apparatus according to clause 2, wherein:

[0217] The integrated circuit includes a plurality of output terminals for outputting current;

[0218] The output terminal is directly coupled to the conductive line; and

[0219] The conductive trace extends directly from the output terminal in a direction perpendicular to the surface and extends to the inductor.

[0220] 22. The apparatus of clause 21, wherein the output terminal is within the portion of the integrated circuit below the inductor.

[0221] 23. The apparatus of clause 2, wherein the integrated circuit is embedded within the circuit board.

[0222] 24. An apparatus according to clause 23, wherein:

[0223] The circuit board includes a first layer, a second layer and a third layer;

[0224] The second layer is between the first and third layers; and

[0225] The integrated circuit is mounted in the second layer.

[0226] 25. An apparatus according to clause 23, wherein:

[0227] The circuit board includes a first metal layer and a second metal layer;

[0228] The conductive trace is coupled between the first metal layer and the second metal layer; and

[0229] An integrated circuit is coupled to the conductive traces in the second metal layer.

[0230] 26. The apparatus according to clause 2, wherein:

[0231] The surface is a first surface;

[0232] The circuit board also includes a second surface; and

[0233] An integrated circuit is mounted on the second surface.

[0234] 27. The apparatus of clause 3, wherein the inductor comprises a plurality of coupled inductors, the coupled inductors sharing an inductor core.

[0235] 28. An apparatus according to clause 27, wherein:

[0236] The integrated circuit includes a control circuit;

[0237] The control circuit determines an output configuration of the coupled inductor; and

[0238] Coupled inductors fan out multiple voltage outputs.

[0239] 29. An apparatus according to clause 27, wherein:

[0240] The integrated circuit includes a control circuit;

[0241] The control circuit outputs a vertical current from the integrated circuit to the inductor, and the vertical current flows in a direction perpendicular to the integrated circuit.

[0242] 30. A power transistor for power conversion, comprising:

[0243] Multiple active regions;

[0244] a plurality of terminals; and

[0245] multiple conductive paths;

[0246] in:

[0247] Each terminal is electrically coupled to at least one of the active regions via at least one of the conductive paths;

[0248] Each conductive path includes one or more laterally oriented metal conductors and one or more vertically oriented metal conductors; and

[0249] In a majority of the conductive paths, the sum of the lengths of the one or more vertically oriented metallic conductors exceeds the sum of the lengths of the one or more laterally oriented metallic conductors.

[0250] 31. The power transistor of clause 30, wherein the laterally oriented metal conductor comprises:

[0251] a first metal conductor in a first metal layer over the active area; and

[0252] a second metal conductor in a second metal layer above the first metal layer,

[0253] Wherein, the width of the first metal conductor is smaller than the width of the second metal conductor.

[0254] 32. The power transistor of clause 31, wherein the current flowing in each laterally-oriented metal conductor in the second metal layer exceeds the current flowing in each laterally-oriented metal conductor in the first metal layer.

[0255] 33. The power transistor of clause 31, wherein the resistance of each laterally-oriented metal conductor in the second metal layer is less than the resistance of each laterally-oriented metal conductor in the first metal layer.

[0256] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A device for power conversion, comprising: An integrated circuit for power conversion, the integrated circuit comprising: a plurality of power transistors; and a plurality of metal regions coupled to the plurality of power transistors, wherein: a first portion of the metal region coupled to source regions of the plurality of power transistors; A second portion of the metal region is coupled to drain regions of the plurality of power transistors; and The first portion and the second portion have at least one of a substantially equal number of metal regions, a substantially equal resistance, or a balanced distribution of metal regions.

2. The apparatus according to claim 1, wherein the integrated circuit is to be mounted on a circuit board, the circuit board comprising a surface and a plurality of conductive lines extending in a direction perpendicular to the surface, the integrated circuit being to be coupled to the conductive lines.

3. The apparatus of claim 2, wherein the integrated circuit is coupled to an inductor mounted on the surface of the circuit board through at least one of the conductive traces, and wherein at least a portion of the integrated circuit is below the inductor.

4. The device according to any one of claims 1 to 3, wherein The plurality of metal regions include: a plurality of first metal regions in the first layer, the first metal regions having a first width; and a plurality of second metal regions in a second layer, the second metal regions having a second width, the second layer being above the first layer, Wherein, the second width is greater than the first width.

5. The device according to claim 4, wherein The second width is twice the first width.

6. The device according to claim 4 or 5, wherein: The plurality of metal regions further include: a plurality of third metal regions in a third layer, the third metal regions having a third width, the third layer being above the second layer, Wherein, the third width is greater than the second width.

7. The device according to claim 6, wherein The third width is twice the second width.

8. The device according to claim 6 or 7, wherein: The plurality of metal regions further include: a plurality of fourth metal regions in a fourth layer below the first layer and having a fourth width, wherein: a first portion of the fourth metal region coupled to source regions of the plurality of power transistors; A second portion of the fourth metal region is coupled to drain regions of the plurality of power transistors; and The fourth width is significantly smaller than the first width.

9. The device according to any one of claims 1 to 8, wherein The plurality of metal regions include: a plurality of first metal regions extending along a first direction in the first layer; and a plurality of second metal regions extending along a second direction in a second layer, the second layer being above the first layer, The second direction is perpendicular to the first direction.

10. The device according to claim 9, wherein The plurality of metal regions further include: A plurality of third metal regions extending along the first direction in a third layer, the third layer being above the second layer.

11. The device according to claim 10, wherein The plurality of power transistors include: a plurality of gate regions extending along the second direction, Wherein, both ends of the gate regions of the plurality of power transistors are coupled to a portion of the first metal region.

12. The device according to claim 11, wherein The integrated circuit further comprises: a plurality of fourth metal regions extending along the second direction in a fourth layer, the fourth layer being above the third layer, The fourth metal region and the gate region extend along the same second direction.

13. The device according to claim 11, wherein The integrated circuit further comprises: a plurality of first vias coupled between the first metal region and the second metal region; and a plurality of second vias coupled between the second metal region and the third metal region, wherein: The first vias have a balanced distribution on the plurality of power transistors; and The second vias have a balanced distribution on the plurality of power transistors.

14. The apparatus according to claim 2, wherein: The conductive traces are located on a common edge of the circuit board.

15. The device according to claim 2 or 14, wherein The integrated circuit will be embedded inside the circuit board.

16. The apparatus according to claim 15, wherein: The circuit board includes a first layer, a second layer and a third layer; The second layer is between the first layer and the third layer; and The integrated circuit is mounted in the second layer.

17. The apparatus according to claim 15, wherein: The circuit board includes a first metal layer and a second metal layer; The conductive line is coupled between the first metal layer and the second metal layer; and The integrated circuit is coupled to the conductive traces in the second metal layer.

18. The apparatus according to claim 2, wherein: The surface is a first surface; The circuit board further includes a second surface; and The integrated circuit is mounted on the second surface.

19. The device according to claim 3, wherein The inductor is connected to buck converter circuitry within the integrated circuit through the conductive line.

20. The device according to claim 3, wherein The inductor is connected to the integrated circuit through the plurality of conductive lines.

21. The device according to claim 3, wherein The inductor is a coupled inductor.

22. The device according to claim 3, wherein The inductor is a chip inductor.

23. The apparatus of claim 3, wherein: The integrated circuit includes charge pump circuitry and buck converter circuitry; and The buck converter circuitry is connected to the inductor via at least one of the conductive lines.

24. The apparatus of claim 3, wherein: The integrated circuit includes charge pump circuitry for two or more charge pumps and buck converter circuitry for at least two buck converters; The inductor includes at least two chip inductors; and The at least two buck converters are respectively connected to corresponding chip inductors among the at least two chip inductors through corresponding conductive lines.

25. The apparatus of claim 3, wherein: The integrated circuit includes a plurality of output terminals for outputting current; The output terminal is directly coupled to the conductive line; as well as The conductive trace extends directly from the output terminal in a direction perpendicular to the surface and extends to the inductor.

26. The device according to claim 25, wherein The output terminal is within the portion of the integrated circuit below the inductor.

27. The apparatus according to claim 3, wherein The inductor includes a plurality of coupled inductors that share an inductor core.

28. The apparatus of claim 27, wherein: The integrated circuit includes a control circuit; The control circuit determines an output configuration of the coupled inductor; and The coupled inductor fans out multiple voltage outputs.

29. The apparatus of claim 27, wherein: The integrated circuit includes a control circuit; The control circuit outputs a vertical current from the integrated circuit to the inductor, the vertical current flowing in a direction perpendicular to the surface of the integrated circuit.

30. A power transistor for power conversion, comprising: Multiple active regions; Multiple terminals; as well as multiple conductive paths; in: each terminal being electrically coupled to at least one of the active regions via at least one of the conductive paths; Each conductive path includes one or more laterally oriented metal conductors and one or more vertically oriented metal conductors; as well as In a majority of the conductive paths, a sum of the lengths of the one or more vertically-oriented metallic conductors exceeds a sum of the lengths of the one or more laterally-oriented metallic conductors.

31. The power transistor according to claim 30, wherein The transversely oriented metal conductor comprises: a first metal conductor in a first metal layer over the active area; and a second metal conductor in a second metal layer above the first metal layer, Wherein, the width of the first metal conductor is smaller than the width of the second metal conductor.

32. The power transistor according to claim 31, wherein The current flowing in each laterally-oriented metal conductor in the second metal layer exceeds the current flowing in each laterally-oriented metal conductor in the first metal layer.

33. The power transistor according to claim 31 or 32, wherein: The resistance of each laterally-oriented metal conductor in the second metal layer is less than the resistance of each laterally-oriented metal conductor in the first metal layer.

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