DRAM unit and manufacturing method thereof

Abstract

The semiconductor structure includes a semiconductor layer, a first gate structure, a second gate structure, a first dielectric layer, a first capacitor, and a second capacitor. The semiconductor layer includes a first cell region and a second cell region. The first cell region includes a first source region, a first drain region, and a first body region between the first source region and the first drain region. The second cell region includes a second source region, a second drain region, and a second body region between the second source region and the second drain region. A first gate structure is on the first side of the semiconductor layer and over the first body region, and a second gate structure is on the first side of the semiconductor layer and over the second body region.

Description

[0001] background

[0002] Related applications

[0003] This application claims priority to U.S. Provisional Patent Application No. 63 / 382,726, filed on November 8, 2022, entitled “Structures and Processes Including Etch Stop Layers,” which is incorporated herein by reference in its entirety. Technical Field

[0004] The present disclosure relates to DRAM cells and methods of manufacturing the same; more particularly, to DRAM cells including capacitors located behind transistors. Background Art

[0005] Memory devices are widely used in a variety of applications. In a memory device, many memory cells are connected in series to form an array for storing data. There are two main types of memory cells: non-volatile memory cells, such as read-only memory (ROM) cells, erasable programmable read-only memory (EPROM) cells, and electrically erasable programmable read-only memory (EEPROM) cells, and volatile memory cells, such as dynamic random access memory (DRAM) cells and static random access memory (SRAM) cells.

[0006] Due to its large storage capacity and low cost, DRAM is one of the most widely used memory storage devices and plays an important role in temporarily storing data for convenient and fast data access. Traditional DRAM cells may include transistors and capacitors (1T1C structure). By charging and discharging the capacitor, the DRAM cell is in the "1" or "0" state, and the transistor controls the access of data. As the density of memory cells needs to increase, the size of memory cells needs to become smaller. However, as the size of capacitors decreases, the effective capacitance of each cell may also decrease. Therefore, in the development of DRAM-based memory devices, the trade-off between capacity and device area has become a major challenge.

[0007] It is therefore desirable to have an improved DRAM cell structure and method of manufacturing the same. Summary of the Invention

[0008] According to the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a semiconductor layer, a first gate structure, a second gate structure, a first dielectric layer, a first capacitor, and a second capacitor. The semiconductor layer includes a first cell region and a second cell region. The first cell region includes a first source region, a first drain region, and a first body region between the first source region and the first drain region. The second cell region includes a second source region, a second drain region, and a second body region between the second source region and the second drain region. The first gate structure is located on a first side of the semiconductor layer and above the first body region, and the second gate structure is located on the first side of the semiconductor layer and above the second body region. The first dielectric layer is located on a second side of the semiconductor layer opposite the first side. The first dielectric layer contacts the semiconductor layer and overlaps both the first source region and the second source region. The first capacitor is located on the second side of the semiconductor layer and is electrically connected to the first source region. The second capacitor is located on the second side of the semiconductor layer and is electrically connected to the second source region.

[0009] In one embodiment, the thickness of the first dielectric layer is in a range from about 2 nm to about 700 nm.

[0010] In one embodiment, the semiconductor structure further includes an isolation structure located between the first source region and the second source region.

[0011] In one embodiment, the first dielectric layer overlaps and contacts the isolation structure.

[0012] In one embodiment, a first interface between the first dielectric layer and the first cell region extends laterally across the first source region, the first drain region, and the first body region; a second interface between the first dielectric layer and the second cell region extends laterally across the second source region, the second drain region, and the second body region; and a third interface between the first dielectric layer and the isolation structure extends from the first interface to the second interface.

[0013] In one embodiment, the first interface, the second interface, and the third interface together form a planar interface having a flatness less than 2 μm and a smoothness less than 2 nm.

[0014] In one embodiment, the semiconductor structure further includes a third capacitor and a fourth capacitor located on the first side of the semiconductor layer, wherein the third capacitor is electrically connected to the first source region, and the fourth capacitor is electrically connected to the second source region.

[0015] In one embodiment, the first dielectric layer includes an etch stop layer, and the etch stop layer includes silicon nitride or silicon oxynitride.

[0016] In one embodiment, the first dielectric layer includes an intermediate layer including silicon oxide or a low-k dielectric material.

[0017] In one embodiment, the first capacitor includes a first electrode electrically connected to the first source region, a second electrode, and a capacitor dielectric located between the first electrode and the second electrode.

[0018] In one embodiment, each of the first electrode and the second electrode includes polysilicon, a metal, or a conductive metal compound.

[0019] In one embodiment, the capacitor dielectric comprises a high-k material.

[0020] In one embodiment, the first electrode is in a container shape, a column shape, a multi-fin shape, or a flat plate shape.

[0021] In one embodiment, the semiconductor structure further includes a first contact structure extending through the first dielectric layer and a second contact structure extending through the first dielectric layer, wherein the first capacitor is electrically connected to the first source region through the first contact structure, and the second capacitor is electrically connected to the second source region through the second contact structure.

[0022] In one embodiment, the height of the first contact structure is substantially equal to the thickness of the first dielectric layer.

[0023] In one embodiment, the height of the first contact structure is in a range from about 2 nm to about 700 nm.

[0024] In one embodiment, a lateral spacing between the first contact structure and the second contact structure is less than 2.5 times a minimum critical dimension.

[0025] In one embodiment, the semiconductor layer comprises a single crystalline semiconductor material.

[0026] According to the present disclosure, a method for manufacturing a semiconductor structure is provided. The method includes providing a semiconductor substrate, the semiconductor substrate including a first substrate, a second substrate located on the first substrate, and a bonding layer located between the first substrate and the second substrate (step (a)). The method includes forming a source region and a drain region in the second substrate, and forming a gate structure on a first side of the second substrate (step (b)). The method includes adding a third substrate to the first side of the second substrate, wherein the second substrate is located between the third substrate and the first substrate (step (c)). The method includes removing the first substrate and the bonding layer (step (d)). The method includes forming a first capacitor on a second side of the second substrate opposite to the first side, wherein the first capacitor is electrically connected to the source region (step (e)).

[0027] In one embodiment, the semiconductor substrate further comprises an etch stop layer between the bonding layer and the second substrate, and the method further comprises, before step (e), (f) removing at least a portion of the etch stop layer.

[0028] In one embodiment, the bonding layer comprises silicon oxide, and the etch stop layer comprises silicon nitride, silicon oxynitride, a doped semiconductor material, an undoped semiconductor material, a metal, or a conductive metal compound.

[0029] In one embodiment, step (f) includes forming an opening extending through the etch stop layer to expose the source region and forming a contact structure in the opening, and step (e) includes forming the first capacitor electrically connected to the contact structure.

[0030] In one embodiment, the second substrate includes silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN).

[0031] In one embodiment, the method further comprises, after step (d), forming a dielectric layer on the second side of the second substrate.

[0032] In one embodiment, the method further includes forming an opening extending through the dielectric layer to expose the source region and forming a contact structure in the opening, wherein step (e) includes forming the first capacitor electrically connected to the contact structure.

[0033] In one embodiment, the semiconductor substrate further includes an intermediate layer located between the etch stop layer and the second substrate.

[0034] In one embodiment, the intermediate layer comprises silicon oxide or a low-k dielectric material.

[0035] In one embodiment, step (f) includes removing the etch stop layer to expose the intermediate layer.

[0036] In one embodiment, the method further includes forming an opening extending through the intermediate layer to expose the source region and forming a contact structure in the opening, wherein step (e) includes forming the first capacitor electrically connected to the contact structure.

[0037] In one embodiment, the method further comprises forming an interconnect structure on the first side of the second substrate before step (c), wherein the interconnect structure is electrically connected to the drain region or the gate structure.

[0038] In one embodiment, the method further comprises forming a second capacitor on the first side of the second substrate before step (c), wherein the second capacitor is electrically connected to the source region.

[0039] In one embodiment, step (d) comprises etching the bonding layer with a first etchant.

[0040] In one embodiment, step (d) includes completely removing the bonding layer of the semiconductor substrate.

[0041] In one embodiment, step (f) includes etching the etch stop layer with a second etchant.

[0042] In one embodiment, the method further comprises, before step (c), (g) forming an isolation structure.

[0043] In one embodiment, step (g) includes removing a portion of the second substrate to form a trench extending through the second substrate (step (g1)). Step (g) includes forming an etch stop layer on a bottom surface of the trench (step (g2)). Step (g) includes forming the isolation structure in the trench (step (g3)).

[0044] In one embodiment, step (d) includes removing the first substrate to expose the bonding layer (step (d1)). Step (d) includes removing the bonding layer to expose the etch stop layer (step (d2)).

[0045] In this disclosure, a new DRAM cell including a one transistor and two capacitors structure (1T2C) is introduced, and a method for manufacturing the same is also introduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 FIG. 1 is a schematic diagram illustrating a semiconductor structure according to the present disclosure.

[0047] Figures 2A to 2KA schematic diagram illustrating an intermediate stage of manufacturing a semiconductor structure according to the present disclosure is shown, wherein the semiconductor structure is similar to Figure 1 The semiconductor structure shown in .

[0048] Figures 3A to 3D A schematic diagram illustrating an intermediate stage of manufacturing a semiconductor structure according to the present disclosure is shown, wherein the semiconductor structure is similar to Figure 1 The semiconductor structure shown in .

[0049] Figure 4 FIG. 1 is a schematic diagram illustrating a semiconductor structure according to the present disclosure.

[0050] Figure 5 FIG. 1 is a schematic diagram illustrating a semiconductor structure according to the present disclosure.

[0051] Figure 6 FIG. 1 is a schematic diagram illustrating a semiconductor structure according to the present disclosure.

[0052] Figure 7 FIG. 1 is a schematic diagram illustrating a semiconductor structure according to the present disclosure.

[0053] Figures 8A to 8J A schematic diagram illustrating an intermediate stage of manufacturing a semiconductor structure according to the present disclosure is shown, wherein the semiconductor structure is similar to Figure 1 The semiconductor structure shown in .

[0054] Figures 9A to 9H A schematic diagram illustrating an intermediate stage of manufacturing a semiconductor structure according to the present disclosure is shown, wherein the semiconductor structure is similar to Figure 1 The semiconductor structure shown in . DETAILED DESCRIPTION

[0055] Even when used in conjunction with a detailed description of certain specific embodiments of this field, the terms used in the following description are intended to be interpreted in the broadest reasonable manner. Although specific terms may be emphasized below, any term intended to be interpreted in any limiting manner will be defined in this embodiment section. Components or functions of semiconductor structures or devices according to the present disclosure may be depicted in the following figures or embodiments, however, the size and shape of the semiconductor structures or devices shown in the figures do not limit the features of the present disclosure.

[0056] As used herein, the term "on" may mean directly over or indirectly over through intervening elements or layers. Spatially relative terms such as "beneath," "below," "lower," "above," "over," "upper," and the like may be used herein to simplify describing the relationship of one element or feature to another element or feature depicted in a figure. These spatially relative terms are intended to encompass different orientations of the device in use or operation relative to that shown in the figures. For example, if the device in the figures is turned over, an element described as "below" or "beneath" another element or feature would then be oriented "above" the other element or feature, thus the exemplary term "below" would encompass both "above" and "below" orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0057] Figure 1 FIG1 is a schematic diagram illustrating an embodiment of a semiconductor structure according to the present disclosure. Figure 1 As shown, the semiconductor structure 100 includes a semiconductor layer 40, a first gate structure 55 and a second gate structure 55' on a first side 40a of the semiconductor layer 40, a first dielectric layer 90 on a second side 40b of the semiconductor layer 40 opposite to the first side 40a, and a first capacitor 60a and a second capacitor 60a' on the second side 40b of the semiconductor layer 40.

[0058] The semiconductor layer 40 comprises a layer of semiconductor material. The semiconductor material of the semiconductor layer 40 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. The semiconductor layer 40 may be a single crystal semiconductor substrate, for example, made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In one embodiment, the thickness of the semiconductor layer 40 may be in the range of 5 nm to 0.2 μm. For example, the thickness of the semiconductor layer 40 may be 10 nm, 25 nm, 50 nm, or 100 nm. These values ​​are provided as examples only and are not intended to be limiting. The semiconductor layer 40 includes a first unit region 50 and a second unit region 50 ′. The first cell region 50 includes a first source region 51, a first drain region 52, and a first body region 53. Each of the first source region 51, the first drain region 52, and the first body region 53 includes a semiconductor material. The first body region 53 is located between the first source region 51 and the first drain region 52.

[0059] In one embodiment, the first source region 51 and the first drain region 52 may be doped with a first type of dopant (e.g., a p-type dopant such as boron, aluminum, gallium, indium, or a combination thereof; or an n-type dopant such as phosphorus, arsenic, antimony, bismuth, or a combination thereof), and the first body region 53 may be doped with a second type of dopant different from the first type of dopant. In one embodiment, the doping concentration of the first source region 51 and the first drain region 52 may be approximately 3.0×10 19 atoms / cm 3 to about 3.0×10 21 atoms / cm 3 In one embodiment, the doping concentration of the first body region 53 may be about 1.0×10 15 atoms / cm 3 to about 1.0×10 19 atoms / cm 3 These values ​​are examples only and are not intended to be limiting. In one embodiment, the first source region 51, the second source region 51', the first drain region 52, and the second drain region 52' may be doped with a first type of dopant, and the first body region 53 may be undoped. Figure 1 In the illustrated embodiment, the first source region 51 and the first drain region 52 extend through the thickness of the first semiconductor layer 40 .

[0060] The second unit region 50' includes a second source region 51', a second drain region 52' and a second body region 53'. The second source region 51', the second drain region 52' and the second body region 53' may be similar to the first source region 51, the first drain region 52 and the first body region 53, respectively. Each of the second source region 51', the second drain region 52' and the second body region 53' includes a semiconductor material. The second body region 52' is a region located between the second source region 51' and the second drain region 52'. In some embodiments, the second source region 51' and the second drain region 52' may be doped with the same dopant as the first source region 51 and the first drain region 52, and the second body region 53' may be doped with the same dopant as the first body region 53. Figure 1 In the illustrated embodiment, the second source region 51 ′ and the second drain region 52 ′ extend through the thickness of the first semiconductor layer 40 .

[0061] A first gate structure 55 is located on the first side 40a of the semiconductor layer 40 and above the first body region 53. A first gate dielectric 54 may be located between the first body region 53 and the first gate structure 55. The first source region 51, the first drain region 52, the first body region 53, the first gate dielectric 54, and the first gate structure 55 may function as a first transistor. Similarly, a second gate structure 55′ is located on the first side 40a of the semiconductor layer 40 and above the second body region 53′. The second gate dielectric 54′ may be located between the second body region 53′ and the second gate structure 55′, and the second source region 51′, the second drain region 52′, the second body region 53′, the second gate dielectric 54′, and the second gate structure 55′ may function as a second transistor.

[0062] The first gate dielectric 54 and the second gate dielectric 54' can each comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material including, but not limited to, hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide, any suitable material, and combinations thereof. The first gate structure 55 and the second gate structure 55' can each comprise a conductive material. By way of example and not limitation, the conductive material can include doped polycrystalline or amorphous silicon, germanium, silicon germanium, a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, and gold), a conductive metal compound material (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, aluminum titanium carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, and nickel silicide), carbon nanotubes, conductive carbon, graphene, or any suitable combination thereof. The conductive material may further include dopants that are doped in during or after deposition. In some embodiments, the first gate structure 55 and the second gate structure 55' may each include a stack of conductive material layers.

[0063] The semiconductor structure 100 includes a first capacitor 60a and a second capacitor 60a' on the second side 40b of the semiconductor layer 40. The first capacitor 60a is electrically connected to the first source region 51, and the second capacitor 60a' is electrically connected to the second source region 51'. As such, the first capacitor 60a and the second capacitor 60a' can each serve as a capacitor of a memory cell. The first capacitor 60a can include a first electrode 61a, a second electrode 63a, and a capacitor dielectric 62a located between the first electrode 61a and the second electrode 63a, wherein the first electrode 61a of the first capacitor 60a is electrically connected to the first source region 51. The second capacitor 60a' can be substantially similar to the first capacitor 60a. The second capacitor 60a' can include a first electrode 61a', a second electrode 63a', and a capacitor dielectric 62a' located between the first electrode 61a' and the second electrode 63a', wherein the first electrode 61a' of the second capacitor 60a' is electrically connected to the second source region 51'. The first electrodes 61a and 61a' and the second electrodes 63a and 63a' can each include at least one conductive material, including but not limited to metals such as W, Ni, Ta, Pt, Cu, Ag, Au, Al, Mo, Ti, Ir, or Ru; doped semiconductor materials such as doped polysilicon and doped germanium; conductive metal compounds such as metal silicides, metal carbides, or metal nitrides, such as WN, TaN, TaSi, TiN, TiSi, TiSiN, TiAlN, MoN, IrOx, RuOx, or RuTiN. The capacitor dielectrics 62a and 62a' can each include silicon oxide or a high-k dielectric material, including but not limited to hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, any suitable material, and / or combinations thereof.

[0064] exist Figure 1 In the embodiment shown, the first electrode 61a of the first capacitor 60a and the first electrode 61a' of the second capacitor 60a' are both pillar-shaped. However, the shapes of the first electrodes 61a and 61a' can be adjusted according to actual applications. Figure 1In the illustrated embodiment, the second electrode 63a of the first capacitor 60a and the second electrode 63a' of the second capacitor 60a' are electrically connected to each other. Depending on the design of the memory array, the second electrodes 63a and 63a' can be further connected to the second electrodes of other capacitors (not shown) connected to other cell regions. By including capacitors on the second side of the semiconductor layer, more capacitors can be connected to the cell regions (for example, capacitors on both sides of the semiconductor can be connected to the source region of the memory cell), which can increase the equivalent capacitance of each cell and provide the capacitance required for memory cells with smaller cell sizes (such as DRAM cells). Furthermore, the capacitors on the second side of the semiconductor layer in the present disclosure can have greater flexibility in capacitor shape and size, which can increase the equivalent capacitance of each cell and / or improve performance.

[0065] The first dielectric layer 90 is located on the second side 40b of the semiconductor layer 40 and contacts the semiconductor layer 40. The first dielectric layer 90 may extend across a plurality of device regions in the semiconductor layer 40. Figure 1 As shown, the first dielectric layer 90 overlaps the first source region 51, the first drain region 52, and the first body region 53 of the first cell region 50, and the second source region 51', the second drain region 52', and the second body region 53' of the second cell region 50'. Although contacts (e.g., the first contact structure 57 and the second contact structure 57') may extend through the first dielectric layer 90 for desired electrical connection, the first dielectric layer 90 extends continuously from a location above the first cell region 50 to a location above the second cell region 50'. In this way, the first dielectric layer 90 provides electrical isolation between regions in the semiconductor layer 40 (e.g., the first drain region 52, the first body region 53, the second drain region 52', and the second body region 53') and components and / or portions of components on the second side 40b of the semiconductor layer 40 (e.g., the first electrodes 61a and 61a' and the second electrodes 63a and 63a'). The first dielectric layer 90 also provides electrical isolation between the first contact structure 57 and the second contact structure 57'. In one embodiment, the first dielectric layer 90 may include one or more layers of dielectric materials, such as silicon oxide, silicon oxynitride, low-k dielectric materials, combinations thereof, and / or other applicable materials. In some embodiments, the thickness T1 of the first dielectric layer 90 is in a range of approximately 2 nm to 700 nm. In some embodiments, the thickness T1 of the first dielectric layer 90 is in a range of approximately 2 nm to approximately 30 nm.

[0066] The semiconductor structure 100 may further include an isolation structure 42, such as a shallow trench isolation (STI) structure, located between the first source region 51 and the second source region 51'. The isolation structure 42 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, combinations thereof, and / or other suitable materials. In one embodiment, the first dielectric layer 90 contacts and overlaps the isolation structure 42.

[0067] like Figure 1 As shown, a first interface S1 between the first dielectric layer 90 and the first cell region 50 of the semiconductor layer 40 extends laterally across the first source region 51, the first drain region 52, and the first body region 53 of the first cell region 50; and a second interface S2 between the first dielectric layer 90 and the second cell region 50' of the semiconductor layer 40 extends laterally across the second source region 51', the second drain region 52', and the second body region 53' of the second cell region 50'. A third interface S3 between the first dielectric layer 90 and the isolation structure 42 extends from the first interface S1 to the second interface S2. Each of the first interface S1, the second interface S2, and the third interface S3 is planar, such that the first interface S1, the second interface S2, and the third interface S3 collectively form a planar interface S. In some embodiments, the planar interface S spanning multiple cell regions in the same wafer on which the cells are fabricated has a flatness of less than 2 μm. In some embodiments, the smoothness of the peak-to-valley height of the planar interface S across the first interface S1, the second interface S2, and the third interface S3 is less than 2 nm. However, the present disclosure is not limited thereto. By configuring a planar surface between the first dielectric layer and the cell region, the plurality of transistors in the memory array can have more stable and consistent electrical performance and lower leakage current due to smaller differences between different cell regions and / or fewer defects at the interface, especially when the semiconductor layer in which the cell region is located is thin.

[0068] exist Figure 1In the illustrated embodiment, the semiconductor structure further includes a first contact structure 57 and a second contact structure 57'. The first contact structure 57 may extend through the first dielectric layer 90, and the first electrode 61a of the first capacitor 60a may be electrically connected to the first source region 51 via the first contact structure 57. Similarly, the second contact structure 57' may extend through the first dielectric layer 90, and the first electrode 61a' of the second capacitor 60a' may be electrically connected to the second source region 51' via the second contact structure 57'. The first and second contact structures 57', 57' may each comprise polysilicon, a metal, a conductive metal compound, a combination thereof, or multiple layers thereof. In one embodiment, the first contact structure 57 and the first electrode 61a of the first capacitor 60a may be formed of the same material, and the second contact structure 57' and the first electrode 61a' of the second capacitor 60a' may be formed of the same material. In one embodiment, the first contact structure 57 and the first electrode 61a of the first capacitor 60a may be integrally formed, and the second contact structure 57' and the first electrode 61a' of the second capacitor 60a' may be integrally formed.

[0069] The first contact structure 57 and the second contact structure 57' may be formed in the openings in the first dielectric layer 90. Figure 1 As shown, the height H1 of the first contact structure 57 is substantially equal to the thickness T1 of the first dielectric layer 90. In one embodiment, the height H1 of the first contact structure is within a range from about 2 nm to about 700 nm. The height H2 of the second contact structure 57' may be substantially equal to the height H1 of the first contact structure 57. In one embodiment, the first dielectric layer 90 extends continuously between the first contact structure 57 and the second contact structure 57' and provides electrical isolation between the first contact structure 57 and the second contact structure 57'. In this way, the lateral spacing D1 between the first contact structure 57 and the second contact structure 57' can be reduced, and the unit cell size can be reduced. In some embodiments, the lateral spacing D1 between the first contact structure 57 and the second contact structure 57' may be less than 2.5 times the minimum critical dimension (F).

[0070] exist Figure 1In the illustrated embodiment, a dielectric layer 72 may be disposed on the first side 40 a of the semiconductor layer 40. The dielectric layer 72 may include an interlayer dielectric (ILD) layer and / or an intermetal dielectric (IMD) layer and may include a dielectric material such as silicon oxide, silicon oxynitride, a low-k dielectric material, combinations thereof, and / or other suitable materials. Exemplary low-k dielectric materials include hydrogen silsesquioxane (HSQ), fluoride silicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), silicon carbide, spin-on-glass (Spin-On-Glass), other suitable low-k materials, and / or combinations thereof.

[0071] exist Figure 1 In the illustrated embodiment, the semiconductor structure 100 may further include a third capacitor 60b and a fourth capacitor 60b' on the first side 40a of the semiconductor layer 40. The third capacitor 60b is electrically connected to the first source region 51, and the fourth capacitor 60b' is electrically connected to the second source region 51'. In this way, the third capacitor 60b and the first capacitor 60a can serve as capacitors for a memory cell, and the fourth capacitor 60b' and the second capacitor 60a' can serve as capacitors for another memory cell. However, in some embodiments, the third capacitor 60b and the fourth capacitor 60b' are not required. The third capacitor 60b includes a first electrode 61b, a second electrode 63b, and a capacitor dielectric 62b located between the first electrode 61b and the second electrode 63b. The fourth capacitor 60' includes a first electrode 61b', a second electrode 63b', and a capacitor dielectric 62b' located between the first electrode 61b' and the second electrode 63b'. In one embodiment, the first electrodes 61b and 61b' and the second electrodes 63b and 63b' may each comprise at least one conductive material, including but not limited to a metal, a conductive metal compound, or a doped semiconductor material, such as doped polysilicon or doped germanium. The capacitor dielectrics 62b and 62b' may each comprise silicon oxide, a high-k dielectric material, including but not limited to hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide, any suitable material, and / or combinations thereof. The second electrodes 63b and 63b' may be electrically connected to each other and, depending on the design of the memory array, may further be connected to the second electrodes of other capacitors (not shown) connected to other cell regions.

[0072] In one embodiment, the semiconductor structure 100 may further include a first drain contact structure 56 and a second drain contact structure 56'. The first drain contact structure 56 is physically and electrically coupled to the first drain region 52, and the second drain contact structure 56' is physically and electrically coupled to the second drain region 52'. In one embodiment, the first drain contact structure 56 and the second drain contact structure 56' may be formed through one or more dielectric layers 72. The first drain contact 56 and the second drain contact 56' may each include titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, copper, some other suitable material, or a combination thereof.

[0073] The semiconductor structure 100 may further include an interconnect structure 70. The interconnect structure 70 may include conductive features (e.g., conductive lines or vias) electrically connected to the first drain region 52 and / or the second drain region 52′ and / or conductive features electrically connected to the first gate structure 55 and / or the second gate structure 55′. The interconnect structure 70 may include titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, copper, some other suitable material, or combinations thereof.

[0074] In one embodiment, the semiconductor structure may further include a second dielectric layer 94 on the second side 40b of the semiconductor layer 40, with the first dielectric layer 90 located between the second dielectric layer 94 and the semiconductor layer 40. The second dielectric layer 94 may include one or more layers of dielectric materials, such as silicon oxide, silicon oxynitride, low-k dielectric materials, combinations thereof, and / or other suitable materials. In one embodiment, the second dielectric layer 94 may include the same material as the first dielectric layer 90. Figure 1 In the illustrated embodiment, the second dielectric layer 94 surrounds the first capacitor 60a and the second capacitor 60a'. However, depending on actual requirements and the design of the memory array, only a portion of the first capacitor 60a and a portion of the second capacitor 60a' may be surrounded by the second dielectric layer 94.

[0075] Figures 2A to 2K A schematic diagram illustrating an intermediate stage in the manufacture of a semiconductor structure similar to Figure 1 A semiconductor structure is shown, wherein like reference numerals indicate like elements.

[0076] like Figure 2A As shown, a semiconductor substrate A1 is provided (step (a)). The semiconductor substrate A1 includes a first substrate 10, a second substrate 40 on the first substrate 10, and a bonding layer 20 between the first substrate 10 and the second substrate 40. Figure 2A In the illustrated embodiment, the semiconductor substrate A1 further includes an etch stop layer 30 between the bonding layer 20 and the second substrate 40 .

[0077] In one embodiment, each of the first substrate 10 and the second substrate 40 is a wafer having a diameter of 6, 8, 12, or 18 inches. In this case, the first substrate 10 may be referred to as a handle wafer and the second substrate 40 may be referred to as a device wafer. The first substrate 10 and the second substrate 40 may each be a single crystal semiconductor substrate, for example, made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In other embodiments, the first substrate 10 may include glass, polysilicon, or ceramic. In one embodiment, the thickness of the second substrate 40 may be in the range of 5 nm to 0.2 μm. This value is only an example and is not intended to be limiting.

[0078] The etch stop layer 30 has a high etch selectivity relative to the bonding layer 20. The etch selectivity of the etch stop layer 30 relative to the bonding layer 20 may refer to the ratio of the etch rate of the bonding layer 20 to the etch rate of the etch stop layer 30 under the same etching conditions. When the etch rate of the bonding layer 20 is substantially faster than the etch rate of the etch stop layer 30 under the same etching conditions, the etch stop layer 30 may have a high etch selectivity relative to the bonding layer 20. In some embodiments, the etch selectivity of the etch stop layer 30 relative to the bonding layer 20 may be higher than 5:1, 10:1, 20:1, 30:1, 50:1, 80:1, 100:1, 200:1, or 300:1. The etching process may be a dry etching process or a wet etching process depending on the materials of the etch stop layer 30 and the bonding layer 20.

[0079] For example, in one embodiment, when the etch stop layer 30 comprises silicon nitride and the bonding layer 20 comprises silicon oxide, a wet etch may be performed using dilute HF (e.g., a weight ratio of H2O to HF of approximately 100:1) as an etchant, and the etch rate of the etch stop layer 30 may be approximately The etching rate of the bonding layer 20 can be approximately It provides an etching selectivity of about 30:1 (oxide / nitride). In another embodiment, when the etch stop layer 30 includes silicon oxynitride and the bonding layer 20 includes silicon oxide, buffered hydrofluoric acid (for example, a solution of 6.6% (weight percentage) HF and 35.7% (weight percentage) NH4F in water) can be used as an etchant to perform wet etching, and the etching rate of the etch stop layer 30 can be about 24.5 nm / min, and the etching rate of the bonding layer 20 can be about 305.7 nm / min, which provides an etching selectivity of about 12.5:1 (oxide / nitride oxide). The present disclosure is not limited to this. Suitable materials for the etch stop layer 30 and the bonding layer 20 can be selected and suitable etching conditions can be selected according to actual needs and material properties. For example, the materials of the etch stop layer 30 and the bonding layer 20 can be selected so that the etch stop layer 30 can serve as an etch stop layer with a higher etching selectivity relative to the bonding layer and / or can serve as an etch stop layer under more ideal etching conditions.

[0080] In some embodiments, the bonding layer 20 includes an oxide such as silicon oxide, and the etch stop layer 30 may include silicon nitride, silicon oxynitride, a doped semiconductor material, an undoped semiconductor material, a metal, a conductive metal compound, or a combination thereof. The doped semiconductor material may be a semiconductor material doped with a p-type dopant, such as boron, aluminum, gallium, indium, or the like, or a combination thereof, or may be a semiconductor material doped with an n-type dopant, such as phosphorus, arsenic, antimony, bismuth, or the like, or a combination thereof. The undoped semiconductor material may be amorphous silicon, polycrystalline silicon, or silicon germanium, or the like, or a combination thereof. In one embodiment, the thickness of the bonding layer 20 may be in a range between 0.2 nm and 1000 nm. In one embodiment, the thickness of the etch stop layer 30 may be in a range between 0.2 nm and 5 nm. However, the present disclosure is not limited thereto. In some embodiments, the thickness of the etch stop layer 30 may be in a range between 0.2 nm and 700 nm, for example, between 2 nm and 700 nm. These values ​​are provided as examples only and are not intended to be limiting. In some embodiments, the etch stop layer 30 can be formed on a substrate (not shown) including the second substrate 40 by epitaxial growth or a deposition process such as CVD, PVD, or ALD, and after the etch stop layer 30 is formed, the substrate can be bonded to the first substrate 10 via the bonding layer 20. In some embodiments, a portion of the substrate can be removed after bonding, while the second substrate 40 remains in the semiconductor substrate A1. A semiconductor substrate including an etch stop layer can be manufactured by bonding two substrates, and the related process is described in application document No. PCT / US23 / 69597, the contents of which are incorporated herein by reference.

[0081] like Figure 2BAs shown, an isolation structure 42 may be formed in the second substrate 40 (step (g)). The isolation structure 42 may be a shallow trench isolation (STI) structure. The isolation structure 42 may include the same structure as described above. Figure 1 Materials similar to those described above may be formed by any suitable method. For example, a trench (not shown) may be etched through second substrate 40 to expose etch stop layer 30, and a dielectric material for forming isolation structure 42 may then be deposited in the trench. A planarization process may also be performed.

[0082] like Figure 2C As shown in , a first source region 51, a second source region 51', a first drain region 52 and a second drain region 52' are formed in the second substrate 40, a first gate structure 55 and a first gate dielectric 54 are formed on the first side 40a of the second substrate 40, and a second gate structure 55' and a second gate dielectric 54' are formed on the first side 40a of the second substrate 40 (step (b)). Figure 2C In the illustrated embodiment, the first source region 51, the first drain region 52, the first body region 53, the first gate dielectric 54 and the first gate structure 55 may serve as a first transistor and may be formed by any suitable method; the second source region 51', the second drain region 52', the second body region 53', the second gate dielectric 54' and the second gate structure 55' may serve as a second transistor and may be formed by any suitable method. In one embodiment, the first source region 51, the second source region 51', the first drain region 52 and the second drain region 52' may be formed by doping the second substrate 40. In one embodiment, a portion of the second substrate 40 may be etched and an epitaxial process may be subsequently performed to form the first source region 51, the second source region 51', the first drain region 52 and the second drain region 52'. Figure 2CIn the illustrated embodiment, the doping process or the etching process is performed in a manner such that a first source region 51, a second source region 51', a first drain region 52, and a second drain region 52' extending through the thickness of the second substrate 40 and in contact with the etch stop layer 30 can be formed. The first gate dielectric 54 and the second gate dielectric 54' can be formed by forming a gate dielectric layer (not shown) on the first side 40a of the second substrate 40 by thermal oxidation, a deposition process such as CVD, PVD, ALD, any suitable method, and / or a combination thereof. The first gate structure 55 and the second gate structure 55' can be formed by forming a gate conductive layer (not shown) on the gate dielectric layer by epitaxial growth, a deposition process such as CVD, PVD, or ALD, any suitable method, and / or a combination thereof. The first source region 51, the second source region 51', the first drain region 52, and the second drain region 52' can be formed before or after the formation of the gate dielectric layer and the gate conductive layer. In some embodiments, a gate replacement process can also be performed subsequently. As Figure 2C As shown, the bottom surface BS3 of the isolation structure 42 is flush with the bottom surfaces BS1 and BS2 of the second substrate 40 in the first cell region 50 and the second cell region 50 ′.

[0083] like Figure 2D As shown, the third capacitor 60b and the fourth capacitor 60b' are formed on the first side 40a of the second substrate 40. The third capacitor 60b and the fourth capacitor 60b' can be formed by any suitable method, which can include a photolithography process, an etching process, a deposition process (e.g., PVD, CVD, ALD, etc.), and / or other applicable processes. For example, the first electrodes 61b and 61b', the capacitor dielectrics 62b and 62b', and the second electrodes 63b and 63b' of the third capacitor 60b and the fourth capacitor 60b' can be deposited on the first side 40a of the second substrate 40. In some embodiments, the first electrode 61b of the third capacitor 60b and the first electrode 61b' of the fourth capacitor 60b' can be deposited in a trench formed in one or more dielectric layers disposed on the first side 40a of the second substrate 40. In some embodiments, the trench can be formed by photolithography patterning and selective anisotropic dry etching.

[0084] The dielectric layer 72 can be formed on the first side 40a of the second substrate 40 by a deposition process such as PVD, CVD, or ALD, a spin coating process, and / or any other suitable method. In some embodiments, the third capacitor 60b and the fourth capacitor 60b' can be formed in one or more dielectric layers in the dielectric layer 72. The first drain contact structure 56, the second drain contact structure 56', and the interconnect structure 70 can be formed in the dielectric layer 72 by any suitable method such as a damascene or dual damascene process.

[0085] like Figure 2E As shown, a third substrate 80 is added to the first side 40a of the second substrate 40, wherein the second substrate 40 is between the third substrate 80 and the first substrate 10 (step (c)). In some embodiments, the third substrate 80 is a wafer having a diameter of 6, 8, 12, or 18 inches. The third substrate 80 can be a handle wafer or a device wafer. In some embodiments, the third substrate 80 can include glass, polycrystalline silicon, or ceramic. In other embodiments, the third substrate 80 can be a single crystal semiconductor substrate, for example, made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). The third substrate 80 can include electronic devices, including but not limited to transistors, diodes, capacitors, and / or resistors. In some embodiments, the devices (not shown) in the third substrate 80 can be electrically coupled to the interconnect structure 70. In one embodiment, the thickness of the third substrate 80 can range from 20 μm to 700 μm. These values ​​are provided as examples only and are not intended to be limiting. The third substrate 80 can provide physical support to the semiconductor structure to prevent damage to devices or structures therein during subsequent processing. In one embodiment, the third substrate 80 can be formed by epitaxial growth, CVD, or PVD. In other embodiments, the third substrate 80 can be bonded to the second substrate 40 by a suitable process such as adhesive bonding or direct bonding.

[0086] like Figure 2F As shown, the first substrate 10 and the bonding layer 20 are removed (step (d)). The first substrate 10 and the bonding layer 20 can be removed by performing suitable processes such as grinding, chemical mechanical polishing (CMP) and etching processes. The etching process can be isotropic etching or anisotropic etching, such as oxide etching, plasma etching, hydrogen peroxide etching, etc. In one embodiment, the first substrate 10 is removed by grinding and / or CMP processes, and the bonding layer 20 including oxide (such as silicon oxide) can be removed by applying a first etchant, such as dilute HF, buffered hydrofluoric acid, as previously described. It should be noted that the etchant and etching conditions can be adjusted according to actual applications, and the present disclosure is not limited thereto. Figure 2F In the embodiment shown, the etch stop layer 30 can be exposed after the first substrate 10 and the bonding layer 20 are removed due to its etching selectivity relative to the bonding layer 20. In one embodiment, the bonding layer 20 is completely removed without using a mask, which can reduce manufacturing costs and preparation time.

[0087] like Figure 2GAs shown, at least a portion of the etch stop layer 30 is removed (step (f)). The etch stop layer 30 can be removed by an etching process such as oxide etching, plasma etching, hydrogen peroxide etching, etc. The etching process can be isotropic etching or anisotropic etching. In one embodiment, the etch stop layer 30 includes silicon nitride, and removing the etch stop layer 30 includes etching the etch stop layer 30 by a second etchant such as hot phosphoric acid, but the present disclosure is not limited thereto. After step (f), at least a portion of the second substrate 40 is exposed. Figure 2G In the embodiment shown, the etch stop layer 30 is completely removed and the etching step can be performed without a mask. Figure 3B ), only a portion of the etch stop layer 30 is removed by a suitable method such as a photolithography and etching process.

[0088] like Figure 2H As shown, a deposited dielectric layer 92 is formed as a first dielectric layer 90 on the second side 40b of the second substrate 40. The deposited dielectric layer 92 may include one or more layers of dielectric materials, such as silicon oxide, silicon oxynitride, low-k dielectric materials, combinations thereof, and / or other suitable materials, and may be formed by a deposition process such as PVD, CVD, or ALD, a spin-on coating process, or any other applicable process.

[0089] The etch stop layer 30 protects the first transistor, the second transistor, and the second side 40b of the isolation structure from the etching process of the bonding layer 20. This prevents defects from forming in the first transistor, the second transistor, and the isolation structure during the etching process, particularly when the second substrate 40 is thin. After removing the etch stop layer 30, the surface of the second substrate 40 exposed can have improved planarity. Consequently, after depositing the dielectric layer 92, a flat interface S can be formed extending from between the deposited dielectric layer 92 and the first cell 50 to between the deposited dielectric layer 92 and the second cell 50'. In some embodiments, the flat interface S has a flatness of less than 2 μm and a smoothness of less than 2 nm. However, the present disclosure is not limited thereto. Furthermore, the methods disclosed herein make it easier to control the thickness of the second substrate (and the cell regions therein). The thickness of the second substrate can be more uniform across multiple cell regions within the same wafer on which the cells are fabricated. This allows cells to have fewer defects in the transistors and achieve less variation in thickness and / or transistor electrical characteristics (such as threshold voltage) between cells. In addition, the etch stop layer 30 can protect the isolation structure 42 during the etching process, so that the isolation structure 42 can remain intact and provide good electrical isolation between cells.

[0090] like Figure 2IAs shown, a first opening 91 and a second opening 91' are formed extending through the deposited dielectric layer 92 to expose the first source region 51 and the second source region 51', respectively. Portions of the dielectric layer 92 can be removed using an etching process through the openings of a patterned mask layer (not shown) to form the first opening 91 and the second opening 91'. Next, the patterned mask layer is removed.

[0091] like Figure 2J As shown, first and second contact structures 57 and 57' are formed in first and second openings 91 and 91', respectively. The first and second contact structures 57 and 57' can each include a metal, a doped semiconductor material, or a conductive metal compound. The first and second contact structures 57 and 57' can be formed by deposition processes such as CVD, PVD, ALD, damascene, dual damascene, or any other applicable method.

[0092] By using the method disclosed herein, a deposited dielectric layer 92 can be formed that is in direct contact with the first source region 51 and the second source region 51' without any residual bonding layer or other portion of the semiconductor layer therebetween. Therefore, during the formation of the opening, it is easier to control the endpoint of the etching process used to expose the source region, so that the opening can be formed to expose the source region while preventing over-etching of the source region. This makes it easier to form a contact structure physically and electrically connected to the corresponding source region in each of the multiple cells. A dielectric layer (such as dielectric layer 92) that provides electrical isolation between adjacent contact structures can also be more easily formed, and the distance between the two contact structures can be reduced to 1F to 2.5F, thereby reducing the cell size.

[0093] like Figure 2K As shown, a first capacitor 60a and a second capacitor 60a' are formed on the second side 40b of the second substrate 40 (step (e)). The first capacitor 60a can be formed to be electrically connected to the first contact structure 57, and the second capacitor 60a' can be formed to be electrically connected to the second contact structure 57'. Therefore, the first capacitor 60a is electrically connected to the first source region 51 and the second capacitor 60' is electrically connected to the second source region 51'. The first capacitor 60a and the second capacitor 60a' can be made by any suitable method, which may include photolithography, etching processes, deposition processes (such as PVD, CVD, ALD, etc.) and / or other applicable processes. For example, the first capacitor 60a and the second capacitor 60a' can be made by a method similar to the aforementioned reference Figure 2D In one embodiment, the first contact structure 57 and the first electrode 61a of the first capacitor 60a may be formed of the same material, and the second contact structure 57 and the first electrode 61a' of the second capacitor 60a' may be formed of the same material. In one embodiment, instead of Figure 2J As shown, the first contact structure 57 and the second contact structure 57' are formed using separate processes. The first contact structure 57 and the first electrode 61a of the first capacitor 60a can be integrally formed, and the second contact structure 57' and the first electrode 61a' of the second capacitor 60a' can be integrally formed. A second dielectric layer 94 can also be formed on the second side 40b of the second substrate 40 and above the deposited dielectric layer 92 using a suitable process, such as a deposition process such as PVD, CVD, or ALD, a spin coating process, and / or any other applicable process.

[0094] The methods disclosed herein make it easier to fabricate capacitors on the second side. Furthermore, this makes it easier to form capacitors with larger sizes and / or advantageous configurations (e.g., advantageous electrode shapes) on the "open" second side of the substrate. Furthermore, forming capacitors on both sides of the transistor can increase the cell capacitance.

[0095] Figures 3A to 3D A schematic diagram depicting an intermediate stage in the fabrication of a semiconductor structure similar to Figure 1 A semiconductor structure is shown, wherein like reference numerals indicate like elements. Figure 3A The semiconductor structure shown can be constructed similarly to the one described above. Figures 2A to 2F The etching stop layer 30 can protect the first transistor, the second transistor and the second side 40b of the isolation structure from the etching process of the bonding layer 20. Since the etching stop layer 30 can be formed on the substrate including the second substrate 40 by epitaxial growth or by a deposition process such as CVD, PVD or ALD, Figure 2A During the manufacturing process of the semiconductor substrate A1 shown, the interface S extending from between the etching stop layer 30 and the first unit area 50 to between the etching stop layer 30 and the second unit area 50' may be flat. In some embodiments, the flat interface S has a flatness of less than 2 μm and a smoothness of less than 2 nm. However, the present disclosure is not limited to this. As a result, the unit will have fewer defects in the transistor, and less difference in thickness and / or electrical characteristics of the transistor (such as threshold voltage) between the units can be achieved. The etching stop layer 30 can protect the isolation structure 42 during the etching process, so that the isolation structure 42 can remain intact and can provide good electrical isolation between the units.

[0096] like Figure 3BAs shown, first and second openings 91 and 91' are formed extending through the etch stop layer 30 to expose the second side 40b of the source region 51. Specifically, instead of completely removing the etch stop layer 30, only a portion of the etch stop layer 30 may be removed using an etching process through openings in a patterned mask layer (not shown) to form the first and second openings 91 and 91'. For example, when the etch stop layer 30 comprises silicon nitride, dry etching may be performed using NF3 as an etching gas using remote plasma to remove only a portion of the etch stop layer 30.

[0097] like Figure 3C As shown, a first contact structure 57 and a second contact structure 57' are formed in the first opening 91 and the second opening 91', respectively. In some embodiments, the formation method of the first contact structure 57 and the second contact structure 57' is similar to the above reference Figure 2J Those described.

[0098] Through the method disclosed herein, the etch stop layer 30 can be formed to directly contact the first source region 51 and the second source region 51' without any other portion of the semiconductor layer interposed therebetween. Therefore, during the formation of the opening, it is easier to control the endpoint of the etching process used to expose the source region, allowing the opening to be formed to expose the source region while preventing over-etching of the source region. This makes it easier to form a contact structure physically and electrically connected to the corresponding source region in each of the multiple cells. The etch stop layer 30 can also provide electrical isolation between adjacent contact structures, thereby shortening the distance between the two contact structures to 1F to 2.5F, thereby reducing the cell size.

[0099] like Figure 3D As shown, a first capacitor 60a and a second capacitor 60a' are formed on the second side 40b of the second substrate 40. The first capacitor 60a can be formed to be electrically connected to the first contact structure 57, and the second capacitor 60a' can be formed to be electrically connected to the second contact structure 57'. Therefore, the first capacitor 60a is electrically connected to the first source region 51, and the second capacitor 60a' is electrically connected to the second source region 51'. A second dielectric layer 94 can also be formed on the second side 40b of the second substrate 40 and located above the etch stop layer 30. In some embodiments, the formation method of the first capacitor 60a, the second capacitor 60a' and the second dielectric layer 94 can be similar to the above reference Figure 2K Describe the formation method.

[0100] exist Figure 3DIn the illustrated embodiment, the first dielectric layer 90 includes an etch stop layer 30. The etch stop layer 30 may include silicon nitride or silicon oxynitride. In one embodiment, the thickness of the etch stop layer 30 may be in a range of 2 nm to 700 nm. This value is provided as an example only and is not intended to be limiting. In some other embodiments, before forming the first opening and the second opening, another deposited dielectric layer (not shown) may be formed over the etch stop layer.

[0101] The methods described herein make it easier to form capacitors on the second side. Furthermore, it can make it easier to form transistors with large dimensions and / or favorable configurations (e.g., favorable electrode shapes) on the "open" second side of the substrate. Furthermore, forming capacitors on both sides of a transistor can increase the cell capacitance.

[0102] Figure 4 FIG. 1 is a schematic diagram illustrating a semiconductor structure according to the present disclosure. Figure 4 The semiconductor structure 200 in FIG. Figure 1 1. In the semiconductor structure 100, like reference numerals denote like elements. In this embodiment, each of the first electrode 61a of the first capacitor 60a and the first electrode 61' of the second capacitor 60a' is container-shaped.

[0103] Figure 5 FIG. 1 is a schematic diagram illustrating a semiconductor structure according to the present disclosure. Figure 5 The semiconductor structure 300 in FIG. Figure 1 In the semiconductor structure 100, like reference numerals denote like elements. In this embodiment, each of the first electrode 61a of the first capacitor 60a and the first electrode 61' of the second capacitor 60a' is multi-fin-shaped.

[0104] Figure 6 FIG. 1 is a schematic diagram illustrating a semiconductor structure according to the present disclosure. Figure 6 The semiconductor structure 400 in FIG. 4 may be substantially similar to Figure 1 1 , wherein like reference numerals denote like elements. In this embodiment, each of the first electrode 61a of the first capacitor 60a and the first electrode 61' of the second capacitor 60a' is plate-shaped.

[0105] Figure 7 FIG. 1 is a schematic diagram illustrating a semiconductor structure according to the present disclosure. Figure 7 The semiconductor structure 500 in FIG. Figure 1In this embodiment, the semiconductor structure 500 includes only the first capacitor 60a and the second capacitor 60a' on the second side 40b of the semiconductor layer 40, without the third capacitor and the fourth capacitor on the first side 40a of the semiconductor layer 40.

[0106] Figures 8A to 8J A schematic diagram illustrating an intermediate stage of manufacturing a semiconductor structure according to an embodiment of the present disclosure, wherein the semiconductor structure is similar to Figure 1 The semiconductor structure shown in .

[0107] like Figure 8A As shown, a semiconductor substrate A2 is provided (step (a)). The semiconductor substrate A2 may be substantially similar to Figure 2A , wherein like reference numerals indicate like elements. Semiconductor substrate A2 includes a first substrate 10, a second substrate 40 positioned on the first substrate 10, and a bonding layer 20 positioned between the first substrate 10 and the second substrate 40. Semiconductor substrate A2 may further include an etch stop layer 30 and an intermediate layer 110, wherein the etch stop layer 30 is positioned between the bonding layer 20 and the second substrate 40, and the intermediate layer 110 is positioned between the etch stop layer 30 and the second substrate 40. In some embodiments, the bonding layer 20 comprises silicon oxide, and the etch stop layer 30 comprises silicon nitride. In some embodiments, the intermediate layer 110 may comprise one or more layers of dielectric material, such as silicon oxide, silicon oxynitride, a low-k dielectric material, combinations thereof, or other applicable materials. Suitable materials for the etch stop layer 30 and the intermediate layer 110 may be selected based on actual needs and material properties. In one embodiment, the thickness of the intermediate layer 110 may be between 2 nm and 700 nm, and the thickness of the etch stop layer 31 may be between 0.2 nm and 5 nm. These values ​​are provided as examples only and are not intended to be limiting. In some embodiments, an intermediate layer 110 and an etch stop layer 30 can be formed on a substrate (not shown) including a second substrate 40 by epitaxial growth or a deposition process such as CVD, PVD, or ALD, and the substrate can be bonded to the first substrate 10 via a bonding layer 20 after the intermediate layer 110 and the etch stop layer 30 are formed. In some embodiments, part of the substrate can be removed after bonding, and the second substrate 40 remains in the semiconductor substrate A2. A semiconductor substrate including an etch stop layer and an intermediate layer can be made by bonding two substrates, and the related process is as described in application document No. PCT / US23 / 69597, the contents of which are cited herein as reference. The aforementioned details regarding the first substrate 10, the bonding layer 20, the etch stop layer 30, and the second substrate 40 are also applicable here.

[0108] like Figure 8BAs shown, an isolation structure 42 such as a shallow trench isolation (STI) may be formed in the second substrate 40 (step (g)). In some embodiments, if applicable, the isolation structure 42 may be fabricated in a manner similar to that described above with reference to FIG. Figure 2B In some embodiments, a trench (not shown) may be formed by etching through the second substrate 40 to expose the intermediate layer 110 , and a dielectric material for forming the isolation structure 42 may then be deposited in the trench.

[0109] like Figure 8C As shown, a first source region 51, a second source region 51', a first drain region 52, and a second drain region 52' are formed in the second substrate 40, a first gate structure 55 and a first gate dielectric 54 are formed on the first side 40a of the second substrate 40, and a second gate structure 55' and a second gate dielectric 54' are formed on the first side 40a of the second substrate 40 (step (b)). In some embodiments, the first source region 51, the second source region 51', the first drain region 52, the second drain region 52', the first body region 53, the second body region 53', the first gate dielectric 54, the second gate dielectric 54', the first gate structure 55, and the second gate structure 55' are formed in a similar manner to the aforementioned reference numerals. Figure 2C The formation method described herein can form a planar interface S extending from between the intermediate layer 110 and the first cell region 50 to between the intermediate layer 110 and the second source region 50'. In some embodiments, the planar interface S has a flatness of less than 2 μm and a smoothness of less than 2 nm. However, the present disclosure is not limited thereto.

[0110] like Figure 8D As shown, a third capacitor 60b and a fourth capacitor 60b' are formed on the first side 40a of the second substrate 40. A dielectric layer 72 may be formed on the first side 40a of the second substrate 40. In some embodiments, the third capacitor 60b and the fourth capacitor 60b' may be formed in one or more dielectric layers in the dielectric layer 72. In some embodiments, the third capacitor 60b, the fourth capacitor 60b', and the dielectric layer 72 may be formed in a manner similar to that described above with reference to FIG. Figure 2D The first drain contact structure 56, the second drain contact structure 56' and the interconnect structure 70 may be formed in the dielectric layer 72 by any suitable method such as a damascene or dual damascene process.

[0111] like Figure 8E As shown, a third substrate 80 is added to the first side 40a of the second substrate 40, wherein the second substrate 40 is located between the third substrate 80 and the first substrate 10 (step (c)). The third substrate 80 can be similar to the above-mentioned Figure 2EThe third substrate 80 is bonded to the second substrate 40 or formed on the second substrate 40 by the process described in the previous section. If applicable, the aforementioned details regarding the third substrate 80 may apply here.

[0112] like Figure 8F As shown, the first substrate 10 and the bonding layer 20 are removed (step (d)). The first substrate 10 and the bonding layer 20 can be removed by a method similar to the above Figure 2F In the process of removal. Figure 8F In the embodiment shown, the bonding layer 20 is completely removed without using a mask. If applicable, the above-mentioned details regarding the first substrate 10 and the bonding layer 20 can be applied here.

[0113] like Figure 8G As shown, at least a portion of the etch stop layer 30 is removed to expose the intermediate layer 110 (step (f)). The etch stop layer 30 may be removed by a process similar to that described above with respect to Figure 2G In the process of removal. Figure 8G In the illustrated embodiment, the etch stop layer 30 is completely removed, and the removal of the etch stop layer 30 can be performed by performing an etching process without using a mask. It is also possible that only a portion of the etch stop layer 30 is removed. In one embodiment, the etch stop layer 30 comprises silicon nitride, and the intermediate layer 110 comprises silicon oxide. In this case, removing the etch stop layer includes etching the etch stop layer 30 using a second etchant, such as hot phosphoric acid. However, the present disclosure is not limited thereto.

[0114] like Figure 8H As shown, a first opening 91 and a second opening 91' extending through the intermediate layer 110 are formed to expose the first source region 51 and the second source region 51' respectively. The first opening 91 and the second opening 91' can be formed by similar means to those described above. Figure 2I and Figure 3B For example, an etching process can be used to remove a portion of the intermediate layer 110 through the opening of the patterned mask layer (not shown) to form the first opening 91 and the second opening 91'. Suitable etchants and etching conditions can be selected according to actual applications.

[0115] like Figure 8I As shown, a first contact structure 57 and a second contact structure 57' are formed in the first opening 91 and the second opening 91', respectively. In some embodiments, the formation method of the first contact structure 57 and the second contact structure 57' is similar to that described in the aforementioned reference. Figure 2J The formation method of .

[0116] By the method disclosed herein, the intermediate layer 110 can be formed to be in direct contact with the first source region 51 and the second source region 51' without any residual bonding layer and other parts of the conductor layer being located therebetween. The etch stop layer 30 can protect the intermediate layer 110 during the etching process of the bonding layer 20, so that the intermediate layer 110 can remain intact and can provide good electrical isolation between adjacent contact structures. Therefore, the distance between the two contact structures can be reduced to 1F to 2.5F, and the cell size can be reduced. And, as discussed above, due to the Figure 8G The illustrated structure provides easier control over the endpoint of the etching process that forms the opening extending through the intermediate layer, which may make it easier to form contact structures physically and electrically connected to the corresponding source regions in each of the plurality of cells.

[0117] like Figure 8J As shown, a first capacitor 60a and a second capacitor 60a' are formed on the second side 40b of the second substrate 40. The first capacitor 60a can be formed to be electrically connected to the first contact structure 57, and the second capacitor 60a' can be formed to be electrically connected to the second contact structure 57'. Therefore, the first capacitor 60a is electrically connected to the first source region 51, and the second capacitor 60a' is electrically connected to the second source region 51'. A second dielectric layer 94 can also be formed on the second side 40b of the second substrate 40 and is located above the intermediate layer 110. In some embodiments, the formation method of the first capacitor 60a, the second capacitor 60a' and the second dielectric layer 94 is similar to the aforementioned reference. Figure 2K The formation method of .

[0118] exist Figure 8J In the illustrated embodiment, the first dielectric layer 90 includes an intermediate layer 110. In one embodiment, the intermediate layer 110 may include silicon oxide or a low-k dielectric material, such as hydrogen silsesquioxane (HSQ), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), silicon carbide, spin-on glass, other suitable low-k dielectric materials, and / or combinations thereof. In some embodiments, the thickness of the intermediate layer 110 may range from 2 nm to 700 nm. In some embodiments, the thickness of the intermediate layer 110 may range from 2 nm to 30 nm. These values ​​are provided as examples only and are not intended to be limiting.

[0119] The methods disclosed herein make it easier to fabricate capacitors on the second side. Furthermore, this makes it easier to form capacitors with larger sizes and / or favorable configurations (e.g., favorable electrode shapes) on the "open" second side of the substrate. Furthermore, forming capacitors on both sides of the transistor can increase the cell capacitance.

[0120] Figures 9A to 9HThe figure shows an intermediate stage of manufacturing a semiconductor structure according to one embodiment of the present disclosure.

[0121] like Figure 9A As shown, a semiconductor substrate A3 is provided (step (a)). The semiconductor substrate A3 may be substantially similar to Figure 2A , wherein like reference numerals indicate like elements. The semiconductor substrate A3 includes a first substrate 10, a second substrate 40 located on the first substrate 10, and a bonding layer 20 between the first substrate 10 and the second substrate 40. In one embodiment, the bonding layer 20 may include silicon oxide. In one embodiment, the semiconductor substrate may be a silicon-on-insulator (SOI) substrate. The aforementioned details regarding the first substrate 10, the second substrate 40, and the bonding layer 20 may also apply here.

[0122] like Figure 9B As shown, a portion of the second substrate 40 is removed to form a groove 45 extending through the second substrate 40 (step (g1)), and the bonding layer 20 can be exposed by the groove 45. Then, an etch stop layer 30 is formed on at least the bottom surface 47 of the groove 45 (step (g2)). Figure 9B In the illustrated embodiment, a portion of the etch stop layer 30 is formed over the first side 40a of the second substrate 40, and another portion of the etch stop layer 30 lines the sidewalls 48 and bottom surface 47 of the trench 45. In some embodiments, the bonding layer 20 comprises silicon oxide, and the etch stop layer 30 may comprise silicon nitride, silicon oxynitride, a doped semiconductor material, an undoped semiconductor material, a metal, or a conductive metal compound. The trench 45 may be formed by performing a suitable method, which may include photolithography, an etching process such as reactive-ion etching (RIE), and / or any applicable process. The etch stop layer 30 may be formed by a deposition process such as CVD, PVD, ALD, etc. The aforementioned details regarding the etch stop layer 30 and the bonding layer 20 also apply here.

[0123] like Figure 9C As shown, an isolation structure 42 is formed in the trench 45 (step (g3)). The isolation structure 42 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate (FSG), a low-k dielectric material, a suitable material, or a combination thereof. The isolation structure 42 may be formed by a suitable method, such as a deposition process, for example, CVD, PVD, ALD. Figure 9CIn the illustrated embodiment, a portion of the etch stop layer 30 is removed by a suitable method, such as CMP, etching, and / or other applicable processes, to expose at least a portion of the second substrate 40 , thereby forming a “liner” etch stop layer 30 between the isolation structure 42 and the bonding layer 20 .

[0124] like Figure 9D As shown, a first source region 51, a second source region 51', a first drain region 52, and a second drain region 52' are formed in the second substrate 40, a first gate structure 55 and a first gate dielectric 54 are formed on the first side 40a of the second substrate 40, and a second gate structure 55' and a second gate dielectric 54' are formed on the first side 40a of the second substrate 40 (step (b)). In some embodiments, the materials and formation methods of the first source region 51, the second source region 51', the first drain region 52, the second drain region 52', the first body region 53, the second body region 53', the first gate dielectric 54, the second gate dielectric 54', the first gate structure 55, and the second gate structure 55' are similar to those described above with respect to Figure 1 and Figure 2C Materials and formation methods.

[0125] Next, a third capacitor 60b and a fourth capacitor 60b' are formed on the first side 40a of the second substrate 40. Specifically, a dielectric layer 72 may be formed on the first side 40a of the second substrate 40, and the third capacitor 60b and the fourth capacitor 60b' may be formed in one or more dielectric layers of the dielectric layer 72. The third capacitor 60b is electrically connected to the first source region 51. The fourth capacitor 60b' is electrically connected to the second source region 51'. In some embodiments, the materials and formation methods of the third capacitor 60b, the fourth capacitor 60b', and the dielectric layer 72 are similar to those described above with reference to FIG. Figure 1 and Figure 2D The materials and formation methods in Figure 1 and Figure 2D Similar materials and similar methods are used to form the first drain contact structure 56, the second drain contact structure 56' and the interconnect structure 70 in the dielectric layer 72. If applicable, the above-mentioned relevant details can be applied here.

[0126] like Figure 9E As shown in FIG, a third substrate 80 is added to the first side 40a of the second substrate 40, wherein the second substrate 40 is located between the third substrate 80 and the first substrate 10 (step (c)). The third substrate 80 can be similar to the above-mentioned Figure 2E The third substrate 80 is bonded to or formed on the second substrate 40 by a process. If applicable, the aforementioned details regarding the third substrate 80 may apply here.

[0127] like Figure 9F As shown, the first substrate 10 is removed to expose the bonding layer 20 (step (d1)). In some embodiments, the removal process may include selective etching, which removes the first substrate 10 without completely etching through the bonding layer 20, and the bonding layer 20 may serve as an etch stop layer. In some embodiments, the removal process may include grinding and / or CMP processes. The bonding layer is then removed to expose the etch stop layer 30 and the second substrate 40 (step (d2)). The removal process may include selective etching, which removes the bonding layer 20 while the etch stop layer 30 and the second substrate 40 remain substantially unchanged. For example, in an embodiment where the bonding layer 20 includes silicon oxide, the etch stop layer 30 includes silicon nitride, and the second substrate 40 includes silicon, the bonding layer 20 may be etched using a first etchant such as dilute HF (e.g., a weight ratio of H2O and HF of approximately 100:1). However, the present disclosure is not limited thereto. Suitable materials and suitable etching conditions may be selected according to actual needs. In Figure 9F In the illustrated embodiment, the bonding layer 20 and the etch stop layer 30 are completely removed without a mask, which can reduce manufacturing costs and production time. During the etching process to remove the bonding layer 20, the etch stop layer 30 can prevent damage to the isolation structure 42, so that the isolation structure 42 remains intact and can provide good electrical isolation between cells.

[0128] like Figure 9G As shown, a dielectric layer 92 is deposited on the second side 40b of the second substrate 40, wherein the etch stop layer 30 is located between the deposited dielectric layer 92 and the isolation structure 42. The dielectric layer 92 may be similar to the aforementioned reference Figure 1 and Figure 2H The dielectric layer in the embodiment of the present invention may be formed by a deposition process such as PVD, CVD or ALD, a spin coating process or any other suitable process. If applicable, the above-mentioned details regarding the deposited dielectric layer 92 may apply here.

[0129] like Figure 9H As shown, a first contact structure 57 and a second contact structure 57' are formed extending through the deposited dielectric layer 92. The first contact structure 57 and the second contact structure 57' can be similar to those described above with reference to FIG. Figure 1 and Figure 2J The first contact structure and the second contact structure in FIG. 5 can be made by similar methods. If applicable, the above-mentioned details about the first contact structure 57 and the second contact structure 57' can be applied here.

[0130] Next, a first capacitor 60a and a second capacitor 60a' are formed on the second side 40b of the second substrate 40 (step (e)). The first capacitor 60a is formed to be electrically connected to the first contact structure 57, and the second capacitor 60a' is formed to be electrically connected to the second contact structure 57'. A second dielectric layer 94 may also be formed on the second side 40b of the second substrate 40 and located above the deposited dielectric layer 92. The first capacitor 60a, the second capacitor 60a', and the second dielectric layer 94 may be similar to the above-mentioned Figure 1 and Figure 2K The first capacitor, the second capacitor and the second dielectric layer can be manufactured using similar methods.

[0131] Figure 9H The semiconductor structure 600 shown in FIG. 1 is substantially similar to Figure 1 The semiconductor structure 100 in FIG. 1 is shown in FIG. 1 , wherein like reference numerals indicate like elements. Figure 9H In the illustrated embodiment, first dielectric layer 90 includes a deposited dielectric layer 92. Etch stop layer 30 is located between deposited dielectric layer 92 and isolation structure 42. Etch stop layer 30 may also be located between first source region 51 and isolation structure 42 and / or between second source region 51′ and isolation structure 42.

[0132] The methods disclosed herein make it easier to fabricate capacitors on the second side. Furthermore, this can make it easier to form capacitors with larger sizes and / or advantageous configurations (e.g., advantageous electrode shapes) on the "open" second side of the substrate. Furthermore, forming capacitors on both sides of the transistor can increase the cell capacitance. Where applicable, the aforementioned details apply here.

[0133] The aforementioned semiconductor structure and its manufacturing method may have one or more of the following advantages.

[0134] 1. The semiconductor structure according to the present disclosure may include a capacitor on the second side of the transistor, which provides greater flexibility in the shape and size of the capacitor. This allows for a capacitor with a larger capacitance, thereby increasing the equivalent capacitance per cell and / or improving performance.

[0135] 2. The semiconductor structure according to the present disclosure can include capacitors on each side of a transistor, forming a one-transistor-two-capacitor (1T2C) memory cell. This can increase the equivalent capacitance of each cell and provide the required capacitance when the memory cell has a smaller cell size.

[0136] 3. The semiconductor structure according to the present disclosure can include a flat interface between the transistor and the first dielectric layer. Consequently, because there is less variation between cell regions and fewer defects in the interface, the multiple transistors in a memory array can have more stable and consistent electrical performance and lower leakage current, especially when the semiconductor layer in which the cell regions are located is very thin.

[0137] 4. The semiconductor structure according to the present disclosure may include a first dielectric layer comprising oxide or low-k material, which may serve as an isolation layer between adjacent contact structures. Thus, the distance between two contact structures can be reduced to 1F to 2.5F, and the cell size can be reduced accordingly.

[0138] 5. The method according to the present disclosure provides a process by which a person skilled in the art can manufacture the aforementioned semiconductor structure, thereby enabling the semiconductor structure to be manufactured in an economical and efficient manner.

[0139] 6. The method according to the present disclosure provides a process by which one skilled in the art can provide capacitors having larger dimensions and / or advantageous configurations on the "open" second side of the substrate.

[0140] 7. The method according to the present disclosure provides a process by which a person skilled in the art can provide a semiconductor structure having capacitors on both sides of a transistor, thereby increasing the cell capacitance value.

[0141] 8. The method according to the present disclosure provides a manufacturing process by which a person skilled in the art can control the endpoint of the etching process used to expose the source region during the process of forming the contact structure. The etch stop layer can prevent over-etching of the source region, thereby making it easier to form a contact structure physically and electrically connected to the corresponding source region in each of the multiple cells.

[0142] The description of the embodiments is provided to enable any person skilled in the art to make and use the invention. Various modifications to the embodiments will be apparent to those skilled in the art, and the novel principles and subject matter identified herein may be applied to other embodiments without requiring inventive step. The claimed subject matter is not limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein. Other embodiments are contemplated as being within the spirit and scope of the disclosed subject matter. Therefore, the present invention is intended to cover modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor structure comprising: a semiconductor layer comprising a first unit region and a second unit region, wherein the first unit region comprises a first source region, a first drain region, and a first body region located between the first source region and the first drain region, and the second unit region comprises a second source region, a second drain region, and a second body region located between the second source region and the second drain region; a first gate structure located on a first side of the semiconductor layer and over the first body region; a second gate structure on the first side of the semiconductor layer and over the second body region; a first dielectric layer located on a second side of the semiconductor layer opposite the first side, wherein the first dielectric layer contacts the semiconductor layer and overlaps both the first source region and the second source region; a first capacitor located on the second side of the semiconductor layer and electrically connected to the first source region; as well as A second capacitor is located on the second side of the semiconductor layer and is electrically connected to the second source region. 2 . The semiconductor structure of claim 1 , wherein the thickness of the first dielectric layer is in a range from about 2 nm to about 700 nm. 3 . The semiconductor structure of claim 1 , further comprising an isolation structure located between the first source region and the second source region. 4 . The semiconductor structure of claim 3 , wherein the first dielectric layer overlaps with and contacts the isolation structure.

5. The semiconductor structure of claim 3 , wherein a first interface between the first dielectric layer and the first cell region extends laterally across the first source region, the first drain region, and the first body region; a second interface between the first dielectric layer and the second cell region extends laterally across the second source region, the second drain region, and the second body region; and a third interface between the first dielectric layer and the isolation structure extends from the first interface to the second interface. 6 . The semiconductor structure of claim 5 , wherein the first interface, the second interface, and the third interface together form a planar interface having a planarity less than 2 μm and a smoothness less than 2 nm.

7. The semiconductor structure of claim 1 , further comprising a third capacitor and a fourth capacitor on the first side of the semiconductor layer, wherein the third capacitor is electrically connected to the first source region and the fourth capacitor is electrically connected to the second source region. 8 . The semiconductor structure of claim 1 , wherein the first dielectric layer comprises an etch stop layer, the etch stop layer comprising silicon nitride or silicon oxynitride. 9 . The semiconductor structure of claim 1 , wherein the first dielectric layer comprises an intermediate layer comprising silicon oxide or a low-k dielectric material. 10 . The semiconductor structure of claim 1 , wherein the first capacitor comprises a first electrode electrically connected to the first source region, a second electrode, and a capacitor dielectric between the first electrode and the second electrode. 11 . The semiconductor structure of claim 10 , wherein each of the first electrode and the second electrode comprises polysilicon, a metal, or a conductive metal compound.

12. The semiconductor structure of claim 10, wherein the capacitor dielectric comprises a high-k material. 13 . The semiconductor structure according to claim 10 , wherein the first electrode is in a container shape, a column shape, a multi-fin shape, or a plate shape.

14. The semiconductor structure of claim 1 , further comprising a first contact structure extending through the first dielectric layer and a second contact structure extending through the first dielectric layer, wherein the first capacitor is electrically connected to the first source region through the first contact structure, and the second capacitor is electrically connected to the second source region through the second contact structure.

15. The semiconductor structure of claim 14, wherein a height of the first contact structure is substantially equal to a thickness of the first dielectric layer. 16 . The semiconductor structure of claim 14 , wherein a height of the first contact structure is in a range from about 2 nm to about 700 nm. 17 . The semiconductor structure of claim 14 , wherein a lateral spacing between the first contact structure and the second contact structure is less than 2.5 times a minimum critical dimension.

18. The semiconductor structure of claim 1, wherein the semiconductor layer comprises a single crystalline semiconductor material.

19. A method for manufacturing a semiconductor structure, comprising: (a) providing a semiconductor substrate including a first substrate, a second substrate located on the first substrate, and a bonding layer located between the first substrate and the second substrate; (b) forming a source region and a drain region in the second substrate, and forming a gate structure on the first side of the second substrate; (c) adding a third substrate on the first side of the second substrate, wherein the second substrate is located between the third substrate and the first substrate; (d) removing the first substrate and the bonding layer; (e) forming a first capacitor on a second side of the second substrate opposite to the first side, wherein the first capacitor is electrically connected to the source region.

20. The method of claim 19, wherein the semiconductor substrate further comprises an etch stop layer between the bonding layer and the second substrate, and the method further comprises, before step (e), (f) removing at least a portion of the etch stop layer.

21. The method of claim 20, wherein the bonding layer comprises silicon oxide, and the etch stop layer comprises silicon nitride, silicon oxynitride, a doped semiconductor material, an undoped semiconductor material, a metal, or a conductive metal compound.

22. The method of claim 20, wherein step (f) comprises forming an opening extending through the etch stop layer to expose the source region and forming a contact structure in the opening, and step (e) comprises forming the first capacitor electrically connected to the contact structure.

23. The method of claim 19, wherein the second substrate comprises silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN).

24. The method of claim 19, further comprising, after step (d), forming a dielectric layer on the second side of the second substrate.

25. The method of claim 24, further comprising forming an opening extending through the dielectric layer to expose the source region and forming a contact structure in the opening, wherein step (e) comprises forming the first capacitor electrically connected to the contact structure.

26. The method of claim 20, wherein the semiconductor substrate further comprises an intermediate layer between the etch stop layer and the second substrate.

27. The method of claim 26, wherein the intermediate layer comprises silicon oxide or a low-k dielectric material.

28. The method of claim 26, wherein step (f) comprises removing the etch stop layer to expose the intermediate layer.

29. The method of claim 26, further comprising forming an opening extending through the intermediate layer to expose the source region and forming a contact structure in the opening, wherein step (e) comprises forming the first capacitor electrically connected to the contact structure.

30. The method of claim 19, further comprising forming an interconnect structure on the first side of the second substrate before step (c), wherein the interconnect structure is electrically connected to the drain region or the gate structure.

31. The method of claim 19, further comprising forming a second capacitor on the first side of the second substrate before step (c), wherein the second capacitor is electrically connected to the source region.

32. The method of claim 19, wherein step (d) comprises etching the bonding layer with a first etchant.

33. The method of claim 19, wherein step (d) comprises completely removing the bonding layer of the semiconductor substrate.

34. The method of claim 20, wherein step (f) comprises etching the etch stop layer with a second etchant.

35. The method of claim 19, further comprising, before step (c), (g) forming an isolation structure.

36. The method of claim 35, wherein step (g) comprises: (g1) removing a portion of the second substrate to form a groove extending through the second substrate; (g2) forming an etch stop layer on the bottom surface of the trench; as well as (g3) Forming the isolation structure in the trench.

37. The method of claim 36, wherein step (d) comprises: (d1) removing the first substrate to expose the bonding layer; as well as (d2) removing the bonding layer to expose the etch stop layer.

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