Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device. The array substrate comprises: a substrate; the first active layer is located in the display area on one side of the substrate; the gate structure is located in the display area on the side, away from the substrate, of the first active layer; the gate structure comprises an auxiliary gate; the orthographic projection of the auxiliary grid electrode on the substrate and the orthographic projection of the first active layer on the substrate have an overlapping area, and the thickness range of the auxiliary grid electrode in the direction perpendicular to the substrate is 20 nm to 200 nm.

Description

Array substrate, display panel, and display device Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the rise of the concept of the metaverse, virtual reality (VR) head-mounted display products have attracted much attention as terminal devices. Micro organic light-emitting display (Micro OLED) products currently have good effects on the market, but Micro OLED products are expensive and difficult to process, making them difficult to popularize.

[0003] Summary of the Invention

[0004] The present disclosure provides an array substrate, a display panel, and a display device. The display panel includes:

[0005] substrate;

[0006] a first active layer, located on one side of the substrate;

[0007] A gate structure is located on a side of the first active layer facing away from the substrate; the gate structure includes an auxiliary gate; the orthographic projection of the auxiliary gate on the substrate has an overlapping area with the orthographic projection of the first active layer on the substrate, and the thickness of the auxiliary gate in a direction perpendicular to the substrate ranges from 20 nm to 200 nm.

[0008] In a possible embodiment, the display substrate further includes: a plurality of gate lines extending along a first direction, a plurality of auxiliary gate lines extending along the first direction, and a plurality of data lines whose main bodies extend along a second direction; the orthographic projections of the auxiliary gate lines on the substrate have overlapping areas with the orthographic projections of the gate lines on the substrate;

[0009] The gate structure also includes: a gate portion; the gate line includes the gate portion, and the auxiliary gate line includes the auxiliary gate; the auxiliary gate covers the orthographic projection of the gate portion on the substrate, and covers at least one side of the gate portion in the second direction; the thickness of the gate portion in the direction perpendicular to the substrate is greater than the thickness of the auxiliary gate in the direction perpendicular to the substrate, and the ratio of the thickness of the gate portion in the direction perpendicular to the substrate to the thickness of the auxiliary gate in the direction perpendicular to the substrate is in a range of 1 to 20.

[0010] In a possible implementation manner, the width a1 of the auxiliary gate in the second direction satisfies the following relationship:

[0011] 1.5≤a1 / a2≤2, where a2 represents the width of the gate portion in the second direction.

[0012] In a possible implementation manner, the width a1 of the auxiliary gate in the second direction satisfies the following relationship:

[0013] 0.5μm≤|a1-a2|≤1.5μm.

[0014] In a possible embodiment, the auxiliary gate line includes: a first auxiliary portion and a second auxiliary portion; wherein the second auxiliary portion of the Nth auxiliary gate line is located on a side of the first auxiliary portion of the Nth auxiliary gate line facing the (N+1)th auxiliary gate line;

[0015] The orthographic projection of the first auxiliary portion of the Nth auxiliary gate line on the substrate coincides with the orthographic projection of the Nth gate line on the substrate, and the orthographic projection of the second auxiliary portion of the Nth auxiliary gate line on the substrate does not overlap with the orthographic projection of the Nth gate line on the substrate.

[0016] In a possible implementation, the Nth auxiliary gate line has a first outer edge away from the (N+1)th gate line, and the Nth gate line has a second outer edge away from the (N+1)th gate line, where N is a positive integer.

[0017] The first outer edge coincides with the second outer edge.

[0018] In a possible implementation manner, the Nth auxiliary gate line has a first outer edge away from the (N+1)th gate line, and the Nth gate line has a second outer edge away from the (N+1)th gate line.

[0019] The second outer edge is located on a side of the first outer edge away from the (N+1)th gate line.

[0020] In a possible implementation, the array substrate further includes: a first electrode located on a side of the gate structure facing away from the substrate, a first insulating layer located between the first electrode and the first active layer, and a second insulating layer located between the first insulating layer and the first active layer;

[0021] The first active layer includes: a first active portion, a second active portion, and a third active portion located between the first active portion and the second active portion; an orthographic projection of the second active portion on the substrate overlaps with an orthographic projection of the data line on the substrate;

[0022] The first insulating layer has a first via hole, and the first electrode is electrically connected to the first active portion at least through the first via hole; the second insulating layer has a third via hole, and the data line is electrically connected to the second active portion at least through the third via hole.

[0023] In a possible implementation manner, the Nth gate line has a third outer edge close to a side of the N+1th gate line, and the Nth gate line satisfies the following relationship:

[0024] b1>b2>0, where b1 represents the distance between the orthographic projection of the third outer edge of the Nth gate line on the substrate and the orthographic projection of the center of the first via on the substrate in the second direction, and b2 represents the distance between the orthographic projection of the second outer edge of the Nth gate line on the substrate and the orthographic projection of the center of the third via on the substrate in the second direction.

[0025] In a possible implementation manner, the Nth gate line has a third outer edge close to a side of the N+1th gate line, and the Nth gate line satisfies the following relationship:

[0026] b3>b4>0, where b3 represents the minimum distance between the orthographic projection of the third outer edge of the Nth gate line on the substrate and the orthographic projection of the first via on the substrate in the second direction, and b2 represents the minimum distance between the orthographic projection of the second outer edge of the Nth gate line on the substrate and the orthographic projection of the third via on the substrate in the second direction.

[0027] In a possible implementation manner, an orthographic projection area of ​​the first via hole on the substrate is larger than an orthographic projection area of ​​the third via hole on the substrate.

[0028] In a possible implementation, the auxiliary gate line has a convex portion protruding along the second direction; an orthographic projection of the convex portion on the substrate has an overlapping area with an orthographic projection of the first active layer on the substrate.

[0029] In a possible implementation, the array substrate further includes: a first electrode located on a side of the gate structure facing away from the substrate, and a first insulating layer located between the first electrode and the first active layer;

[0030] The first active layer includes: a first active portion; the first insulating layer has a first via hole, and the first electrode is electrically connected to the first active portion at least through the first via hole;

[0031] In parallel with the first direction, a minimum distance between the first via hole and the protrusion is greater than or equal to zero.

[0032] In a possible implementation manner, the array substrate further includes: a second insulating layer located between the first insulating layer and the first active layer;

[0033] The first active layer further includes: a second active portion, and a third active portion located between the first active portion and the second active portion; an orthographic projection of the second active portion on the substrate overlaps with an orthographic projection of the data line on the substrate; the second insulating layer has a third via hole, and the data line is electrically connected to the second active portion at least through the third via hole;

[0034] In parallel with the first direction, a minimum distance between the third via hole and the protrusion is greater than or equal to zero.

[0035] In a possible implementation, the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the substrate in an area defined by the intersection of the gate line and the data line, so that the first electrode is electrically connected to the first active layer through the first via hole.

[0036] In a possible implementation manner, the second insulating layer has a second via hole;

[0037] The array substrate also includes: a connecting electrode located between the first electrode and the first active layer, wherein the connecting electrode portion is located on the side of the first insulating layer away from the substrate and contacts the first electrode; the first electrode is electrically connected to the first active layer at the second via hole and the first via hole through the connecting electrode.

[0038] In a possible implementation manner, the orthographic projection of the second via hole on the substrate is located within the orthographic projection of the substrate in an area defined by the intersection of the gate line and the data line.

[0039] In one possible embodiment, the orthographic projections of the first via and the second via on the substrate are located between the orthographic projections of the Nth gate line and the N+1th gate line on the substrate, and in a direction perpendicular to the first direction, the orthographic projection of the first via on the substrate is located on a side of the orthographic projection of the second via on the substrate away from the Nth gate line, where N is a positive integer.

[0040] In a possible implementation manner, the connecting electrode includes: a first sub-connecting electrode located between the second insulating layer and the first insulating layer, and a second sub-connecting electrode located between the first electrode and the first insulating layer;

[0041] The first sub-connecting electrode is partially located at the bottom of the second via hole and contacts the first active layer at the bottom of the second via hole, and partially extends to the bottom of the first via hole on the side of the second insulating layer facing away from the substrate, and contacts the second sub-bridging electrode at the bottom of the first via hole;

[0042] The second sub-connecting electrode is partially located at the bottom of the first via hole and contacts the first sub-connecting electrode at the bottom of the first via hole, and partially extends to the side of the first insulating layer away from the substrate and contacts the first electrode.

[0043] In a possible implementation, the array substrate further includes: a third insulating layer filled in the first via hole, and a step difference between a surface of the third insulating layer facing away from the substrate and a surface of the first insulating layer facing away from the substrate is less than 0.2 μm.

[0044] In a possible implementation, the orthographic projection of the first via on the substrate covers the orthographic projection of the second via on the substrate; one end of the connecting electrode is in direct contact with and overlapped with the first active layer, and the other end is in direct contact with and overlapped with the first electrode.

[0045] In a possible embodiment, the array substrate further includes: a third insulating layer filled in the second via hole and the first via hole, and the step difference between the surface of the third insulating layer away from the substrate and the surface of the first insulating layer away from the substrate is less than 0.2 μm.

[0046] In a possible implementation, the array substrate further includes: a first gate layer and a first source-drain layer; the first gate layer includes the gate line; the first source-drain layer includes the data line;

[0047] The first active layer further includes: a second active portion, and a third active portion connecting the first active portion and the second active portion; an orthographic projection of the second active portion on the substrate overlaps with an orthographic projection of the data line on the substrate;

[0048] The array substrate further includes a gate driving circuit located in the non-display area. The gate driving circuit board includes a first driving active layer, a first driving gate, and a first driving source and drain.

[0049] In a possible implementation manner, an orthographic projection of the gate structure on the substrate covers at least a portion of the third active portion.

[0050] In a possible implementation manner, the third active portion includes: an overlapping portion, an orthographic projection of the overlapping portion on the substrate overlapping with an orthographic projection of the gate portion on the substrate;

[0051] The orthographic projection of the gate structure on the substrate at least covers the orthographic projection of the overlapping portion on the substrate.

[0052] In a possible implementation manner, the auxiliary gate is located on a side of the gate portion facing the substrate.

[0053] In a possible implementation manner, the auxiliary gate is located on a side of the gate portion facing away from the substrate.

[0054] In a possible implementation, the gate structure includes: the gate portion; the auxiliary gates located on both sides of the gate portion in the second direction; and the orthographic projection of the gate portion on the substrate does not overlap with the orthographic projection of the auxiliary gate on the substrate.

[0055] In a possible implementation manner, a maximum distance between the auxiliary gates and their orthographic projections on the substrate in the second direction is greater than or equal to a maximum distance between the gate portions and their orthographic projections on the substrate in the second direction.

[0056] In a possible implementation, the gate line extends from a first end to a second end along the first direction; the first active layer includes a first active group and a second active group alternately arranged along the second direction;

[0057] The first active group includes: a plurality of first active patterns extending along a third direction and arranged sequentially along the first direction, the first active pattern including the first active portion, the second active portion, and the third active portion; an angle formed between the first active pattern and the gate line toward the first end is an acute angle;

[0058] The second active group includes: a plurality of second active patterns extending along a fourth direction and arranged sequentially along the first direction, the second active pattern includes the first active portion, the second active portion and the third active portion; the angle formed by the second active pattern and the gate line toward the first end is an obtuse angle.

[0059] In a possible implementation manner, the gate line extends from a first end to a second end along the first direction;

[0060] The first active portion, the second active portion, and the third active portion all extend along the second direction, and form a right angle with the gate line toward the first end.

[0061] In a possible implementation manner, the gate line extends from a first end to a second end along the first direction;

[0062] The first active portion and the second active portion both extend along the second direction, and an extension line of the first active portion does not overlap with an extension line of the third active portion; an angle formed by at least a portion of the third active portion and the gate line toward the first end is an acute angle.

[0063] In a possible implementation manner, the first active portion, the second active portion, and the third active portion all extend along the first direction, and a gap exists between an orthographic projection of the first active layer on the substrate and an orthographic projection of the gate line on the substrate;

[0064] The gate structure includes: an auxiliary gate located on the side of the first active layer facing away from the substrate, the auxiliary gate extends along the second direction, and its orthographic projection on the substrate covers the orthographic projection of the third active portion on the substrate, and covers part of the orthographic projection of the gate line on the substrate.

[0065] In a possible embodiment, the first gate layer is located on the side of the first active layer facing the substrate; the gate line further includes a gate line branch extending along the second direction; and the orthographic projection of the auxiliary gate on the substrate covers the orthographic projection of the gate line branch on the substrate.

[0066] In a possible implementation, the material of the auxiliary gate includes: indium tin oxide, indium-doped zinc oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, or indium-doped cadmium oxide.

[0067] In a possible embodiment, the data line includes: a first data portion and a second data portion extending along the second direction and alternately arranged along the second direction, and a third data portion connecting the first data portion and the second data portion and extending along the first direction, wherein the extension line of the first data portion does not overlap with the extension line of the second data portion.

[0068] In a possible implementation, the array substrate further includes: a common electrode located on a side of the first electrode facing away from the substrate;

[0069] The common electrode includes: a first common electrode portion extending along the first direction, and a second common electrode portion extending along the second direction; the orthographic projection of the first common electrode portion on the substrate covers the orthographic projection of the gate line on the substrate, and the orthographic projection of the second common electrode portion on the substrate covers the orthographic projection of the data line on the substrate;

[0070] The orthographic projection of the first via hole on the substrate is located within the orthographic projection of the substrate at the intersection of the first common electrode portion and the second common electrode portion.

[0071] An embodiment of the present disclosure further provides a display device, which includes the array substrate provided in the embodiment of the present disclosure.

[0072] An embodiment of the present disclosure further provides a display device, which includes the display panel provided in the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] FIG1A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0074] FIG1B is a schematic diagram of a single film layer of the first active layer in FIG1A ;

[0075] FIG1C is a schematic diagram of a single film layer of the gate line layer in FIG1A ;

[0076] FIG1D is a schematic diagram of a single film layer of the data line in FIG1A ;

[0077] FIG1E is a schematic diagram of the first sub-connecting electrode in FIG1A ;

[0078] FIG1F is a schematic diagram of the outer contours of the second sub-connecting electrode and the first electrode in FIG1A ;

[0079] FIG2A is a schematic cross-sectional view of FIG1A taken along the dotted line E1F1; ...

[0080] FIG2B is a schematic cross-sectional view of two via holes provided by an embodiment of the present disclosure;

[0081] FIG2C is a schematic diagram of another embodiment of the present disclosure at two vias;

[0082] FIG3 is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0083] FIG4 is a schematic cross-sectional view along the dotted line E2F2 in FIG3 ;

[0084] FIG5A is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure;

[0085] FIG5B is a second schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0086] FIG6 is a third schematic cross-sectional view of an array substrate provided in an embodiment of the present disclosure;

[0087] FIG7 is a fourth cross-sectional schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0088] FIG8 is a fifth schematic cross-sectional view of an array substrate provided in an embodiment of the present disclosure;

[0089] FIG9A is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0090] FIG9B is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0091] FIG9C is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0092] FIG9D is a seventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0093] FIG9E is an eighth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0094] FIG9F is a ninth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0095] FIG9G is a tenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0096] FIG10 is an eleventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0097] FIG11 is a twelfth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0098] FIG12A is a schematic cross-sectional view taken along the dotted line E6F6 in FIG12B ;

[0099] FIG12B is a thirteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0100] FIG13A is a schematic cross-sectional view taken along the dotted line E7F7 in FIG13B ;

[0101] FIG13B is a fourteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0102] FIG14A is a fifteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0103] FIG14B is a schematic diagram of a single film layer of the common electrode in FIG14A;

[0104] FIG15 is a fifth cross-sectional schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0105] FIG16 is a sixth schematic cross-sectional view of an array substrate provided in an embodiment of the present disclosure;

[0106] FIG17 is a seventh cross-sectional schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0107] FIG18 is an eighth cross-sectional schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0108] FIG19 is a ninth cross-sectional schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0109] FIG20 is a tenth cross-sectional schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0110] FIG21 is a schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present disclosure;

[0111] FIG22 is a second schematic diagram of the array substrate manufacturing process according to an embodiment of the present disclosure;

[0112] Figure 23 shows the auxiliary gate thickness. Schematic diagram of the transfer characteristic curve of the transistor when ;

[0113] Figure 24 shows the auxiliary gate thickness. Schematic diagram of the transfer characteristic curve of the transistor when ;

[0114] Figure 25 shows the auxiliary gate thickness. Schematic diagram of the transfer characteristic curve of the transistor when ;

[0115] Figure 26 shows the auxiliary gate thickness. Schematic diagram of the transfer characteristic curve of the transistor when . DETAILED DESCRIPTION

[0116] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0117] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0118] In this specification, ordinal numbers such as "first", "second", and "third" are provided to avoid confusion among constituent elements, rather than to limit the quantity. The "plurality" in this disclosure may include two or more.

[0119] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0120] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0121] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0122] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0123] The gate of a transistor can also be referred to as the control electrode. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source electrode" and "drain electrode" may be interchanged.

[0124] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0125] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0126] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0127] In this specification, "approximately" and "substantially" are used without strict limits and allow for process and measurement errors. In this specification, "substantially the same" may refer to values ​​that differ by less than 10%.

[0128] For ultra-high-resolution display products, optimizing the line width and via size can directly and effectively increase the aperture ratio of the pixel area, thereby optimizing the display effect. However, the impact of reducing the channel length also poses corresponding challenges to the short-channel characteristics of the transistors in the display backplane. When the channel length is less than 2μm, the oxide transistor will exhibit a more obvious short-channel effect, which mainly includes the drain-induced barrier lowering (DIBL) effect and the diffusion effect of conductive doping. Both will affect the characteristics of the oxide transistor, making the characteristics unreliable.

[0129] In view of this, an embodiment of the present disclosure provides an array substrate, as shown in Figures 5A-5B, 6-8, 9A-9F, 10, 11, 12A, 12B, 13A, and 13B, wherein Figure 5A may be a cross-sectional view along dotted line E3F3 of Figure 9A, along dotted line E4F4 of Figure 10, and along dotted line E5F5 of Figure 11, and Figure 5B may be a cross-sectional view along dotted line E3F3 of Figure 9B, wherein the Z-axis direction in the cross-sectional view may be a direction perpendicular to the substrate, and the array substrate includes:

[0130] substrate 11;

[0131] The first active layer 2 is located in the display area on one side of the substrate 11;

[0132] The gate structure G is located in the display area on the side of the first active layer 2 facing away from the substrate 11; the gate structure G includes at least an auxiliary gate G2; the orthographic projection of the auxiliary gate G2 on the substrate 11 has an overlapping area with the orthographic projection of the first active layer 2 on the substrate 11, and the thickness of the auxiliary gate G2 in the direction perpendicular to the substrate 11 ranges from 20 nm to 200 nm.

[0133] In the embodiment of the present disclosure, the gate structure G includes an auxiliary gate G2. On the one hand, it can block the injection of some ions when the first active layer is subsequently conductive, extend the channel length of the first active layer, ensure the characteristics of the oxide transistor, avoid the drain-induced barrier lowering effect and the diffusion effect of conductive doping, and the thickness range of the auxiliary gate G2 in the direction perpendicular to the substrate 11 is 20nm to 200nm, which can not only ensure that the auxiliary gate G2 has a certain blocking effect on the injected ions for subsequent conductive processing, but also ensure that it is not too thick, resulting in the problem that direct crystallization cannot be graphically removed.

[0134] In one possible embodiment, the thickness of the auxiliary gate G2 in the direction perpendicular to the substrate 11 may range from 30 nm to 100 nm; in one possible embodiment, the thickness of the auxiliary gate G2 in the direction perpendicular to the substrate 11 may range from 40 nm to 70 nm; in one possible embodiment, the thickness of the auxiliary gate G2 in the direction perpendicular to the substrate 11 may range from 50 nm to 60 nm; in one possible embodiment, the thickness of the auxiliary gate G2 in the direction perpendicular to the substrate 11 may be 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 135 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm or 200 nm.

[0135] In one possible embodiment, referring to FIG. 5A and FIG. 9A , the display substrate further includes: a plurality of gate lines 31 extending along a first direction X, a plurality of auxiliary gate lines G20 extending along the first direction X, and a plurality of data lines 41 whose main bodies extend along a second direction Y; an orthographic projection of the auxiliary gate lines G20 on the substrate 11 overlaps with an orthographic projection of the gate lines 31 on the substrate 11;

[0136] The gate structure G also includes: a gate portion G1; the gate line 31 includes the gate portion G1, and the auxiliary gate line G20 includes an auxiliary gate G2; the orthographic projection of the auxiliary gate G2 on the substrate 11 covers the orthographic projection of the gate portion G1 on the substrate 11, and at least one side of the covering gate portion G1 in the two side areas in the second direction Y.

[0137] In one possible embodiment, the thickness of the gate portion G1 in a direction perpendicular to the substrate 11 is greater than the thickness of the auxiliary gate G2 in the direction perpendicular to the substrate 11, and the ratio of the thickness of the gate portion G1 in the direction perpendicular to the substrate 11 to the thickness of the auxiliary gate G2 in the direction perpendicular to the substrate 11 is in a range of 1 to 20. In one possible embodiment, the ratio of the thickness of the gate portion G1 in the direction perpendicular to the substrate 11 to the thickness of the auxiliary gate G2 in the direction perpendicular to the substrate 11 may be 1, 1.2, 1.4, 1.6, 1.8, 2, 4, 6, 8, 10, 12, 14, 16, 18, or 20.

[0138] In a possible implementation, the thickness of the gate portion G1 in a direction perpendicular to the substrate 11 may be 280 nm, 300 nm, 320 nm, 340 nm, 360 nm, 380 nm, 400 nm, 450 nm, or 500 nm.

[0139] It should be noted that the main body of the data line 41 is along the second direction Y, which can be understood as the data line 41 extending along the second direction Y on the entire array substrate, but may be bent at a local position.

[0140] In a possible implementation, as shown in FIG9A , the width a1 of the auxiliary gate G2 in the second direction Y satisfies the following relationship:

[0141] 1.5≤a1 / a2≤2, where a2 represents the width of the gate portion G1 in the second direction Y. In the disclosed embodiment, 1.5≤a1 / a2 can ensure a larger opening area by reducing the line width of the gate line 31; a1 / a2≤2 can ensure the characteristics of the oxide transistor and avoid the problem of the first via K1 and / or the third via K3 being too close to the gate line 31 in the ultra-high PPI structure, causing the first via K1 and / or the third via K3 to overlap with the gate line 31 and causing the risk of a short circuit (GDS) between the gate line 31 and the data line 41.

[0142] In a possible implementation, as shown in FIG9A , the width a1 of the auxiliary gate G2 in the second direction satisfies the following relationship:

[0143] 0.5μm≤|a1-a2|≤1.5μm. In this way, the line width of the gate line 31 is reduced to ensure a larger opening area and avoid the risk of a short circuit (GDS) between the gate line 31 and the data line 41 caused by the first via K1 and / or the third via K3 being too close to the gate line 31 in the ultra-high PPI structure.

[0144] In one possible embodiment, the width a1 of the gate G1 in the second direction Y can be 1.8 μm, 1.9 μm, 2 μm, 2.1 μm, or 2.2 μm; the width a1 of the auxiliary gate G2 in the second direction can be 2.8 μm, 2.9 μm, 3 μm, 3.1 μm, or 3.2 μm; a1-a2=0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, or 1.2 μm. In one possible embodiment, the width a1 of the gate G1 in the second direction Y is 2 μm, and the auxiliary gate G2 has a single-side compensation of 0.5 μm.

[0145] In one possible embodiment, referring to FIG. 5B and FIG. 9B , the auxiliary gate line G20 includes a first auxiliary portion G211 and a second auxiliary portion G212 electrically connected to the first auxiliary portion G211. The second auxiliary portion G212 of the Nth auxiliary gate line G20 is located on a side of the first auxiliary portion G211 of the Nth auxiliary gate line G20 that faces the N+1th auxiliary gate line G20, where N is a positive integer.

[0146] The orthographic projection of the first auxiliary portion G211 of the Nth auxiliary gate line G20 on the substrate 11 coincides with the orthographic projection of the Nth gate line 31 on the substrate 11, and the orthographic projection of the second auxiliary portion G212 of the Nth auxiliary gate line G20 on the substrate 11 does not overlap with the orthographic projection of the Nth gate line 31 on the substrate 11. In the disclosed embodiment, the gate line 31 can be moved upward so that the second auxiliary portion G212 of the Nth auxiliary gate line G20 is located on the side of the first auxiliary portion G211 of the Nth auxiliary gate line G20 facing the N+1th auxiliary gate line G20. Since the first via K1 has a deeper hole depth and a larger area, it is more likely to overlap with the gate line 31 due to process errors. By moving the gate line 31 upward, the distance between the gate line 31 and the first via K1 can be increased, thereby reducing the probability of the gate line 31 overlapping with the first via K1 and avoiding GDS defects.

[0147] In a possible implementation, the N+1th gate line 31 may be the next gate line 31 of the Nth gate line 31 in the gate signal scanning direction, that is, when each gate line 31 is loaded with a gate signal, the Nth gate line 31 is loaded with a gate signal before the N+1th gate line 31.

[0148] In a possible embodiment, referring to FIG9B , the gate line 31 has a first axis k1 extending along the first direction X, and the gate line 31 is symmetrical about the first axis k1; the auxiliary gate line G20 has a second axis k2 extending along the first direction X, and the auxiliary gate line G20 is symmetrical about the second axis k2; the first axis k1 of the Nth gate line 31 is located on the side of the second axis k2 of the Nth auxiliary gate line 31 away from the N+1th gate line 31.

[0149] In a possible embodiment, referring to FIG. 9B , the Nth auxiliary gate line G20 has a first outer edge w1 away from the side of the N+1th gate line 31, and the Nth gate line 31 has a second outer edge w2 away from the side of the N+1th gate line 31; the first outer edge w1 coincides with the second outer edge w2.

[0150] In a possible embodiment, referring to FIG9C , the Nth auxiliary gate line G20 has a first outer edge w1 away from the side of the N+1th gate line 31, and the Nth gate line 31 has a second outer edge w2 away from the side of the N+1th gate line 31; the second outer edge w2 is located on the side of the first outer edge w1 away from the N+1th gate line 31.

[0151] In a possible embodiment, referring to FIG. 5A and FIG. 9A , the array substrate further includes: a first electrode 53 located on a side of the gate structure G facing away from the substrate 11 , a first insulating layer 151 located between the first electrode 53 and the first active layer 2 , and a second insulating layer 141 located between the first insulating layer 151 and the first active layer 2 ;

[0152] The first active layer 2 includes a first active portion 21, a second active portion 22, and a third active portion 23 located between the first active portion 21 and the second active portion 22. The first active portion 21 is located in the light-transmitting region P, and the orthographic projection of the second active portion 22 on the substrate 11 partially overlaps with the orthographic projection of the data line 41 on the substrate 11.

[0153] The first insulating layer 151 has a first via hole K1 , and the first electrode 53 is electrically connected to the first active portion 21 at least through the first via hole K1 ; the second insulating layer 141 has a third via hole K3 , and the data line 41 is electrically connected to the second active portion 22 at least through the third via hole K3 .

[0154] In one possible embodiment, the first electrode 53 is electrically connected to the first active portion 21 at least through the first via K1. It can be understood that the first electrode 53 is not directly electrically connected to the first active portion 21, and the electrical connection between the two can also be achieved through other vias and other structures. For example, as shown in Figure 5A, the second insulating layer 141 can also have a second via K2, and the first electrode 53 can specifically be electrically connected to the first active layer 2 through the first via K1 and the second via K2.

[0155] In a possible implementation, as shown in FIG9C , the Nth gate line has a third outer edge close to the N+1th gate line, and the Nth gate line satisfies the following relationship:

[0156] b1>b2>0, where b1 represents the minimum distance between the orthographic projection of the third outer edge w3 of the N-th gate line 31 on the substrate 11 and the orthographic projection of the center of the first via K1 on the substrate 11 in the second direction Y, and b2 represents the minimum distance between the orthographic projection of the second outer edge w2 of the N-th gate line 31 on the substrate 11 and the orthographic projection of the center of the third via K3 on the substrate 11 in the second direction Y.

[0157] In a possible implementation, as shown in FIG9C , the Nth gate line 31 has a third outer edge w3 close to the N+1th gate line, and the Nth gate line 31 satisfies the following relationship:

[0158] b3>b4>0, where b3 represents the minimum distance between the orthographic projection of the third outer edge w3 of the Nth gate line 31 on the substrate 11 and the orthographic projection of the first via K1 on the substrate 11 in the second direction Y, and b2 represents the minimum distance between the orthographic projection of the second outer edge w2 of the Nth gate line 31 on the substrate 11 and the orthographic projection of the third via K3 on the substrate 11 in the second direction Y.

[0159] In a possible implementation, as shown in FIG. 5A , the orthographic projection area of ​​the first via hole K1 on the substrate 11 is larger than the orthographic projection area of ​​the third via hole K3 on the substrate 11 .

[0160] In one possible embodiment, as shown in FIG9D , the auxiliary gate line G20 has a protrusion G21 protruding along the second direction Y; the orthographic projection of the protrusion G21 on the substrate 11 has an overlapping area with the orthographic projection of the first active layer 2 on the substrate 11. In the disclosed embodiment, the auxiliary gate line G20 has a protrusion G21 protruding along the second direction Y; the orthographic projection of the protrusion G21 on the substrate 11 has an overlapping area with the orthographic projection of the first active layer 2 on the substrate 11. That is, the channel region overlapping with the first active layer 2 has a relatively wide width in the second direction Y, ensuring the characteristics of the oxide transistor. At the positions corresponding to the first via K1 and / or the third via K3, the auxiliary gate G2 is retracted to avoid the first via K1 and / or the third via K3, reducing the probability of the gate line 31 overlapping with the first via K1 and / or the third via K3, thereby avoiding GDS defects.

[0161] In a possible embodiment, in combination with Figures 5A and 9D, the array substrate further includes: a first electrode 53 located on the side of the gate structure G facing away from the substrate 11, and a first insulating layer 151 located between the first electrode 53 and the first active layer 2; the first active layer 2 includes: a first active portion 21; the first active portion 21 is located in the light-transmitting area P; the first insulating layer 151 has a first via hole K1, and the first electrode 53 is electrically connected to the first active portion 21 through the first via hole K1; in a direction parallel to the first direction X, the minimum distance a3 between the first via hole K1 and the protrusion G21 is greater than or equal to zero.

[0162] In a possible embodiment, as shown in Figure 5A and Figure 9D, the protrusion G21 has a first protrusion edge y1 extending along the second direction Y, and the extension line of the first protrusion edge y1 on the substrate 11 does not overlap with the orthographic projection of the first via K1 on the substrate 11.

[0163] In a possible embodiment, in combination with Figures 5A and 9D, the array substrate further includes: a second insulating layer 141 located between the first insulating layer 151 and the first active layer 2; the first active layer 2 further includes: a second active portion 22, and a third active portion 23 located between the first active portion 21 and the second active portion 22; the orthographic projection of the second active portion 22 on the substrate 11 partially overlaps with the orthographic projection of the data line 41 on the substrate 11; the second insulating layer 141 has a third via K3, and the data line 41 is electrically connected to the second active portion 22 through the third via K3; in a direction parallel to the first direction X, the minimum distance a4 between the third via K3 and the protrusion G21 is greater than or equal to zero.

[0164] In a possible implementation manner, as shown in combination with FIG. 5A and FIG. 9D , the extension line of the orthographic projection of the edge y1 of the first protrusion on the substrate 11 does not overlap with the orthographic projection of the third via 3K on the substrate.

[0165] In a possible embodiment, referring to FIG9E , the protrusion G21 may extend in the first direction X all the way to the area where the first via K1 and the third via K3 are located. For example, as shown in FIG9E , the orthographic projection of the protrusion G21 on the substrate 11 may cover the overlapping edge of the first active layer 2 and the gate line 31, and further, the entire channel area of ​​the auxiliary gate G2 overlapping with the first active layer 2 may have a wider width in the second direction Y, thereby ensuring that the characteristics of the oxide transistor are ensured.

[0166] In one possible embodiment, as shown in Figures 9F and 9G , a block-shaped auxiliary gate G2 may be provided in the overlapping region between the first active layer 2 and the gate line 31. This allows the auxiliary gate G2 to have a relatively wide width in the second direction Y across the entire channel region overlapping the first active layer 2, thereby ensuring the characteristics of the oxide transistor. In one possible embodiment, the block-shaped auxiliary gate G2 may be rectangular, as shown in Figure 9F ; in another possible embodiment, the block-shaped auxiliary gate G2 may be a parallelogram, as shown in Figure 9G .

[0167] In one possible embodiment, referring to Figures 5A and 4, the first via hole K1 may pass through the first insulating layer 151 and the second insulating layer 141 to achieve electrical connection between the first electrode 53 and the first active layer 2; in another possible embodiment, referring to Figures 2A-2C, the first via hole K1 may pass through the first insulating layer 151, and the second insulating layer 141 may further have a second via hole K2, and the first electrode 53 may be electrically connected to the first active layer 2 through the first via hole K1 and the second via hole K2.

[0168] In a possible embodiment, referring to Figures 23, 24, 25, and 26, Figures 23, 24, 25, and 26 are schematic diagrams of transfer characteristic curves corresponding to the array substrate structure shown in Figure 5A, where a1-a2 is 1 μm, and the transistor source Vd is loaded with 0.1V, 5.1V, and 10.1V voltages, respectively. The horizontal axis represents the transistor gate voltage Vg, in V, and the vertical axis represents the transistor drain current Ig, in A. The thickness of the auxiliary gate G2 corresponding to Figure 23 is The thickness of the auxiliary gate G2 corresponding to FIG24 is The thickness of the auxiliary gate G2 corresponding to FIG25 is The thickness of the auxiliary gate G2 corresponding to FIG26 is According to FIG. 23, FIG. 24, FIG. 25, and FIG. 26, when the thickness of the auxiliary gate G2 is When the thickness of the auxiliary gate G2 is greater than 400 nm, the transistor leakage current is large, the transistor characteristics are poor, and the ion implantation cannot be effectively blocked during the conductorization process. When the thickness of the auxiliary gate G2 is greater than 400 nm, the transistor leakage current is small, and the transistor channel performance can be guaranteed. Considering that transistor performance is also affected by other factors (such as gate line width, ion implantation dose of the active layer, oxygen content of the gate insulation layer, etc.), the thickness of the auxiliary gate G2 can range from 20 nm to 200 nm based on various factors.

[0169] Currently, the best option for ultra-high PPI is liquid crystal display (LCD) technology. This is because in the LCD display structure, the pixel area circuit has only one switching transistor (TFT), which is very conducive to achieving high PPI. However, the transmittance of LCD is relatively low, and it is necessary to develop a backplane process solution with a high aperture ratio. Especially when the PPI reaches above 2000, various line widths, line spacings and via sizes reach the limit of the display manufacturing equipment, and the area of ​​the opening area is sharply compressed. A new backplane structure is needed to improve the backlight efficiency.

[0170] In view of this, an embodiment of the present disclosure provides an array substrate, as shown in Figures 1A to 1F, 2A, 2B, and 2C, wherein Figure 1B is a schematic diagram of a single film layer of the first active layer in Figure 1A, Figure 1C is a schematic diagram of a single film layer of the gate line layer in Figure 1A, Figure 1D is a schematic diagram of a single film layer of the data line in Figure 1A, Figure 1E is a schematic diagram of the first sub-connecting electrode in Figure 1A, Figure 1F is a schematic diagram of the outer contours of the second sub-connecting electrode and the first electrode in Figure 1A, Figure 2A is one of the schematic cross-sectional views taken at the dotted line E1F1 of Figure 1A, Figure 2B is a schematic cross-sectional view of two via holes provided in an embodiment of the present disclosure, and Figure 2C is a schematic diagram of another schematic view of two via holes provided in an embodiment of the present disclosure. The array substrate has a display area and a non-display area located outside the display area, the display area having a plurality of light-transmitting areas P, wherein the array substrate includes:

[0171] A first transistor (not shown in the figure) is located in the display area on one side of the substrate 11, and the first transistor includes a first active layer 2;

[0172] The first electrode 53 is located on the side of the first active layer 2 facing away from the substrate 11; specifically, the first electrode 53 may be a pixel electrode;

[0173] The first insulating layer 151 is located between the first active layer 2 and the first electrode 53 and contacts the first electrode 53. It has a first via hole K1 that penetrates the first insulating layer 151. The orthographic projection of the first via hole K1 on the substrate 11 is located within the orthographic projection of the light-transmitting region P on the substrate 11. Specifically, the orthographic projection area of ​​the light-transmitting region P on the substrate 11 is larger than the orthographic projection area of ​​the first via hole K1 on the substrate 11. The orthographic projection of the light-transmitting region P on the substrate 11 covers the orthographic projection of the first via hole K1 on the substrate 11, so that the first electrode 53 is electrically connected to the first active layer 2 through the first via hole K1. Specifically, the first insulating layer 151 can be a first planar layer.

[0174] In the embodiment of the present disclosure, the first via K1 electrically connecting the first electrode 53 and the first active layer 2 is set in the light-transmitting area P. Compared with the prior art, when the first via K1 electrically connecting the first electrode 53 and the first active layer 2 is set at the location of the wiring in the non-light-transmitting area, part of the area in the first electrode is used for electrical connection with the first active layer, and part of the area is used for display. The area for electrical connection is located outside the light-transmitting area P and cannot be used for display, so that the effective area of ​​the first electrode 53 is small. In the embodiment of the present disclosure, the first via K1 electrically connecting the first electrode 53 and the first active layer 2 is located in the light-transmitting area P. The first electrode 53 is electrically connected to the first active layer 2 and is also used for display, which increases the effective area of ​​the first electrode 53, improves the liquid crystal efficiency (the liquid crystal's ability to deflect linearly polarized light), and improves the light transmittance of the array substrate.

[0175] Specifically, the light-transmitting area P can be understood as the area in the array substrate where the sub-pixels are used for display. Specifically, the array substrate can have a black matrix, and the black matrix can have a black matrix opening; the orthographic projection of the light-transmitting area P on the substrate 11 can coincide with the orthographic projection of the black matrix opening on the substrate 11. Specifically, the first via K1 can be located in the area defined by the intersection of the gate line and the data line; specifically, since the array substrate is provided with other non-transparent structures in addition to the gate line and the data line, such as the black matrix, a light-shielding layer located on the side of the active layer facing the substrate for shielding the active layer from light, etc., the provision of the black matrix and the light-shielding layer will further reduce the area defined by the intersection of the gate line and the data line, thereby forming the final light-transmitting area P.

[0176] Specifically, the array substrate may include a shading structure (not shown in the figure), and the orthographic projection of the shading structure on the substrate 1 does not overlap with the orthographic projection of the pixel opening P area on the substrate 1; specifically, the array substrate may include an array substrate and a color filter substrate arranged relative to each other, and the shading structure may include a black matrix arranged on the array substrate and / or the color filter substrate, and the shading structure may also include a shading layer located on the array substrate, and specifically, the shading layer may be a shading metal layer.

[0177] In one possible embodiment, referring to Figures 1A-1F, 2A, 2B, and 2C, the array substrate further includes: a second insulating layer 141 located between the first insulating layer 151 and the first active layer 2, the second insulating layer 141 having a second via K2; and a connecting electrode 50 located between the first electrode 53 and the first active layer 2. The connecting electrode portion 50 is located on a side of the first insulating layer 151 facing away from the substrate 11 and contacts the first electrode 53. The first electrode 53 is electrically connected to the first active layer 2 at the second via K2 and the first via K1 via the connecting electrode 50. Specifically, the second insulating layer 141 may be a first interlayer dielectric layer.

[0178] In one possible embodiment, referring to Figures 1A-1F, 2A, 2B, and 2C, the orthographic projection of the second via K2 on the substrate 11 is located within the orthographic projection of the light-transmitting region P on the substrate 11. Specifically, the orthographic projection area of ​​the light-transmitting region P on the substrate 11 is larger than the orthographic projection area of ​​the second via K2 on the substrate 11, and the orthographic projection of the light-transmitting region P on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In another possible embodiment, the second via K2 may not be located in the light-transmitting region P; alternatively, the second via K2 may be partially located in the light-transmitting region P and partially located outside the light-transmitting region P.

[0179] In a possible embodiment, referring to Figures 1A-1F, 2A, 2B and 2C, the center of the orthographic projection of the first via K1 on the substrate 11 does not coincide with the center of the orthographic projection of the second via K2 on the substrate 11; specifically, the array substrate includes: a first gate layer; the first gate layer includes a plurality of gate lines 31 extending along a first direction; the orthographic projections of the first via K1 and the second via K2 on the substrate 11 are located between the orthographic projections of the Nth gate line 31 and the N+1th gate line 31 on the substrate, and in a direction perpendicular to the first direction X, the orthographic projection of the first via K1 on the substrate 11 is located on the side of the orthographic projection of the second via K2 on the substrate 11 away from the Nth gate line 31, where N is a positive integer.

[0180] It should be noted that the Nth gate line and the N+1th gate line are two adjacent gate lines on which the array substrate loads the scanning signals in sequence, and the N+1th gate line is the next gate line of the Nth gate line in the scanning direction of the scanning signal, that is, when the array substrate loads the scanning signal, it first loads the scanning signal to the Nth gate line, and then loads the scanning signal to the N+1th gate line, that is, the Nth gate line is loaded with the scanning signal before the N+1th gate line.

[0181] In a possible embodiment, referring to Figures 1A to 1F, 2A, 2B and 2C, the orthographic projection of the first via K1 on the substrate 11 and the orthographic projection of the second via K2 on the substrate 11 do not overlap with each other; specifically, the connecting electrode 50 includes: a first sub-connecting electrode 51 located between the second insulating layer 141 and the first insulating layer 151, and a second sub-connecting electrode 52 located between the first electrode 53 and the first insulating layer 151; the first sub-connecting electrode 51 is partially located at the bottom of the second via hole K2 and contacts the first active layer 2 at the bottom of the second via hole K2, and partially extends to the bottom of the first via hole K1 on the side of the second insulating layer 141 away from the substrate 11, and contacts the second sub-connecting electrode 52 at the bottom of the first via hole K1; the second sub-connecting electrode 52 is partially located at the bottom of the first via hole K1 and contacts the first sub-connecting electrode 51 at the bottom of the first via hole K1, and partially extends to the side of the first insulating layer 151 away from the substrate 11 and contacts the first electrode 53. In the embodiment of the present disclosure, the array substrate includes a first via K1 and a second via K2, that is, the first via K1 is made in the first insulating layer 151, and the second via K2 is made in the second insulating layer 141, and the first electrode 53 is electrically connected to the first active layer 2 through a two-step etching process. Compared with directly electrically connecting the first electrode 53 to the first active layer 2 through one via hole, the etching difficulty is greater. In the embodiment of the present disclosure, the first electrode 53 is electrically connected to the first active layer 2 through two via holes, which is less difficult in process production and easy to implement.

[0182] Specifically, as shown in Figures 1A-1F, 2A, 2B, and 2C, the first sub-connecting electrode 51 is partially located at the bottom of the second via hole K2 to achieve contact and overlap with the first active layer 2. It partially covers the sidewalls of the second via hole K2 and extends uphill to the portion above the second insulating layer 141 and to the bottom of the first via hole K1 to achieve electrical connection with the second sub-connecting electrode 52. Specifically, the orthographic projection of the first sub-connecting electrode 51 on the substrate 11 can cover part of the orthographic projection of the second via hole K2 on the substrate 11, or it can cover the entire orthographic projection of the second via hole K2 on the substrate 11.

[0183] The second sub-connecting electrode 52 is partially located at the bottom of the first via hole K1, contacts the first sub-connecting electrode 51, partially covers the sidewalls of the first via hole K1, and extends outwardly to the periphery of the first via hole K1 and covers the portion above the first insulating layer 151, thereby achieving contact and overlap with the first electrode 53. Specifically, the orthographic projection of the second sub-connecting electrode 52 on the substrate 11 can cover part of the orthographic projection of the first via hole K1 on the substrate 11, or can cover the entire orthographic projection of the first via hole K1 on the substrate 11.

[0184] The specific pattern of the second sub-connecting electrode 52 can be designed as needed, and its orthographic projection on the substrate 11 can be a triangle, quadrilateral, pentagon, hexagon, circle, ellipse, or other irregular shape. The specific pattern of the second sub-connecting electrode 52 must meet the following requirements: on the one hand, it can achieve contact and overlap with the first electrode 53; on the other hand, after being stacked with the first electrode 53, the overall outer contour of the two covers the orthographic projections of the first via K1 and the second via K2 on the substrate 11. Specifically, as shown in Figure 1F, the overall outer contour shape of the second sub-connecting electrode 52 and the first electrode 53 after being stacked can be a strip shape, and the maximum length a1 in the first direction X can be less than the maximum length a2 in the second direction Y, the maximum length a1 in the first direction X can be less than the length of the light-transmitting area P in the first direction X, or the maximum length a1 in the first direction X can be equal to the length of the light-transmitting area P in the first direction X; the extended length a2 in the second direction Y can be greater than the length of the light-transmitting area P in the second direction Y; or the extended length a2 in the second direction Y can be equal to the length of the light-transmitting area P in the second direction Y; or the extended length a2 in the second direction Y can be less than the length of the light-transmitting area P in the second direction Y.

[0185] In one possible embodiment, the second sub-connection electrode 52 at the first via hole K1 may only cover the side of the first insulating layer 151 facing away from the substrate 11, as shown in FIG2A ; the second sub-connection electrode 52 may also cover the entire outer edge of the first insulating layer 151 facing away from the substrate 11, as shown in FIG2B ; in one possible embodiment, the second sub-connection electrode 52 at the bottom of the first via hole K1 may cover the entire bottom of the first via hole K1, as shown in FIG2A ; the second sub-connection electrode 52 at the bottom of the first via hole K1 may cover a portion of the bottom of the first via hole K1, as shown in FIG2C .

[0186] Specifically, as shown in Figure 1F, the overall outer contour of the second sub-connecting electrode 52 and the first electrode 53 after being stacked may include: a first main body portion Z1, a second extension portion Z2 extending from one end of the first main body portion Z1, and a third extension portion Z3 extending from the other end of the first main body portion Z1, wherein the extension direction of the second extension portion Z2 may be different from the extension direction of the first main body portion Z1, and the extension direction of the third extension portion Z3 may be different from the extension direction of the first main body portion Z1. The first main body portion Z1 may extend along the second direction Y, and the first angle α1 formed by the extension direction of the second extension portion Z2 and the first direction X may range from 15° to 75°, specifically, for example, 45°; the second angle α2 formed by the extension direction of the third extension portion Z3 and the first direction X may range from -115 to -165°, specifically, for example, -135°. The orthographic projection of the second extension Z2 on the substrate 11 may not overlap with the orthographic projection of the gate line 31 on one side of the light-transmitting region P on the substrate 11; alternatively, the orthographic projection of the second extension Z2 on the substrate 11 may partially overlap with the orthographic projection of the gate line 31 on one side of the light-transmitting region P on the substrate 11; the orthographic projection of the third extension Z3 on the substrate 11 may not overlap with the orthographic projection of the gate line 31 on the other side of the light-transmitting region P on the substrate 11, and the orthographic projection of the third extension Z3 on the substrate 11 may partially overlap with the orthographic projection of the gate line 31 on the other side of the light-transmitting region P on the substrate 11. At least a portion of the first main portion Z1 is exposed to the light-transmitting region P.

[0187] In a possible embodiment, referring to Figures 1A to 1F, 2A, 2B, and 2C, the array substrate further includes: a third insulating layer 152 filled in the first via hole K1, and the surface of the third insulating layer 152 facing away from the substrate 11 has a step difference of less than 0.2 μm from the surface of the first insulating layer 151 facing away from the substrate 11. Specifically, the third insulating layer 152 can be a second flat layer. In the embodiment of the present disclosure, the array substrate further includes a third insulating layer 152 filled in the first via hole K1, which can flatten the step around the first via hole K1, and the surface of the third insulating layer 152 facing away from the substrate 11 has a step difference of less than 0.2 μm from the surface of the first insulating layer 151 facing away from the substrate 11. This can avoid abnormal liquid crystal orientation during the cell alignment process if the step difference is greater than 0.2 μm, and avoid light leakage caused by excessive step difference around the first via hole K1.

[0188] Specifically, the first insulating layer 151 is a first flat layer. Because this layer is typically thick, light leakage occurs when vias are provided. In conventional designs, vias are located where light-shielding metal traces are located to block light leakage. In the disclosed embodiment, the first via K1 of the first insulating layer 151 is located in the light-transmitting region P, which increases the effective area of ​​the first electrode 53 and improves liquid crystal efficiency. The third insulating layer 152 fills the gap and eliminates light leakage caused by step differences.

[0189] In a possible embodiment, referring to Figures 3 and 4, Figure 4 may be a schematic cross-sectional view of Figure 3 along the dotted line E2F2, in which the orthographic projection of the first via K1 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11; one end of the connecting electrode 50 is in direct contact and overlap with the first active layer 2, and the other end is in direct contact and overlap with the first electrode 53. Specifically, the second via K2 and the first via K1 can be formed by a one-step etching method. In the embodiment of the present disclosure, the orthographic projection of the first via K1 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In specific implementation, the first insulating layer 151 and the second insulating layer 141 can be etched in a one-step method, which can reduce one via in the light-transmitting area P and save two mask processes when patterning the second insulating layer 141 and the first sub-connecting electrode 51.

[0190] In one possible embodiment, referring to FIG3 and FIG4 , the array substrate further includes: a third insulating layer 152 filling the second via hole K2 and the first via hole K1, and the surface of the third insulating layer 152 facing away from the substrate 11 has a step difference of less than 0.2 μm from the surface of the first insulating layer 151 facing away from the substrate 11. In the disclosed embodiment, the array substrate further includes the third insulating layer 152 filling the second via hole K2 and the first via hole K1, which can flatten the step around the first and second via holes K1 and K2, and the surface of the third insulating layer 152 facing away from the substrate 11 has a step difference of less than 0.2 μm from the surface of the first insulating layer 151 facing away from the substrate 11. This can avoid abnormal liquid crystal orientation during the cell alignment process if the step difference is greater than 0.2 μm, and avoid light leakage caused by excessive step difference around the first via hole K1.

[0191] In one possible embodiment, the material of the first active layer 2 includes a rare earth element-doped metal oxide. Specifically, the material of the first active layer 2 is a metal oxide semiconductor material, which may include any one or more of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element-doped metal oxide (RE-OS), wherein the rare earth element-doped metal oxide may include lanthanide-doped metal oxide (Ln-OS). The crystal state of the active layer material may be amorphous, partially crystalline, or polycrystalline. In the embodiment of the present disclosure, the material of the first active layer 2 is a rare earth element-doped metal oxide. The first active layer 2 can maintain stable performance even when exposed to light, thereby eliminating the need for a light shielding layer in the light-transmitting region P, further improving the aperture ratio of the array substrate.

[0192] In one possible embodiment, referring to Figures 1A to 4 , the orthographic projection of the first electrode 53 on the substrate 11 covers the orthographic projections of the first via K1 and the second via K2 on the substrate 11. Since the second sub-connecting electrode 52 is distributed within the first via K1 and the first sub-connecting electrode 51 is distributed within the second via K2, the connecting electrodes within the holes can form an electric field with the electrode layer above the first electrode 53 (e.g., the common electrode layer), which may interfere with the normal electric field formed by the first electrode 53 and the common electrode layer, thereby affecting the normal deflection of the liquid crystal. In the embodiment of the present disclosure, by covering the orthographic projections of the first via K1 and the second via K2 on the substrate 11 by the first electrode 53, the electric field within the holes can be shielded, thereby achieving a stable electric field effect.

[0193] In one possible implementation, as shown in Figures 1A-4 , the first active layer 2 includes a first active portion 21 located in a light-transmitting region P. The first electrode 53 is electrically connected to the first active portion 21 via a first via K1. In the disclosed embodiment, the first active layer 2 includes the first active portion 21 located in the light-transmitting region P, thereby achieving electrical connection with the first electrode 53 in the light-transmitting region P.

[0194] In one possible embodiment, as shown in Figures 1A-4, the array substrate further includes: a first source-drain layer, the first source-drain layer including a plurality of data lines 41, the main body of which extends along the second direction Y; the first active layer 2 further including: a second active portion 22, and a third active portion 23 connecting the first active portion 21 and the second active portion 22; the orthographic projection of the second active portion 22 on the substrate 11 partially overlaps with the orthographic projection of the data line 41 on the substrate 11; the second insulating layer 141 further includes a third via K3 exposing a portion of the second active portion 22, and the data line 41 is electrically connected to the second active portion 22 through the third via K3. In the disclosed embodiment, the first active layer 2 further includes the second active portion 22 overlapping with the data line 41, thereby achieving conductive electrical connection between the first active layer 2 and the data line 41.

[0195] In one possible embodiment, referring to Figures 1A and 1C , the array substrate further includes a gate structure G located on a side of the first active layer 2 facing away from the substrate 11. The orthographic projection of the gate structure G on the substrate 11 covers at least a portion of the third active portion 23. In specific implementations, the gate structure G can be composed of various structures, which are described in detail below.

[0196] In one possible embodiment, referring to Figures 1A and 1C , the gate line 31 includes a gate portion G1 (shown in the thick black box in Figure 1C ); the third active portion 23 includes an overlapping portion D (shown in the thick black box in Figure 1B ); the orthographic projection of the overlapping portion D on the substrate 11 overlaps the orthographic projection of the gate portion G1 on the substrate 11; the orthographic projection of the gate structure G on the substrate 11 at least covers the orthographic projection of the overlapping portion D on the substrate 11. Specifically, in the structure shown in Figure 1A , the overlapping portion D can be understood as the region of the third active portion 23 that overlaps with the gate line 31, as shown in Figure 1B .

[0197] In a possible implementation, referring to FIG. 1A and FIG. 2A , FIG. 2B and FIG. 2C , the gate structure G may include only the gate portion G1 .

[0198] In one possible embodiment, the gate structure G may also include: a gate portion G1 and an auxiliary gate G2. Specifically, the material of the gate portion G1 may be the same as the material of the gate line 31; the auxiliary gate G2 may be a transparent structure. Specifically, the material of the auxiliary gate G2 may include: metal oxide (for example, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0199] Specifically, the auxiliary gate G2 can be located on the side of the gate portion G1 facing the substrate 11, or on the side of the gate portion G1 facing away from the substrate 11, as described in detail below. For example, referring to FIG5A , FIG5A may be a cross-sectional view along the dotted line E3F3 of FIG9A , a cross-sectional view along the dotted line E4F4 of FIG10 , or a cross-sectional view along the dotted line E5F5 of FIG11 , the gate structure G may include: a gate portion G1, and an auxiliary gate G2 located on the side of the gate portion G1 facing the substrate 11; the orthographic projection of the auxiliary gate G2 on the substrate 11 covers the orthographic projection of the gate portion G1 on the substrate 11, and covers at least one side of the gate portion G1 in the two side regions in the second direction Y. Specifically, as shown in Figure 5A, the orthographic projection of the auxiliary gate G2 on the substrate 11 covers the orthographic projection of the gate portion G1 on the substrate 11, and covers the two side areas of the gate portion G1 in the second direction Y; specifically, the orthographic projection of the auxiliary gate G2 on the substrate 11 can also be the orthographic projection of the covering gate portion G1 on the substrate 11, and one side of the two side areas of the covering gate portion G1 in the second direction Y.

[0200] It should be noted that the first via hole shown in FIG. 5A may also be connected in the same manner as shown in FIG. 2A and FIG. 4 .

[0201] In one possible embodiment, referring to FIG6 and FIG7 , the gate structure G includes: a gate portion G1, and an auxiliary gate G2 located on a side of the gate portion G1 facing away from the substrate 11; the orthographic projection of the auxiliary gate G2 on the substrate 11 covers the orthographic projection of the gate portion G1 on the substrate 11, and covers at least one side of the gate portion G1 in the two side regions in the second direction Y. Specifically, for example, referring to FIG6 , the orthographic projection of the auxiliary gate G2 on the substrate 11 covers the orthographic projection of the gate portion G1 on the substrate 11, and covers the two side regions of the gate portion G1 in the second direction Y; specifically, for another example, referring to FIG7 , the orthographic projection of the auxiliary gate G2 on the substrate 11 covers the orthographic projection of the gate portion G1 on the substrate 11, and covers one side of the two side regions of the gate portion G1 in the second direction Y.

[0202] In one possible embodiment, as shown in FIG8 , the gate structure G includes a gate portion G1 and auxiliary gates G2 located on both sides of the gate portion G1 in the second direction Y. The orthographic projection of the gate portion G1 on the substrate 11 does not overlap with the orthographic projection of the auxiliary gate G2 on the substrate 11. That is, the orthographic projection of the auxiliary gate G2 on the substrate 11 is located on both sides of the orthographic projection of the gate portion G1 on the substrate 11.

[0203] In one possible embodiment, referring to Figures 5A to 8 , the maximum spacing e2 between the orthogonal projections of the auxiliary gates G2 on the substrate 11 in the second direction Y is greater than or equal to the maximum spacing a1 between the orthogonal projections of the gate portions G1 on the substrate 11 in the second direction Y. It should be noted that for the array substrate structure shown in Figures 5A to 7 , the maximum spacing a2 between the orthogonal projections of the auxiliary gates G2 on the substrate 11 in the second direction Y can be understood as the width of the auxiliary gates G2 in the second direction Y; and for the array substrate structure shown in Figure 8 , the maximum spacing a2 between the orthogonal projections of the auxiliary gates G2 on the substrate 11 in the second direction Y can be understood as the maximum distance between two auxiliary gates G2 in the second direction Y.

[0204] In specific implementations, the first active layer 2 may have a variety of different pattern shapes, which are described in detail below.

[0205] In one possible embodiment, the first active layer 2 may include a plurality of oblique linear patterns. Specifically, referring to FIG. 9A , a cross-sectional view along the dotted line E3F3 in FIG. 9A may be as shown in FIG. 5A , wherein the gate line 31 extends from the first end A to the second end B along the first direction X; the first active layer 2 includes a first active group 210 and a second active group 220 alternately arranged in the second direction Y; the first active group 210 includes: a plurality of first active patterns 211 extending along the third direction J1 and sequentially arranged along the first direction X, the first active patterns 211 being arranged in sequence along the first direction X. 211 includes a first active portion 21, a second active portion 22 and a third active portion 23; an angle β1 formed by the first active pattern 211 and the gate line 31 toward the first end A is an acute angle; the second active group 220 includes: a plurality of second active patterns 222 extending along the fourth direction J2 and arranged in sequence along the first direction X, the second active pattern 222 includes the first active portion 21, the second active portion 22 and the third active portion 23; an angle β2 formed by the second active pattern 222 and the gate line 31 toward the first end A is an obtuse angle.

[0206] In one possible embodiment, the first active layer 2 may include a plurality of (vertical) linear patterns extending along the second direction. Specifically, referring to FIG10 , the cross-sectional view along the dotted line E4F4 in FIG10 may be as shown in FIG5A , and the gate line 31 extends from the first end A to the second end B along the first direction X; the first active portion 21 , the second active portion 22 , and the third active portion 23 all extend along the second direction Y, and the angle β3 formed with the gate line 31 toward the first end A is a right angle.

[0207] In one possible embodiment, the first active layer 2 may include multiple oblique and non-linear patterns, specifically, referring to Figures 1A, 1B and 11. The cross-sectional view of Figure 11 along the dotted line E5F5 may be as shown in Figure 5A, and the gate line 31 extends from the first end A to the second end B along the first direction X; the first active portion 21 and the second active portion 22 both extend along the second direction Y, and the extension line of the first active portion 21 does not coincide with the extension line of the third active portion 23; the angle β4 formed by at least a portion of the third active portion 23 and the gate line 31 toward the first end A is an acute angle.

[0208] In one possible embodiment, as shown in conjunction with Figures 1A to 11, the area of ​​the first active layer 2 for overlapping with the first electrode 53 can be used as the first active portion 21, the area for overlapping with the data line 41 can be used as the second active portion 22, and the remaining area can be used as the third active portion 23. In one possible embodiment, as shown in Figures 1A and 1B, the third active portion 23 only includes a portion extending in one direction, such as only an obliquely extending portion, and the obliquely extending portion overlaps with the gate line 31 to form at least a portion of the channel region (in the embodiment of the present disclosure, the channel region may also include a region formed by the overlap of the auxiliary gate G2 and the third active portion 23); in another possible embodiment, as shown in Figure 11, the third active portion 23 may include multiple portions extending in different directions, such as an obliquely extending portion and a vertically extending portion, wherein the vertically extending portion overlaps with the gate line 31 to form at least a portion of the channel region (in the embodiment of the present disclosure, the channel region may also include a region formed by the overlap of the auxiliary gate G2 and the third active portion 23).

[0209] In one possible embodiment, the first active layer 2 may include a (horizontal) linear pattern extending along the first direction, specifically, see Figures 12A and 12B, wherein Figure 12A may be a cross-sectional schematic diagram of Figure 12B along the dotted line E6F6, the first active portion 21, the second active portion 22, and the third active portion 23 all extend along the first direction X, and there is a gap between the orthographic projection of the first active layer 2 on the substrate 11 and the orthographic projection of the gate line 31 on the substrate 11; the third active portion 23 is located in the light-transmitting area P; the gate structure G includes: an auxiliary gate G2 located on the side of the first active layer 2 facing away from the substrate 11, the auxiliary gate G2 extends along the second direction Y, and the orthographic projection of the substrate 11 covers the orthographic projection of the third active portion 23 on the substrate 11, and covers part of the orthographic projection of the gate line 31 on the substrate 11. Specifically, the gate structure G may only include: an auxiliary gate G2; the first gate layer (i.e., the layer where the gate line 31 is located) may be located on the side of the first active layer 2 facing away from the substrate 11; the auxiliary gate G2 is located on the side of the gate line 31 facing away from the substrate 11, and is in contact and overlapped with the gate line 31; a portion of the auxiliary gate G2 overlaps with the third active portion 23 to form a channel region, and another portion overlaps with the gate line 31 to achieve contact and overlap with the gate line 31. In the embodiment of the present disclosure, a transparent auxiliary gate G2 may be provided in the light-transmitting region P, and the gate line 31 may serve only as a routing line, overlapping with the auxiliary gate G2 in the non-light-transmitting region. Because the channel region of the first active layer 2 and the auxiliary gate G2 are both made of transparent materials, placement in the light-transmitting region P does not reduce transmittance. Therefore, the width of the auxiliary gate G2 can be appropriately increased, thereby further ensuring transistor characteristics.

[0210] In one possible embodiment, referring to FIG13A and FIG13B , FIG13A may be a schematic cross-sectional view taken along the dotted line E7F7 of FIG13B , wherein the gate line 31 further includes a gate line branch 32 extending along the second direction Y; the orthographic projection of the auxiliary gate G2 on the substrate 11 covers the orthographic projection of the gate line branch 32 on the substrate 11. Specifically, the first gate layer (i.e., the layer where the gate line 31 is located) may be located on the side of the first active layer 2 facing the substrate 11, that is, the first gate layer is placed downward, the gate line branch 32 serves as the bottom gate, and the auxiliary gate G2 is overlapped with the bottom gate (gate line branch 32) by drilling a hole (such as the via K4 in FIG13B ). On the one hand, the gate control force can be further enhanced, especially for the back channel portion; on the other hand, the gate line branch 32 is equivalent to adding a light shielding layer to the oxide transistor, thereby improving the light stability characteristics of the oxide transistor.

[0211] In a possible implementation, the material of the auxiliary gate G2 includes: indium tin oxide, indium-doped zinc oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, or indium-doped cadmium oxide.

[0212] In a possible embodiment, referring to FIG. 9A or FIG. 10 , the data line 41 may include: a first data portion 411 and a second data portion 412 extending along the second direction Y and alternately arranged along the second direction Y, and a third data portion 413 connecting the first data portion 411 and the second data portion 412 and extending along the first direction X, wherein the extension line of the first data portion 411 does not overlap with the extension line of the second data portion 412.

[0213] In a possible implementation, as shown in FIG. 1A , FIG. 11 , FIG. 12B , and FIG. 13B , the data line 41 may also extend only along the second direction Y. As shown in FIG.

[0214] It should be noted that in order to clearly illustrate the specific composition of the gate structure G, the remaining film layers are simplified in Figures 5A-13B. In a specific implementation, the array substrate shown in Figures 5A-13B may also include the film layers shown in Figures 1A-4, and the conduction method between the first electrode 53 and the first active layer 2 may also be as shown in Figures 1A-4.

[0215] In one possible embodiment, referring to Figures 14A and 14B, where Figure 14B may be a single-layer diagram of the common electrode in Figure 14A, the array substrate further includes: a common electrode 6 located on the side of the first electrode 5 facing away from the substrate 11; the common electrode 6 includes: a first common electrode portion 61 extending along a first direction X, and a second common electrode portion 62 extending along a second direction Y; the orthographic projection of the first common electrode portion 61 on the substrate 11 overlaps the orthographic projection of the gate line 31 on the substrate 11, and the orthographic projection of the second common electrode portion 62 on the substrate 11 overlaps the orthographic projection of the data line 41 on the substrate 11; the orthographic projection of the first via K1 on the substrate 11 is located within the orthographic projection of the substrate where the first common electrode portion 61 and the second common electrode portion 62 intersect. In one possible embodiment, the orthographic projection of the second via K2 on the substrate 11 is also located within the orthographic projection of the substrate where the first common electrode portion 61 and the second common electrode portion 62 intersect. In the embodiment of the present disclosure, the first electrode 53 is a strip design and the common electrode 6 is a mesh design. Through simulation, it can be seen that the array substrate of the embodiment of the present disclosure can significantly improve the liquid crystal efficiency, which can increase the liquid crystal efficiency from 54.2% of the conventional design to 58.4%.

[0216] In a possible embodiment, referring to Figures 15 and 16, the array substrate further includes: a first light-shielding layer 7 located on the side of the common electrode 6 away from the first electrode 53 and in direct contact with the common electrode 6, and a spacer 8 located on the side of the first light-shielding layer 7 away from the first electrode layer 53; the orthographic projection of the common electrode 6 on the substrate 11 covers the orthographic projection of the first light-shielding layer 7 on the substrate 11, and the line width of the first light-shielding layer 7 is smaller than the line width of the common electrode 6; the orthographic projection of the first light-shielding layer 7 on the substrate 11 covers the orthographic projection of the spacer 8 on the substrate 11, and the line width of the spacer 8 is smaller than the line width of the first light-shielding layer 7.

[0217] Specifically, the first light-shielding layer 7 can be made of a blackened metal material, and the spacer 8 can be made of molybdenum or aluminum (i.e., a material that can be wet-etched). The first light-shielding layer 7 and the spacer 8 can be formed by a mask process, using wet etching plus dry etching, and utilizing the difference in etching bias (bias) between the spacer 8 and the first light-shielding layer 7, so that the first light-shielding layer 7 and the spacer 8 form a step shape.

[0218] Specifically, the thickness of the first light shielding layer 7 can be 30 nm to 80 nm, and the thickness of the spacer 8 can be 0.4 μm to 1 μm. The first light shielding layer 7 can shield the gate lines 31 and the data lines 41 and reduce the resistance of the common electrode 6 .

[0219] In one possible embodiment, the orthographic projection of the first light-shielding layer 7 on the substrate 11 covers the orthographic projection of the data line 41 on the substrate 11, and covers the orthographic projection of the gate line 31 on the substrate 11; the orthographic projection of the spacer 8 on the substrate 11 covers the orthographic projection of the data line 41 on the substrate 11, and covers the orthographic projection of the gate line 31 on the substrate 11.

[0220] Specifically, the shapes of the first light-shielding layer 7 and the spacer 8 can be similar to the pattern shape of the common electrode 6 shown in Figure 14A, that is, the first light-shielding layer 7 can include a first light-shielding portion extending along the first direction X, and a second light-shielding portion extending along the second direction Y, and the first light-shielding portion and the second light-shielding portion intersect to form a mesh structure; the spacer 8 can include a first spacer portion extending along the first direction X, and a second spacer portion extending along the second direction Y, and the first spacer portion and the second spacer portion intersect to form a mesh structure. The spacer 8 with a mesh structure can be designed with a narrower line width, which is beneficial to improving the aperture ratio of the array substrate.

[0221] In a possible embodiment, referring to Figures 17 to 20, the array substrate further includes a gate driving circuit located in the non-display area BB, and the gate driving circuit board includes: a first driving active layer 201, a first driving gate 301 located on the side of the first driving active layer 201 away from the substrate 11, and a first driving source and drain 401 located on the side of the first driving gate 301 away from the first driving active layer 201.

[0222] In one possible embodiment, as shown in FIG17 , the first driving active layer 201 and the first active layer 2 are made of the same layer and material; the first driving gate 301 and the first gate layer are made of the same layer and material, that is, the first driving gate 301 and the gate line 31 are made of the same layer and material; the first driving source and drain electrode 401 and the first source and drain electrode layer are made of the same layer and material, that is, the first driving source and drain electrode 401 and the data line 41 are made of the same layer and material. Specifically, the first active layer 2 and the first driving active layer 201 can both be oxide active layers. Specifically, for example, the material of the first active layer 2 can include: amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), or indium zinc tin oxide (IZTO). In the embodiment of the present disclosure, the corresponding film layers of the display area AA and the non-display area BB are made of the same layer and material. At the same time as the film layers of the display area AA are formed, the corresponding film layers of the non-display area can be formed, thereby simplifying the manufacturing process of the array substrate.

[0223] In one possible embodiment, as shown in FIG17 , the array substrate further includes a second gate layer located between the substrate 11 and the first active layer 2 ; the second gate layer includes: a first gate 302 located in the display area AA, and a second driving gate 303 located in the non-display area BB; wherein the orthographic projection of the gate line 31 on the substrate 11 covers the orthographic projection of the first gate 302 on the substrate 11; and the orthographic projection of the second driving gate 303 on the substrate 11 covers the orthographic projection of the first driving gate 301 on the substrate 11. In the disclosed embodiment, when the transistor active layers in both the display and non-display areas are made of oxide, the transistors in the gate driving circuit of the non-display area adopt an oxide dual-gate structure, and the bottom gate size is larger than the top gate size (the single-side wrapping size can be 0.5 μm to 2 μm), which can effectively improve the transistor on-state current and device stability. For the transistors in the light-transmitting area, the bottom gate size is smaller than the top gate size (the bottom gate is 0.3 μm to 0.6 μm smaller on one side than the top gate), which can avoid affecting the aperture ratio.

[0224] In one possible embodiment, as shown in FIG18 , the array substrate further includes a second gate electrode 304 located in the display area AA and between the substrate 11 and the first active layer 2; the first driver source and drain electrode 401 is formed from the same layer and material as the second gate electrode 304; and the material of the first driver active layer 201 includes polysilicon. In the disclosed embodiment, considering that the current high-transition oxide gate drive circuit design is not mature enough, the transistor size in the gate drive circuit is large, resulting in an excessively large frame. In the disclosed embodiment, a low-temperature polysilicon transistor design can be used in the gate drive circuit, wherein the first driver source and drain electrode 401 of the low-temperature polysilicon transistor is formed from the same layer as the bottom gate (second gate electrode 304) of the display area transistor and is formed by a single mask process, which can simplify the manufacturing process of the array substrate; and the bottom gate (second gate electrode 304) design of the display area can shield the first active layer 2 of the display area oxide, thereby improving the stability of the display area transistor.

[0225] In one possible embodiment, as shown in Figures 19 and 20, the first driver source drain 401 is in the same layer and material as the first source and drain layer, that is, the first driver source drain 401 is in the same layer and material as the data line 41; the material of the first driver active layer 201 includes: polysilicon. Specifically, in the embodiment of the present disclosure, the first active layer 2 of the display area transistor can adopt an oxide active layer, and the transistor in the non-display area can adopt a polysilicon active layer. Oxide thin film transistors have advantages such as low leakage current, and low-temperature polysilicon thin film transistors have advantages such as high mobility and fast charging. Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on an array substrate to form a low-temperature polycrystalline oxide array substrate. By utilizing the advantages of both, high resolution (Pixel Per Inch, PPI) and low-frequency driving can be achieved, which can reduce power consumption and improve display quality. In addition, in the embodiment of the present disclosure, the first driver source drain 401 is in the same layer and material as the first source and drain layer, which can simplify the manufacturing process of the array substrate.

[0226] Specifically, with reference to FIG. 1A to FIG. 20 , the array substrate further includes at least one of the following:

[0227] a second interlayer dielectric layer 142 located between the substrate 11 and the first active layer 2;

[0228] a first gate insulating layer 132 located between the second interlayer dielectric layer 142 and the substrate 11;

[0229] a buffer layer 12 located between the first gate insulating layer 132 and the substrate 11;

[0230] a second gate insulating layer 131 located between the first active layer 2 and the gate portion G1;

[0231] a third gate insulating layer 133 located between the second insulating layer 131 and the second insulating layer 141;

[0232] a third interlayer dielectric layer 143 located between the first sub-connecting electrode 51 and the second insulating layer 141 ;

[0233] The passivation layer 53 is located on a side of the first electrode 53 facing away from the third insulating layer 152 .

[0234] In some examples, the buffer layer 12, the first insulating layer 151, the second insulating layer 141, and the third insulating layer 152 may be inorganic insulating layers. For example, the buffer layer 12, the first insulating layer 151, the second insulating layer 141, and the third insulating layer 152 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first gate layer, the first source and drain layer, the second gate layer, and the second source and drain layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure, such as Ti / Al / Ti.

[0235] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0236] Based on the same inventive concept, as shown in FIG. 21 , an embodiment of the present disclosure further provides a method for manufacturing a display panel as provided in an embodiment of the present disclosure, which includes:

[0237] Step S100, providing a substrate; specifically, the substrate may be a glass substrate; specifically, a buffer layer may be deposited on one side of the substrate, wherein the buffer layer may be made of SiN / SiO2 and may have a thickness ranging from 200 nm to 500 nm;

[0238] Step S200: forming a first active layer and a first insulating layer on one side of the substrate, and forming a first via hole in the first insulating layer; specifically, a light-resistant metal oxide active layer can be deposited, and the material can be rare earth-doped IZO or IGZO and other materials, which can stabilize the transistor characteristics under light, and the thickness is 20nm to 50nm; then, a second gate insulating layer 131 can be deposited, and the material can be SiO2, and the thickness can be 100nm to 150nm, and then the first gate layer can be deposited, and the material can be Al, Ti or Mo, Cu and other materials, and the thickness can be 200nm to 500nm. nm, photolithography and etching are performed to form the gate line and the gate shape; then, the second insulating layer 141 is deposited, the material of which can be SiO2 / SiN with a thickness of 300nm to 500nm, and then holes are opened; then, the first source and drain layer is deposited, the material of which can be similar to that of the gate line, and then patterned; then, a via hole is opened in the light-transmitting area to form a second via hole K2, connecting to the first active layer 2, and then a first sub-connecting electrode 51 layer is deposited in the second via hole K2 and patterned; then, the first insulating layer 151 is deposited to flatten the lower second via hole K2 and the metal step, and then the first via hole K1 is opened in the light-transmitting area;

[0239] Step S300: forming a first electrode on a side of the first insulating layer away from the first active layer, so that the first electrode is electrically connected to the first active layer through a first via hole. Specifically, a second sub-connecting electrode 52 in contact with the first sub-connecting electrode 51 is deposited in the first via hole K1; then, a filling process is performed through the third insulating layer 152, and a glue coating and ashing scheme is adopted to ensure that the step difference between the filled third insulating layer 152 and the first insulating layer 151 is within 0.2μm to reduce light leakage, and then the first electrode 53 is covered at the via hole position in the light-transmitting area to shield the electric field in the hole, and the deposition of the passivation layer 16 and the common electrode 6 is continued; then, the first light-shielding layer 7 and the spacer 8 are deposited, and the first light-shielding layer 7 is made of blackened metal material, and the spacer 8 is made of metal Mo or Al and other materials that can be wet-etched. The first light-shielding layer 7 and the spacer 8 are formed as a mask, the thickness of the first light-shielding layer 7 is 30nm~80nm, and the thickness of the spacer 8 is 0.4μm~1μm. The difference in etching bias between the spacer 8 and the first light-shielding layer 7 is used to form a wrapping relationship between the first light-shielding layer 7 and the spacer 8.

[0240] In a possible implementation, step S200 of forming a first active layer and a first insulating layer on one side of the substrate includes:

[0241] Step S211, forming a second insulating layer on a side of the first active layer facing away from the substrate, and forming an exposed second via hole in the second insulating layer;

[0242] Step S212, forming a first sub-connecting electrode in the area where the second via hole is located;

[0243] Step S213, forming a first insulating layer on a side of the second insulating layer away from the first active layer, and forming a first via hole in the first insulating layer;

[0244] Step S214, forming a second sub-connecting electrode in the area where the first via hole is located;

[0245] Step S215 , filling a third insulating layer in a region of the second sub-connecting electrode that is away from the first sub-connecting electrode and located at the first via hole.

[0246] In a possible implementation, step S200 of forming a first active layer and a first insulating layer on one side of the substrate includes:

[0247] Step S221: forming a second insulating layer on a side of the first active layer facing away from the substrate;

[0248] Step S222, forming a first insulating layer on a side of the second insulating layer away from the first active layer;

[0249] Step S223: forming a first via hole penetrating the first insulating layer and a second via hole penetrating the second insulating layer and exposing a portion of the first active layer through a patterning process;

[0250] Step S224, forming a connecting electrode in the area where the second via hole and the first via hole are located;

[0251] Step S225 , filling a third insulating layer in the area of ​​the second via hole and the first via hole on the side of the connecting electrode away from the first active layer.

[0252] In a possible implementation, as shown in FIG22 , after step S300, the manufacturing method further includes:

[0253] Step S400: forming a first light shielding film and a spacer film in sequence on a side of the first electrode facing away from the substrate;

[0254] Step S500 : patterning the first light shielding film and the spacer film through a mask process to form a first light shielding layer and spacers.

[0255] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0256] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein, Including: A substrate; A first active layer located on one side of the substrate; A gate structure located on the side of the first active layer facing away from the substrate; The gate structure includes an auxiliary gate; The orthographic projection of the auxiliary gate on the substrate has an overlapping area with the orthographic projection of the first active layer on the substrate, and the thickness of the auxiliary gate in the direction perpendicular to the substrate ranges from 20 nm to 200 nm.

2. The array substrate according to claim 1, wherein, The display substrate further includes: a plurality of gate lines extending in a first direction, a plurality of auxiliary gate lines extending in the first direction, and a plurality of data lines extending in a second direction along the main body; the orthographic projection of the auxiliary gate line on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate; The gate structure further includes: a gate portion; the gate line includes the gate portion, and the auxiliary gate line includes the auxiliary gate; the orthographic projection of the auxiliary gate on the substrate covers the orthographic projection of the gate portion on the substrate and at least one side of the two side regions of the gate portion in the second direction; the thickness of the gate portion in the direction perpendicular to the substrate is greater than the thickness of the auxiliary gate in the direction perpendicular to the substrate, and the ratio range of the thickness of the gate portion in the direction perpendicular to the substrate to the thickness of the auxiliary gate in the direction perpendicular to the substrate is 1 to 20.

3. The array substrate according to claim 2, wherein, The width a1 of the auxiliary gate in the second direction satisfies the following relationship: 1.5 ≤ a1 / a2 ≤ 2, where a2 represents the width of the gate portion in the second direction.

4. The array substrate according to claim 3, wherein, The width a1 of the auxiliary gate in the second direction satisfies the following relationship: 0.5 μm ≤ |a1 - a2| ≤ 1.5 μm.

5. The array substrate according to any one of claims 2 - 4, wherein, The auxiliary gate line includes: a first auxiliary portion and a second auxiliary portion electrically connected to the first auxiliary portion; wherein, the second auxiliary portion of the Nth auxiliary gate line is located on the side of the first auxiliary portion of the Nth auxiliary gate line facing the (N + 1)th auxiliary gate line, where N is a positive integer; The orthographic projection of the first auxiliary portion of the Nth auxiliary gate line on the substrate coincides with the orthographic projection of the Nth gate line on the substrate, and the orthographic projection of the second auxiliary portion of the Nth auxiliary gate line on the substrate does not overlap with the orthographic projection of the Nth gate line on the substrate.

6. The array substrate according to any one of claims 2 - 4, wherein, The Nth auxiliary gate line has a first outer edge on the side away from the (N + 1)th gate line, and the Nth gate line has a second outer edge on the side away from the (N + 1)th gate line; The first outer edge coincides with the second outer edge.

7. The array substrate according to any one of claims 2 - 4, wherein, The Nth auxiliary gate line has a first outer edge on the side away from the (N + 1)th gate line, and the Nth gate line has a second outer edge on the side away from the (N + 1)th gate line, where N is a positive integer; The second outer edge is located on the side of the first outer edge away from the (N + 1)th gate line.

8. The array substrate according to claim 6 or 7, wherein, The array substrate further includes: a first electrode located on the side of the gate structure facing away from the substrate, a first insulating layer located between the first electrode and the first active layer, and a second insulating layer located between the first insulating layer and the first active layer; The first active layer includes: a first active portion, a second active portion, and a third active portion located between the first active portion and the second active portion; the orthographic projection of the second active portion on the substrate overlaps with the orthographic projection of the data line on the substrate; The first insulating layer has a first via hole, and the first electrode is electrically connected to the first active portion at least through the first via hole; the second insulating layer has a third via hole, and the data line is electrically connected to the second active portion at least through the third via hole.

9. The array substrate according to claim 8, wherein, The Nth gate line has a third outer edge close to one side of the N+1th gate line, and the Nth gate line satisfies the following relationship: b1>b2>0, wherein b1 represents the positive projection of the third outer edge of the Nth gate line on the substrate and the maximum positive projection of the center of the first via hole on the substrate in the second direction. Small distance, b2 represents the minimum distance between the orthographic projection of the second outer edge of the Nth gate line on the substrate and the orthographic projection of the center of the third via hole on the substrate in the second direction.

10. The array substrate according to claim 8 or 9, wherein, The Nth gate line has a third outer edge close to one side of the N+1th gate line, and the Nth gate line satisfies the following relationship: b3>b4>0, wherein b3 represents the minimum distance between the orthographic projection of the third outer edge of the Nth gate line on the substrate and the orthographic projection of the first via on the substrate in the second direction, and b2 represents the minimum distance between the orthographic projection of the second outer edge of the Nth gate line on the substrate and the orthographic projection of the third via on the substrate in the second direction.

11. The array substrate according to any one of claims 8 - 10, wherein, The orthographic projection area of ​​the first via hole on the substrate is larger than the orthographic projection area of ​​the third via hole on the substrate.

12. The array substrate according to claim 2, wherein, The auxiliary gate line has a convex portion protruding along the second direction; an orthographic projection of the convex portion on the substrate has an overlapping area with an orthographic projection of the first active layer on the substrate.

13. The array substrate according to claim 12, wherein, The array substrate further comprises: a first electrode located at a side of the gate structure away from the substrate, and a first insulating layer located between the first electrode and the first active layer; The first active layer includes: a first active portion; the first insulating layer has a first via hole, and the first electrode is electrically connected to the first active portion at least through the first via hole; In parallel with the first direction, a minimum distance between the first via hole and the protrusion is greater than or equal to zero.

14. The array substrate according to claim 12, wherein, The array substrate further includes: a second insulating layer located between the first insulating layer and the first active layer; The first active layer further includes: a second active portion, and a third active portion located between the first active portion and the second active portion; the orthographic projection of the second active portion on the substrate overlaps with the orthographic projection of the data line on the substrate; the second insulating layer has a third via hole, and the data line is electrically connected to the second active portion at least through the third via hole; In parallel with the first direction, the minimum distance between the third via hole and the protrusion is greater than At zero.

15. The array substrate according to any one of claims 8 - 11, 13, and 14, wherein, The orthographic projection of the first via on the substrate is located within the orthographic projection of the region defined by the intersection of the gate line and the data line on the substrate, so that the first electrode is electrically connected to the first active layer through the first via.

16. The array substrate according to claim 15, wherein, The second insulating layer has a second via. The array substrate further includes: a connection electrode located between the first electrode and the first active layer, the connection electrode is partially located on the side of the first insulating layer away from the substrate and contacts the first electrode; the first electrode is electrically connected to the first active layer through the connection electrode at the second via and the first via.

17. The array substrate according to claim 16, wherein, The orthographic projection of the second via on the substrate is located within the orthographic projection of the region defined by the intersection of the gate line and the data line on the substrate.

18. The array substrate according to claim 16 or 17, wherein, The orthographic projections of the first via and the second via on the substrate are located between the orthographic projections of the Nth gate line and the (N + 1)th gate line on the substrate, and in a direction perpendicular to the first direction, the orthographic projection of the first via on the substrate is located on the side of the orthographic projection of the second via on the substrate away from the Nth gate line, where N is a positive integer.

19. The array substrate according to claim 18, wherein, The connection electrode includes: a first sub-connection electrode located between the second insulating layer and the first insulating layer, and a second sub-connection electrode located between the first electrode and the first insulating layer; The first sub-connection electrode is partially located at the bottom of the second via and contacts the first active layer at the bottom of the second via, and partially extends to the bottom of the first via on the side of the second insulating layer away from the substrate and contacts the second sub-lap electrode at the bottom of the first via; The second sub-connection electrode is partially located at the bottom of the first via and contacts the first sub-connection electrode at the bottom of the first via, and partially extends to the side of the first insulating layer away from the substrate and contacts the first electrode.

20. The array substrate according to claim 18 or 19, wherein, The array substrate further includes: a third insulating layer filled in the first via, and the step difference between the surface of the third insulating layer away from the substrate and the surface of the first insulating layer away from the substrate is less than 0.2 μm.

21. The array substrate according to claim 16 or 17, wherein, The orthographic projection of the first via on the substrate covers the orthographic projection of the second via on the substrate; one end of the connection electrode is directly in contact and lapped with the first active layer, and the other end is directly in contact and lapped with the first electrode.

22. The array substrate according to claim 21, wherein, The array substrate further includes: a third insulating layer filled in the second via and the first via, and the step difference between the surface of the third insulating layer away from the substrate and the surface of the first insulating layer away from the substrate is less than 0.2 μm.

23. The array substrate according to any one of claims 2 - 22, wherein, The array substrate further includes: a first gate layer, a first source-drain layer; the first gate layer includes the gate line; the first source-drain layer includes the data line; The first active layer further includes: a second active portion, and a third active portion connecting the first active portion and the second active portion; the orthographic projection of the second active portion on the substrate partially overlaps with the orthographic projection of the data line on the substrate. The array substrate further comprises a gate driving circuit located in the non-display area, and the gate driving circuit board comprises: a first driving active layer, a first driving gate, and a first driving source and drain.

24. The array substrate according to claim 23, wherein, The gate structure covers at least a portion of the third active portion in an orthographic projection on the substrate.

25. The array substrate according to claim 24, wherein, The third active portion includes: an overlapping portion, the orthographic projection of the overlapping portion on the substrate overlaps with the orthographic projection of the gate portion on the substrate; The orthographic projection of the gate structure on the substrate at least covers the orthographic projection of the overlapping portion on the substrate.

26. The array substrate according to claim 25, wherein, The auxiliary gate is located on a side of the gate portion facing the substrate.

27. The array substrate according to claim 25, wherein, The auxiliary gate is located at a side of the gate portion facing away from the substrate.

28. The array substrate according to claim 1, wherein, The gate structure comprises: the gate portion; the auxiliary gates are located at both sides of the gate portion in the second direction; and the orthographic projection of the gate portion on the substrate does not overlap with the orthographic projection of the auxiliary gate on the substrate.

29. The array substrate according to any one of claims 26-28, wherein, A maximum spacing between orthographic projections of the auxiliary gates on the substrate in the second direction is greater than or equal to a maximum spacing between orthographic projections of the gate portions on the substrate in the second direction.

30. The array substrate according to any one of claims 2-29, wherein, The gate line extends from the first end to the second end along the first direction; the first active layer includes a first active group and a second active group alternately arranged in the second direction; The first active group includes: a plurality of first active patterns extending along a third direction and arranged in sequence along the first direction, the first active pattern including the first active portion, the second active portion and the third active portion; an angle formed by the first active pattern and the gate line toward the first end is an acute angle; The second active group includes: a plurality of second active patterns extending along a fourth direction and arranged sequentially along the first direction, the second active pattern includes the first active portion, the second active portion and the third active portion; an angle formed by the second active pattern and the gate line toward the first end is an obtuse angle.

31. The array substrate according to any one of claims 22-29, wherein, The gate line extends from the first end to the second end along the first direction; The first active portion, the second active portion, and the third active portion all extend along the second direction, and an angle formed with the gate line toward the first end is a right angle.

32. The array substrate according to any one of claims 2-29, wherein, The gate line extends from the first end to the second end along the first direction; The first active portion and the second active portion both extend along the second direction, and an extension line of the first active portion does not overlap with an extension line of the third active portion; an angle formed by at least part of the third active portion and the gate line toward the first end is an acute angle.

33. The array substrate according to claim 25, wherein, The first active portion, the second active portion, and the third active portion all extend along the first direction, and there is a gap between the orthographic projection of the first active layer on the substrate and the orthographic projection of the gate line on the substrate; The gate structure includes: an auxiliary gate located on the side of the first active layer away from the substrate, the auxiliary gate extends along the second direction, and its orthographic projection on the substrate covers the orthographic projection of the third active portion on the substrate, and covers part of the orthographic projection of the gate line on the substrate.

34. The array substrate according to claim 33, wherein, The first gate layer is located on the side of the first active layer facing the substrate; the gate line further includes a gate line branch extending along the second direction; the auxiliary gate covers the projection of the gate line branch on the substrate in the projection of the substrate.

35. The array substrate according to any one of claims 26-34, wherein, The material of the auxiliary gate includes: indium tin oxide, indium-doped zinc oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, or indium-doped cadmium oxide.

36. The array substrate according to any one of claims 25-33, wherein, The data line includes: a first data portion, a second data portion extending along the second direction and arranged alternately along the second direction, and a third data portion connecting the first data portion and the second data portion and extending along the first direction, wherein the extension line of the first data portion does not coincide with the extension line of the second data portion.

37. The array substrate according to any one of claims 25-36, wherein, The array substrate further includes: a common electrode located on the side of the first electrode facing away from the substrate; The common electrode includes: a first common electrode portion extending along the first direction, and a second common electrode portion extending along the second direction; the projection of the first common electrode portion on the substrate covers the projection of the gate line on the substrate, and the projection of the second common electrode portion on the substrate covers the projection of the data line on the substrate; The projection of the first via on the substrate is located within the projection of the region formed by the intersection of the first common electrode portion and the second common electrode portion on the substrate.

38. A display panel, wherein, Comprising the array substrate according to any one of claims 1-37.

39. A display device, wherein, Comprising the display panel according to claim 38.

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