IGBT (Insulated Gate Bipolar Translator) safe straight-through detection protection method and system

Abstract

The invention discloses an IGBT safe straight-through detection protection method and system, and relates to the field of transistor detection, and the protection method comprises the steps: obtaining the defect information of a transistor based on a quantum sensor, judging the electric field disturbance state generated in the straight-through detection process of the transistor according to the defect information, and predicting the feasibility of the straight-through detection of the transistor; adjusting the start-stop state of transistor through detection according to the feasibility, and evaluating the accuracy of transistor through detection based on the adjustment result and the temperature and stress change of the transistor captured by the optical fiber sensor; and generating a transistor temperature and stress adaptive adjustment scheme according to the accuracy evaluation result, and taking the adaptive adjustment scheme as a straight-through detection protection strategy to protect the transistor straight-through detection process. According to the method, the detection starting and stopping time is automatically adjusted when the feasibility is insufficient, straight-through detection is prevented from being carried out in an unstable and high-risk state, and therefore it is ensured that the detection has higher reliability and execution success rate.

Description

Technical Field

[0001] The present invention relates to the field of transistor detection, and in particular to an IGBT safe through-detection protection method and system. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is an insulated gate bipolar transistor, a composite fully controlled voltage-driven power semiconductor device composed of BJT (bipolar junction transistor) and MOS (insulated gate field effect transistor). It has the advantages of both the high input impedance of MOSFET and the low on-state voltage drop of GTR. IGBT module is a modular semiconductor product composed of IGBT (insulated gate bipolar transistor chip) and FWD (diode chip) packaged through a specific circuit bridge. The packaged IGBT module can be directly used in inverters, UPS uninterruptible power supplies and other equipment.

[0003] IGBT shoot-through detection refers to a method in power electronics applications that intentionally puts the IGBT in a marginal operating state for a short period of time where the upper and lower bridge arms may shoot through (short circuit) in order to verify the health status of the IGBT device or judge its reliability, and detects whether its performance meets the standard requirements by capturing its electrical response characteristics.

[0004] However, during the detection process, the IGBT through-test method in the existing technology cannot determine the feasibility of the through-test based on the workload of the IGBT itself, which makes it easy to force the through-test when the defect is aggravated, causing the IGBT to burn out or fail during the detection process, increasing the testing cost.

[0005] Currently, no effective solutions have been proposed for the problems in related technologies. Summary of the Invention

[0006] In response to the problems in the related art, the present invention proposes an IGBT safe through-detection protection method and system to overcome the above technical problems existing in the existing related art.

[0007] To this end, the specific technical solutions adopted in the present invention are as follows:

[0008] In a first aspect, the present invention provides an IGBT safety through-detection protection method, the protection method comprising:

[0009] The quantum sensor is used to obtain transistor defect information, and the electric field disturbance state generated by the transistor during the through-test process is determined based on the defect information, thereby predicting the feasibility of the through-test of the transistor.

[0010] Adjust the start and stop states of transistor through-test based on feasibility, and evaluate the accuracy of transistor through-test based on the adjustment results and the temperature and stress changes of the transistor captured by the optical fiber sensor;

[0011] An adaptive adjustment scheme for transistor temperature and stress is generated based on the accuracy evaluation results, and the adaptive adjustment scheme is used as a through-detection protection strategy to protect the transistor through-detection process.

[0012] Preferably, the defect information of the transistor is obtained based on the quantum sensor, and the electric field disturbance state generated by the transistor during the through-test process is determined based on the defect information. The feasibility of predicting the through-test of the transistor includes:

[0013] The quantum sensor signal is calibrated based on the quantum sensor calibration rules, the color scattering spectrum data corresponding to the transistor is detected, and the surface scanning image of the transistor is obtained by combining with a transmission electron microscope;

[0014] Multivariate scattering correction technology is used to perform discriminant analysis on the color scattered light spectrum data to obtain the state of metal impurities in the transistor, and the surface scanning image is reconstructed to extract the lattice dislocation state of the transistor;

[0015] Analyze the correlation between electric field perturbations and the states of metal impurities and lattice dislocations, and build a combined prediction model using a cross-cutting algorithm to determine the perturbation trend generated by transistors during through-testing.

[0016] Predict the gate voltage change and emitter voltage change values ​​caused by the shoot-through test process based on the disturbance trend, analyze the electric field distortion state based on the change values, and compare the difference between the electric field distortion state and the electric field state under the standard state;

[0017] If the electric field distortion state is less than or equal to the standard state, it indicates that the transistor through-test can be performed. If the electric field distortion state is greater than the standard state, it indicates that the transistor through-test cannot be performed.

[0018] Preferably, using a multivariate scattering correction technique to perform discriminant analysis on the color scattered light spectrum data to obtain the metal impurity state in the transistor, and reconstructing a surface scanning image to extract the lattice dislocation state of the transistor includes:

[0019] Perform difference centering and standard deviation scaling on the color scattered light spectrum data, and combine it with the ideal spectrum of the transistor to analyze the presence of metal impurities in the transistor;

[0020] According to the analysis results, linear regression processing is performed on the color scattered light spectrum data and the ideal spectrum of the transistor to obtain the regression coefficient and slope, correct the baseline offset of the color scattered light spectrum data, and generate a change curve of the color scattered light spectrum data;

[0021] The change curvature of the metal impurities is analyzed based on the tangent slope of any spectral data point on the change curve, and the morphological curve of the metal impurities in the transistor is determined according to the change curvature to obtain the state of the metal impurities;

[0022] The surface scanning image is reconstructed based on the resolution generative adversarial network model, and the defect feature values ​​of the surface scanning image are extracted by combining the kernel principal component method to identify the lattice dislocation state of the transistor.

[0023] Preferably, reconstructing the surface scanning image according to the resolution generative adversarial network model and extracting the defect characteristic value of the surface scanning image in combination with the kernel principal component method to identify the lattice dislocation state of the transistor includes:

[0024] Scan each pixel point corresponding to the surface scanning image based on the scanning order principle, and perform difference processing on the pixel points according to the scanning results to obtain a surface scanning image completed with difference processing;

[0025] The surface scan image is reconstructed using a super-resolution generative adversarial network, and a reconstruction range function is defined to verify the reconstruction performance of the surface scan image and determine the reconstruction quality.

[0026] The lattice position difference between the reconstructed surface scanning image and the transistor standard image is extracted using kernel principal components to construct a feature data set, which is then partitioned to obtain the lattice change feature vector of the surface scanning image.

[0027] Orthogonal processing is performed on the lattice change characteristic vector to output the defect characteristic value of the surface scanning imaging image, and the defect characteristic value is used as the lattice dislocation state result of the transistor.

[0028] Preferably, the expression of the reconstruction range function is:

[0029]

[0030] Where R represents the reconstruction range, (A HB ) x,y,z Represents the RGB value of the surface scan image at the pixel coordinate x, y, z position after differential processing, C a Indicates the width of the surface scan image, D a Indicates the height of the surface scan image, (A LB ) x,y,z Represents the RGB value of the original image surface scanned image at the pixel coordinate x, y, z position, represents the probability of all training samples on the nth image channel discriminator G in the generative adversarial network, Represents the RGB value of the reconstructed surface scan image at the pixel coordinate x, y, z position, and N represents the number of image channels.

[0031] Preferably, analyzing the correlation between the electric field disturbance and the metal impurity state and the lattice dislocation state, and building a combined prediction model in combination with the vertical and horizontal cross algorithm to determine the disturbance trend generated by the transistor during the through-test process includes:

[0032] Perform data alignment processing on the electric field disturbance, metal impurity state, and lattice dislocation state, analyze the corresponding correlations using mutual information technology, and extract the metal impurity state and lattice dislocation state with the greatest correlation as the correlated state set;

[0033] The metal impurity state and the lattice dislocation state are transformed, and a penalty factor is introduced to convert the solution process of the electric field perturbation effect into an unconstrained variational process to generate several components;

[0034] The parameter state of the recurrent neural network is optimized by using two updating methods: horizontal cross and vertical cross, and the optimized recurrent neural network is used as a combined prediction model;

[0035] The relevant state sets of each component are superimposed and input into the combined prediction model. The electric field disturbance state is analyzed based on the model output results, and the disturbance trend generated by the transistor during the through-detection process is analyzed in combination with the electric field disturbance state.

[0036] Preferably, adjusting the start and stop states of the transistor through detection according to feasibility, and evaluating the accuracy of the transistor through detection based on the adjustment result and the temperature and stress changes of the transistor captured by the optical fiber sensor include:

[0037] When the feasibility results indicate that the transistor through-test can be performed, the transistor through-test is initiated and a fiber optic sensor is installed on the transistor surface to capture the instantaneous temperature rise and thermal stress data during the transistor through-test process;

[0038] Align the instantaneous temperature rise data and thermal stress data with the start and stop timestamps of the transistor through-test, and evaluate the current conduction characteristics and cracks of the transistor during the through-test based on the alignment results.

[0039] According to the current conduction characteristics and crack status, the strength changes and distortion of the detection signal characteristics during the through-test process are analyzed, and the accuracy of the through-test is evaluated based on the strength changes and distortion.

[0040] Preferably, aligning the instantaneous temperature rise data and the thermal stress data with the start and stop timestamps of the transistor through-test respectively, and evaluating the current conduction characteristics and cracks corresponding to the transistor during the through-test process according to the alignment results includes:

[0041] Create an event identifier for the through-test process based on the transistor through-test start and stop timestamps, define a unified time base based on the event identifier, and use the unified time base to align the transistor through-test start and stop timestamps with the instantaneous temperature rise data and thermal stress data respectively.

[0042] The root mean square and linear kurtosis indices of the instantaneous temperature rise data and thermal stress data were determined respectively, a two-dimensional performance index sequence was constructed, and a through-test benchmark model was constructed in combination with kernel density estimation to quantify the differences;

[0043] Based on the difference results, the current conduction capability of the transistor is inferred, and the changing trend of the output results of the through-detection benchmark model is determined to obtain the mutation characteristics of the transistor and output the crack assessment results.

[0044] Preferably, the root mean square and linear kurtosis indexes of the instantaneous temperature rise data and the thermal stress data are determined respectively, a two-dimensional performance index sequence is constructed, and a through-test benchmark model is constructed in combination with kernel density estimation to quantify the differences, including:

[0045] The instantaneous temperature rise data and thermal stress data are respectively used as random variable sequences, and the random variable sequences are arranged according to size to obtain an order sequence, and linear moments are generated to determine the linear taper index corresponding to the instantaneous temperature rise data and thermal stress data;

[0046] The root mean square of the instantaneous temperature rise data and thermal stress data is obtained, and the root mean square is combined with the linear taper index to generate a two-dimensional performance index sequence. Based on the two-dimensional performance index sequence, a direct detection benchmark model is constructed using kernel density.

[0047] The baseline values ​​of instantaneous temperature rise and thermal stress data output by the through-detection benchmark model are used, and the quantitative differences between the output results of the through-detection benchmark model and the state standards are analyzed based on the distance measurement technology.

[0048] In a second aspect, the present invention further proposes an IGBT safe through-detection protection system, which includes:

[0049] A feasibility detection module is used to obtain transistor defect information based on quantum sensors, and to determine the electric field disturbance state generated by the transistor during the through-test process based on the defect information, thereby predicting the feasibility of the transistor through-test.

[0050] An accuracy detection module is used to adjust the start and stop states of the transistor through-test according to feasibility, and evaluate the accuracy of the transistor through-test based on the adjustment results and the temperature and stress changes of the transistor captured by the optical fiber sensor;

[0051] The protection strategy generation module is used to generate a transistor temperature and stress adaptive adjustment plan based on the accuracy evaluation result, and use the adaptive adjustment plan as a through-detection protection strategy to protect the transistor through-detection process.

[0052] The beneficial effects of the present invention are:

[0053] 1. The present invention uses quantum sensors to capture the internal defect information of transistors with high sensitivity, and based on the analysis of the electric field disturbance state caused by the defects, dynamically determines whether the through-test is suitable for execution under the current environment. When feasibility is insufficient, it automatically adjusts the detection start and stop time to avoid through-testing under unstable and high-risk conditions, thereby ensuring that the detection itself has higher reliability and execution success rate. At the same time, based on the temperature and stress data captured during the detection, it accurately evaluates whether the through-test process truly reflects the health status of the transistor, and generates an adaptive adjustment plan for the current transistor state, so that subsequent through-tests can automatically adapt to the actual health status of the transistor, minimize the additional burden on the transistor, and extend the device life.

[0054] 2. The present invention provides high-resolution information on tiny defects inside transistors based on color scattered line spectrum data and surface scanning imaging images, and can accurately detect potential failure risks at an early stage that traditional detection methods cannot perceive. At the same time, through correlation analysis of electric field disturbances with metal impurities and lattice dislocations, and the use of vertical and horizontal cross-calculus algorithms to establish a combined prediction model, the purpose of quantitatively predicting the changing trend of the electric field stability of transistors in direct-through detection is achieved, and the electric field distortion state is inferred based on this, and then a difference analysis is performed with the standard state, thereby achieving a quantitative assessment of the electric field stability, avoiding forced testing of transistors in a state of exacerbated defects, and effectively reducing the probability of device burnout and failure, thereby achieving a quantitative assessment of the electric field stability, which not only improves the early warning capability of the defect evolution process, but also effectively avoids forced testing of transistors in a state of exacerbated defects, greatly reducing the risk of device burnout, thermal breakdown, etc. caused by electric field anomalies, and thus provides a scientific basis for the formulation of subsequent electrical safety strategies such as insulation reinforcement, grounding protection, and leakage protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0056] Figure 1 This is a flow chart of an IGBT safety shoot-through detection and protection method according to an embodiment of the present invention;

[0057] Figure 2 The figure is a principle block diagram of an IGBT safety shoot-through detection and protection system according to an embodiment of the present invention.

[0058] In the picture:

[0059] 1. Feasibility detection module; 2. Accuracy detection module; 3. Protection strategy generation module. DETAILED DESCRIPTION

[0060] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention. They are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. By referring to these contents, ordinary technicians in this field should be able to understand other possible implementation methods and the advantages of the present invention.

[0061] According to an embodiment of the present invention, a method and system for detecting and protecting an IGBT safety shoot-through are provided.

[0062] The present invention will now be further described with reference to the accompanying drawings and specific embodiments. Figure 1 As shown, according to the IGBT safe through-detection protection method of an embodiment of the present invention, the protection method includes:

[0063] Step S1: obtaining defect information of the transistor based on the quantum sensor, and judging the electric field disturbance state generated by the transistor during the through-test process according to the defect information, and predicting the feasibility of the through-test of the transistor.

[0064] In one embodiment, defect information of a transistor is obtained based on a quantum sensor, and the electric field disturbance state generated by the transistor during a through-test is determined based on the defect information. Predicting the feasibility of the through-test of the transistor includes:

[0065] The quantum sensor signal is calibrated based on the quantum sensor calibration rules, the color scattering spectrum data corresponding to the transistor is detected, and the surface scanning image of the transistor is obtained by combining with a transmission electron microscope;

[0066] Multivariate scattering correction technology is used to perform discriminant analysis on the color scattered light spectrum data to obtain the state of metal impurities in the transistor, and the surface scanning image is reconstructed to extract the lattice dislocation state of the transistor;

[0067] Analyze the correlation between electric field perturbations and the states of metal impurities and lattice dislocations, and build a combined prediction model using a cross-cutting algorithm to determine the perturbation trend generated by transistors during through-testing.

[0068] Predict the gate voltage change and emitter voltage change values ​​caused by the shoot-through test process based on the disturbance trend, analyze the electric field distortion state based on the change values, and compare the difference between the electric field distortion state and the electric field state under the standard state;

[0069] If the electric field distortion state is less than or equal to the standard state, it indicates that the transistor through-test can be performed. If the electric field distortion state is greater than the standard state, it indicates that the transistor through-test cannot be performed.

[0070] Based on the above steps, high-resolution information is provided for tiny defects inside the transistor according to the color scattered line spectrum data and surface scanning imaging, and the correlation analysis between the electric field disturbance and metal impurities and lattice dislocations is judged. Based on this, the electric field distortion state is inferred, and then the difference analysis is performed with the standard state, realizing the quantitative evaluation of the electric field stability, avoiding forced testing of the transistor when the defect is aggravated, thereby effectively reducing the probability of device burnout and failure.

[0071] Specifically, in the process of using multivariate scattering correction technology to perform discriminant analysis on color scattered light spectrum data, obtain the state of metal impurities in the transistor, and reconstruct the surface scanning image to extract the lattice dislocation state of the transistor, the color scattered light spectrum data can be difference-centered and standard-deviation-scaled, and combined with the ideal spectrum of the transistor to analyze the presence of metal impurities in the transistor; according to the analysis results, linear regression processing is performed on the color scattered light spectrum data and the ideal spectrum of the transistor to obtain the regression coefficient and slope, correct the baseline offset of the color scattered light spectrum data, and generate a change curve of the color scattered light spectrum data; based on the tangent slope of any spectral data point on the change curve, the change curvature of the metal impurities is analyzed, and the morphological curve of the metal impurities in the transistor is discriminated according to the change curvature to obtain the state of the metal impurities; according to the resolution generative adversarial network model, the surface scanning image is reconstructed, and the defect characteristic values ​​of the surface scanning image are extracted in combination with the kernel principal component method to identify the lattice dislocation state of the transistor.

[0072] Among them, in the process of reconstructing the surface scanning image according to the resolution generative adversarial network model, and extracting the defect characteristic value of the surface scanning image in combination with the kernel principal component method to identify the lattice dislocation state of the transistor, each pixel point corresponding to the surface scanning image can be scanned based on the scanning order principle, and the pixel points can be difference processed according to the scanning results to obtain the surface scanning image after the difference processing; the surface scanning image is reconstructed using the super-resolution generative adversarial network, and the reconstruction range function is defined to verify the reconstruction performance of the surface scanning image and determine the reconstruction quality; the kernel principal component is used to extract the lattice position difference between the reconstructed surface scanning image and the transistor standard image, and a feature data set is constructed, and the feature data set is divided and processed to obtain the lattice change feature vector of the surface scanning image; the lattice change feature vector is orthogonalized to output the defect characteristic value of the surface scanning image, and the defect characteristic value is used as the lattice dislocation state result of the transistor.

[0073] Among them, the expression of the reconstruction range function is:

[0074]

[0075] Where R represents the reconstruction range, (A HB ) x,y,z Represents the RGB value of the surface scan image at the pixel coordinate x, y, z position after differential processing, C a Indicates the width of the surface scan image, D a Indicates the height of the surface scan image, (A LB ) x,y,z Represents the RGB value of the original image surface scanned image at the pixel coordinate x, y, z position, represents the probability of all training samples on the nth image channel discriminator G in the generative adversarial network, Represents the RGB value of the reconstructed surface scan image at the pixel coordinate x, y, z position, and N represents the number of image channels.

[0076] It should be noted here that the reconstruction range function is composed of content loss and adversarial loss. The setting of the reconstruction range function determines the reconstruction performance of the generative adversarial network. The content loss ensures the processing of high-frequency information in the surface scanned image during the reconstruction process, so that the reconstructed image effect is as close to the visual experience effect as possible. The adversarial loss is set based on the probability of all training samples on the discriminator.

[0077] Specifically, in defining the reconstruction range function to verify the reconstruction performance of the surface scan imaging image, the content loss is first calculated in the process of determining the reconstruction quality. LB and the difference processed image A HB The mean square error (MSE) of the weighted current pixel A HB The mean square error is a measure of the pixel-level reconstruction accuracy. The smaller the error, the closer the reconstructed image is to the original image. The brightness area (A HB The error of large values ​​will be amplified, emphasizing the sensitivity of reconstruction quality in high-brightness areas. The errors are averaged to avoid the influence of image size on the results.

[0078] The adversarial loss is to use the output probability G of the discriminator D d , combined with the reconstructed image The channel value of G is used to evaluate the “realism” of the generated image. d Close to 1 (the discriminator thinks the image is real), then lgG d Approaching 0, the contribution is small; if G d Lower, lgG d A negative value may suppress the reconstruction quality score and weight it by the channel value of the reconstructed image. It may be used to emphasize the importance of different channels (such as RGB). The coefficient is 10 -3It is used to balance the magnitude of the two items to prevent the discriminator item from dominating the overall score.

[0079] The small content loss MSE indicates that the reconstructed image is highly consistent with the original image at the pixel level. The adversarial loss approaches 0, indicating that the discriminator believes that the reconstructed image is close to the true distribution. By minimizing R, the pixel-level accuracy and the perceptual quality of the generated image can be optimized simultaneously, avoiding over-smoothing or distortion problems caused by relying on a single indicator.

[0080] It should be explained that in the process of extracting the lattice dislocation state and metal impurity state of the transistor, the global mean is first subtracted from the data of each wavelength point in the original spectral data to eliminate the bias, and the data of each wavelength point is divided by its standard deviation to make different features comparable and facilitate subsequent analysis. The purpose here is to eliminate the amplitude differences and offsets in the original spectral data caused by different acquisition conditions, and at the same time introduce a standard, defect-free ideal spectrum of the transistor, compare the processed spectral data with the ideal spectrum, and identify abnormal signal changes caused by metal impurities.

[0081] Each set of color scattering line spectrum data (sample) is used as the independent variable, and the ideal spectrum is used as the dependent variable for linear regression to obtain the regression coefficient (intercept) and slope (slope). If the slope deviates from 1 and the regression coefficient deviates from 0, it means that there is spectral distortion, which characterizes the distribution and degree of metal impurities. At the same time, the corrected data after regression is used to generate a color scattering line change curve, and the tangent slope of any spectral point on the change curve is calculated. The signal change rate at different wavelengths is observed, and the changing trend of the metal impurity morphology (concentrated, diffuse, locally concentrated, etc.) is judged by the changing curvature. Finally, a metal impurity state description model inside the transistor is obtained.

[0082] During the lattice dislocation state extraction process, pixels are scanned row by row and column by column, the intensity value of each pixel is recorded, and missing or abnormal pixels are interpolated (such as linear interpolation or Lagrangian interpolation) to obtain continuous and complete imaging data. At the same time, a super-resolution generative adversarial network (SR-GAN) is introduced. It takes a low-resolution surface scan image as input and a high-resolution fine image as output. A discriminator is trained to distinguish between true and false reconstructed images, improving the recovery of image detail. The reconstructed high-resolution scan image is compared with a standard transistor image, and the principal component differences between the two in a high-dimensional feature space (after nonlinear mapping) are extracted. The difference results contain microscopic defect information of the lattice dislocation. The difference features are then extracted to form a lattice change feature dataset. The lattice change feature vectors are orthogonalized (such as through the Gram-Schmidt process or PCA) to further eliminate redundant features and retain the main defect information. Finally, the defect feature values ​​of the transistor surface scan image are output and used as the quantification result of the lattice dislocation state.

[0083] Furthermore, by combining multivariate scatter correction technology (MSC), super-resolution generative adversarial network (SR-GAN) and kernel principal component analysis (KPCA), it is possible to accurately extract microscopic defect information including the metal impurity state and lattice dislocation state of the transistor from spectral data and surface scanning images, laying the foundation for the feasibility analysis of subsequent through-detection.

[0084] Among them, in the process of analyzing the correlation between the electric field disturbance and the metal impurity state and the lattice dislocation state, and combining the vertical and horizontal crossover algorithms to construct a combined prediction model to judge the disturbance trend generated by the transistor during the through-detection process, the electric field disturbance and the metal impurity state and the lattice dislocation state can be data aligned, and the corresponding correlation can be analyzed by combining the mutual information technology, and the metal impurity state and the lattice dislocation state with the largest correlation can be extracted as the related state set; the metal impurity state and the lattice dislocation state are transformed, and a penalty factor is introduced to convert the electric field disturbance influence solution process into an unconstrained variational process to generate several components; the parameter state of the recurrent neural network is optimized by using the horizontal crossover and vertical crossover update methods, and the optimized recurrent neural network is used as the combined prediction model; each component is superimposed on the related state set and input into the combined prediction model, the electric field disturbance state is analyzed based on the model output results, and the disturbance trend generated by the transistor during the through-detection process is analyzed in combination with the electric field disturbance state.

[0085] It should be explained that in the process of analyzing the disturbance trend generated by the transistor during the through-test process, the electric field disturbance data, metal impurity state data, and lattice dislocation state data obtained by the test must first be time-stamped, spatially positioned, or sampled in sequence. The purpose is to ensure that different data types can be directly compared and analyzed at the same time and at the same position. At the same time, the mutual information technology (MI) is used to measure the nonlinear correlation between the electric field disturbance and the metal impurity state and the lattice dislocation state, and the metal impurity state and lattice dislocation state with the largest mutual information value are selected to form a set of related states for subsequent analysis.

[0086] At the same time, feature transformations are performed on the metal impurity state and lattice dislocation state, including orthogonal transformation (such as PCA) and nonlinear kernel transformation (such as KPCA), so that the feature space is more suitable for modeling the changing law of electric field perturbations. The influence of electric field perturbations on state variables is modeled as an optimization problem, and by introducing a penalty factor (Penalty Term), the constrained optimization is converted into an unconstrained variational problem (to facilitate subsequent algorithm solutions), thereby generating a series of new state components, each of which describes a certain disturbance influence characteristic.

[0087] By combining the RNN prediction model to model the temporal relationship between electric field disturbances and state variables, and using lateral crossover and vertical crossover, the model can better understand the interaction between different physical quantities at the same time (such as the lateral impact of metal impurity changes on electric field disturbances), strengthen the ability to model the long-range dependency between historical state changes and future disturbance trends, enhance the expressive power and convergence speed of RNN through lateral and vertical crossover, and use the optimized RNN as the final combined prediction model for predictive analysis of electric field disturbance trends.

[0088] The generated state components are combined with the metal impurity state and lattice dislocation state in the relevant state set and input into the combined prediction model. The combined prediction model outputs the current state or future change trend of the electric field disturbance. Based on the predicted electric field disturbance trend, it is determined whether the transistor will produce abnormal changes during the through-test process.

[0089] Furthermore, after the introduction of mutual information and penalty factors, unconstrained optimization greatly reduces the computational complexity and improves the solution speed. Based on the vertical and horizontal cross-technology, horizontal modeling is coupled with time physical quantities, and vertical modeling of historical trend evolution greatly improves the prediction accuracy. Ultimately, it is possible to judge in advance the potential electric field failure risk of transistors during the detection process.

[0090] Step S2, adjusting the start and stop states of the transistor through detection according to feasibility, and evaluating the accuracy of the transistor through detection based on the adjustment result and the temperature and stress changes of the transistor captured by the optical fiber sensor.

[0091] In one embodiment, adjusting the start and stop states of transistor through-detection based on feasibility, and evaluating the accuracy of transistor through-detection based on the adjustment results and the temperature and stress changes of the transistor captured by the optical fiber sensor, includes:

[0092] When the feasibility results indicate that the transistor through-test can be performed, the transistor through-test is initiated and a fiber optic sensor is installed on the transistor surface to capture the instantaneous temperature rise and thermal stress data during the transistor through-test process;

[0093] Align the instantaneous temperature rise data and thermal stress data with the start and stop timestamps of the transistor through-test, and evaluate the current conduction characteristics and cracks of the transistor during the through-test based on the alignment results.

[0094] According to the current conduction characteristics and crack status, the strength changes and distortion of the detection signal characteristics during the through-test process are analyzed, and the accuracy of the through-test is evaluated based on the strength changes and distortion.

[0095] Furthermore, feasibility confirmation is performed before direct-through testing to ensure that testing is started only when the transistor status allows it, avoiding sudden failure, burning or thermal breakdown during testing due to problems such as excessive metal impurities and severe lattice dislocations, reducing testing risks, avoiding device damage, and improving the stability and reliability of the testing system itself. By installing optical fiber sensors on the surface of the transistor, instantaneous temperature rise (temperature change curve) and thermal stress changes (stress distribution curve) are monitored in real time, capturing the physical state at every moment of the testing process, and providing accurate and continuous data basis for subsequent analysis.

[0096] Among them, in the process of aligning the instantaneous temperature rise data and thermal stress data with the start and stop timestamps of the transistor forward detection respectively, and evaluating the current conduction characteristics and cracks corresponding to the transistor during the forward detection process based on the alignment results, an event identifier can be created for the forward detection process based on the start and stop timestamps of the transistor forward detection, and a unified time base can be defined based on the event identifier. The start and stop timestamps of the transistor forward detection are aligned with the instantaneous temperature rise data and thermal stress data respectively using the unified time base; the root mean square and linear kurtosis indicators of the instantaneous temperature rise data and the thermal stress data are judged respectively, a two-dimensional performance indicator sequence is constructed, and the forward detection benchmark model is constructed in combination with kernel density estimation to quantify the difference; the current conduction capability of the transistor is inferred based on the difference results, and the changing trend of the output results of the forward detection benchmark model is judged to obtain the mutation characteristics of the transistor, and the crack assessment results are output.

[0097] Specifically, in the process of respectively judging the root mean square and linear kurtosis index of the instantaneous temperature rise data and the thermal stress data, constructing a two-dimensional performance index sequence, and combining the kernel density estimation to construct the direct detection benchmark model to quantify the difference, the instantaneous temperature rise data and the thermal stress data can be respectively used as random variable sequences, and the random variable sequences can be arranged according to size to obtain an order sequence, and a linear moment can be generated to judge the linear kurtosis index corresponding to the instantaneous temperature rise data and the thermal stress data; the root mean square of the instantaneous temperature rise data and the thermal stress data is obtained, and the root mean square is combined with the linear kurtosis index to generate a two-dimensional performance index sequence, and the direct detection benchmark model is constructed based on the two-dimensional performance index sequence using the kernel density; the direct detection benchmark model is used to output the benchmark values ​​of the instantaneous temperature rise and thermal stress data, and the quantitative difference between the output results of the direct detection benchmark model and the state standard is analyzed based on the distance measurement technology.

[0098] It should be explained that in the process of constructing a through-detection benchmark model to quantify the differences, the key event identifiers (EventIDs) in the detection process can be defined based on the transistor through-detection start and stop timestamps. For example, the detection start is EventStart and the detection stop is EventStop. Each detection cycle corresponds to an independent event number. With the event identifier as the center, a unified time axis benchmark is defined. For example, the start time of each detection is normalized to 0 seconds. All data (temperature rise, stress, detection signal) are time-aligned with this benchmark to eliminate errors caused by different sampling starting points. The purpose is to ensure that different data sources (temperature, stress, current) are in a unified time and space coordinate system during analysis, ensuring the accuracy of subsequent data fusion and comparison.

[0099] The temperature rise data and thermal stress data are aligned with the detection start and stop timestamps according to a unified time base to ensure that at each time point, they can correspond to the specific temperature rise and stress change. The purpose here is to form a standardized temperature-stress-detection action correspondence, laying the foundation for subsequent feature extraction and trend analysis.

[0100] The root mean square (RMS) measures the energy and overall fluctuation of temperature and stress changes. Linear kurtosis measures the sharpness of the data distribution. High kurtosis often indicates a sudden change or anomaly. The RMS and Kurtosis values ​​are calculated for the aligned temperature and stress data within a local time window. These values ​​are combined to form a two-dimensional performance indicator sequence (i.e., an RMS-Kurtosis pair is present at each moment). This two-dimensional performance indicator sequence is then modeled using kernel density estimation (KDE). KDE can smoothly estimate the probability density function of the data distribution. A baseline model for direct-conductivity detection is established, representing the probability distribution model of temperature-stress changes under normal conduction conditions. The (RMS-Kurtosis) sequence captured during real-time detection is compared with the baseline model. By calculating the probability density offset and distribution differences, the degree of conduction anomaly and crack initiation are quantified. The temporal trend of the baseline model output is observed. Once a significant sudden change (such as a rapid change in the probability density extreme value) is detected, a conduction sudden change is determined.

[0101] Step S3: generating a transistor temperature and stress adaptive adjustment scheme based on the accuracy evaluation result, and using the adaptive adjustment scheme as a through-detection protection strategy to protect the transistor through-detection process.

[0102] In one embodiment, an adaptive adjustment plan is dynamically formulated based on the characteristics of the current detection data, mainly including: temperature control adjustment, such as low detection current amplitude, reducing instantaneous thermal shock, extending the detection cycle, increasing the cooling time window or adding pulse detection instead of continuous detection to alleviate continuous temperature rise; stress control adjustment, such as reducing external mechanical constraints (such as pressing force), adjusting the detection angle, and avoiding stress-vulnerable areas; dynamic adjustment of detection parameters, such as dynamically adjusting the detection threshold, adjusting the detection strategy according to instantaneous heat / stress changes (such as switching to a flexible detection mode), etc., and then dynamically adapting the detection conditions according to the device status in real time to ensure continued detection while protecting the transistor.

[0103] The generated adaptive adjustment scheme is programmed and solidified into a protection strategy and automatically executed. The protection strategy includes trigger conditions (when accuracy decreases), adjustment measures (such as reducing current and delaying detection) and recovery conditions (the original detection mode can be restored after the temperature and stress return to normal). It realizes dynamic protection during the transistor pass-through detection process, reduces human intervention, and improves the autonomous intelligence level of the detection system.

[0104] Through this dynamic control process, real-time protection of the entire process of transistor pass-through detection is achieved, which effectively reduces dependence on manual intervention and comprehensively improves the level of autonomous intelligence in the detection system. When characteristic signals such as abnormal electric field distribution, current mutation or instantaneous overload are identified during the detection process, electrical protection responses will be automatically triggered, such as current limiting, circuit breaking or switching the system to low power mode, to prevent the risk of electrical fires caused by local charge accumulation or local heating of the device.

[0105] like Figure 2 As shown, according to another embodiment of the present invention, an IGBT safe through-detection protection system is also proposed, and the protection system includes:

[0106] Feasibility detection module 1 is used to obtain transistor defect information based on the quantum sensor, and determine the electric field disturbance state generated by the transistor during the through-test process based on the defect information, and predict the feasibility of the transistor through-test;

[0107] Accuracy detection module 2, used to adjust the start and stop states of the transistor through detection according to feasibility, and evaluate the accuracy of the transistor through detection based on the adjustment results and the temperature and stress changes of the transistor captured by the optical fiber sensor;

[0108] The protection strategy generation module 3 is used to generate a transistor temperature and stress adaptive adjustment scheme based on the accuracy evaluation result, and use the adaptive adjustment scheme as a through-detection protection strategy to protect the transistor through-detection process.

[0109] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An IGBT safe through-detection protection method, characterized in that: The protection methods include: The quantum sensor is used to obtain transistor defect information, and the electric field disturbance state generated by the transistor during the through-test process is determined based on the defect information, thereby predicting the feasibility of the through-test of the transistor. Adjust the start and stop states of transistor through-test based on feasibility, and evaluate the accuracy of transistor through-test based on the adjustment results and the temperature and stress changes of the transistor captured by the optical fiber sensor; An adaptive adjustment scheme for transistor temperature and stress is generated based on the accuracy evaluation results, and the adaptive adjustment scheme is used as a through-detection protection strategy to protect the transistor through-detection process.

2. The IGBT safety through-detection protection method according to claim 1, characterized in that: The method of obtaining transistor defect information based on quantum sensors and determining the electric field disturbance state generated by the transistor during the through-test process based on the defect information, and predicting the feasibility of the transistor through-test includes: The quantum sensor signal is calibrated based on the quantum sensor calibration rules, the color scattering spectrum data corresponding to the transistor is detected, and the surface scanning image of the transistor is obtained by combining with a transmission electron microscope; Multivariate scattering correction technology is used to perform discriminant analysis on the color scattered light spectrum data to obtain the state of metal impurities in the transistor, and the surface scanning image is reconstructed to extract the lattice dislocation state of the transistor; Analyze the correlation between electric field perturbations and the states of metal impurities and lattice dislocations, and build a combined prediction model using a cross-cutting algorithm to determine the perturbation trend generated by transistors during through-testing. Predict the gate voltage change and emitter voltage change values ​​caused by the shoot-through test process based on the disturbance trend, analyze the electric field distortion state based on the change values, and compare the difference between the electric field distortion state and the electric field state under the standard state; If the electric field distortion state is less than or equal to the standard state, it indicates that the transistor through-test can be performed. If the electric field distortion state is greater than the standard state, it indicates that the transistor through-test cannot be performed.

3. The IGBT safety through-detection protection method according to claim 2, characterized in that: The method of using the multivariate scattering correction technology to perform discriminant analysis on the color scattered light spectrum data to obtain the metal impurity state in the transistor and reconstructing the surface scanning image to extract the lattice dislocation state of the transistor includes: Perform difference centering and standard deviation scaling on the color scattered light spectrum data, and combine it with the ideal spectrum of the transistor to analyze the presence of metal impurities in the transistor; According to the analysis results, linear regression processing is performed on the color scattered light spectrum data and the ideal spectrum of the transistor to obtain the regression coefficient and slope, correct the baseline offset of the color scattered light spectrum data, and generate a change curve of the color scattered light spectrum data; The change curvature of the metal impurities is analyzed based on the tangent slope of any spectral data point on the change curve, and the morphological curve of the metal impurities in the transistor is determined according to the change curvature to obtain the state of the metal impurities; The surface scanning image is reconstructed based on the resolution generative adversarial network model, and the defect feature values ​​of the surface scanning image are extracted by combining the kernel principal component method to identify the lattice dislocation state of the transistor.

4. The IGBT safety through-detection protection method according to claim 3, characterized in that: The reconstructing of the surface scanning image according to the resolution generative adversarial network model and extracting the defect characteristic value of the surface scanning image in combination with the kernel principal component method to identify the lattice dislocation state of the transistor includes: Scan each pixel point corresponding to the surface scanning image based on the scanning order principle, and perform difference processing on the pixel points according to the scanning results to obtain a surface scanning image completed with difference processing; The surface scan image is reconstructed using a super-resolution generative adversarial network, and a reconstruction range function is defined to verify the reconstruction performance of the surface scan image and determine the reconstruction quality. The lattice position difference between the reconstructed surface scanning image and the transistor standard image is extracted using kernel principal components to construct a feature data set, which is then partitioned to obtain the lattice change feature vector of the surface scanning image. Orthogonal processing is performed on the lattice change characteristic vector to output the defect characteristic value of the surface scanning imaging image, and the defect characteristic value is used as the lattice dislocation state result of the transistor.

5. The IGBT safe through-detection protection method according to claim 4, characterized in that: The expression of the reconstruction range function is: Where R represents the reconstruction range, (A HB ) x,y,z Represents the RGB value of the surface scan image at the pixel coordinate x, y, z position after differential processing, C a Indicates the width of the surface scan image, D a Indicates the height of the surface scan image, (A LB ) x,y,z Represents the RGB value of the original image surface scanned image at the pixel coordinate x, y, z position, represents the probability of all training samples on the nth image channel discriminator G in the generative adversarial network, Represents the RGB value of the reconstructed surface scan image at the pixel coordinate x, y, z position, and N represents the number of image channels.

6. The IGBT safety through-detection protection method according to claim 5, characterized in that: The analysis of the correlation between the electric field disturbance and the metal impurity state and the lattice dislocation state, and the construction of a combined prediction model in combination with the vertical and horizontal cross algorithm to determine the disturbance trend generated by the transistor during the through-test process includes: Perform data alignment processing on the electric field disturbance, metal impurity state, and lattice dislocation state, analyze the corresponding correlations using mutual information technology, and extract the metal impurity state and lattice dislocation state with the greatest correlation as the correlated state set; The metal impurity state and the lattice dislocation state are transformed, and a penalty factor is introduced to convert the solution process of the electric field perturbation effect into an unconstrained variational process to generate several components; The parameter state of the recurrent neural network is optimized by using two updating methods: horizontal cross and vertical cross, and the optimized recurrent neural network is used as a combined prediction model; The relevant state sets of each component are superimposed and input into the combined prediction model. The electric field disturbance state is analyzed based on the model output results, and the disturbance trend generated by the transistor during the through-detection process is analyzed in combination with the electric field disturbance state.

7. The IGBT safety through-detection protection method according to claim 1, characterized in that: The method of adjusting the start and stop states of the transistor through-detection according to feasibility, and evaluating the accuracy of the transistor through-detection based on the adjustment results and the temperature and stress changes of the transistor captured by the optical fiber sensor, includes: When the feasibility results indicate that the transistor through-test can be performed, the transistor through-test is initiated and a fiber optic sensor is installed on the transistor surface to capture the instantaneous temperature rise and thermal stress data during the transistor through-test process; Align the instantaneous temperature rise data and thermal stress data with the start and stop timestamps of the transistor through-test, and evaluate the current conduction characteristics and cracks of the transistor during the through-test based on the alignment results. According to the current conduction characteristics and crack status, the strength changes and distortion of the detection signal characteristics during the through-test process are analyzed, and the accuracy of the through-test is evaluated based on the strength changes and distortion.

8. The IGBT safe through-detection protection method according to claim 7, characterized in that: The step of aligning the instantaneous temperature rise data and the thermal stress data with the start and stop timestamps of the transistor through-test, and evaluating the current conduction characteristics and cracks of the transistor during the through-test according to the alignment results includes: Create an event identifier for the through-test process based on the transistor through-test start and stop timestamps, define a unified time base based on the event identifier, and use the unified time base to align the transistor through-test start and stop timestamps with the instantaneous temperature rise data and thermal stress data respectively. The root mean square and linear kurtosis indices of the instantaneous temperature rise data and thermal stress data were determined respectively, a two-dimensional performance index sequence was constructed, and a through-test benchmark model was constructed in combination with kernel density estimation to quantify the differences; Based on the difference results, the current conduction capability of the transistor is inferred, and the changing trend of the output results of the through-detection benchmark model is determined to obtain the mutation characteristics of the transistor and output the crack assessment results.

9. The IGBT safe through-detection protection method according to claim 8, characterized in that: The aforementioned methods of determining the root mean square and linear kurtosis indexes of the instantaneous temperature rise data and the thermal stress data, constructing a two-dimensional performance index sequence, and combining the kernel density estimation to construct a through-test benchmark model to quantify the differences include: The instantaneous temperature rise data and thermal stress data are respectively used as random variable sequences, and the random variable sequences are arranged according to size to obtain an order sequence, and a linear moment is generated to determine the linear taper index corresponding to the instantaneous temperature rise data and the thermal stress data; The root mean square of the instantaneous temperature rise data and thermal stress data is obtained, and the root mean square is combined with the linear taper index to generate a two-dimensional performance index sequence. Based on the two-dimensional performance index sequence, a direct detection benchmark model is constructed using kernel density. The baseline values ​​of instantaneous temperature rise and thermal stress data output by the through-detection benchmark model are used, and the quantitative differences between the output results of the through-detection benchmark model and the state standards are analyzed based on the distance measurement technology.

10. An IGBT safety through-detection and protection system, used to implement an IGBT safety through-detection and protection method according to any one of claims 1 to 9, characterized in that: The protection system includes: A feasibility detection module is used to obtain transistor defect information based on quantum sensors, and to determine the electric field disturbance state generated by the transistor during the through-test process based on the defect information, thereby predicting the feasibility of the transistor through-test. An accuracy detection module is used to adjust the start and stop states of the transistor through-test according to feasibility, and evaluate the accuracy of the transistor through-test based on the adjustment results and the temperature and stress changes of the transistor captured by the optical fiber sensor; The protection strategy generation module is used to generate a transistor temperature and stress adaptive adjustment plan based on the accuracy evaluation result, and use the adaptive adjustment plan as a through-detection protection strategy to protect the transistor through-detection process.

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