Test equipment and test method thereof
By introducing a gating component into the test equipment to independently control the unidirectional channel, the problem of low test efficiency of the aging test equipment is solved, and a more efficient aging test is achieved.
Patent Information
- Application Number
- CN202410268579.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-08
- Publication Date
- 2025-09-09
AI Technical Summary
Existing aging test equipment has low test efficiency. Especially in the aging test of semiconductor chips, unidirectional channels cannot be controlled independently, resulting in waste of test resources and reduced efficiency.
The strobe component included in the test equipment is used to independently control the unidirectional channel through the strobe component so that its output signal matches the pin definition and status of the chip under test, including using a tri-state buffer and the strobe component to enable the third sub-test channel.
The expanded use of the unidirectional channel is realized, the test efficiency of the test device is improved, the waste of test resources is avoided, and the effectiveness of the aging test is enhanced.
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Figure CN120610143A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a testing device and a testing method thereof. Background Art
[0002] Burn-in testing is an electrical stress test that uses high voltage and temperature to accelerate electrical failures and screen marginal devices. Burn-in testing can be performed using standard automated test equipment (ATE) or specially designed burn-in testing equipment with voltage and temperature stress capabilities.
[0003] In the related art, when using aging test equipment to test the device to be tested, there is a problem of low test efficiency. Summary of the Invention
[0004] The embodiments of the present disclosure provide a testing device and a testing method thereof.
[0005] In a first aspect, an embodiment of the present disclosure provides a test device, comprising: a test channel module; the test channel module comprises a first test channel and a second test channel; the first test channel comprises a first sub-test channel and a second sub-test channel, the first sub-test channel is a unidirectional channel, and the second sub-test channel is a bidirectional channel; the second test channel comprises a third sub-test channel and a gating component, the third sub-test channel is a unidirectional channel, the input end of the gating component is connected to the third sub-test channel, the output end of the gating component is connected to the chip to be tested, and the gating component is configured to make the signal output by the second test channel match the chip to be tested.
[0006] In an optional embodiment, the gating component is specifically configured to make the signal output by the second test channel match the pin definition of the chip to be tested.
[0007] In an optional embodiment, the second test channel is connected to the DQS pin of the chip to be tested; when the pin of the DQS pin is defined as an input pin, the selection component is in a selection state, and the second test channel outputs a test signal; when the pin of the DQS pin is defined as an output pin, the selection component is in a non-selection state, and the second test channel does not output the test signal.
[0008] In an optional embodiment, the gating component is specifically configured to make the signal output by the second test channel match the state of the chip to be tested; when the chip to be tested is in a non-data reading state, the gating component is in a gating state, and the second test channel outputs a test signal; when the chip to be tested is in a data reading state, the gating component is in a non-gating state, and the second test channel does not output the test signal.
[0009] In an optional embodiment, the selection component includes N tri-state buffers; the third sub-test channel includes a test enable channel and N test control channels; the enable ends of the N tri-state buffers are connected to the test enable channel, and the input ends of the N tri-state buffers are respectively connected to the N test control channels; N is a positive integer not less than 2.
[0010] In an optional embodiment, the output end of each of the N tri-state buffers is connected to a DQS pin of the chip to be tested; when the pin of the DQS pin is defined as an input pin, the selection signal output by the test enable channel indicates selection, and the tri-state buffer outputs the test signal output by the test control channel; when the pin of the DQS pin is defined as an output pin, the selection signal output by the test enable channel indicates non-selection, and the tri-state buffer outputs a high-impedance signal.
[0011] In an optional implementation, the output end of the first sub-test channel is connected to the control pin of the chip under test; the output end of the second sub-test channel is connected to the data output pin of the chip under test.
[0012] In an optional embodiment, the first sub-test channel, the second sub-test channel and the third sub-test channel are configured to output the test signal; and the second sub-test channel is further configured to receive the output signal of the chip under test.
[0013] In an optional embodiment, the chip to be tested includes a three-dimensional memory.
[0014] In an optional embodiment, the gating component is detachably connected to the third sub-test channel.
[0015] In an optional embodiment, the system further includes: a control module;
[0016] The control module is connected to the test channel module and is used to output test instructions to the test channel module.
[0017] In a second aspect, an embodiment of the present disclosure provides a testing method for a testing device, wherein the testing device includes a first test channel and a second test channel, the first test channel includes a first sub-test channel and a second sub-test channel, and the second test channel includes a third sub-test channel and a gating component; the method includes: receiving a test instruction; in response to the test instruction, the first sub-test channel transmits a test signal to the chip to be tested, the second sub-test channel transmits a test signal to the chip to be tested and / or receives an output signal of the chip to be tested, and the gating component makes the signal output by the second test channel match the chip to be tested.
[0018] In an optional embodiment, the gating component enables the signal output by the second test channel to match the chip under test, including: the gating component enables the signal output by the second test channel to match the pin definition of the chip under test.
[0019] In an optional embodiment, the method further includes: determining a selection signal for controlling the selection component based on the pin definition of the DQS pin of the chip to be tested; the selection component enables the signal output by the second test channel to match the pin definition of the chip to be tested, including: when the pin definition of the DQS pin is an input pin, the selection signal indicates selection, and the second test channel outputs a test signal; when the pin definition of the DQS pin is an output pin, the selection signal indicates non-selection, and the second test channel does not output a test signal.
[0020] In an optional embodiment, the method further includes: determining a selection signal for controlling the selection component according to the test state of the chip to be tested; the selection component makes the signal output by the second test channel match the pin definition of the chip to be tested, including: when the chip to be tested is in a non-data read test state, the selection signal indicates selection, and the second test channel outputs a test signal; when the chip to be tested is in a data read test state, the selection signal indicates non-selection, and the second test channel does not output a test signal.
[0021] The embodiment of the present disclosure provides a test device and a test method thereof, wherein the test device includes: a test channel module; the test channel module includes a first test channel and a second test channel; the first test channel includes a first sub-test channel and a second sub-test channel, the first sub-test channel is a unidirectional channel, and the second sub-test channel is a bidirectional channel; the second test channel includes a third sub-test channel and a gating component, the third sub-test channel is a unidirectional channel, the input end of the gating component is connected to the third sub-test channel, the output end of the gating component is connected to the chip to be tested, and the gating component is configured to make the signal output by the second test channel match the chip to be tested. In this way, the unidirectional channel (the third sub-test channel) can be enabled and independently controlled by the gating component, so that the signal output by the unidirectional channel can be matched with the chip to be tested based on the gating component. The present disclosure realizes the expanded use of test channels, expands the application scenarios of unidirectional channels, and thus improves the test efficiency of the test device. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 A schematic structural diagram of a test device provided in an embodiment of the present disclosure;
[0023] Figure 2 A schematic structural diagram of a second test channel provided in an embodiment of the present disclosure;
[0024] Figure 3 A schematic diagram of a gating component provided in an embodiment of the present disclosure;
[0025] Figure 4 A schematic diagram of a tri-state buffer and its truth table provided in an embodiment of the present disclosure;
[0026] Figure 5 A flowchart of a testing method for a testing device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.
[0028] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.
[0029] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.
[0030] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.
[0031] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0032] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0033] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.
[0034] With the rapid development of semiconductor integrated circuits, semiconductor chips are becoming increasingly integrated and their functions are becoming increasingly complex. To ensure proper operation of semiconductor chips during use, they must be tested for timing, electrical properties, integrity, and other aspects using testing equipment after manufacturing to ensure their quality.
[0035] Figure 1 A schematic diagram of the structure of a test device provided in an embodiment of the present disclosure is shown. Figure 2 A schematic diagram of the structure of a second test channel provided in an embodiment of the present disclosure, referring to Figure 1 and Figure 2 The embodiment of the present disclosure provides a test device 100, which includes: a test channel module 110; the test channel module 110 includes a first test channel 111 and a second test channel 112; the first test channel includes a first sub-test channel and a second sub-test channel, the first sub-test channel is a unidirectional channel, and the second sub-test channel is a bidirectional channel;
[0036] The second test channel 112 includes a third sub-test channel 1121 and a gating component 1122. The third sub-test channel 1121 is a unidirectional channel. The input end of the gating component 1122 is connected to the third sub-test channel 1121, and the output end of the gating component 1122 is connected to the chip to be tested. The gating component 1122 is configured to make the signal output by the second test channel match the chip to be tested.
[0037] In the embodiment of the present disclosure, the second test channel includes a third sub-test channel and a gating component. In this way, the enabling of the unidirectional channel (the third sub-test channel) can be independently controlled through the gating component, so that the signal output by the unidirectional channel can be matched with the chip to be tested based on the gating component.
[0038] In the embodiment of the present disclosure, a test device is used to implement the test of the chip under test; here, the test device has multiple test channels (TCh, Tester Channel), each of which is connected to one type of controlled pin among multiple types of controlled pins of multiple chips under test (DUT, Device Under Test).
[0039] In the semiconductor manufacturing process, chip manufacturing has very high process requirements, and the entire process requires numerous tests to ensure the quality of the final product. Among these, the produced chips must undergo product reliability testing to determine the chip's performance, and product burn-in life testing is a very important part of product reliability testing. Common burn-in life testing projects include burn-in testing. Burn-in testing is the process of simulating the various factors involved in real-world use conditions to test the chip under test, and conducting corresponding conditions to strengthen the test. For example, semiconductor chips are easily affected by high temperatures or high voltages during use, which can lead to performance degradation such as data loss, slower read / write speeds, and reduced storage capacity. During the testing process, the chip under test is first connected to a test board. Specifically, the chip under test is then connected to the test channels on the test board. Based on the desired function of the chip under test, voltage and temperature conditions are adjusted to achieve the required test environment. A control module then performs functional testing on the chip under test on the test board to detect defective chips. In some embodiments, the functional tests required for the chip under test during the burn-in test typically include storage capacity testing, read / write speed testing, and data retention testing.
[0040] In some embodiments, multiple types of pins to be controlled include but are not limited to control pins, data output pins, input and output enable pins, input data expectation pins, etc. Specifically, for example, chip select enable (CE) pin, output enable (OE) pin, data queue (DQ) pin, strobe signal (DQS) pin, write enable (WE) pin, read enable (RE) pin, write protect (WP) pin, device busy / idle status (R / B) pin, etc.
[0041] It should be noted that the types of pins in the embodiments of the present disclosure are only used to illustrate the present disclosure and are not intended to limit the scope of the present disclosure.
[0042] In some embodiments, the gating component is specifically configured to make the signal output by the second test channel match the pin definition of the chip under test.
[0043] Here, the pin definition is used to characterize the function or type of the pin. In a specific example, the DQ pin is used as a data output pin, and the pin definition of the DQ pin is a data output pin.
[0044] In some embodiments, the output of the first sub-test channel is connected to a control pin of the chip under test; the output of the second sub-test channel is connected to a data output pin of the chip under test. In a specific example, the output of the first sub-test channel is connected to a CE pin of the chip under test; the output of the second sub-test channel is connected to a DQ pin of the chip under test.
[0045] In some embodiments, the second test channel is connected to the DQS pin of the chip under test;
[0046] When the DQS pin is defined as an input pin, the gating component is in a gating state, and the second test channel outputs a test signal;
[0047] When the DQS pin is defined as an output pin, the gating component is in a non-gating state, and the second test channel does not output the test signal.
[0048] In the embodiment of the present disclosure, when the pin of the DQS pin is defined as an input pin, the selection component is in the selection state, and the test signal output by the third sub-test channel is transmitted to the DQS pin of the chip to be tested; when the pin of the DQS pin is defined as an output pin, the selection component is in the non-selection state, and the test signal output by the third sub-test channel is not transmitted to the DQS pin of the chip to be tested.
[0049] In the embodiments of the present disclosure, the above-mentioned test equipment can be an aging test equipment. The overall scheme of the aging test is to supply power signals and test signals to the device under test, and let the device under test work continuously and uninterruptedly for a set time at high and low temperatures or room temperature, thereby accelerating the failure of the chip under test and screening out good products. The aging test requires the use of a aging test board (BIB, Burn In Board). In some embodiments, the aging test equipment has fewer test channels, generally including 100 drive channels and 72 input / output (I / O) channels. There are usually more than 200 chips under test on a aging test board, so when the number of chips under test is greater than the number of test channels, in order to improve the efficiency of the aging test, multiple chips under test inevitably need to share test channels. Here, each test channel can be connected to one or more pins to be controlled of the same type; and in order to improve the test efficiency, multiple pins to be controlled of the same type are usually connected to one test channel; here, the multiple pins to be controlled of the same type come from multiple chips under test.
[0050] In some embodiments, the first sub-test channel is a driving channel, the second sub-test channel is an I / O channel, and the third sub-test channel is a driving channel.
[0051] For DDR4 or DDR5 memory protocols, the DQS pin is bidirectional. This means it can function as both an input and an output. When used as an input, the memory controller can sample the data signal based on the rising and / or falling edges of the data strobe signal (DQS). The data strobe signal synchronizes data transmission between the memory and the memory controller, facilitating accurate data readout by the memory controller.
[0052] In some embodiments, the driver channel is a unidirectional channel used to output test signals, while the I / O channel is a bidirectional channel that can be used to both receive output signals from the chip under test and output test signals. In one specific example, the driver channel is typically connected to the DQS pin of the chip under test, and the I / O channel is typically connected to the DQ pin of the chip under test. Furthermore, the number of I / O channels in burn-in test equipment is very limited, typically reserved only for the DQ pin.
[0053] Since the test signal output by the driver channel of the aging test equipment cannot be changed after the hardware test plan is determined, that is, the enable of the driver channel cannot be independently controlled, so it cannot stop outputting the test signal. Therefore, when the DQS pin is used as both an input pin and an output pin, if the DQS pin of the chip under test is connected to the driver channel, the normal test of the chip under test may fail due to the mismatch between the pin and the test channel, thereby causing the test to fail. If the DQS pin is connected to the I / O channel to match its pin definition, this will result in a reduction in the resources allocated to the DQ pin of the aging test equipment, and the number of chips under test that the aging test equipment can measure simultaneously will decrease, thereby reducing the efficiency of the aging test.
[0054] In the disclosed embodiment, the DQS pin is connected to the second test channel, and the gating component can be used to independently control the enablement of the unidirectional channel (the third sub-test channel), thereby controlling the output and non-output of its test signal. In other words, the gating component can be used to ensure that the signal output by the unidirectional channel matches the pin definition of the DQS pin of the chip under test.
[0055] In the embodiment of the present disclosure, the third sub-test channel is independently controlled by the selection component, so that when the DQS pin of the chip under test is used as an output pin, there is no input of the test signal of the test equipment, thereby realizing the data output function.
[0056] In some embodiments, the gating component includes N tri-state buffers; the third sub-test channel includes a test enable channel and N test control channels; the enable ends of the N tri-state buffers are connected to the test enable channel, and the input ends of the N tri-state buffers are respectively connected to the N test control channels; N is a positive integer not less than 2.
[0057] Figure 3 A schematic diagram of a gating component provided in an embodiment of the present disclosure, with reference to Figure 3 The selection component includes 8 tri-state buffers, and the third sub-test channel includes a test enable channel CTRL-DP and 8 test control channels DP1-DP8; the enable ends of the 8 tri-state buffers are connected to the test enable channel CTRL-DP, and the input ends of the 8 tri-state buffers are respectively connected to the 8 test control channels DP1-DP8.
[0058] In some embodiments, an output end of each of the N tri-state buffers is connected to a DQS pin of the chip under test;
[0059] When the DQS pin is defined as an input pin, the strobe signal output by the test enable channel indicates strobe, and the tri-state buffer outputs the test signal output by the test control channel;
[0060] When the DQS pin is defined as an output pin, the selection signal output by the test enable channel indicates non-selection, and the tri-state buffer outputs a high-impedance signal.
[0061] Here, the test enable channel and the test control channel may both be driving channels.
[0062] Figure 4 A schematic diagram of a tri-state buffer and its truth table provided in an embodiment of the present disclosure, refer to Figure 4 The tri-state buffer has two input terminals and an output terminal, an enable control terminal and an output terminal. The input terminal of the tri-state buffer is connected to the test control channel, the enable control terminal of the tri-state buffer is connected to the test enable channel, and the output terminal of the tri-state buffer is connected to the DQS pin of the chip under test.
[0063] When the enable control input is high (H), the output of the tri-state buffer outputs a high impedance signal (Z) regardless of the input signal. That is, the tri-state buffer is in a non-selected state at this time. Therefore, the test signal output by the test control channel cannot be output to the DQS pin of the chip under test, so the test signal output by the test control channel will not affect the DQS pin of the chip under test.
[0064] When the enable control input is low (L) and the input is also low (L), the tri-state buffer is in the selected state, and the output of the tri-state buffer outputs the same low level (L) as the input. When the enable control input is low (L) and the input is high (H), the tri-state buffer is in the selected state, and the output of the tri-state buffer outputs the same high level (H) as the input. Even when the enable control input is low (L), the tri-state buffer is in the selected state, so the test signal output by the test control channel is output to the DQS pin of the chip under test through the tri-state buffer.
[0065] By controlling the select signal output by the test enable channel, the tri-state buffer can be controlled to be enabled or disabled. In other words, by controlling the signal input to the enable control terminal of the tri-state buffer, the on / off state between the test control channel and the DQS pin can be controlled. When the select signal input to the enable control terminal is "0," the tri-state buffer is in the enabled state, the test control channel and the DQS pin are in the conductive state, and the test signal output by the test control channel is output to the DQS pin of the chip under test via the tri-state buffer. When the select signal input to the enable control terminal is "1," the tri-state buffer is in the disabled state, outputting a high-impedance signal, thereby disconnecting the test control channel and the DQS pin. The test signal output by the test control channel cannot be output to the DQS pin of the chip under test via the tri-state buffer.
[0066] refer to Figure 3 and Figure 4 The eight tri-state buffers of the gating component are controlled by the gating signals E1 and E2 output by the test enable channel to control their gating / non-gating. When the gating signals E1 and E2 are "1", the tri-state buffers are in the gating state (enabled state), and the test signals output by the test control channel are output to the DQS pin of the chip under test through the tri-state buffers. When the gating signals E1 and E2 are "0", the tri-state buffers are in the non-gating state (standby state), and they output high-impedance signals, so that the test signals output by the test control channel cannot be output to the DQS pin of the chip under test through the tri-state buffers.
[0067] In some embodiments, the gating component is specifically configured to make the signal output by the second test channel match the state of the chip under test;
[0068] When the chip under test is in a non-data reading state, the gating component is in a gating state, and the second test channel outputs a test signal;
[0069] When the chip under test is in a data readout state, the gating component is in a non-gating state, and the second test channel does not output the test signal.
[0070] In the embodiment of the present disclosure, when the chip to be tested is in a non-data reading state, the selection component is in a selection state, and the test signal output by the third sub-test channel is transmitted to the chip to be tested; when the chip to be tested is in a data reading state, the selection component is in a non-selection state, and the test signal output by the third sub-test channel is not transmitted to the chip to be tested.
[0071] When the memory controller reads data from the chip under test (CUT), it sends a read enable (RE) signal to the CUT. Upon receiving the RE signal, the CUT prepares the data signal on the DQ pin and simultaneously generates a data strobe signal on the DQS pin. The memory controller samples the data signal on the DQ pin based on the rising and / or falling edges of the data strobe signal. The data strobe signal synchronizes data transmission between the CUT and the memory controller, facilitating accurate data readout by the memory controller.
[0072] It should be noted here that when the test device directly tests the chip under test, the test device can act as a memory controller and send a read command or a combination sequence including a read command, as well as a read enable signal, to the chip under test. When the test device sends a read command or a combination sequence including a read command, as well as a read enable signal, to the chip under test, the chip under test is in a data readout test state, and the DQS pin serves as an output pin. The test device can obtain the data signal of the chip under test based on the I / O channel connected to the DQ pin. However, when the DQS pin serves as an output pin to output a data selection signal, it is usually not necessary to sample the data signal output by the DQS pin.
[0073] In some embodiments, the strobe signal output by the test enable channel can be triggered by an RE signal. In a specific example, when the test equipment needs to test the data readout performance of the chip under test, the test equipment sends the RE signal to the chip under test. After the RE signal is sent for a preset period of time, the strobe signal output by the test enable channel changes from "1" to "0," thereby placing the tri-state buffer in a non-strobed state and outputting a high-impedance signal. As a result, the second test channel does not output a test signal.
[0074] In some embodiments, the first sub-test channel, the second sub-test channel, and the third sub-test channel are configured to output the test signal; and the second sub-test channel is further configured to receive an output signal of the chip under test.
[0075] In the embodiment of the present disclosure, the first sub-test channel is a driving channel for outputting test signals; the second sub-test channel is an I / O channel, which can be used both to output test signals and to receive output signals of the chip under test; the third sub-test channel is a driving channel for outputting test signals.
[0076] In some embodiments, the chip under test includes a three-dimensional memory.
[0077] Here, the chip under test may include a semiconductor chip or a device including a semiconductor chip. For example, the chip under test may be a memory device, including but not limited to a three-dimensional NAND memory device; for example, the chip under test may be a memory system, such as a solid-state drive (SSD).
[0078] In some embodiments, the gating component is detachably connected to the third sub-test channel.
[0079] In this way, when the DQS pin of the chip under test is used as an input pin, the strobe component can be removed from the test equipment, so that the third sub-test channel is connected to the DQS pin as a normal drive channel. When the DQS pin of the chip under test is used as an output pin, the strobe component can be assembled on the test equipment, so that the third sub-test channel can be used as a drive channel whose enable can be controlled. That is, the output or non-output of the test signal of the third sub-test channel can be controlled by the strobe component.
[0080] refer to Figure 1 ,In some embodiments, the testing device 100 further includes: a control module 120;
[0081] The control module 120 is connected to the test channel module 110 and is configured to output a test instruction to the test channel module 110 .
[0082] In the embodiment of the present disclosure, the control module may be used to provide a test instruction for the test, and the test channel module outputs a test signal based on the test instruction, thereby implementing an aging test based on the test signal.
[0083] The embodiment of the present disclosure provides a test device and a test method thereof, wherein the test device includes: a test channel module; the test channel module includes a first test channel and a second test channel; the first test channel includes a first sub-test channel and a second sub-test channel, the first sub-test channel is a unidirectional channel, and the second sub-test channel is a bidirectional channel; the second test channel includes a third sub-test channel and a gating component, the third sub-test channel is a unidirectional channel, the input end of the gating component is connected to the third sub-test channel, the output end of the gating component is connected to the chip to be tested, and the gating component is configured to make the signal output by the second test channel match the chip to be tested. In this way, the unidirectional channel (the third sub-test channel) can be enabled and independently controlled by the gating component, so that the signal output by the unidirectional channel can be matched with the chip to be tested based on the gating component. The present disclosure realizes the expanded use of test channels, expands the application scenarios of unidirectional channels, and thus improves the test efficiency of the test device.
[0084] Based on the above-mentioned test device, an embodiment of the present disclosure further provides a test method for the test device, wherein the test device includes a first test channel and a second test channel, the first test channel includes a first sub-test channel and a second sub-test channel, and the second test channel includes a third sub-test channel and a gating component; Figure 5 As shown, the test methods include:
[0085] Step 501: receiving a test instruction;
[0086] Step 502: In response to the test instruction, the first sub-test channel transmits a test signal to the chip under test, the second sub-test channel transmits a test signal to the chip under test and / or receives an output signal of the chip under test, and the gating component makes the signal output by the second test channel match the chip under test.
[0087] In some embodiments, in response to the test instruction, the gating component causes the signal output by the second test channel to match the chip under test, including:
[0088] In response to the test instruction, the gating component enables the signal output by the second test channel to match the pin definition of the chip under test.
[0089] In some embodiments, the method further comprises:
[0090] Determining a gating signal for controlling the gating component according to a pin definition of a DQS pin of the chip to be tested;
[0091] In response to the test instruction, the gating component makes the signal output by the second test channel match the pin definition of the chip under test, including:
[0092] When the DQS pin is defined as an input pin, the strobe signal indicates strobe, and the second test channel outputs a test signal;
[0093] When the DQS pin is defined as an output pin, the selection signal indicates non-selection, and the second test channel does not output a test signal.
[0094] Here, the second test channel is connected to the DQS pin of the chip to be tested. When the test device needs to read data from the chip to be tested, the test device sends an RE signal to the chip to be tested, and determines the pin definition of the DQS pin of the chip to be tested as an output pin based on the RE signal, so that the gating signal for controlling the gating component can be determined. In other words, the gating signal for controlling the gating component can be determined based on the RE signal. In a specific example, when the test device needs to read data from the chip to be tested, the test device sends an RE signal to the chip to be tested. After the RE signal is sent for a preset time period, the gating signal input to the gating component changes from "1" to "0", thereby making the gating component in a non-gating state, and it outputs a high-impedance signal, so that the second test channel does not output a test signal.
[0095] In some embodiments, the method further comprises:
[0096] Determining a gating signal for controlling the gating component according to a test state of the chip to be tested;
[0097] In response to the test instruction, the gating component makes the signal output by the second test channel match the pin definition of the chip under test, including:
[0098] When the chip under test is in a non-data readout test state, the strobe signal indicates strobe, and the second test channel outputs a test signal;
[0099] When the chip under test is in a data readout test state, the selection signal indicates non-selection, and the second test channel does not output a test signal.
[0100] Here, the second test channel is connected to the DQS pin of the chip to be tested. When the test equipment needs to test the data readout performance of the chip to be tested, the test equipment sends an RE signal to the chip to be tested, and determines based on the RE signal that the chip to be tested is in a data readout test state, so that the gating signal for controlling the gating component can be determined. In other words, the gating signal for controlling the gating component can be determined based on the RE signal. In a specific example, when the test equipment needs to test the data readout performance of the chip to be tested, the test equipment sends an RE signal to the chip to be tested. After the RE signal is sent for a preset time period, the gating signal input to the gating component changes from "1" to "0", thereby making the gating component in a non-gating state, which outputs a high-impedance signal, so that the second test channel does not output a test signal.
[0101] It should be noted that the description of the test method of the above test device is similar to the description of the above test device and has similar beneficial effects as the test device embodiment. For technical details not disclosed in the test method embodiment of the test device of the present disclosure, please refer to the description of the test device embodiment of the present disclosure for understanding.
[0102] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.
[0103] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.
Claims
1. A testing device, characterized in that: include: Test channel module; The test channel module includes a first test channel and a second test channel; The first test channel includes a first sub-test channel and a second sub-test channel, the first sub-test channel is a unidirectional channel, and the second sub-test channel is a bidirectional channel; The second test channel includes a third sub-test channel and a gating component. The third sub-test channel is a unidirectional channel. The input end of the gating component is connected to the third sub-test channel, and the output end of the gating component is connected to the chip to be tested. The gating component is configured to make the signal output by the second test channel match the chip to be tested.
2. The testing device according to claim 1, characterized in that The gating component is specifically configured to make the signal output by the second test channel match the pin definition of the chip to be tested.
3. The testing device according to claim 2, characterized in that The second test channel is connected to the DQS pin of the chip to be tested; When the DQS pin is defined as an input pin, the gating component is in a gating state, and the second test channel outputs a test signal; When the DQS pin is defined as an output pin, the gating component is in a non-gating state, and the second test channel does not output the test signal.
4. The testing device according to claim 1, wherein: The gating component is specifically configured to make the signal output by the second test channel match the state of the chip to be tested; When the chip under test is in a non-data reading state, the gating component is in a gating state, and the second test channel outputs a test signal; When the chip under test is in a data readout state, the gating component is in a non-gating state, and the second test channel does not output the test signal.
5. The testing device according to claim 1, characterized in that The gating component includes N tri-state buffers; the third sub-test channel includes a test enable channel and N test control channels; the enable terminals of the N tri-state buffers are connected to the test enable channels, and the input terminals of the N tri-state buffers are respectively connected to the N test control channels; N is a positive integer not less than 2.
6. The testing device according to claim 5, characterized in that An output end of each of the N tri-state buffers is connected to a DQS pin of the chip to be tested; When the DQS pin is defined as an input pin, the strobe signal output by the test enable channel indicates strobe, and the tri-state buffer outputs the test signal output by the test control channel; When the DQS pin is defined as an output pin, the selection signal output by the test enable channel indicates non-selection, and the tri-state buffer outputs a high-impedance signal.
7. The testing device according to claim 1, characterized in that The output end of the first sub-test channel is connected to the control pin of the chip under test; the output end of the second sub-test channel is connected to the data output pin of the chip under test.
8. The testing device according to claim 1, wherein: The first sub-test channel, the second sub-test channel, and the third sub-test channel are configured to output the test signal; the second sub-test channel is further configured to receive the output signal of the chip under test.
9. The testing device according to claim 1, characterized in that The chip to be tested includes a three-dimensional memory.
10. The testing device according to claim 1, wherein: The gating component is detachably connected to the third sub-test channel.
11. The testing device according to claim 1, wherein: Also includes: Control module; The control module is connected to the test channel module and is used to output test instructions to the test channel module.
12. A testing method for a testing device, characterized in that: The test device includes a first test channel and a second test channel, the first test channel includes a first sub-test channel and a second sub-test channel, and the second test channel includes a third sub-test channel and a gating component; the method includes: Receive test instructions; In response to the test instruction, the first sub-test channel transmits the test signal to the chip under test, the second sub-test channel transmits the test signal to the chip under test and / or receives the output signal of the chip under test, and the selection component makes the signal output by the second test channel match the chip under test.
13. The method according to claim 12, characterized in that The gating component enables the signal output by the second test channel to match the chip under test, including: The gating component enables the signal output by the second test channel to match the pin definition of the chip to be tested.
14. The method according to claim 13, characterized in that The method further comprises: Determining a gating signal for controlling the gating component according to a pin definition of a DQS pin of the chip to be tested; The gating component makes the signal output by the second test channel match the pin definition of the chip under test, including: When the DQS pin is defined as an input pin, the strobe signal indicates strobe, and the second test channel outputs a test signal; When the DQS pin is defined as an output pin, the selection signal indicates non-selection, and the second test channel does not output a test signal.
15. The method according to claim 12, characterized in that The method further comprises: Determining a gating signal for controlling the gating component according to a test state of the chip to be tested; The gating component makes the signal output by the second test channel match the pin definition of the chip under test, including: When the chip under test is in a non-data readout test state, the strobe signal indicates strobe, and the second test channel outputs a test signal; When the chip under test is in a data readout test state, the selection signal indicates non-selection, and the second test channel does not output a test signal.