Storage and calculation integrated chip

Abstract

The invention discloses a storage and calculation integrated chip which comprises a logic core particle and at least one storage core particle. The logic core grain includes a computing unit. The at least one storage core particle is stacked with the logic core particle, the storage core particle comprises a storage unit, one of the logic core particle and the at least one storage core particle further comprises a first power supply network, the other of the logic core particle and the at least one storage core particle further comprises a second power supply network, and the second power supply network and the first power supply network are vertically interconnected through a first interconnection structure; the first power supply network is configured to transfer power of an external power source to the first interconnection structure and the second power supply network, the second power supply network is configured to transfer power to the storage unit and / or the computing unit, the first interconnection structure is configured to transfer power to the second power supply network and a target unit, and the target unit is the storage unit or the computing unit. The invention provides a scheme for enhancing the power supply performance of the storage unit and / or the computing unit.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a storage and computing integrated chip. Background Art

[0002] With the rapid development of semiconductor technology, chip manufacturing processes are constantly moving towards finer scales. For example, storage chips and logic chips are integrated into storage and computing integrated chips through three-dimensional stacking. Traditional packaging technology can no longer meet the power supply performance requirements of storage and computing integrated chips.

[0003] In the related art, power is supplied to logic chips and storage chips through a packaging substrate. Due to the unreasonable design of the power supply network, the power supply performance of the storage and computing integrated chip is poor. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a storage and computing integrated chip that overcomes the above problems or at least partially solves the above problems.

[0005] A first aspect of the present invention provides a storage and computing integrated chip, comprising:

[0006] Logic core particles, including computing units;

[0007] at least one memory chip, stacked with the logic chip, the memory chip including a memory unit;

[0008] Among them, one of the logic core and the at least one storage core also includes a first power supply network, and the other also includes a second power supply network, the second power supply network and the first power supply network are vertically interconnected through a first interconnection structure, the first power supply network is configured to transmit power from an external power supply to the first interconnection structure and the second power supply network, the second power supply network is configured to transmit the power to the storage unit and / or the computing unit, the first interconnection structure is configured to transmit the power to the second power supply network and the target unit, and the target unit is the storage unit or the computing unit.

[0009] Optionally, the at least one storage core comprises:

[0010] A first storage chip, comprising a first storage unit;

[0011] A second storage core, disposed between the first storage core and the logic core, comprising a second storage unit;

[0012] The second power supply network is provided in the first memory core, in the second memory core, and between the first memory core and the second memory core.

[0013] Optionally, the second power supply network includes: a first power supply layer, a second power supply layer and a second interconnection structure;

[0014] The first power supply layer is provided on the first storage core and is electrically connected to the first storage unit; the second power supply layer is provided on the second storage core and is electrically connected to the second storage unit; the second interconnect structure includes a hybrid bonding structure provided between the first storage core and the second storage core and a first through-silicon via penetrating the second storage core, the first power supply layer is electrically connected to the second power supply layer and the second storage unit through the hybrid bonding structure and the first through-silicon via, and the second power supply layer is electrically connected to the computing unit through the first through-silicon via and the first interconnect structure;

[0015] The first power supply network includes: a third power supply layer, which is provided in the logic core, electrically connected to the computing unit, and electrically connected to the second power supply layer through the first interconnection structure.

[0016] Optionally, the at least one storage core comprises:

[0017] A first storage chip, comprising a first storage unit;

[0018] A second storage core, disposed between the first storage core and the logic core, comprising a second storage unit;

[0019] The first power supply network is provided in the first memory core, in the second memory core, and between the first memory core and the second memory core.

[0020] Optionally, the first power supply network includes: a first power supply layer, a second power supply layer and a second interconnection structure;

[0021] The first power supply layer is provided on the logic core and is electrically connected to the computing unit; the second power supply layer is provided on the second storage core and is electrically connected to the second storage unit; the second interconnect structure includes a hybrid bonding structure provided between the logic core and the second storage core and a first through-silicon via penetrating the second storage core, the first power supply layer is electrically connected to the second power supply layer and the second storage unit through the hybrid bonding structure and the first through-silicon via, and the second power supply layer is electrically connected to the first storage unit through the first through-silicon via and the first interconnect structure;

[0022] The second power supply network includes: a third power supply layer, which is provided on the first memory core and is electrically connected to the second power supply layer through the first interconnection structure.

[0023] Optionally, the first memory core comprises: a first crystal back and a first crystal face arranged opposite to each other;

[0024] The second memory core comprises: a second crystal back and a second crystal face disposed opposite to each other, wherein the second crystal back is closer to the first crystal face than the second crystal face;

[0025] The logic core comprises: a third crystal back and a third crystal plane arranged opposite to each other, wherein the third crystal plane is closer to the second crystal plane than the third crystal back, or the third crystal back is closer to the second crystal plane than the third crystal plane;

[0026] The storage and computing integrated chip further includes: a packaging substrate, the third back surface or third surface of the logic core is arranged close to the packaging substrate, or the first back surface or first surface of the first storage core is arranged close to the packaging substrate.

[0027] Optionally, the third backside of the logic core is disposed close to the package substrate, or the first backside of the first memory core is disposed close to the package substrate, and the storage-computing integrated chip further includes:

[0028] a third interconnect structure comprising a second through-silicon via and a bump, wherein the second through-silicon via extends from the third backside to the third crystal plane, or the second through-silicon via extends from the first crystal plane to the first backside, and the first power supply network is connected to the bump through the second through-silicon via;

[0029] The packaging substrate is provided with the external power supply, and the external power supply is electrically connected to the first power supply network through the bump and the second through-silicon via.

[0030] Optionally, the third crystal face of the logic core is disposed close to the packaging substrate, or the first crystal face of the first memory core is disposed close to the packaging substrate, and the storage-computing integrated chip further includes:

[0031] bumps;

[0032] The packaging substrate is provided with the external power supply, and the external power supply is electrically connected to the first power supply network through the bump.

[0033] Optionally, in a direction perpendicular to the logic chip, the thickness of the first memory chip is greater than the thickness of the second memory chip.

[0034] Optionally, the at least one storage core comprises:

[0035] The first memory chip includes a first memory unit and the second power supply network, and has a first back surface and a first front surface that are oppositely arranged;

[0036] The logic core comprises the first power supply network and a third backside and a third surface that are arranged opposite to each other, wherein the third backside is closer to the first surface than the third surface;

[0037] The storage and computing integrated chip further includes: a bump and a packaging substrate, the packaging substrate is provided with the external power supply, and the external power supply is electrically connected to the first power supply network through the bump.

[0038] The technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0039] The storage and computing integrated chip of the present invention includes a logic core and at least one storage core. The logic core includes a computing unit. At least one storage core is stacked with the logic core, and the storage core includes a storage unit. Among them, one of the logic core and the at least one storage core also includes a first power supply network, and the other also includes a second power supply network. The second power supply network and the first power supply network are vertically interconnected through a first interconnection structure. The first power supply network is configured to transmit power from an external power supply to the first interconnection structure and the second power supply network. The second power supply network is configured to transmit power to the storage unit and / or the computing unit. The first interconnection structure is configured to transmit power to the second power supply network and the target unit, and the target unit is a storage unit or a computing unit.

[0040] Therefore, after the present application transmits power to the first interconnection structure and the second power supply network through the first power supply network, the power can be transmitted back to the computing unit or storage unit through the first interconnection structure, and can also be transmitted back to the storage unit and / or computing unit through the second power supply network, thereby enhancing the laying range of the power supply network of the storage and computing integrated chip and enhancing the power supply performance of the storage unit and / or computing unit.

[0041] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0043] Figure 1 A first partial cross-sectional schematic diagram of the storage and computing integrated chip according to an embodiment of the present application is shown;

[0044] Figure 2A second partial cross-sectional schematic diagram of the storage-computing integrated chip according to an embodiment of the present application is shown;

[0045] Figure 3 A third partial cross-sectional schematic diagram of the storage-computing integrated chip according to an embodiment of the present application is shown;

[0046] Figure 4 A fourth partial cross-sectional schematic diagram of the storage-computing integrated chip according to an embodiment of the present application is shown;

[0047] Figure 5 A fifth partial cross-sectional schematic diagram of the storage-computing integrated chip according to an embodiment of the present application is shown;

[0048] Figure 6 A schematic diagram of the planar layout of the storage and computing integrated chip of an embodiment of the present application is shown.

[0049] Among them, 100 is a storage and computing integrated chip; 1 is a storage core; 11 is a first storage core; 111 is a first storage unit; 112 is a first back surface; 113 is a first crystal surface; 12 is a second storage core; 121 is a second storage unit; 122 is a second back surface; 123 is a second crystal surface; 2 is a logic core; 21 is a computing unit; 22 is a third back surface; 23 is a third crystal surface; 31 is a first power supply network; 32 is a second power supply network; 4 is a first interconnection structure; 5 is a second interconnection structure; 51 is a hybrid bonding structure; 52 is a first through silicon via; 6 is a packaging substrate; 7 is a third interconnection structure; 71 is a second through silicon via; 72 is a bump. DETAILED DESCRIPTION

[0050] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0051] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0052] It should also be noted that the terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that shown or described.

[0053] As used herein, "about," "approximately," "substantially," or "substantially" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0054] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0055] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application.

[0056] With the rapid development of semiconductor technology, chip manufacturing processes are constantly moving towards finer scales. For example, storage chips and logic chips are integrated into storage and computing integrated chips through three-dimensional stacking. Traditional packaging technology can no longer meet the power supply performance requirements of storage and computing integrated chips.

[0057] In the related art, power is supplied to logic and memory chips via a packaging substrate. However, due to an unreasonable design of the power supply network, for example, if the packaging substrate is provided with a power supply, the memory chips are arranged close to the packaging substrate, the memory chips and logic chips are stacked together in three dimensions, and the packaging substrate is used to supply power to the memory and logic chips in a unidirectional upward direction, as the speed of the logic chips increases and / or the capacity of the memory chips increases, this unidirectional power supply method cannot meet the power supply performance requirements of the integrated storage and computing chip, resulting in local power shortages or overall power shortages. For example, if the circuits in a certain area of ​​the logic chip are densely packed and used for logic calculations, the layout of the logic calculation circuits in this area will block the extension of the power supply network (i.e., it is impossible to lay power lines in this area), resulting in local power shortages in this area. For example, because the power supply network itself has power supply overhead, the use of an upward unidirectional power supply method will result in insufficient power supply to the chips further up. On the one hand, in the pursuit of maximum circuit performance, insufficient power supply may cause the circuit voltage to drop. For example, after the core voltage drops, errors will occur in the storage and computing process. For example, the circuit itself may flip, but it cannot flip due to insufficient flip voltage.

[0058] In view of this, an embodiment of the present application provides a storage and computing integrated chip. After the storage and computing integrated chip transmits power to the first interconnection structure and the second power supply network through the first power supply network, the power can be transmitted back to the computing unit or storage unit through the first interconnection structure, and can also be transmitted back to the storage unit and / or computing unit through the second power supply network, thereby enhancing the laying range of the power supply network of the storage and computing integrated chip and enhancing the power supply performance of the storage unit and / or computing unit.

[0059] The storage and computing integrated chip of the embodiment of the present application is described below with reference to specific drawings.

[0060] See also Figure 1 , shows a first partial cross-sectional structural schematic diagram of the storage and computing integrated chip of an embodiment of the present application.

[0061] According to a first aspect of the present invention, there is provided a storage-computing integrated chip 100, comprising: a logic core 2 and at least one storage core 1. The logic core 2 comprises a computing unit 21; at least one storage core 1 is stacked with the logic core 2, and the storage core 1 comprises a storage unit; wherein, one of the logic core 2 and the at least one storage core 1 further comprises a first power supply network 31, and the other further comprises a second power supply network 32, wherein the second power supply network 32 is vertically interconnected with the first power supply network 31 via a first interconnection structure 4, wherein the first power supply network 31 is configured to transmit power from an external power source to the first interconnection structure 4 and the second power supply network 32, wherein the second power supply network 32 is configured to transmit the power to the storage unit and / or the computing unit 21, and wherein the first interconnection structure 4 is configured to transmit the power to the second power supply network 32 and a target unit, wherein the target unit is the storage unit or the computing unit 21.

[0062] For example, the logic core 2 may include one or more computing units 21, and the storage core 1 may include one or more storage units, which are not limited here.

[0063] It is understandable that the embodiments of the present application treat at least one memory chip 1 as a whole and illustrate the layout of the first power supply network 31 and the second power supply network 32. The logic chip 2 and the at least one memory chip 1 may include the first power supply network 31, and the other may include the second power supply network 32. Alternatively, the logic chip 2 includes the second power supply network 32, and the at least one memory chip 1 includes the first power supply network 31.

[0064] Among them, when the logic core 2 includes a first power supply network 31 and the at least one storage core 1 includes a second power supply network 32, the first power supply network 31 and the computing unit 21 are located in the same core, and the second power supply network 32 and the computing unit 21 are located in different cores; therefore, assuming that the power of the external power supply is transmitted from the first power supply network 31 to the second power supply network 32 through the first interconnection structure 4 as forward transmission, the power can also be transmitted in the reverse direction to the computing unit 21 through the first interconnection structure 4, or the second power supply network 32 can be transmitted in the reverse direction to the computing unit 21 through the first interconnection structure 4, thereby providing auxiliary power supply based on reverse transmission power on the basis of traditional forward power supply, thereby improving the power supply performance of the storage and computing integrated chip 100.

[0065] Among them, when the logic chip 2 includes a second power supply network 32 and the at least one storage chip 1 includes a first power supply network 31, the second power supply network 32 and the computing unit 21 are located in the same chip, and the second power supply network 32 and the storage unit are located in different chips; therefore, assuming that the power of the external power supply is transmitted to the second power supply network 32 through the first power supply network 31 as forward transmission, the power can also be transmitted in the reverse direction to the storage unit through the first interconnection structure 4, or the second power supply network 32 can be transmitted in the reverse direction to the storage unit through the first interconnection structure 4, so that on the basis of traditional forward power supply, auxiliary power supply is performed based on reverse transmission power, thereby improving the power supply performance of the storage and computing integrated chip 100.

[0066] In addition, when there are multiple storage core particles 1, the second power supply network 32 in the storage core particle 1 of the upper layer can also reversely supply power to the storage unit of the storage core particle 1 of the lower layer, and / or reversely supply power to the computing unit 21 of the logic core particle 2, thereby improving the power supply performance of the storage and computing integrated chip 100.

[0067] In some embodiments, when the second power supply network 32 is vertically interconnected with the first power supply network 31 through the first interconnection structure 4, the first interconnection structure 4 may be an interconnection structure based on three-dimensional integration technology. For example: a three-dimensional integration region is set in the logic core 2, and a corresponding three-dimensional integration region is set in the at least one storage core 1, and the vertical interconnection between the second power supply network 32 and the first power supply network 31 is achieved by setting through silicon vias (TSVs) and / or hybrid bonding structures 51 between the three-dimensional integration regions. Exemplarily, the first interconnection structure 4 of the present application includes a first metal sheet arranged on the top layer of one of the two adjacent cores and a second metal sheet on the top layer of the other core, and the first metal sheet and the second metal sheet are bonded to be electrically connected, for example, by thermal cycle bonding.

[0068] It is understood that in order to achieve the matching positioning of the first metal sheet and the second metal sheet, two thin metal layers are usually placed on the top layer of the side where the two adjacent core particles are close to each other, and then the first metal sheet and the second metal sheet are respectively placed on the thin metal layers. As a result, the film layer where the first interconnect structure 4 is located is usually conductive, so it can transmit power.

[0069] It can be understood that the drawings of the embodiments of the present application show the main layout areas of the first power supply network 31 and the second power supply network 32 in each core particle, but do not specifically show the routing layout of the first power supply network 31 and the second power supply network 32. The routing can be performed in the main layout area according to actual preparation needs, and no limitation is made here.

[0070] Continue to see Figure 1In some embodiments, the at least one storage core 1 includes: a first storage core 11 and a second storage core 12. The first storage core 11 includes a first storage unit 111; the second storage core 12 is arranged between the first storage core 11 and the logic core 2 and includes a second storage unit 121; the second power supply network 32 is arranged in the first storage core 11, in the second storage core 12, and between the first storage core 11 and the second storage core 12.

[0071] It is understandable that in Figure 1 In the embodiment, the electrical connection between the first power supply network 31 and the second power supply network 32 constructs multiple auxiliary power supply paths. For example: Power supply path ①: After the power of the external power supply is transmitted to the first interconnection structure 4 through the first power supply network 31 of the logic core 2, it can be transmitted downward in reverse through the first interconnection structure 4 to the computing unit 21 to provide auxiliary power to the computing unit 21. Alternatively, power supply path ②: After the power of the external power supply is transmitted to the second power supply network 32 in the first storage core 11 through the first power supply network 31 and the second interconnection structure 5, the second power supply network 32 can provide auxiliary power to the computing unit 21 downward through the first interconnection structure 4. Alternatively, power supply path ③: When the power of the external power supply reaches the interconnection structure between the two storage cores 1 (the second interconnection structure 5 below) through the first power supply network 31, it can be transmitted downward through the second interconnection structure 5 to the storage unit of the second storage core 12 and / or transmitted to the computing unit 21 of the logic core 2 through the second interconnection structure 5 and the first interconnection structure 4 for auxiliary power supply. Alternatively, power supply path ④: when the power of the external power supply is transmitted to the second power supply network 32 of the second storage chip 12 through the first power supply network 31 and the second interconnection structure 5 and the second power supply network 32 in the first storage chip 11, it can be transmitted downward through the interconnection structure between the two storage chips 1 (the second interconnection structure 5 below) to the storage unit of the second storage chip 12 and / or transmitted through the second interconnection structure 5 and the first interconnection structure 4 to the computing unit 21 of the logic chip 2 for auxiliary power supply.

[0072] Therefore, according to the power supply requirements of the storage unit and the computing unit 21 in the storage-computing integration, local power supply or global power supply can be performed on demand to improve the local power supply performance or the global power supply performance.

[0073] Continue to see Figure 1In one embodiment, the second power supply network 32 includes: a first power supply layer (not shown), a second power supply layer (not shown) and a second interconnection structure 5; the first power supply layer is arranged in the first storage core 11 and is electrically connected to the first storage unit 111; the second power supply layer is arranged in the second storage core 12 and is electrically connected to the second storage unit 121; the second interconnection structure 5 includes a hybrid bonding structure 51 arranged between the first storage core 11 and the second storage core 12 and a first silicon via 52 passing through the second storage core 12, the first power supply layer is electrically connected to the second power supply layer and the second storage unit 121 through the hybrid bonding structure 51 and the first silicon via 52, and the second power supply layer is electrically connected to the computing unit 21 through the first silicon via 52 and the first interconnection structure 4; the first power supply network 31 includes: a third power supply layer (not shown), which is arranged in the logic core 2, electrically connected to the computing unit 21, and electrically connected to the second power supply layer through the first interconnection structure 4.

[0074] It can be understood that the first power supply layer, the second power supply layer and the third power supply layer can be metal wire layers, wherein the third power supply layer can be prepared on the same layer as the metal layer in the logic core 2, the first power supply layer can be prepared on the same layer as the metal layer of the first storage core 11, and the second power supply layer can be prepared on the same layer as the metal layer of the second storage core 12.

[0075] Exemplarily, the hybrid bonding structure 51 includes: a third metal sheet disposed on the first memory core 11 and a fourth metal sheet disposed on the second memory core 12 , and the third metal sheet and the fourth metal sheet are bonded to be electrically connected.

[0076] It is understood that to achieve the matching positioning of the third and fourth metal sheets, two thin metal layers are typically provided on the top layer of the side where the first and second memory chips 11 and 12 are close to each other, and then the third and fourth metal sheets are respectively provided on the thin metal layers. As a result, the film layer where the hybrid bonding structure 51 is located is generally conductive, thereby enabling power transmission.

[0077] It can be understood that, based on the above, power supply path ① is specifically as follows: after the power of the external power supply is transmitted to the first interconnect structure 4 through the third power supply layer, it can be transmitted downward in the reverse direction through the first interconnect structure 4 to the computing unit 21, thereby providing auxiliary power to the computing unit 21. Power supply path ② is specifically as follows: the power of the external power supply is transmitted to the second power supply layer through the third power supply layer and the first interconnect structure 4, and the second power supply layer can provide auxiliary power to the computing unit 21 downward through the first interconnect structure 4. Power supply path ③ is specifically as follows: the power of the external power supply is transmitted to the second interconnect structure 5 through the third power supply layer and the first interconnect structure 4, and can be transmitted downward through the second interconnect structure 5 to the storage unit of the second storage core 12 and / or transmitted to the computing unit 21 of the logic core 2 through the second interconnect structure 5 and the first interconnect structure 4 for auxiliary power supply. Power supply path ④ is specifically as follows: the power of the external power supply is transmitted to the first power supply layer through the third power supply layer, the first interconnect structure 4, and the second interconnect structure 5, and can be transmitted downward in the reverse direction to the storage unit of the second storage core 12 and / or transmitted to the computing unit 21 of the logic core 2 through the second interconnect structure 5 and the first interconnect structure 4 for auxiliary power supply.

[0078] Figure 2 A second partial cross-sectional structural schematic diagram of the storage and computing integrated chip of an embodiment of the present application is shown.

[0079] In some embodiments, the at least one storage core 1 includes: a first storage core 11 and a second storage core 12. The first storage core 11 includes a first storage unit 111; the second storage core 12 is arranged between the first storage core 11 and the logic core 2 and includes a second storage unit 121; the first power supply network 31 is arranged in the first storage core 11, in the second storage core 12, and between the first storage core 11 and the second storage core 12.

[0080] In some embodiments, the first power supply network 31 includes: a first power supply layer, a second power supply layer, and a second interconnect structure 5. The first power supply layer is provided in the logic core 2 and is electrically connected to the computing unit 21; the second power supply layer is provided in the second storage core 12 and is electrically connected to the second storage unit 121; the second interconnect structure 5 includes a hybrid bonding structure 51 provided between the logic core 2 and the second storage core 12 and a first silicon via 52 extending through the second storage core 12. The first power supply layer is electrically connected to the second power supply layer and the second storage unit 121 via the hybrid bonding structure 51 and the first silicon via 52, and the second power supply layer is electrically connected to the first storage unit 111 via the first silicon via 52 and the first interconnect structure 4. The second power supply network 32 includes: a third power supply layer provided in the first storage core 11 and electrically connected to the second power supply layer via the first interconnect structure 4.

[0081] It is understandable that in Figure 2 In the embodiment, the first power supply network 31 and the second power supply network 32 construct multiple power supply paths. For example: power supply path ① is: after the power of the external power supply is transmitted to the first interconnection structure 4 through the third power supply layer, it can be transmitted downward in reverse through the first interconnection structure 4 to the first storage unit 111 to provide auxiliary power supply to the first storage unit 111. Power supply path ② is specifically: the power of the external power supply is transmitted to the second power supply layer through the third power supply layer and the first interconnection structure 4, and the second power supply layer can provide auxiliary power supply to the first storage unit 111 downward through the first interconnection structure 4. Power supply path ③ is specifically: the power of the external power supply is transmitted to the second interconnection structure 5 through the third power supply layer and the first interconnection structure 4, and can be transmitted downward through the second interconnection structure 5 to the second storage unit 121 of the second storage core 12 and / or transmitted to the first storage unit 111 through the second interconnection structure 5 and the first interconnection structure 4 for auxiliary power supply. Power supply path ④ is specifically as follows: the power of the external power supply is transmitted to the first power supply layer through the third power supply layer, the first interconnection structure 4 and the second interconnection structure 5, and can be transmitted downward in the reverse direction to the second storage unit 121 and / or transmitted to the first storage unit 111 through the second interconnection structure 5 and the first interconnection structure 4 for auxiliary power supply.

[0082] In some embodiments, the first memory core 11 includes: a first crystal back 112 and a first crystal face 113 arranged opposite to each other; the second memory core 12 includes: a second crystal back 122 and a second crystal face 123 arranged opposite to each other, the second crystal back 122 being closer to the first crystal face 113 than the second crystal face 123; the logic core 2 includes: a third crystal back 22 and a third crystal face 23 arranged opposite to each other, the third crystal face 23 being closer to the second crystal face 123 than the third crystal back 22 (e.g., Figure 1Alternatively, the third crystal back 22 is closer to the second crystal plane 123 than the third crystal plane 23 (as shown in FIG. Figure 2 shown).

[0083] Figure 3 A third partial cross-sectional schematic diagram of the storage and computing integrated chip of an embodiment of the present application is shown. Figure 4 A fourth partial cross-sectional schematic diagram of the storage and computing integrated chip of an embodiment of the present application is shown.

[0084] In some embodiments, the package substrate 6 is further included, the third back surface 22 (eg, Figure 1 ) or the third crystal plane 23 (such as Figure 2 ) is disposed close to the package substrate 6, or the first back surface 112 of the first memory core 11 (such as Figure 3 ) or the first crystal plane 113 is arranged close to the package substrate 6 (eg Figure 4 ).

[0085] It can be understood that the logic core 2 and the storage core 1 are integrated on the packaging substrate 6, and the packaging substrate 6 is provided with an external power supply, which is provided on the pad. When the third crystal plane 23 is closer to the second crystal plane 123 than the third crystal back 22, it means that the crystal plane of the logic core 2 is set relative to the crystal plane of the second storage core 12. At this time, the crystal back of the logic core 2 faces the packaging substrate 6, and it is necessary to pass through the crystal back of the logic core 2 through the PAD TSV (pad silicon through via) in the logic core 2 so that it can be interconnected with the pad. When the third crystal back 22 is closer to the second crystal plane 123 than the third crystal back 23, it means that the crystal back of the logic core 2 is set relative to the crystal plane of the second storage core 12. At this time, the crystal plane of the logic core 2 faces the packaging substrate 6. At this time, there is no need to set the PAD TSV, and it can be directly connected to the pad. Among them, when the crystal surface of the logic core 2 faces the packaging substrate 6, the thickness of the logic core 2 can be set to be thinner, thereby reducing costs. This setting method can be applied to the field of artificial intelligence, which requires the use of PCIE (Peripheral Component Interconnect Express) to obtain a large amount of data from the outside world and output a large amount of data. The high-speed interface circuit is more sensitive to interconnection and transit, so it is not convenient to set PAD TSV.

[0086] Similarly, when the back of the first storage core 11 faces the packaging substrate 6, it is necessary to penetrate the back of the logic core 2 through a PADTSV (pad through silicon via) in the logic core 2 so that it can be interconnected with the pad. When the first storage core 11 faces the packaging substrate 6, there is no need to set a PAD TSV, and it can be directly connected to the pad. Among them, when the crystal surface of the first storage core 11 faces the packaging substrate 6, the thickness of the first storage core 11 can be set to be thinner, thereby reducing costs. This setting method can be applied to the field of artificial intelligence, which requires the use of PCIE to obtain a large amount of data from the outside world and output a large amount of data. The high-speed interface circuit is more sensitive to interconnection and transit, so it is not convenient to set a PAD TSV.

[0087] Continue to see Figure 1 or Figure 3 In some embodiments, the third back surface 22 of the logic core 2 is arranged close to the packaging substrate 6, or the first back surface 112 of the first storage core 11 is arranged close to the packaging substrate 6, and the storage and computing integrated chip 100 also includes: a third interconnect structure 7, including a second through-silicon via 71 and a bump 72, the second through-silicon via 71 extends from the third back surface 22 to the third crystal surface 23, or the second through-silicon via 71 extends from the first back surface 112 to the first crystal surface 112, and the first power supply network 31 is connected to the bump 72 through the second through-silicon via 71; the packaging substrate 6 is provided with the external power supply, and the external power supply is electrically connected to the first power supply network 31 through the bump 72 and the second through-silicon via 71.

[0088] It can be understood that when the back of the logic core 2 faces the packaging substrate 6, or the back of the first storage core 11 faces the packaging substrate 6, if the first power supply network 31 is to be electrically connected to the external power supply, it is necessary to pass through the back of the logic core 2 through a PAD TSV (pad silicon via) in the logic core 2 or the first storage core 11 so as to be interconnected with the pad. Therefore, the present application realizes electrical connection with the external power supply by setting a second silicon via 71 and a bump 72.

[0089] When the second TSV 71 is provided, the power of the external power supply can be used to auxiliary power the computing unit 21 or the first storage unit 111 through the second TSV 71 and the first power supply network 31, that is, power supply path ⑤.

[0090] Continue to see Figure 2 or Figure 4In some embodiments, the third crystal plane 23 of the logic core 2 is arranged close to the packaging substrate 6, or the first crystal plane 113 of the first storage core 11 is arranged close to the packaging substrate 6, and the storage and computing integrated chip 100 also includes: a bump 72; the packaging substrate 6 is provided with the external power supply, and the external power supply is electrically connected to the first power supply network 31 through the bump 72.

[0091] It is understandable that when the crystal face of the logic core 2 or the crystal face of the first memory core 11 faces the package substrate 6 , there is no need to set PAD TSVs, and the first power supply network 31 can be directly connected to the external power supply through the bumps 72 .

[0092] In some embodiments, in a direction perpendicular to the logic chip 2 , the thickness of the first memory chip 11 is greater than the thickness of the second memory chip 12 .

[0093] It is understood that when vertically interconnecting at least one memory chip 1 and a logic chip 2 based on three-dimensional heterogeneous integration technology, the second memory chip 12 needs to be made relatively thin, for example, at the micron level, so that through-silicon vias can be drilled in the second memory chip 12. Furthermore, because the entire chip requires a certain thickness for support, the first memory chip 11 also requires a certain thickness. Therefore, the thickness of the first memory chip 11 is greater than that of the second memory chip 12.

[0094] Figure 5 The fifth partial cross-sectional structural diagram of the storage and computing integrated chip of an embodiment of the present application is shown.

[0095] In some embodiments, the at least one memory chip 1 comprises:

[0096] The first storage core 11 includes a first storage unit 111 and the second power supply network 32, and has a first crystal back 112 and a first crystal surface 113 arranged opposite to each other; the logic core 2 includes the first power supply network 31 and a third crystal back 22 and a third crystal surface 23 arranged opposite to each other, and the third crystal back 22 is closer to the first crystal surface 113 than the third crystal surface 23.

[0097] In some embodiments, it further includes: a bump 72 ; a packaging substrate 6 , provided with the external power supply, and the external power supply is electrically connected to the first power supply network 31 through the bump 72 .

[0098] It can be understood that since the computing unit 21 is usually the unit with the highest power consumption in the storage and computing integrated chip 100, when a layer of storage core particles 1 and a layer of logic core particles 2 are stacked, the metal layer of the first storage core particle 11 can be used to lay out the second power supply network 32, and the second power supply network 32 can provide auxiliary power supply to the computing unit 21 in reverse. Compared with the traditional computing unit 21 that can only rely on the power supply metal layer laid out in the logic core particle 2 for horizontal power supply, the present application is based on the second power supply network 32 to provide auxiliary power supply to the computing unit 21 vertically, which can improve the power supply performance of the computing unit 21.

[0099] In some embodiments, the computing unit 21 and the storage unit can implement data interaction based on a vertical interconnection structure. For details, please refer to relevant technologies and will not be repeated here.

[0100] Figure 6 A schematic diagram of the planar layout of the storage and computing integrated chip of an embodiment of the present application is shown.

[0101] like Figure 6 As shown, the stacked storage units and computing units 21 are arranged in the middle area, and the first power supply network 31 and the second power supply network 32 are arranged around each storage unit and each computing unit 21 to provide auxiliary power supply to the storage units and computing units 21.

[0102] Therefore, in the embodiment of the present application, by stacking the logic core 2 and at least one storage core 1 based on three-dimensional heterogeneous integration, the first power supply network 31 and the second power supply network 32 form a vertical power supply network with the characteristic of low AC impedance, and the first power supply network 31 and the second power supply network 32 form a three-dimensional Faraday ring with each storage unit and each computing unit 21, thereby improving the performance of the three-dimensional vertical interconnection channel and improving signal integrity.

[0103] It should be noted that the first power supply network 31 and the second power supply network 32 of the embodiment of the present application are auxiliary power supply networks arranged outside the conventional power supply network, wherein the conventional power supply network and the auxiliary power supply network of the present application can be connected to different external power supply chips respectively, for example, the conventional power supply network is connected to the first power supply chip, and the auxiliary power supply network is connected to the second power supply chip, that is, the external power supply described in the embodiment of the present application above, wherein the laying and power supply principles of the conventional power supply network can refer to relevant technologies and will not be repeated here.

[0104] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general-purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing this type of system. In addition, the present invention is not directed to any specific programming language. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the above description of specific languages ​​is for the purpose of disclosing the best mode of the present invention.

[0105] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0106] Similarly, it should be understood that in order to streamline the disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof.

[0107] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition may be divided into multiple submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including accompanying abstracts and drawings) may be replaced by alternative features providing the same, equivalent or similar purpose.

[0108] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features and not other features included in other embodiments, the combination of features from different embodiments is intended to be within the scope of the present invention and to form different embodiments.

[0109] It should be noted that the above embodiments illustrate the present invention and do not limit it. Any reference symbols placed between brackets should not be construed as limiting the present invention. The word "comprising" does not exclude the presence of components or steps not listed in the present invention. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The present invention can be implemented by means of hardware comprising several different components and by means of appropriately programmed computers. In embodiments where several means are listed, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

Claims

1. A storage and computing integrated chip, characterized in that: include: Logic core particles, including computing units; at least one memory chip, stacked with the logic chip, the memory chip including a memory unit; Among them, one of the logic core and the at least one storage core also includes a first power supply network, and the other also includes a second power supply network, the second power supply network and the first power supply network are vertically interconnected through a first interconnection structure, the first power supply network is configured to transmit power from an external power supply to the first interconnection structure and the second power supply network, the second power supply network is configured to transmit the power to the storage unit and / or the computing unit, the first interconnection structure is configured to transmit the power to the second power supply network and the target unit, and the target unit is the storage unit or the computing unit.

2. The integrated storage and computing chip according to claim 1, characterized in that: The at least one storage core comprises: A first storage chip, comprising a first storage unit; A second storage core, disposed between the first storage core and the logic core, comprising a second storage unit; The second power supply network is provided in the first memory core, in the second memory core, and between the first memory core and the second memory core.

3. The integrated storage and computing chip according to claim 2, characterized in that: The second power supply network includes: a first power supply layer, a second power supply layer, and a second interconnection structure; The first power supply layer is provided on the first storage core and is electrically connected to the first storage unit; the second power supply layer is provided on the second storage core and is electrically connected to the second storage unit; the second interconnect structure includes a hybrid bonding structure provided between the first storage core and the second storage core and a first through-silicon via penetrating the second storage core, the first power supply layer is electrically connected to the second power supply layer and the second storage unit through the hybrid bonding structure and the first through-silicon via, and the second power supply layer is electrically connected to the computing unit through the first through-silicon via and the first interconnect structure; The first power supply network includes: a third power supply layer, which is provided in the logic core, electrically connected to the computing unit, and electrically connected to the second power supply layer through the first interconnection structure.

4. The integrated storage and computing chip according to claim 1, characterized in that: The at least one storage core comprises: A first storage chip, comprising a first storage unit; A second storage core, disposed between the first storage core and the logic core, comprising a second storage unit; The first power supply network is provided in the first memory core, in the second memory core, and between the first memory core and the second memory core.

5. The integrated storage and computing chip according to claim 4, characterized in that: The first power supply network includes: a first power supply layer, a second power supply layer and a second interconnection structure; The first power supply layer is provided on the logic core and is electrically connected to the computing unit; the second power supply layer is provided on the second storage core and is electrically connected to the second storage unit; the second interconnect structure includes a hybrid bonding structure provided between the logic core and the second storage core and a first through-silicon via penetrating the second storage core, the first power supply layer is electrically connected to the second power supply layer and the second storage unit through the hybrid bonding structure and the first through-silicon via, and the second power supply layer is electrically connected to the first storage unit through the first through-silicon via and the first interconnect structure; The second power supply network includes: a third power supply layer, which is provided on the first memory core and is electrically connected to the second power supply layer through the first interconnection structure.

6. The integrated storage and computing chip according to any one of claims 2 to 5, characterized in that: The first memory core comprises: a first crystal back and a first crystal face arranged opposite to each other; The second memory core comprises: a second crystal back and a second crystal face disposed opposite to each other, wherein the second crystal back is closer to the first crystal face than the second crystal face; The logic core comprises: a third crystal back and a third crystal plane arranged opposite to each other, wherein the third crystal plane is closer to the second crystal plane than the third crystal back, or the third crystal back is closer to the second crystal plane than the third crystal plane; The storage and computing integrated chip further includes: a packaging substrate, the third back surface or third surface of the logic core is arranged close to the packaging substrate, or the first back surface or first surface of the first storage core is arranged close to the packaging substrate.

7. The integrated storage and computing chip according to claim 6, characterized in that: The third back surface of the logic core is disposed close to the package substrate, or the first back surface of the first memory core is disposed close to the package substrate, and the storage-computing integrated chip further includes: a third interconnect structure comprising a second through-silicon via and a bump, wherein the second through-silicon via extends from the third backside to the third crystal plane, or the second through-silicon via extends from the first crystal plane to the first backside, and the first power supply network is connected to the bump through the second through-silicon via; The packaging substrate is provided with the external power supply, and the external power supply is electrically connected to the first power supply network through the bump and the second through-silicon via.

8. The storage and computing integrated chip according to claim 6, characterized in that: The third crystal surface of the logic core is arranged close to the packaging substrate, or the first crystal surface of the first memory core is arranged close to the packaging substrate, and the storage-computing integrated chip further includes: bumps; The packaging substrate is provided with the external power supply, and the external power supply is electrically connected to the first power supply network through the bump.

9. The integrated storage and computing chip according to any one of claims 2-5, 6-8, characterized in that: In a direction perpendicular to the logic chip, the thickness of the first memory chip is greater than the thickness of the second memory chip.

10. The storage and computing integrated chip according to claim 1, characterized in that: The at least one storage core comprises: The first memory chip includes a first memory unit and the second power supply network, and has a first back surface and a first front surface that are oppositely arranged; The logic core comprises the first power supply network and a third backside and a third crystal face that are arranged opposite to each other, wherein the third backside is closer to the first crystal face than the third crystal face; The storage and computing integrated chip further includes a bump and a packaging substrate, the packaging substrate is provided with the external power supply, and the external power supply is electrically connected to the first power supply network through the bump.

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