Flash memory test structure, layout and manufacturing method thereof

Abstract

The invention provides a test structure of a flash memory, a layout and a manufacturing method thereof. The test structure comprises a substrate, a plurality of rows of parallel word lines extending in the X direction and a plurality of columns of parallel Y-direction active regions extending in the Y direction. An X-direction active region is arranged between two adjacent rows of Y-direction active regions, and the X-direction active region is connected with the Y-direction active regions of the adjacent regions on the two sides to form an H region. A first floating gate located at the upper left corner, a second floating gate located at the lower left corner, a third floating gate located at the upper right corner and a fourth floating gate located at the lower right corner are arranged over the H region. The first floating gate and the second floating gate are connected and are led out through a first contact hole; the third floating gate and the fourth floating gate are connected and are led out through a second contact hole; one of the first contact hole and the second contact hole is connected with high voltage, and the other one is connected with low voltage, so that electric leakage or breakdown voltage between floating gates of two adjacent columns of storage units in the H region can be effectively monitored; when problems are found, reworking and rectification are carried out in time, and bit line failure and programming failure are avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a flash memory test structure, a layout and a manufacturing method thereof. Background Art

[0002] Flash memory has been widely adopted as the optimal choice for non-volatile memory applications due to its high density, low price, and electrically programmable and erasable nature. Generally speaking, floating gate flash memory shares a similar primary memory cell structure: a stacked gate structure consisting of a floating gate and a control gate that at least partially covers the floating gate. The control gate, through coupling, controls the storage and release of electrons in the floating gate.

[0003] Flash memory includes multiple storage cells arranged in an array, such as Figure 1 As shown, the lateral connection between two adjacent columns of active areas is H-shaped, defined as the H region (the area within the blue box). As semiconductor device sizes continue to shrink, the spacing between adjacent memory cells also decreases. The floating gates of two adjacent columns of memory cells (e.g., FG1 and FG3, FG2 and FG4) should be regular rectangles. However, the difficulty in controlling the etching process at small sizes, coupled with the inherent pattern alignment deviations during lithography, can lead to asymmetric H regions in the actual structure. The resulting floating gates are prone to arcs, potentially creating a bridging risk and defect. Between the floating gates of two adjacent columns of memory cells (e.g., FG1 and FG3) lies a bowl-shaped dielectric layer. The curved corners of the first and third floating gates FG1 and FG3, located at the bottom of the bowl, are nearly connected. If the curved corners of the first and third floating gates FG1 and FG3 connect, the floating gate polysilicon will become conductive, causing both the first and third floating gates FG1 and FG3 to connect to or short-circuit the bit line BL, leading to bit line BL failure. Furthermore, leakage occurs between the first and third floating gates FG1 and FG3 of the two independent memory cells, causing programming failure. Currently, there is no effective method for monitoring the connection (short circuit) between two adjacent independent floating gates within the H region. Summary of the Invention

[0004] The purpose of the present invention is to provide a flash memory test structure, layout and manufacturing method thereof, which can effectively monitor the leakage or breakdown voltage between the floating gates of two adjacent columns of memory cells in the H region; when problems are found, timely rework and rectification can be carried out to avoid bit line BL failure and programming failure.

[0005] The present invention provides a flash memory test structure, comprising:

[0006] a substrate, wherein an X direction and a Y direction perpendicular to each other are defined in a plane parallel to the substrate;

[0007] A plurality of parallel word lines extending along the X direction are located above the substrate, wherein each word line has stacked floating gates and control gates on both sides along the Y direction;

[0008] A plurality of parallel columns of Y-direction active regions extending along the Y-direction are located in the substrate, an X-direction active region is disposed between two adjacent columns of the Y-direction active regions, the X-direction active region and the Y-direction active regions of adjacent regions on both sides are connected to form an H region; directly above the H region are a first floating gate of a first memory cell located in the upper left corner, a second floating gate of a second memory cell located in the lower left corner, a third floating gate of a third memory cell located in the upper right corner, and a fourth floating gate of a fourth memory cell located in the lower right corner;

[0009] The first floating gate and the second floating gate of the memory cells located in two adjacent rows of the nth column within the H region, each on a side close to the X-direction active region, are connected and led out through a first contact hole; and the third floating gate and the fourth floating gate of the memory cells located in two adjacent rows of the n+1th column within the H region, each on a side close to the X-direction active region, are connected and led out through a second contact hole.

[0010] One of the first contact hole and the second contact hole is used for connecting to a high voltage, and the other is used for connecting to a low voltage, so as to test leakage or breakdown voltage between floating gates of two adjacent columns of memory cells in the H region.

[0011] Furthermore, the reconstructed rows and columns are formed with the H regions as units, and the H regions are staggered in the reconstructed rows and columns.

[0012] Further, in the odd-numbered reconstruction columns, the H regions are distributed in the odd-numbered reconstruction rows, and in the even-numbered reconstruction columns, the H regions are distributed in the even-numbered reconstruction rows; or in the even-numbered reconstruction columns, the H regions are distributed in the odd-numbered reconstruction rows, and in the odd-numbered reconstruction columns, the H regions are distributed in the even-numbered reconstruction rows.

[0013] Furthermore, the test structure includes multiple H regions, one H region leads to one first contact hole and one second contact hole, multiple first contact holes are electrically connected through the first wire layer; multiple second contact holes are electrically connected through the second wire layer; leakage between the floating gates of two adjacent columns in any one of the H regions can be tested.

[0014] Furthermore, one of the first contact hole and the second contact hole is used to connect to a high voltage, and the other is used to connect to a low voltage. The high voltage range is 6V to 12V; the low voltage is approximately 0V.

[0015] Furthermore, the test structure includes the storage units arranged in an array;

[0016] The test structure includes a plurality of parallel rows of floating gate pattern regions extending along the X direction; each row of the floating gate pattern regions includes the word line and the floating gates and control gates stacked on both sides of the word line in the Y direction;

[0017] The overlapping area of ​​the Y-direction active area and the floating gate pattern area is the storage unit;

[0018] The first contact hole is located in the gap between two adjacent columns of the Y-direction active regions; the second contact hole is also located in the gap between two adjacent columns of the Y-direction active regions.

[0019] The present invention also provides a test structure layout for a flash memory, which defines mutually perpendicular X and Y directions in a plane parallel to a substrate; comprising:

[0020] A floating gate layer, the floating gate layer comprising a plurality of parallel rows of floating gate graphic regions extending along the X direction; each row of the floating gate graphic regions comprising a word line and floating gates and control gates stacked on both sides of the word line in the Y direction;

[0021] an active area layer, the active area layer comprising a plurality of parallel columns of Y-direction active areas extending along the Y-direction, an X-direction active area being disposed between two adjacent columns of the Y-direction active areas, the X-direction active area being connected to the Y-direction active areas of adjacent areas on both sides to form an H region; and directly above the H region comprising a first floating gate of a first storage cell located in the upper left corner, a second floating gate of a second storage cell located in the lower left corner, a third floating gate of a third storage cell located in the upper right corner, and a fourth floating gate of a fourth storage cell located in the lower right corner;

[0022] a control gate removal plate layer, the control gate removal plate layer comprising a plurality of sub-clearance regions distributed along the X-direction, the sub-clearance regions being located on both sides of the X-direction active region; the control gate material layer in the sub-clearance regions being etched away; the sub-clearance regions exposing floating gate connection regions, the floating gate connection regions comprising a first floating gate connection region and a second floating gate connection region; the first floating gate connection region being a connection region between the first floating gate and the second floating gate of two adjacent rows of memory cells in the nth column directly above the H region, each adjacent to the X-direction active region; and the second floating gate connection region being a connection region between the third floating gate and the fourth floating gate of two adjacent rows of memory cells in the n+1th column directly above the H region, each adjacent to the X-direction active region.

[0023] A contact hole plate layer, the contact hole plate layer comprising: a first contact hole and a second contact hole; wherein the sub-cleared area covers the first contact hole and the second contact hole; the first floating gate connection area is led out through the first contact hole; and the second floating gate connection area is led out through the second contact hole; one of the first contact hole and the second contact hole is connected to a high voltage and the other is connected to a low voltage, so as to test the leakage or breakdown voltage between the floating gates of the memory cells in two adjacent columns in the H region;

[0024] A control gate contact hole plate layer, wherein the control gate contact hole plate layer includes a plurality of sub-reserved areas distributed in strips along the Y direction, and the floating gate material layer of the sub-reserved areas is retained until the final state; the sub-reserved areas cover all the first contact holes in the same column and cover all the second contact holes in the same column.

[0025] The present invention also provides a method for manufacturing a flash memory test structure, comprising:

[0026] S1. Providing a substrate, defining mutually perpendicular X and Y directions in a plane parallel to the substrate; forming a plurality of parallel columns of Y-direction active regions extending along the Y direction in the substrate, an X-direction active region being disposed between two adjacent columns of the Y-direction active regions, and the X-direction active region and the Y-direction active regions in adjacent regions on both sides being connected to form an H region;

[0027] S2. forming a stacked layer comprising a floating gate material layer, a spacer layer, a control gate material layer, and a first spacer on the substrate in sequence; and forming a plurality of parallel word lines extending along the X direction in the stacked layer;

[0028] S3, etching away the control gate material layer and the spacer layer located in the floating gate connection region; the floating gate connection region includes a floating gate connection region 1 and a floating gate connection region 2; the floating gate connection region 1 is a connection region between the first floating gate and the second floating gate of the memory cells in the nth column and the adjacent rows located directly above the H region, each close to the X-direction active region; the floating gate connection region 2 is a connection region between the third floating gate and the fourth floating gate of the memory cells in the n+1th column and the adjacent rows located directly above the H region, each close to the X-direction active region;

[0029] S4, etching the control gate material layer, the spacer layer, and the floating gate material layer to form a floating gate and a control gate;

[0030] S5. Form a dielectric layer covering the word line, the floating gate, and the control gate, and etch a first contact hole and a second contact hole in the dielectric layer; the first contact hole leads to the first floating gate connection region, and the second contact hole leads to the second floating gate connection region.

[0031] Furthermore, step S3 specifically includes:

[0032] S31, forming a first photoresist layer, wherein the first photoresist layer covers the word line and exposes the floating gate connection region;

[0033] S32, using the first photoresist layer as a mask, etching and removing the control gate material layer and the spacer layer located in the floating gate connection region;

[0034] S33 , removing the first photoresist layer by an ashing process.

[0035] Furthermore, step S4 specifically includes:

[0036] S41, forming a second photoresist layer, wherein the second photoresist layer covers the word line, the floating gate material layer in the floating gate connection region, and a gap between two adjacent memory cells;

[0037] S42, using the second photoresist layer as a mask, etching and removing the exposed control gate material layer, the spacer layer, and the floating gate material layer to form the floating gate and the control gate;

[0038] S43 , removing the second photoresist layer by an ashing process.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] The present invention provides a flash memory test structure, layout, and manufacturing method thereof, comprising: a substrate, multiple rows of parallel word lines extending in the X direction located above the substrate, and multiple columns of parallel Y-direction active regions extending in the Y direction located within the substrate. An X-direction active region is disposed between two adjacent columns of Y-direction active regions. The X-direction active region is connected to the Y-direction active regions of adjacent regions on both sides to form an H region. Directly above the H region are a first floating gate located in the upper left corner, a second floating gate located in the lower left corner, a third floating gate located in the upper right corner, and a fourth floating gate located in the lower right corner. The first floating gate and the second floating gate of two adjacent rows of memory cells in the nth column within the H region are connected and led out through a first contact hole; the third floating gate and the fourth floating gate of two adjacent rows of memory cells in the n+1th column within the H region are connected and led out through a second contact hole; one of the first contact hole and the second contact hole is used to connect to a high voltage, and the other is used to connect to a low voltage, which can effectively monitor the leakage or breakdown voltage between the floating gates of the memory cells in two adjacent columns within the H region; due to the inherent pattern alignment deviation of the lithography machine during operation, the H region (H structure) in the actual structure may become asymmetric, so there may be a risk of bridging, resulting in a bridging defect. The test structure of the flash memory of the present invention specifically tests for such bridging defects. If problems are found, timely rework and rectification can be carried out to avoid bit line BL failure and programming failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a flash memory structure.

[0042] Figure 2 This is a test structure layout of the flash memory according to an embodiment of the present invention.

[0043] Figure 3 For the Figure 2 Schematic cross-sectional view of Y1Y2.

[0044] Figure 4 FIG. 1 is a top view of a test structure of a flash memory according to an embodiment of the present invention.

[0045] Figure 5 1 is a flow chart of a method for fabricating a flash memory test structure according to an embodiment of the present invention.

[0046] Figure 6 FIG. 1 is a schematic diagram of a method for fabricating a flash memory test structure after word lines are formed according to an embodiment of the present invention.

[0047] Figure 7 FIG. 1 is a schematic diagram of a method for fabricating a flash memory test structure after forming a first photoresist layer according to an embodiment of the present invention.

[0048] Figure 8 This is a schematic diagram of the method for manufacturing a flash memory test structure after etching the control gate material layer and the spacer layer located in the floating gate connection region in an embodiment of the present invention.

[0049] Figure 9 FIG. 1 is a schematic diagram of a method for fabricating a flash memory test structure after forming a second photoresist layer according to an embodiment of the present invention.

[0050] Figure 10 This is a schematic diagram of a method for fabricating a flash memory test structure after forming a floating gate and a control gate in an embodiment of the present invention.

[0051] Figure 11 This is a schematic diagram of a method for fabricating a flash memory test structure after forming a first contact hole according to an embodiment of the present invention.

[0052] The accompanying drawings are numerals as follows:

[0053] 10-substrate; 11-first memory cell; 12-second memory cell; 20-H region; 21-Y-direction active region; 22-X-direction active region; 30-floating gate graphic region; 31-word line; 32-word line isolation layer; 33-first sidewall; 41-first contact hole; 42-second contact hole; 51-first photoresist layer; 52-second photoresist layer; FG1-first floating gate; FG2-second floating gate; FG3-third floating gate; FG4-fourth floating gate; 60-floating gate material layer; 70-spacer layer; 80-control gate material layer; A-floating gate connection region; B-sub-retention region; C-sub-clear region. DETAILED DESCRIPTION

[0054] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0055] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0056] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0057] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0058] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] Figure 2 This is a test structure layout of the flash memory according to an embodiment of the present invention. Figure 3 For the Figure 2 Schematic cross-sectional view of Y1Y2. Figure 4 FIG. 1 is a top view of a test structure of a flash memory according to an embodiment of the present invention.

[0060] The embodiment of the present invention provides a flash memory test structure, such as Figures 2 to 4 Shown, including:

[0061] The substrate 10 defines an X direction and a Y direction perpendicular to each other in a plane parallel to the substrate 10; and a direction perpendicular to the substrate is defined as a Z direction.

[0062] Multiple parallel rows of word lines 31 extending along the X direction are located above the substrate 10. Floating gates and control gates CG1 are stacked from bottom to top along the Z direction on both sides of each row of word lines 31 along the Y direction.

[0063] Multiple parallel columns of Y-direction active regions 21 extending along the Y-direction are located in the substrate 10. An X-direction active region 22 is disposed between two adjacent columns of Y-direction active regions 21. The X-direction active region 22 is connected to the Y-direction active regions 21 in adjacent regions on both sides to form an H region 20. Directly above the H region are the first floating gate FG1 of the first memory cell 11 in the upper left corner, the second floating gate FG2 of the second memory cell 12 in the lower left corner, the third floating gate FG3 of the third memory cell in the upper right corner, and the fourth floating gate FG4 of the fourth memory cell in the lower right corner.

[0064] The first floating gate FG1 and the second floating gate FG2 of the memory cells in the nth column and the adjacent rows in the H region, each close to the X-direction active region 22, are connected and led out through the first contact hole 41; and the third floating gate FG3 and the fourth floating gate FG4 of the memory cells in the n+1th column and the adjacent rows in the H region, each close to the X-direction active region, are connected and led out through the second contact hole 42.

[0065] One of the first contact hole 41 and the second contact hole 42 is connected to a high voltage, and the other is connected to a low voltage, so as to test leakage or breakdown voltage between floating gates of two adjacent columns of memory cells in the H region 20 .

[0066] Specifically, the material of substrate 10 may be silicon. In other embodiments, the material of substrate 10 includes silicon carbide, silicon germanium, a multinary semiconductor material composed of Group III-V elements, silicon-on-insulator, or germanium-on-insulator. The multinary semiconductor material composed of Group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0067] The test structure includes memory cells arranged in an array; the test structure includes multiple parallel rows of floating gate graphic regions 30 extending along the X direction; each row of floating gate graphic regions 30 includes a word line 31 and floating gates and control gates stacked on both sides of the word line in the Y direction; the overlapping area of ​​the Y-direction active area 21 and the floating gate graphic region 30 is the memory cell.

[0068] Reconstructed rows and columns are formed using H regions 20 as units, and the H regions are staggered in the reconstructed rows and columns. For example, in odd-numbered reconstructed columns, the H regions are distributed in odd-numbered reconstructed rows, and in even-numbered reconstructed columns, the H regions are distributed in even-numbered reconstructed rows; or in even-numbered reconstructed columns, the H regions are distributed in odd-numbered reconstructed rows, and in odd-numbered reconstructed columns, the H regions are distributed in even-numbered reconstructed rows.

[0069] The test structure includes multiple H-regions 20, which are areas where two adjacent columns of Y-direction active areas 21 are connected laterally (in the X direction). Each H-region 20 leads to a first contact hole 41 and a second contact hole 42. The multiple first contact holes 41 are electrically connected via a first conductive layer, while the multiple second contact holes 42 are electrically connected via a second conductive layer. This allows leakage between two adjacent floating gates within any H-region to be detected. The presence of leakage indicates a problem with the flash memory product's manufacturing process, requiring prompt rework and rectification. One of the first and second contact holes is designed to connect to a high voltage, while the other is designed to connect to a low voltage. The high voltage range is 6V to 12V, while the low voltage is approximately 0V. The first contact hole in the dielectric layer is filled with a metal layer that serves as a first bonding pad, while the second contact hole in the dielectric layer is filled with a metal layer that serves as a second bonding pad. A first interconnect metal layer covers the dielectric layer and fills the first contact holes, interconnecting all first contact holes. A second interconnect metal layer covers the dielectric layer and fills the second contact holes, interconnecting all second contact holes. The first interconnection metal layer and the second interconnection metal layer can be formed by the same metal layer process, but are not connected to each other.

[0070] Each word line 31 is provided with floating gates, control gates CG1, and first spacers 33 stacked from bottom to top along the Z direction on both sides along the Y direction. A second spacer 34 may be formed later to cover the floating gates, control gates, and sidewalls of the first spacer 33.

[0071] In the same wafer, most of the wafer area is used to produce flash memory products, and a small part of the wafer area is used to produce the flash memory test structure of the present invention, which is used to monitor the manufacturing process of the flash memory product, especially to detect the leakage or breakdown voltage between the floating gates of two adjacent columns of memory cells in the H area.

[0072] The present invention also provides a flash memory test structure layout, which defines mutually perpendicular X and Y directions in a plane parallel to the substrate; the flash memory test structure layout is used to form the flash memory test structure introduced above.

[0073] The test structure layout of the flash memory, such as Figure 2 and Figure 8 Shown, including:

[0074] A floating gate layer, the floating gate layer comprising a plurality of parallel rows of floating gate pattern regions 30 extending in the X direction; each row of the floating gate pattern regions comprising a word line and floating gates and control gates stacked on both sides of the word line in the Y direction;

[0075] The active area layout layer includes multiple parallel columns of Y-direction active regions 21 extending along the Y direction, an X-direction active region 22 is provided between two adjacent columns of Y-direction active regions 21, and the X-direction active region 22 is connected to the Y-direction active regions 21 in adjacent areas on both sides to form an H region 20; directly above the H region 20 includes a first floating gate FG1 in the first storage cell located in the upper left corner, a second floating gate FG2 in the second storage cell located in the lower left corner, a third floating gate FG3 in the third storage cell located in the upper right corner, and a fourth floating gate FG4 in the fourth storage cell located in the lower right corner.

[0076] The control grid removal layer includes a plurality of sub-clearing areas C distributed along the X direction ( Figure 2 Green box), sub-clear regions C are located on both sides of the X-direction active region 22; the control gate material layer 80 of the sub-clear region C is etched away; the sub-clear region C exposes the floating gate connection region A, which includes a floating gate connection region 1 and a floating gate connection region 2; the floating gate connection region 1 is the connection region between the first floating gate FG1 and the second floating gate FG2 of the two adjacent rows of memory cells in the nth column directly above the H region, each close to the side of the X-direction active region 22; the floating gate connection region 2 is the connection region between the third floating gate FG3 and the fourth floating gate FG4 of the two adjacent rows of memory cells in the n+1th column directly above the H region, each close to the side of the X-direction active region 22.

[0077] Specific, combined Figure 2 、 Figure 7 and Figure 8 , using the control gate removal pattern layer as a mask to form a patterned first photoresist layer 51, when etching the gate of the logic area of ​​the flash memory on the same wafer, the control gate material layer 80 and the spacer layer 70 in the exposed area of ​​the first photoresist layer 51 in the test area where the test structure of the flash memory of the present invention is located (including the floating gate connection area A) can be etched away to form Figure 8 The control gate removal layer (including several sub-cleared areas C) is used to open all contact hole areas in the test area.

[0078] The contact hole plate layer includes: a first contact hole 41 and a second contact hole 42; wherein the sub-clear area C covers the first contact hole 41 and the second contact hole 42; the floating gate connection area 1 is led out through the first contact hole 41; and the floating gate connection area 2 is led out through the second contact hole 42; one of the first contact hole 41 and the second contact hole 42 is connected to a high voltage and the other is connected to a low voltage to test the leakage or breakdown voltage between the floating gates of two adjacent columns of memory cells in the H area.

[0079] The control gate contact aperture pattern layer includes several sub-reserved regions B distributed in strips along the Y direction. The floating gate material layer 60 in the sub-reserved regions B remains until the final state of the flash memory. One sub-reserved region B covers all first contact holes 41 in the same column, and another sub-reserved region B covers all second contact holes 42 in the same column. Specifically, the sub-reserved regions B cover all required contact holes in strips along the Y direction. When etching the control gate material layer 80 and floating gate material layer 60 in the normal flash memory area, the photoresist protects the floating gate material layer 60 in the sub-reserved regions B from being etched. The floating gate material layer 60 retained in the sub-reserved regions B is used for subsequent contact hole connections.

[0080] The embodiment of the present invention also provides a method for manufacturing a test structure of a flash memory, such as Figure 5 Shown, including:

[0081] S1. Providing a substrate, defining mutually perpendicular X and Y directions in a plane parallel to the substrate; forming a plurality of parallel columns of Y-direction active regions extending along the Y direction in the substrate, with an X-direction active region disposed between two adjacent columns of Y-direction active regions, and connecting the X-direction active region and the Y-direction active regions of adjacent regions on both sides to form an H region;

[0082] S2. forming a stacked layer comprising a floating gate material layer, a spacer layer, a control gate material layer, and a first spacer on the substrate in sequence; forming a plurality of parallel word lines extending along the X direction in the stacked layer;

[0083] S3, etching away the control gate material layer and the spacer layer located in the floating gate connection region; the floating gate connection region includes a floating gate connection region 1 and a floating gate connection region 2; the floating gate connection region 1 is a connection region between the first floating gate and the second floating gate of two adjacent rows of memory cells in the nth column directly above the H region, each close to the X-direction active region; the floating gate connection region 2 is a connection region between the third floating gate and the fourth floating gate of two adjacent rows of memory cells in the n+1th column directly above the H region, each close to the X-direction active region;

[0084] S4, etching the control gate material layer, the spacer layer and the floating gate material layer to form a floating gate and a control gate;

[0085] S5. Form a dielectric layer covering the word line, floating gate, and control gate, and etch a first contact hole and a second contact hole in the dielectric layer; the first contact hole leads to the first floating gate connection region, and the second contact hole leads to the second floating gate connection region.

[0086] The following describes in detail the steps of the method for manufacturing a flash memory test structure according to an embodiment of the present invention with reference to the accompanying drawings.

[0087] like Figure 6 and Figure 2 As shown, a substrate is provided, wherein an X-direction and a Y-direction perpendicular to each other are defined in a plane parallel to the substrate 10; a plurality of parallel columns of Y-direction active regions 21 extending along the Y-direction are formed in the substrate 10, an X-direction active region 22 is provided between two adjacent columns of Y-direction active regions 21, and the X-direction active region 22 is connected to the Y-direction active regions 21 in adjacent regions on both sides to form an H region 20;

[0088] A floating gate material layer 60, a spacer layer 70, a control gate material layer 80, and a first sidewall spacer are sequentially formed on the substrate. Multiple parallel rows of word lines 31 extending in the X direction are also formed on the substrate. The word lines 31 are located within the accommodation spaces formed by the floating gate material layer 60, the spacer layer 70, the control gate material layer 80, and the first sidewall spacer. A word line isolation layer 32 may also be formed on the surface of the word lines 31 to protect the word lines. The floating gate material layer 60 and the control gate material layer 80 can be formed by a deposition process, such as plasma chemical vapor deposition, low-pressure chemical vapor deposition, or sub-atmospheric pressure chemical vapor deposition. The spacer layer 70 is, for example, an ONO layer (a bottom oxide layer, a silicon nitride layer, and a top oxide layer).

[0089] like Figure 7 and Figure 2As shown, a first photoresist layer 51 is formed, which covers the word line 31 and exposes the floating gate connection region A. The floating gate connection region A includes a floating gate connection region 1 and a floating gate connection region 2. The floating gate connection region 1 is a connection region between the first floating gate FG1 and the second floating gate FG2 of the two adjacent rows of memory cells in the nth column directly above the H region, each close to the X-direction active region 22. The floating gate connection region 2 is a connection region between the third floating gate FG3 and the fourth floating gate FG4 of the two adjacent rows of memory cells in the n+1th column within the H region, each close to the X-direction active region.

[0090] like Figure 7 and Figure 8 As shown, the control gate material layer 80 and the spacer layer 70 located in the floating gate connection region A are etched away using the first photoresist layer 51 as a mask; thereafter, an ashing process may be used to remove the first photoresist layer 51 .

[0091] like Figure 9 As shown, a second photoresist layer 52 is formed, and the second photoresist layer 52 covers the word line 31 and the floating gate material layer 60 in the floating gate connection region A and the gap between two adjacent memory cells.

[0092] like Figure 10 As shown, the second photoresist layer 52 is used as a mask to etch away the exposed control gate material layer 80 , the spacer layer 70 and the floating gate material layer 60 to form a floating gate and a control gate; thereafter, the second photoresist layer 52 may be removed by an ashing process.

[0093] The present invention refines and changes the first photoresist layer 51 and the second photoresist layer 52. The first photoresist layer 51 and the second photoresist layer 52 already existed in the process before the improvement. The present invention achieves layout changes by refining and changing the first photoresist layer 51 and the second photoresist layer 52 without adding a new mask layer. The layout changes can realize the test structure of the flash memory of the present invention. Figure 11 As shown, a dielectric layer (not shown) is formed to cover the word line 31, the floating gate and the control gate, and a first contact hole 41 and a second contact hole (not shown) are etched in the dielectric layer; the first contact hole 41 leads to the floating gate connection area 1, and the second contact hole leads to the floating gate connection area 2.

[0094] In flash memory chips before the improvement, the floating gate is surrounded by a dielectric layer or covered by a control gate. The floating gate is not directly connected to the contact hole, and voltage cannot be applied directly to the floating gate. Generally, the potential on the floating gate is affected by the control gate potential, etc., so the floating gate potential is limited and cannot be higher.

[0095] The present invention directly connects the contact holes (i.e., the first contact hole 41 and the second contact hole) to the two bridged floating gates through a layout combination of mask levels, without adding mask levels or additional masks, and voltage can be directly applied to the floating gate through the contact holes. The potential on the floating gate is no longer affected by the control gate potential, etc., so the floating gate potential can be appropriately increased as needed.

[0096] In summary, the present invention provides a flash memory test structure and a method for fabricating the same, comprising: a substrate, multiple rows of parallel word lines extending in the X direction above the substrate, and multiple columns of parallel Y-direction active regions extending in the Y direction within the substrate. An X-direction active region is disposed between two adjacent columns of Y-direction active regions. The X-direction active region is connected to the Y-direction active regions of adjacent regions on either side to form an H region. Directly above the H region are a first floating gate located in the upper left corner, a second floating gate located in the lower left corner, a third floating gate located in the upper right corner, and a fourth floating gate located in the lower right corner. The first floating gate and the second floating gate of the two adjacent rows of memory cells in the nth column within the H region are connected and led out through the first contact hole; the third floating gate and the fourth floating gate of the two adjacent rows of memory cells in the n+1th column within the H region are connected and led out through the second contact hole; one of the first contact hole and the second contact hole is used to connect to a high voltage and the other is used to connect to a low voltage, which can effectively monitor the leakage or breakdown voltage between the floating gates of the memory cells in two adjacent columns within the H region; if problems are found, rework and rectification are carried out in time to avoid bit line BL failure and programming failure.

[0097] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The methods disclosed in the embodiments are described briefly because they correspond to the devices disclosed in the embodiments. For relevant details, refer to the method description.

[0098] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A flash memory test structure, characterized in that: include: a substrate, wherein an X direction and a Y direction perpendicular to each other are defined in a plane parallel to the substrate; A plurality of parallel word lines extending along the X direction are located above the substrate, wherein each word line has stacked floating gates and control gates on both sides along the Y direction; A plurality of parallel columns of Y-direction active regions extending along the Y-direction are located in the substrate, an X-direction active region is disposed between two adjacent columns of the Y-direction active regions, the X-direction active region and the Y-direction active regions of adjacent regions on both sides are connected to form an H region; directly above the H region are a first floating gate of a first memory cell located in the upper left corner, a second floating gate of a second memory cell located in the lower left corner, a third floating gate of a third memory cell located in the upper right corner, and a fourth floating gate of a fourth memory cell located in the lower right corner; The first floating gate and the second floating gate of the memory cells located in two adjacent rows of the nth column within the H region, each on a side close to the X-direction active region, are connected and led out through a first contact hole; and the third floating gate and the fourth floating gate of the memory cells located in two adjacent rows of the n+1th column within the H region, each on a side close to the X-direction active region, are connected and led out through a second contact hole. One of the first contact hole and the second contact hole is connected to a high voltage, and the other is connected to a low voltage, so as to test leakage or breakdown voltage between floating gates of two adjacent columns of memory cells in the H region.

2. The flash memory test structure according to claim 1, wherein: Reconstructed rows and columns are formed with the H regions as units, and the H regions are staggered in the reconstructed rows and columns.

3. The flash memory test structure according to claim 2, wherein: In the odd-numbered reconstruction columns, the H regions are distributed in the odd-numbered reconstruction rows, and in the even-numbered reconstruction columns, the H regions are distributed in the even-numbered reconstruction rows; Alternatively, in the even-numbered reconstruction columns, the H regions are distributed in the odd-numbered reconstruction rows, and in the odd-numbered reconstruction columns, the H regions are distributed in the even-numbered reconstruction rows.

4. The flash memory test structure according to claim 1, wherein: The test structure includes multiple H regions, each of which leads to one first contact hole and one second contact hole. The multiple first contact holes are electrically connected through a first conductor layer; the multiple second contact holes are electrically connected through a second conductor layer; and leakage between two adjacent columns of floating gates in any one of the H regions can be tested.

5. The flash memory test structure according to claim 1, wherein: One of the first contact hole and the second contact hole is used for receiving a high voltage, and the other is used for receiving a low voltage. The high voltage range is 6V to 12V; the low voltage is approximately 0V.

6. The flash memory test structure according to claim 1, wherein: The test structure includes the storage units arranged in an array; The test structure includes a plurality of parallel rows of floating gate pattern regions extending along the X direction; each row of the floating gate pattern regions includes the word line and the floating gates and control gates stacked on both sides of the word line in the Y direction; The overlapping area of ​​the Y-direction active area and the floating gate pattern area is the memory cell; The first contact hole is located in the gap between two adjacent columns of the Y-direction active regions; the second contact hole is also located in the gap between two adjacent columns of the Y-direction active regions.

7. A test structure layout for a flash memory, wherein an X direction and a Y direction perpendicular to each other are defined in a plane parallel to a substrate; characterized in that: include: A floating grid layer, the floating grid layer comprising a plurality of parallel rows of floating grid graphic areas extending along the X direction; Each row of the floating gate pattern area includes a word line and floating gates and control gates stacked on both sides of the word line in the Y direction; an active area layer, the active area layer comprising a plurality of parallel columns of Y-direction active areas extending along the Y-direction, an X-direction active area being disposed between two adjacent columns of the Y-direction active areas, the X-direction active area being connected to the Y-direction active areas of adjacent areas on both sides to form an H region; and directly above the H region comprising a first floating gate of a first storage cell located in the upper left corner, a second floating gate of a second storage cell located in the lower left corner, a third floating gate of a third storage cell located in the upper right corner, and a fourth floating gate of a fourth storage cell located in the lower right corner; a control gate removal plate layer, the control gate removal plate layer comprising a plurality of sub-clearance regions distributed along the X-direction, the sub-clearance regions being located on both sides of the X-direction active region; the control gate material layer in the sub-clearance regions being etched away; the sub-clearance regions exposing floating gate connection regions, the floating gate connection regions comprising a first floating gate connection region and a second floating gate connection region; the first floating gate connection region being a connection region between the first floating gate and the second floating gate of two adjacent rows of memory cells in the nth column directly above the H region, each adjacent to the X-direction active region; and the second floating gate connection region being a connection region between the third floating gate and the fourth floating gate of two adjacent rows of memory cells in the n+1th column directly above the H region, each adjacent to the X-direction active region. A contact hole plate layer, the contact hole plate layer comprising: a first contact hole and a second contact hole; wherein the sub-cleared area covers the first contact hole and the second contact hole; the first floating gate connection area is led out through the first contact hole; and the second floating gate connection area is led out through the second contact hole; one of the first contact hole and the second contact hole is connected to a high voltage and the other is connected to a low voltage, so as to test the leakage or breakdown voltage between the floating gates of the memory cells in two adjacent columns in the H region; A control gate contact hole plate layer, wherein the control gate contact hole plate layer includes a plurality of sub-reserved areas distributed in strips along the Y direction, and the floating gate material layer of the sub-reserved areas is retained until the final state; the sub-reserved areas cover all the first contact holes in the same column and cover all the second contact holes in the same column.

8. A method for manufacturing a test structure of a flash memory, characterized in that: include: S1. Providing a substrate, defining mutually perpendicular X and Y directions in a plane parallel to the substrate; forming a plurality of parallel columns of Y-direction active regions extending along the Y direction in the substrate, an X-direction active region being disposed between two adjacent columns of the Y-direction active regions, and the X-direction active region and the Y-direction active regions in adjacent regions on both sides being connected to form an H region; S2. forming a stacked layer comprising a floating gate material layer, a spacer layer, a control gate material layer, and a first spacer on the substrate in sequence; and forming a plurality of parallel word lines extending along the X direction in the stacked layer; S3, etching away the control gate material layer and the spacer layer located in the floating gate connection region; the floating gate connection region includes a floating gate connection region 1 and a floating gate connection region 2; the floating gate connection region 1 is a connection region between the first floating gate and the second floating gate of the memory cells in the nth column and the adjacent rows located directly above the H region, each close to the X-direction active region; the floating gate connection region 2 is a connection region between the third floating gate and the fourth floating gate of the memory cells in the n+1th column and the adjacent rows located directly above the H region, each close to the X-direction active region; S4, etching the control gate material layer, the spacer layer, and the floating gate material layer to form a floating gate and a control gate; S5. Form a dielectric layer covering the word line, the floating gate, and the control gate, and etch a first contact hole and a second contact hole in the dielectric layer; the first contact hole leads to the first floating gate connection region, and the second contact hole leads to the second floating gate connection region.

9. The method for manufacturing a flash memory test structure according to claim 8, wherein: Step S3 specifically includes: S31, forming a first photoresist layer, wherein the first photoresist layer covers the word line and exposes the floating gate connection region; S32, using the first photoresist layer as a mask, etching and removing the control gate material layer and the spacer layer located in the floating gate connection region; S33 , removing the first photoresist layer by an ashing process.

10. The method for manufacturing a flash memory test structure according to claim 8, wherein: Step S4 specifically includes: S41, forming a second photoresist layer, wherein the second photoresist layer covers the word line, the floating gate material layer in the floating gate connection region, and a gap between two adjacent memory cells; S42, using the second photoresist layer as a mask, etching and removing the exposed control gate material layer, the spacer layer, and the floating gate material layer to form the floating gate and the control gate; S43 , removing the second photoresist layer by an ashing process.

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