Semiconductor structure and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure and electronic equipment. The semiconductor structure comprises a plurality of sensing amplification circuits arranged along a first direction; devices in the sensing amplification circuit are arranged on the active device layer. The plurality of wire groups are arranged along the first direction, the wire groups are arranged on the first conductive layer above the active device layer, and one wire group is connected with a device in the corresponding sensing amplification circuit; wherein the wire group comprises a first wire and a second wire; the first wires and the second wires in the same wire group corresponding to at least part of the sensing amplifier circuit are twisted, so that at least part of the second wires are positioned among the first wires in different wire groups; when the sensing amplification circuit is in an amplification stage, the potential of the first wire and the potential of the second wire in the same wire group represent different data.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and is related to but not limited to a semiconductor structure and electronic equipment. Background Art

[0002] A memory typically includes a sensing amplifier circuit and an equalization circuit. After charge sharing occurs between the storage capacitor and the bit line, a voltage difference forms between the bit line and its complementary bit line. The sensing amplifier circuit amplifies this voltage difference to convert the data stored on the storage capacitor into a voltage corresponding to a logic 1 or 0, which is then displayed on the bit line. Furthermore, after a read operation, a write-back operation restores the charge on the storage capacitor to its pre-read state, and the equalization circuit restores the potentials on the bit line and complementary bit line to their pre-charge sharing states.

[0003] When the distance between different bit lines is very close and the timing is inconsistent, signal coupling will occur between them. Signal coupling will not only cause crosstalk between signals, but also affect the stability of signal transmission of the entire chip. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and an electronic device.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, comprising:

[0006] A plurality of sensing amplifier circuits are arranged along a first direction; the devices in the sensing amplifier circuits are arranged in an active device layer;

[0007] a plurality of conductive line groups arranged along the first direction, the conductive line groups being disposed in a first conductive layer above the active device layer, wherein one conductive line group is connected to a corresponding device in the sensing amplifier circuit;

[0008] The wire group includes a first wire and a second wire; the first wire and the second wire within the same wire group corresponding to at least a portion of the sense amplifier circuit are twisted so that at least a portion of the second wire is located between first wires in different wire groups; when the sense amplifier circuit is in an amplification phase, the potential of the first wire and the potential of the second wire within the same wire group represent different data;

[0009] The first direction and the second direction are two intersecting directions on the plane where the semiconductor structure is located.

[0010] In some embodiments, the semiconductor structure further includes: a memory array located on both sides of the plurality of sense amplifier circuits along the second direction;

[0011] The conductive line group includes a sensing line, a complementary sensing line, a bit line, and a complementary bit line; the bit line comes from the memory array on the first side, and the complementary bit line comes from the memory array on the second side; the sensing line is used to transmit data to the bit line, and the complementary sensing line is used to transmit data to the complementary bit line;

[0012] The first conductive line is one of the bit line, the complementary bit line, the sensing line, or the complementary sensing line, and the second conductive line is one of the sensing line or the complementary sensing line.

[0013] In some embodiments, the plurality of sensing amplifier circuits are divided into a plurality of sensing amplifier circuit groups, each of the sensing amplifier circuit groups including two non-overlapping sensing amplifier circuits arranged along the first direction;

[0014] The wire groups corresponding to the two sensing amplifier circuits in the same sensing amplifier circuit group are respectively a first wire group and a second wire group;

[0015] The first portion of the first conductive wire group and the first portion of the second conductive wire group are mirror-symmetrical along the second direction, and the second portion of the first conductive wire group overlaps with the second portion of the second conductive wire group after translation along the first direction;

[0016] or,

[0017] The first conductor group is translated along the first direction and overlaps with the second conductor group;

[0018] or,

[0019] The first conductive line group and the second conductive line group are mirror-symmetrical along the second direction.

[0020] In some embodiments, for the first conductive line group, the first end of the sensing line is located on a side of the first end of the complementary bit line away from the second conductive line group; the first end of the sensing line refers to an end of the sensing line close to the complementary bit line, and the first end of the complementary bit line refers to an end of the complementary bit line away from the sensing line;

[0021] The sensing lines in the second conductive line group are mirror-symmetrical to the sensing lines in the first conductive line group.

[0022] In some embodiments, the first conductive layer is a single conductive layer, the first conductive line is a complementary bit line, and the second conductive line is a sensing line.

[0023] In some embodiments, the sensing line of the first conductive line group includes a first sub-segment, a second sub-segment, and a third sub-segment; the complementary bit line of the first conductive line group includes a fourth sub-segment and a fifth sub-segment; the first sub-segment to the fifth sub-segment all extend along the second direction;

[0024] The first sub-segment, the fifth sub-segment and the third sub-segment are arranged in sequence along the second direction;

[0025] The fourth sub-segment, the second sub-segment and the complementary sensing lines of the first conductive line group are arranged in sequence along the second direction;

[0026] The third sub-segment and the complementary sensing wires of the first conductive line group are arranged adjacent to each other along the first direction;

[0027] The first sub-segment is located on a side of the fourth sub-segment away from the second wire group;

[0028] The second conductive line group and the first conductive line group are mirror-symmetrical.

[0029] In some embodiments, the complementary sensing lines of the first conductive line group, the complementary bit lines of the third conductive line group, the complementary bit lines of the fourth conductive line group, and the complementary sensing lines of the second conductive line group are sequentially arranged along the first direction;

[0030] The sensing amplifier circuit corresponding to the third wire group and the sensing amplifier circuit corresponding to the first wire group respectively belong to the sensing amplifier circuit groups adjacent to each other along the second direction, and the sensing amplifier circuit corresponding to the fourth wire group and the sensing amplifier circuit corresponding to the second wire group respectively belong to the sensing amplifier circuit groups adjacent to each other along the second direction.

[0031] In some embodiments, the first sub-segment and the second sub-segment are connected through a connection structure of the same conductive layer, and the second sub-segment and the third sub-segment are connected through a connection structure of the same conductive layer;

[0032] The fourth sub-segment and the fifth sub-segment are connected via a connection structure spanning different conductive layers or via a gate layer.

[0033] In some embodiments, the first conductive layer includes a first conductive sublayer and a second conductive sublayer stacked along a third direction;

[0034] The sensing lines and the complementary sensing lines of the same wire group are twisted, and the third direction is perpendicular to the plane where the semiconductor structure is located.

[0035] In some embodiments, the sense line of the second conductive line group is twisted with the complementary bit line of the second conductive line group.

[0036] In some embodiments, the complementary bit lines, sense lines, and at least a portion of the complementary sense lines of the first conductive line group and the complementary bit lines, sense lines, and at least a portion of the complementary sense lines of the second conductive line group are all located in the first conductive sublayer;

[0037] The sensing line of the first conductive line group includes a first subsegment and a second subsegment, the complementary sensing line of the first conductive line group includes a third subsegment and a fourth subsegment, the sensing line of the second conductive line group includes a fifth subsegment, a sixth subsegment, and a seventh subsegment, the complementary sensing line of the second conductive line group includes an eighth subsegment and a ninth subsegment, and the complementary bit line of the second conductive line group includes a tenth subsegment and an eleventh subsegment; the first to eleventh subsegments all extend along the second direction;

[0038] The third sub-segment and the second sub-segment are aligned along the second direction;

[0039] The first sub-segment, the fourth sub-segment, and the complementary bit lines of the first conductive line group are aligned along the second direction;

[0040] The eighth sub-segment, the sixth sub-segment, and the tenth sub-segment are aligned along the second direction;

[0041] The fifth sub-segment, the ninth sub-segment, the eleventh sub-segment and the seventh sub-segment are aligned along the second direction;

[0042] The third sub-segment, the first sub-segment, the eighth sub-segment and the fifth sub-segment are arranged in sequence along the first direction;

[0043] The second sub-segment, the fourth sub-segment, the sixth sub-segment, and the ninth sub-segment are arranged in sequence along the first direction.

[0044] In some embodiments, the complementary bit lines of the third conductive line group and the complementary bit lines of the fourth conductive line group are located in the second conductive sublayer;

[0045] The projections of the complementary bit lines of the third conductive line group and the complementary bit lines of the first conductive line group along the third direction at least partially overlap; the projections of the complementary bit lines of the fourth conductive line group and the complementary bit lines of the second conductive line group along the third direction at least partially overlap;

[0046] The sensing amplifier circuit corresponding to the third wire group and the sensing amplifier circuit corresponding to the first wire group respectively belong to the sensing amplifier circuit groups adjacent to each other along the second direction, and the sensing amplifier circuit corresponding to the fourth wire group and the sensing amplifier circuit corresponding to the second wire group respectively belong to the sensing amplifier circuit groups adjacent to each other along the second direction.

[0047] In some embodiments, the first sub-segment and the second sub-segment are connected through a connection structure of the same conductive sub-layer, the fifth sub-segment and the sixth sub-segment are connected through a connection structure of the same conductive layer; and the sixth sub-segment and the seventh sub-segment are connected through a connection structure of the same conductive layer.

[0048] The third sub-segment and the fourth sub-segment are connected via a connection structure spanning different conductive layers or via a gate layer;

[0049] The eighth sub-segment and the ninth sub-segment are connected via a connection structure spanning different conductive layers or via the gate layer;

[0050] The tenth sub-segment and the eleventh sub-segment are connected via a connection structure spanning different conductive layers or via the gate layer.

[0051] In some embodiments, a projection of the first sub-segment in the third direction is located on an N-type amplifier transistor of the sense amplifier circuit;

[0052] A projection of the fifth subsegment in the third direction is located on a bias cancellation transistor or a precharge transistor of the sense amplifier circuit.

[0053] In some embodiments, the projection of the seventh subsegment in the third direction is located on the N-type amplifier transistor of the sense amplifier circuit;

[0054] The projection of the eleventh subsegment in the third direction is located on the isolation transistor or the pre-charge transistor of the sense amplifier circuit;

[0055] Projections of the fourth sub-segment and the ninth sub-segment in the third direction are located on the P-type amplifier tube of the sense amplifier circuit.

[0056] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure as described in any one of the above embodiments.

[0057] Embodiments of the present disclosure provide a semiconductor structure and electronic device. The semiconductor structure includes: a plurality of sensing amplifier circuits arranged along a first direction; devices in the sensing amplifier circuits are disposed in an active device layer; a plurality of conductive wire groups arranged along the first direction, each conductive wire group disposed in a first conductive layer above the active device layer, each conductive wire group being connected to a device in a corresponding sensing amplifier circuit; a conductive wire group including a first conductive wire and a second conductive wire; first conductive wires and second conductive wires within the same conductive wire group corresponding to at least a portion of the sensing amplifier circuits are twisted such that at least a portion of the second conductive wire is located between first conductive wires in different conductive wire groups; and when the sensing amplifier circuit is in an amplification phase, the potential of the first conductive wire and the potential of the second conductive wire within the same conductive wire group represent different data.

[0058] Here, since both the first and second wires extend along the second direction, and the first and second wires within the same wire group are twisted, at least a portion of the second wire is located between first wires in different wire groups. Furthermore, since, when the sensing amplifier circuit is in the amplification stage, the voltage of the first wire of another group affects the voltage of the first and second wires in the current wire group, i.e., simultaneously raises or lowers the voltage of the first and second wires in the current wire group, this helps to avoid a reduction in the voltage difference between the first and second wires in the current wire group due to affecting only the voltage of the first wire (or second wire) in the current wire group, thereby ensuring that the sensing amplifier circuit can effectively amplify data. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0060] Figure 1 Schematic diagram of the layout structure of the wire group provided in the embodiment of the present disclosure Figure 1 ;

[0061] Figure 2 A schematic diagram of the layout structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0062] Figure 3 A schematic diagram of the structure of a sensing amplifier circuit provided in an embodiment of the present disclosure;

[0063] Figure 4 Schematic diagram of the layout structure of the wire group provided in the embodiment of the present disclosure Figure 2 ;

[0064] Figure 5 Schematic diagram of the layout structure of the wire group provided in the embodiment of the present disclosure Figure 3 ;

[0065] Figure 6 Schematic diagram of the layout structure of the wire group provided in the embodiment of the present disclosure Figure 4 ;

[0066] Figure 7 Schematic diagram of the layout structure of the wire group provided in the embodiment of the present disclosure Figure 5 ;

[0067] Figure 8 Schematic diagram of the layout structure of the wire group provided in the embodiment of the present disclosure Figure 6 ;

[0068] Figure 9Schematic diagram of the layout structure of the wire group provided in the embodiment of the present disclosure Figure 7 ;

[0069] Figure 10 Schematic diagram of the layout structure of the wire group provided in the embodiment of the present disclosure Figure 8 ;

[0070] Figure 11 Schematic diagram of the layout structure of the wire group provided in the embodiment of the present disclosure Figure 9 ;

[0071] Figure 12 A schematic diagram of the layout structure of various components in the sensing amplifier circuit provided in an embodiment of the present disclosure;

[0072] Figure 13 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0073] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0074] In the following description, numerous details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0075] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0076] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0077] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0078] Before introducing the embodiments of the present disclosure, we first define the three directions that may be used in describing the three-dimensional structure in the following embodiments. These three directions may include a first (X-axis), a second (Y-axis), and a third (Z-axis). The Z-axis may be a direction perpendicular to the plane in which the semiconductor structure resides. The X-axis and Y-axis are two mutually perpendicular directions on the plane in which the semiconductor structure resides, wherein the Y-axis may be the direction in which the first conductive line extends.

[0079] The present disclosure provides a semiconductor structure 100, such as Figure 1 and Figure 2 As shown, the semiconductor structure 100 includes: a plurality of sensing amplifier circuits SA arranged along the X-axis direction (refer to Figure 2 ); the devices in the sensing amplifier circuit SA (Sensing Amplifier Circuit) are arranged in the active device layer; a plurality of wire groups 110 arranged along the X-axis direction (refer to Figure 1), a wire group 110 is disposed in a first conductive layer above the active device layer, and a wire group 110 is connected to a device in a corresponding sensing amplifier circuit SA; wherein the wire group 110 includes a first wire 111 and a second wire 112, and the first wire 111 and the second wire 112 both extend along the Y-axis direction; the first wire 111 and the second wire 112 within the same wire group 110 are twisted so that at least a portion of the second wire 112 is located between the first wires 111 in different wire groups 110; when the sensing amplifier circuit SA is in the amplification stage, the potential of the first wire 111 and the potential of the second wire 112 in the same wire group represent different data.

[0080] It should be noted that Figure 1 Components in the sense amplifier circuit SA are not shown; only the first conductive line 111 and the second conductive line 112 in one conductive line group 110 and the first conductive line 111 in the adjacent conductive line group 110 are shown.

[0081] In the disclosed embodiment, the active device layer is the core functional layer of the semiconductor structure 100. The devices in the sense amplifier circuit SA include active elements such as transistors, for example, N-type amplifiers and P-type amplifiers. The first conductive layer can be the first metal layer (Metal 1, M1) in the semiconductor structure 100. The first metal layer is the metal layer closest to the active device layer and is used for signal transmission and routing. The conductive line group 110 disposed in the first conductive layer can connect the ports of different devices in the sense amplifier circuit SA (such as the source, drain, and gate of the transistor) to higher-level metal wiring (such as the second metal layer, Metal 2, M2). The second metal layer is another metal layer located above and closest to the first metal layer.

[0082] In this disclosure, please continue to refer to Figure 1 The phrase "both the first conductor 111 and the second conductor 112 extend in the Y-axis direction" means that the majority of the first conductor 111 and the second conductor 112 extend in the Y-axis direction, but not every portion of the first conductor 111 and the second conductor 112 extends in the Y-axis direction. In other words, the first conductor 111 and the second conductor 112 may have portions extending in the X-axis or Z-axis direction due to routing, winding, or jumpering. For example, within the same conductor assembly 110, the first conductor 111 may extend in the Y-axis direction, then extend in the X-axis direction to jumper to the second conductor 112, and then extend in the Y-axis direction again.

[0083] In this disclosure, please continue to refer to Figure 1The twisting of the first wire 111 and the second wire 112 within the same wire group 110 means that the first wire 111 and the second wire 112 within the same wire group 110 periodically exchange left and right positions along their extension paths, or in other words, exchange paths with each other at least once (similar to the DNA double helix structure); for example, within the same wire group 110, the second wire 112 jumps to the path of the first wire 111 along its extension path, and at the same time, the first wire 111 jumps to the path of the second wire 112 along its extension path.

[0084] In addition, please continue to refer to the embodiment of this disclosure. Figure 1 At least part of the second wire 112 is located between the first wires 111 in different wire groups 110, which means that at least part of the second wire 112 is located between the first wire 111 in the wire group 110 where the second wire 112 is located and the first wire 111 in another wire group.

[0085] It should be noted that in the embodiment of the present disclosure, different wire groups 110 correspond to different memory cells, and their data may be the same or different. Because the first wire 111 and the second wire 112 in the same wire group 110 represent different data, the first wire 111 can be a bit line or an internal wiring connected to the bit line in the sense amplifier circuit SA, and the second wire 112 can be a complementary bit line or an internal wiring connected to the complementary bit line in the sense amplifier circuit SA. In this case, because at least a portion of the second wire 112 is located between first wires 111 in different groups, the voltage of the first wire 111 in the other group will affect the voltage of the first wire 111 and the second wire 112 in the current wire group, that is, simultaneously increase or decrease the voltage of the first wire 111 and the second wire 112 in the current wire group. This helps avoid reducing the voltage difference between the first wire 111 and the second wire 112 in the current wire group due to affecting only the voltage of the first wire 111 (or the second wire 112) in the current wire group, thereby ensuring that the sense amplifier circuit can effectively amplify data.

[0086] Next, please refer to Figures 2 to 12 , the semiconductor structure 100 is introduced in detail.

[0087] In some embodiments, please refer to Figure 2 and Figure 3The semiconductor structure 100 further includes: a memory array 120 located on both sides of the plurality of sense amplifier circuits SA along the Y-axis; a conductive line group 110 including a sense line SABL, a complementary sense line SABLB, a bit line BL, and a complementary bit line BLB; the bit line BL originates from the memory array 120 on the first side, and the complementary bit line BLB originates from the memory array 120 on the second side; the sense line SABL is used to transmit data to the bit line BL, and the complementary sense line SABLB is used to transmit data to the complementary bit line BLB; a first conductive line 111 is one of the bit line BL, the complementary bit line BLB, the sense line SABL, or the complementary sense line SABLB; and a second conductive line 112 is one of the sense line SABL or the complementary sense line SABLB. When the sense amplifier circuit SA is in the amplification phase, the potential of the first conductive line 111 and the potential of the second conductive line 112 represent different data.

[0088] In the embodiment of the present disclosure, the memory array 120 has n rows and m columns of memory cells, each of which is used to store 1 bit of data, that is, a memory array 120 can store n×m bits of data; after a word line is selected, a specific memory cell is selected by selecting the switch unit corresponding to the column address, and data stored in the memory cell is read out or data is written to the memory cell; wherein n and m are positive integers.

[0089] It should be noted that Figure 2 Only two memory arrays 120 arranged along the Y-axis direction and a plurality of sense amplifier circuits SA located between the two memory arrays 120 are shown (two rows are shown, with four sense amplifier circuits in each row as an example); in fact, the semiconductor structure 100 may include a plurality of memory arrays 120 arranged along the Y-axis direction, with a plurality of sense amplifier circuits SA between adjacent memory arrays 120 (for example, two rows along the Y-axis direction, with 256 sense amplifier circuits SA in each row). In addition, Figure 2 The figure also schematically shows word lines WL connected to the memory array 120.

[0090] For further information, please refer to Figure 2 The sensing amplifier circuit SA is coupled to the memory array 120 on the first side through the bit line BL and to the memory array 120 on the second side through the complementary bit line BLB, and is used to sense the voltage of the memory cell and output a logic 1 or 0 corresponding to the voltage.

[0091] In some embodiments, the devices in the sensing amplifier circuit SA include: a sensing amplifier module, connected to the bit line BL through the sensing line SABL, connected to the complementary bit line BLB through the complementary sensing line SABLB, for sensing the voltage of the storage cell in the storage array and outputting a logic 1 or 0 corresponding to the voltage.

[0092] For details, please continue to refer to Figure 3 The sensing amplifier module includes: a first N-type amplifier tube M7, a second N-type amplifier tube M8, a first P-type amplifier tube M1, and a second P-type amplifier tube M2. The gate of the first N-type amplifier tube M7 is connected to the bit line BL, the drain of the first N-type amplifier tube M7 is connected to the complementary sensing line SABLB, and the source of the first N-type amplifier tube is connected to the second signal terminal NCS. When the sensing amplifier module is in the amplification phase, the second signal terminal NCS is electrically connected to the voltage corresponding to a logic 0. The gate of the second N-type amplifier tube M8 is connected to the complementary bit line BLB, the drain of the second N-type amplifier tube M8 is connected to the sensing line SABL, and the source of the second N-type amplifier tube M8 is connected to the second signal terminal NCS. The first N-type amplifier tube M7 and the second N-type amplifier tube M8 are both NMOS (Negative channel Metal Oxide Semiconductor) transistors. The gate of the first P-type amplifier transistor M1 is connected to the sensing line SABL, the drain of the first P-type amplifier transistor M1 is connected to the complementary sensing line SABLB, and the source of the first P-type amplifier transistor M1 is connected to the first signal terminal PCS. When the sensing amplifier module is in the amplification phase, the first signal terminal PCS is electrically connected to the voltage corresponding to a logic 1. The gate of the second P-type amplifier transistor M2 is connected to the complementary sensing line SABLB, the drain of the second P-type amplifier transistor M2 is connected to the sensing line SABL, and the source of the second P-type amplifier transistor M2 is connected to the first signal terminal PCS. Both the first P-type amplifier transistor M1 and the second P-type amplifier transistor M2 are PMOS (Positive Channel Metal Oxide Semiconductor) transistors.

[0093] In some embodiments, the device in the sensing amplifier circuit SA further includes: an isolation module, connected between the sensing line SABL and the bit line BL, and connected between the complementary sensing line SABLB and the complementary bit line BLB, for isolating or turning on the potential change between the bit line BL and the sensing line SABL according to the isolation signal iso, and isolating or turning on the potential change between the complementary bit line BLB and the complementary sensing line SABLB.

[0094] For details, please continue to refer to Figure 3 The isolation module includes a first isolation transistor M3 and a second isolation transistor M4. The gate of the first isolation transistor M3 is configured to receive an isolation signal iso, the source of the first isolation transistor M3 is connected to the bit line BL, and the drain of the first isolation transistor M3 is connected to the sensing line SABL. The gate of the second isolation transistor M4 is configured to receive an isolation signal iso, the source of the second isolation transistor M4 is connected to the complementary bit line BLB, and the drain of the second isolation transistor M4 is connected to the complementary sensing line SABLB.

[0095] In some embodiments, the devices in the sensing amplifier circuit SA further include: a bias cancellation module, connected between the sensing line SABL and the complementary bit line BLB, and connected between the complementary sensing line SABLB and the bit line BL, for eliminating the threshold voltage deviation between the first N-type amplifier tube M7 and the second N-type amplifier tube M8 in the sensing amplifier module according to the bias cancellation signal Oc.

[0096] For details, please continue to refer to Figure 3 The bias cancellation module includes a first bias cancellation transistor M5 and a second bias cancellation transistor M6. The gate of the first bias cancellation transistor M5 is configured to receive a bias cancellation signal Oc, the source of the first bias cancellation transistor M5 is connected to the bit line BL, and the drain of the first bias cancellation transistor M5 is connected to the complementary sensing line SABLB. The gate of the second bias cancellation transistor M6 is configured to receive a bias cancellation signal Oc, the source of the second bias cancellation transistor M6 is connected to the complementary bit line BLB, and the drain of the second bias cancellation transistor M6 is connected to the sensing line SABL.

[0097] In some embodiments, please refer to Figure 3 The semiconductor structure further includes: a first column select transistor M10 and a second column select transistor M11; wherein the first column select transistor M10 is disposed between the local data line LIO and the bit line BL; the gate of the first column select transistor M10 is configured to receive a select signal CSL, the source of the first column select transistor M10 is connected to the bit line BL, and the drain of the first column select transistor M10 is connected to the local data line LIO. The second column select transistor M11 is disposed between the local complementary data line LION and the complementary bit line BLB; the gate of the second column select transistor M11 is configured to receive a select signal CSL, the source of the second column select transistor M11 is connected to the complementary bit line BLB, and the drain of the second column select transistor M11 is connected to the local complementary data line LION.

[0098] In some embodiments, the device in the sensing amplifier circuit SA further includes: a pre-charge transistor M9; wherein the drain of the pre-charge transistor M9 is connected to the sensing line SABL and / or the complementary sensing line SABLB, and the gate of the pre-charge transistor M9 is used to receive the pre-charge signal PreEO, and when the pre-charge signal PreEO is activated (for example, at a high level), the pre-charge transistor M9 is turned on to provide a pre-charge voltage Vad2 to the sensing line SABL or the complementary sensing line SABLB.

[0099] In the embodiment of the present disclosure, the first conductive line 111 is one of the bit line BL, the complementary bit line BLB, the sensing line SABL, or the complementary sensing line SABLB, and the second conductive line 112 is one of the sensing line SABL or the complementary sensing line SABLB. At the same time, when the sensing amplifier circuit SA is in the amplification stage, the potential of the first conductive line 111 and the potential of the second conductive line 112 represent different data.

[0100] For example, when the first conductive line 111 is a complementary bit line BLB, the second conductive line 112 can be a sensing line SABL; for another example, when the first conductive line 111 is a bit line BL, the second conductive line 112 can be a complementary sensing line SABLB; for another example, the first conductive line 111 can also be a sensing line SABL, and the second conductive line 112 can also be a complementary sensing line SABLB; and so on. In this way, the voltage of the first conductive line 111 of another group can simultaneously affect the voltage of the first conductive line 111 and the second conductive line 112 in the current conductive line group, that is, simultaneously increase or decrease the voltage of the first conductive line 111 and the second conductive line 112 in the current conductive line group. This helps avoid reducing the voltage difference between the first conductive line 111 and the second conductive line 112 in the current conductive line group due to affecting only the voltage of the first conductive line 111 (or the second conductive line 112) in the current conductive line group, thereby ensuring that the sense amplifier circuit can effectively amplify data.

[0101] In some embodiments, please refer to Figure 2 The plurality of sensing amplifier circuits SA are divided into a plurality of sensing amplifier circuit groups 130. Each sensing amplifier circuit group 130 includes two non-overlapping sensing amplifier circuits SA arranged along the X-axis direction. The two sensing amplifier circuits SA in the same sensing amplifier circuit group 130 correspond to the first conductive line group 110a and the second conductive line group 110b, respectively.

[0102] For example, please refer to Figure 2 , the sensing amplifier circuits SA1 and SA2 can form a sensing amplifier circuit group 130; while referring to Figure 4 The wire group 110 corresponding to the sensing amplifier circuit SA1 serves as the first wire group 110 a , and the wire group 110 corresponding to the sensing amplifier circuit SA2 serves as the second wire group 110 b .

[0103] In some embodiments, please refer to Figure 4 or Figure 5 The first conductive line group 110a and the second conductive line group 110b are mirror-symmetrical along the Y-axis direction.

[0104] For example, see Figure 4 or Figure 5The first conductive line 111a and the second conductive line 112b in the first conductive line group 110a are mirror-symmetrical with the first conductive line 111b and the second conductive line 112b in the second conductive line group 110b along the Y-axis direction.

[0105] In some embodiments, please refer to Figure 6 or Figure 7 , the first wire group 110a is translated along the X-axis direction and overlaps with the second wire group 110b.

[0106] For example, see Figure 6 or Figure 7 After the first wire 111a and the second wire 112b in the first wire group 110a are translated along the X-axis direction, they overlap with the first wire 111b and the second wire 112b in the second wire group 110b.

[0107] In some embodiments, please refer to Figure 8 The first part of the first wire group 110a and the first part of the second wire group 110b are mirror-symmetrical along the Y-axis direction, and the second part of the first wire group 110a overlaps with the second part of the second wire group 110b after being translated along the X-axis direction.

[0108] For example, see Figure 8 The first portion of first wire group 110a and the first portion of second wire group 110b are located in region A. In region A, first wire 111a and second wire 112b in first wire group 110a are mirror-symmetric with first wire 111b and second wire 112b in second wire group 110b along the Y-axis. The second portion of first wire group 110a and the second portion of second wire group 110b are located in region B. In region B, first wire 111a and second wire 112b in first wire group 110a, after translation along the X-axis, overlap with first wire 111b and second wire 112b in second wire group 110b.

[0109] It should be noted that Figure 8 1 , the first wire 111a and the second wire 112b in the first wire group 110a are referred to as BLB1 and SABL1, respectively, and the first wire 111b and the second wire 112b in the second wire group 110b are referred to as BLB2 and SABL2, respectively. In some other embodiments, the first wire 111a and the second wire 112b in the first wire group 110a may be referred to as SABL1 and SABLB1, respectively, and the first wire 111b and the second wire 112b in the second wire group 110b may be referred to as SABL2 and SABLB2, respectively.

[0110] In some embodiments, the first conductive layer is a single conductive layer (eg Figure 4 or Figure 6The first conductive line 111 is a complementary bit line BLB, and the second conductive line 112 is a sensing line SABL.

[0111] In some embodiments, please refer to Figure 4 or Figure 6 For the first wire group 110a, the first end of the sensing line SABL1 (as shown in area C) is located on the side of the first end of the complementary bit line BLB1 (as shown in area D) away from the second wire group 110b; the first end of the sensing line SABL1 refers to the end of the sensing line SABL1 close to the complementary bit line BLB1, and the first end of the complementary bit line BLB1 refers to the end of the complementary bit line BLB1 away from the sensing line SABL1.

[0112] In some embodiments, please combine Figure 2 ,as well as Figure 4 or Figure 6 The regions between the two memory arrays 120 are, in order, the BLSA region (bit line sensing area), the LIOSA region (local data line sensing area), and the BLSA region. That is, the BLSA region is located between the memory array 120 and the LIOSA region. The BLSA region is equipped with a sense amplifier for amplifying the voltage difference between a bit line and a complementary bit line, while the LIOSA region is equipped with a sense amplifier for amplifying the voltage difference between a local data line and a local complementary data line. The first end of the sense line SABL1 (shown in region C) is closer to the adjacent memory array 120, rather than to the local data line sensing area. The first end of the complementary bit line BLB1 (shown in region D) is closer to the adjacent memory array 120, rather than to the local data line sensing area.

[0113] In some embodiments, please refer to Figure 4 or Figure 6 The first end (as shown in area C) and the second end (not shown) of the sensing line SABL1 are aligned in the Y-axis direction, or are in the same line parallel to the Y-axis; wherein the second end of the sensing line SABL1 refers to the end opposite to the first end of the sensing line SABL1.

[0114] In some embodiments, please refer to Figure 4 or Figure 6 The wire groups also include complementary sensing lines. For the complementary sensing line SABLB1 in the first wire group 110a, it is located between the sensing line SABL1 and the sensing line SABL2 (or complementary sensing line SABLB2) in the other wire group 110b. The first end (as shown in region C) and the second end of the sensing line SABL1 are located on the side of the complementary sensing line SABLB1 away from the second wire group 110b.

[0115] It should be noted that the lanes mentioned in this disclosure refer to the linear space extending along the Y-axis direction, and different lanes are arranged along the X-direction. Figures 4 to 8 as well as Figure 11 In the description, the lines in the four lanes are described, and in Figure 9 and Figure 10 In the figure, the routing within the six lanes is described.

[0116] In some embodiments, please refer to Figure 4 The sensing line SABL1 in the first conductive line group 110a is mirror-symmetrical to the sensing line SABL2 in the second conductive line group 110b. Figure 6 After the sensing line SABL1 in the first conductive line group 110a is translated along the X-axis direction, it overlaps with the sensing line SABL2 in the second conductive line group 110b.

[0117] In some embodiments, the first conductive layer includes first conductive sublayers stacked along the Z-axis direction (eg, Figure 8 The first conductive line 111 refers to the complementary bit line BLB, the second conductive line 112 refers to the sensing line SABL, and the complementary bit line BLB and the sensing line SABL in at least part of the sensing amplifier circuit SA are twisted (e.g., Figure 8 In addition, please continue to refer to Figure 8 When the wire group also includes complementary sensing lines, the sensing lines SABL and the complementary sensing lines SABLB in the same wire group 110 can also be twisted with each other; for example, the sensing lines SABL1 and the complementary sensing lines SABLB1 in the first wire group 110a are twisted with each other, and the sensing lines SABL2 and the complementary sensing lines SABLB2 in the second wire group 110b are twisted with each other.

[0118] In some embodiments, please refer to Figure 5 、 Figure 7 or Figure 8 For the first wire group 110a, the first end of the sensing line SABL1 (as shown in area C) is located on the side of the first end of the complementary bit line BLB1 (as shown in area D) away from the second wire group 110b; the first end of the sensing line SABL1 refers to the end of the sensing line SABL1 close to the complementary bit line BLB1, and the first end of the complementary bit line BLB1 refers to the end of the complementary bit line BLB1 away from the sensing line SABL1.

[0119] In some embodiments, please combine Figure 2 ,as well as Figure 5 、 Figure 7 or Figure 8The regions between the two memory arrays 120 are, in order, the BLSA region, the LIOSA region, and the BLSA region. That is, the BLSA region is located between the memory array 120 and the LIOSA region. The first end of the sense line SABL1 (shown in region C) is closer to the adjacent memory array 120 than to the local data line sensing region. The first end of the complementary bit line BLB1 (shown in region D) is closer to the adjacent memory array 120 than to the local data line sensing region.

[0120] In some embodiments, please refer to Figure 5 、 Figure 7 or Figure 8 The first end (as shown in area C) and the second end (not shown) of the sensing line SABL1 are adjacent to each other; wherein the second end of the sensing line SABL1 refers to the end opposite to the first end of the sensing line SABL1.

[0121] In some embodiments, please refer to Figure 5 、 Figure 7 or Figure 8 , the wire group also includes a complementary sensing line; for the complementary sensing line SABLB1 in the first wire group 110a, it is located on the line where the first end of the sensing line SABL1 is located; the second end of the sensing line SABL1 and the first end of the complementary bit line BLB1 are on the same line.

[0122] In some embodiments, please refer to Figure 5 The sensing line SABL1 in the first conductive line group 110a is mirror-symmetrical to the sensing line SABL2 in the second conductive line group 110b. Figure 7 After the sensing line SABL1 in the first conductive line group 110a is translated along the X-axis direction, it overlaps with the sensing line SABL2 in the second conductive line group 110b. Figure 8 In region A, the sensing line SABL1 in the first wire group 110a is mirror-symmetrical to the sensing line SABL2 in the second wire group 110b; in region B, the sensing line SABL1 in the first wire group 110a is translated along the X-axis and overlaps with the sensing line SABL2 in the second wire group 110b.

[0123] Please refer to Figure 8 The first end (as shown in area C) and the second end (not shown) of the sensing line SABL1 are adjacent to each other; at the same time, the first end and the second end of the sensing line SABL2 are aligned in the Y-axis direction.

[0124] In the embodiment of the present disclosure, the first conductive layer is a single conductive layer (M1 layer). Figure 4Based on the above, the layout of the plurality of conductive line groups is described in detail. The first conductive line 111 is a complementary bit line BLB, and the second conductive line 112 is a sensing line SABL.

[0125] In the embodiment of the present disclosure, the sensing line SABL and the complementary sensing line SABLB of the same wire group 110 are twisted; for example, please refer to Figure 9 , the sensing line SABL1 of the first conductive line group 110 a and the complementary bit line BLB1 of the first conductive line group 110 a are twisted.

[0126] In some embodiments, please refer to Figure 9 The sensing line SABL1 of the first wire group 110a includes a first sub-segment 11, a second sub-segment 12, and a third sub-segment 13, and the complementary bit line BLB1 of the first wire group 110a includes a fourth sub-segment 14 and a fifth sub-segment 15; the first sub-segment 11 to the fifth sub-segment 15 all extend along the Y-axis direction; the first sub-segment 11, the fifth sub-segment 15, and the third sub-segment 13 are arranged in sequence along the Y-axis direction; the fourth sub-segment 14, the second sub-segment 12, and the complementary sensing line SABLB1 of the first wire group 110a are arranged in sequence along the Y-axis direction; the third sub-segment 12 and the complementary sensing line SABLB1 of the first wire group 110a are arranged adjacent to each other along the X-axis direction; the first sub-segment 11 is located on the side of the fourth sub-segment 14 away from the second wire group 110b; the second wire group 110b and the first wire group 110a are mirror-symmetrical.

[0127] In this disclosure, please combine Figure 2 and Figure 9 To clearly distinguish the sense amplifier circuits SA and corresponding wire groups 110 in the sense amplifier circuit groups 130 adjacent along the Y-axis, in the following description, the wire group corresponding to the sense amplifier circuit SA3 is referred to as the third wire group 110c, and the wire group corresponding to the sense amplifier circuit SA4 is referred to as the fourth wire group 110d. In other words, the sense amplifier circuit SA3 corresponding to the third wire group 110c and the sense amplifier circuit SA1 corresponding to the first wire group 110a each belong to the sense amplifier circuit groups 130 adjacent along the Y-axis, while the sense amplifier circuit SA4 corresponding to the fourth wire group 110d and the sense amplifier circuit SA2 corresponding to the second wire group 110b each belong to the sense amplifier circuit groups 130 adjacent along the Y-axis.

[0128] In some embodiments, please refer to Figure 9 The complementary sensing line SABLB1 of the first wire group 110a, the complementary bit line BLB3 (that is, the first wire 111c) of the third wire group 110c, the complementary bit line BLB4 (that is, the first wire 111d) of the fourth wire group 110d, and the complementary sensing line SABLB2 of the second wire group 110b are arranged in sequence along the X-axis direction.

[0129] In some embodiments, please refer to Figure 9 , the first sub-segment 11 and the second sub-segment 12 are connected through the connection structure of the same conductive layer, the second sub-segment 12 and the third sub-segment 13 are connected through the connection structure of the same conductive layer; the fourth sub-segment 14 and the fifth sub-segment 15 are connected through the connection structure across different conductive layers or through the gate layer. In the embodiment of this disclosure, please continue to refer to Figure 9 The fourth sub-segment 14 and the fifth sub-segment 15 are connected through a connection structure spanning different conductive layers or through a gate layer. Specifically, the fourth sub-segment 14 and the fifth sub-segment 15 are located on the first conductive layer (M1 layer). To avoid conflict with the complementary bit line BLB1 and the sensing line SABL1 of the first conductive line group 110a, the fourth sub-segment 14 is connected to the gate layer in the underlying active device layer after it approaches one end of the sensing line SABL1 (i.e., connected to the gate of the device in the active device layer, for example). Figure 12 The fourth sub-segment 14 is connected to the end of the fifth sub-segment 15 close to the sensing line SABL1 in the X-axis direction through the gate of the device in the gate layer.

[0130] Accordingly, because the conductive layer of the fourth sub-segment 14 has already been changed to the gate layer before the line change, the fourth sub-segment 14 includes two parts located on the first conductive layer and the gate layer, respectively. Similarly, the fifth sub-segment 15 also includes two parts located on the first conductive layer and the gate layer, respectively. When referring to jumpers later, the conductive layers of each sub-segment can be understood in the same way as described here and will not be further explained.

[0131] In this way, by using the gate to cross layers, the wires can achieve line changes, which not only avoids the long connection windings caused by layout limitations, reduces resistance and delay, but also further reduces the number of line lanes occupied and avoids line congestion. In addition, in some other embodiments, the fourth sub-segment 14 and the fifth sub-segment 15 can also be connected through the connection structure of the same conductive layer, while the first sub-segment 11 and the second sub-segment 12 can be connected through the connection structure of different conductive layers or through the gate layer. The present disclosure does not limit the sub-segments connected by the specific jumper wires, and subsequent embodiments can be understood in this way.

[0132] Book Figure 9In the illustrated embodiment, when the sense amplifier circuit SA is in the amplification stage, the potential of the complementary bit line BLB is different from the potential of the sensing line SABL. Furthermore, since the sensing line SABL1 of the first wire group 110a is located between the complementary bit line BLB1 of the first wire group 110a and the complementary bit line BLB3 of the third wire group, that is, the second sub-segment 12 is located between the fifth sub-segment 15 and the complementary bit line BLB3 of the third wire group, the complementary bit line BLB3 can simultaneously exert a coupling effect on the complementary bit line BLB1 and the sensing line SABL1, causing the potentials of the complementary bit line BLB1 and the sensing line SABL1 to be simultaneously pulled up or down, thereby ensuring that the voltage difference between the complementary bit line BLB1 and the sensing line SABL1 meets the amplification requirement.

[0133] In some embodiments, the first conductive layer includes a first conductive sublayer (M1-1 layer) and a second conductive sublayer (M1-2 layer) stacked along the Z-axis direction, and the heights of the first conductive sublayer and the second conductive sublayer are both lower than the height of the upper electrode of the storage capacitor in the memory cell. Figure 8 Based on the above, the layout of the plurality of conductive line groups is described in detail. The first conductive line 111 is a complementary bit line BLB, and the second conductive line 112 is a sensing line SABL.

[0134] In some embodiments, the sensing line SABL and the complementary sensing line SABLB of the same wire group 110 are twisted. Figure 10 , the sensing line SABL2 of the second conductive line group 110b and the complementary bit line BLB2 of the second conductive line group 110b are twisted.

[0135] In some embodiments, please refer to Figure 10 The complementary bit line BLB1, the sensing line SABL1, and at least a portion of the complementary sensing line SABLB1 of the first wire group 110a, and the complementary bit line BLB2, the sensing line SABL2, and at least a portion of the complementary sensing line SABLB2 of the second wire group 110b are all located in the first conductive sublayer (M1-1 layer).

[0136] Here, the complementary bit line BLB1, the sensing line SABL1, and at least a portion of the complementary sensing line SABLB1 of the first conductive line group 110a are all located in the first conductive sublayer, which means that at least a portion of the complementary bit line BLB1, at least a portion of the sensing line SABL1, and at least a portion of the complementary sensing line SABLB1 are all located in the first conductive sublayer; the same applies to the second conductive line group 110b.

[0137] It should be noted that at least a portion of the complementary sensing line SABLB1 and at least a portion of the complementary sensing line SABLB2 are jumped to the second conductive layer (ie, the second metal layer M2 ) or the gate layer.

[0138] In this disclosure, please continue to refer to Figure 10 The sensing line SABL1 of the first conductive line group 110a includes a first sub-segment 11 and a second sub-segment 12, the complementary sensing line SABLB1 of the first conductive line group 110a includes a third sub-segment 13 and a fourth sub-segment 14, the sensing line SABL2 of the second conductive line group 110b includes a fifth sub-segment 15, a sixth sub-segment 16 and a seventh sub-segment 17, the complementary sensing line SABLB2 of the second conductive line group 110b includes an eighth sub-segment 18 and a ninth sub-segment 19, and the complementary bit line BLB2 of the second conductive line group 110b includes a tenth sub-segment 20 and an eleventh sub-segment 21; the first sub-segments 11 to 11th sub-segments 21 are all along the Y-axis. The third subsegment 13 and the second subsegment 12 are aligned along the Y-axis direction; the first subsegment 11, the fourth subsegment 14, and the complementary bit line BLB1 of the first conductive line group 110a are aligned along the Y-axis direction; the eighth subsegment 18, the sixth subsegment 16, and the tenth subsegment 20 are aligned along the Y-axis direction; the fifth subsegment 15, the ninth subsegment 19, the eleventh subsegment 21, and the seventh subsegment 17 are aligned along the Y-axis direction; the third subsegment 13, the first subsegment 11, the eighth subsegment 18, and the fifth subsegment 15 are arranged in sequence along the X-axis direction; the second subsegment 12, the fourth subsegment 14, the sixth subsegment 16, and the ninth subsegment 19 are arranged in sequence along the X-axis direction.

[0139] In this disclosure, please combine Figure 2 and Figure 10 To clearly distinguish the sense amplifier circuits SA and corresponding wire groups 110 in the sense amplifier circuit groups 130 adjacent along the Y-axis, in the following description, the wire group corresponding to the sense amplifier circuit SA3 is referred to as the third wire group 110c, and the wire group corresponding to the sense amplifier circuit SA4 is referred to as the fourth wire group 110d. In other words, the sense amplifier circuit SA3 corresponding to the third wire group 110c and the sense amplifier circuit SA1 corresponding to the first wire group 110a each belong to the sense amplifier circuit groups 130 adjacent along the Y-axis, while the sense amplifier circuit SA4 corresponding to the fourth wire group 110d and the sense amplifier circuit SA2 corresponding to the second wire group 110b each belong to the sense amplifier circuit groups 130 adjacent along the Y-axis.

[0140] It should be noted that, in order to clearly show Figure 10 The positional relationship of the wires in the first conductive sublayer (M1-1 layer), Figure 10 The wires in the second conductive sublayer (M1-2 layer) are drawn outside the first conductive line group 110a and the second conductive line group 110b; in fact, the positions of the wires in the second conductive sublayer (M1-2 layer) are as follows: Figure 11 shown.

[0141] In some embodiments, please refer to Figure 10 and Figure 11The complementary bit line BLB3 of the third wire group 110c and the complementary bit line BLB4 of the fourth wire group 110d are located in the second conductive sublayer (M1-2 layer); the projections of the complementary bit line BLB3 of the third wire group 110c and the complementary bit line BLB1 of the first wire group 110a along the Z-axis direction at least partially overlap; the projections of the complementary bit line BLB4 of the fourth wire group 110d and the complementary bit line BLB2 of the second wire group 110b along the Z-axis direction at least partially overlap.

[0142] In some embodiments, please refer to Figure 10 The first subsegment 11 and the second subsegment 12 are connected via a connection structure on the same conductive sublayer; the fifth subsegment 15 and the sixth subsegment 16 are connected via a connection structure on the same conductive layer; the sixth subsegment 16 and the seventh subsegment 17 are connected via a connection structure on the same conductive layer; the third subsegment 13 and the fourth subsegment 14 are connected via a connection structure that spans different conductive layers or via a gate layer; the eighth subsegment 18 and the ninth subsegment 19 are connected via a connection structure that spans different conductive layers or via a gate layer; and the tenth subsegment 20 and the eleventh subsegment 21 are connected via a connection structure that spans different conductive layers or via a gate layer. In this way, cross-layer connections (e.g., via a gate layer or a second conductive layer) help avoid excessively long connection wires due to layout limitations, thereby reducing resistance and delay.

[0143] exist Figure 11 In the illustrated embodiment, since part of the complementary bit line BLB2 (i.e., the eleventh subsegment 21) and part of the sensing line SABL2 (i.e., the seventh subsegment) of the second conductive line group 110b are not located in the adjacent lower layer of the complementary bit line BLB4 in the fourth conductive line group 110d, it is beneficial to reduce the coupling between the complementary bit line BLB2 and the sensing line SABL2 and the complementary bit line BLB4.

[0144] In addition, the complementary sensing line SABLB1 and the sensing line SABL1 of the first wire group 110a extend side by side and are twisted with each other (as shown by the first sub-segment 11 and the third sub-segment 13, and the second sub-segment 12 and the fourth sub-segment 14). This can reduce the variation amplitude of the noise in the sensing amplifier circuit SA, thereby making the noise more uniform, which is beneficial to improving the performance of the semiconductor structure.

[0145] It should be noted that the above embodiment is described by taking the first conductive line 111 as the complementary bit line BLB and the second conductive line 112 as the sensing line SABL as an example; in other embodiments, the first conductive line 111 can be the bit line BL, and the second conductive line 112 can be the complementary sensing line SABLB. Please refer to the above embodiment for understanding of the layout method, and the present disclosure is not limited to this.

[0146] In some embodiments, please refer to Figure 9 and Figure 12The projection of the first sub-segment 11 in the Z-axis direction is located on the N-type amplifier tube of the sensing amplifier circuit SA; the projection of the fifth sub-segment 15 in the Z-axis direction is located on the bias cancellation transistor or the pre-charge transistor of the sensing amplifier circuit SA.

[0147] In the embodiment of the present disclosure, Figure 12 FIG. 4 shows the layout structure of each device in the sensing amplifier circuit SA, wherein: Figure 12 The dotted box in the middle is a device in the sensing amplifier circuit SA. The specific connection relationship can be referred to Figure 2 Understand.

[0148] In some embodiments, please refer to Figure 9 and Figure 12 Taking the example of the first end of the first sub-segment 11 (as shown in area C in the figure) being located above the first N-type amplifier transistor, the first sub-segment 11 is connected to the source or drain of the first N-type amplifier transistor in a direction from the first isolation transistor to the first N-type amplifier transistor, with the connection point being located in the middle of the first N-type amplifier transistor. The projection of the fifth sub-segment 15 in the Z-axis direction is located on the first bias cancellation transistor or the first pre-charge transistor of the sense amplifier circuit SA.

[0149] In some embodiments, please refer to Figure 10 and Figure 12 The projection of the seventh sub-segment 17 in the Z-axis direction is located on the N-type amplifier tube of the sensing amplifier circuit SA; the projection of the eleventh sub-segment 21 in the Z-axis direction is located on the isolation transistor of the sensing amplifier circuit SA; and the projections of the fourth and ninth sub-segments in the Z-axis direction are located on the P-type amplifier tube of the sensing amplifier circuit SA.

[0150] In the embodiment of the present disclosure, taking the seventh sub-segment 17 as an example where it is located above the surface of the first N-type amplifier tube, the projection of the seventh sub-segment 17 in the Z-axis direction is located on the middle portion of the first N-type amplifier tube of the sensing amplifier circuit SA; the projection of the eleventh sub-segment 21 in the Z-axis direction is located on the first isolation transistor or the first pre-charge transistor of the sensing amplifier circuit SA; and the projections of the fourth and ninth sub-segments in the Z-axis direction are located on the middle portion of the first P-type amplifier tube of the sensing amplifier circuit SA.

[0151] In addition, the present disclosure also provides an electronic device. Figure 13 A schematic diagram of the structure of an electronic device 200 provided in an embodiment of the present disclosure is shown in FIG. Figure 13 As shown, the electronic device 200 includes: a processor 210; and any semiconductor structure 100 in the above embodiments; wherein the memory is coupled to the processor.

[0152] In some embodiments, electronic devices include but are not limited to mobile phones, tablet computers, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, vehicle-mounted devices, servers, workstations, etc.

[0153] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in non-targeted ways. The structural embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0154] The features disclosed in several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0155] The above are only some embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that include: a plurality of sensing amplifier circuits arranged along a first direction; The devices in the sensing amplifier circuit are arranged in the active device layer; a plurality of conductive line groups arranged along the first direction, the conductive line groups being disposed in a first conductive layer above the active device layer, wherein one conductive line group is connected to a corresponding device in the sensing amplifier circuit; The wire group includes a first wire and a second wire; the first wire and the second wire within the same wire group corresponding to at least a portion of the sense amplifier circuit are twisted so that at least a portion of the second wire is located between first wires in different wire groups; when the sense amplifier circuit is in an amplification phase, the potential of the first wire and the potential of the second wire within the same wire group represent different data; The first direction and the second direction are two intersecting directions on the plane where the semiconductor structure is located.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a memory array located on both sides of the plurality of sensing amplifier circuits along the second direction; The conductive line group includes a sensing line, a complementary sensing line, a bit line, and a complementary bit line; the bit line comes from the memory array on the first side, and the complementary bit line comes from the memory array on the second side; the sensing line is used to transmit data to the bit line, and the complementary sensing line is used to transmit data to the complementary bit line; The first conductive line is one of the bit line, the complementary bit line, the sensing line, or the complementary sensing line, and the second conductive line is one of the sensing line or the complementary sensing line.

3. The semiconductor structure according to claim 2, wherein: The plurality of sensing amplifier circuits are divided into a plurality of sensing amplifier circuit groups, each of the sensing amplifier circuit groups including two non-overlapping sensing amplifier circuits arranged along the first direction; The wire groups corresponding to the two sensing amplifier circuits in the same sensing amplifier circuit group are respectively a first wire group and a second wire group; The first portion of the first conductive wire group and the first portion of the second conductive wire group are mirror-symmetrical along the second direction, and the second portion of the first conductive wire group overlaps with the second portion of the second conductive wire group after translation along the first direction; or, The first conductor group is translated along the first direction and overlaps with the second conductor group; or, The first conductive line group and the second conductive line group are mirror-symmetrical along the second direction.

4. The semiconductor structure according to claim 3, wherein: For the first conductive line group, the first end of the sensing line is located on a side of the first end of the complementary bit line away from the second conductive line group; the first end of the sensing line refers to an end of the sensing line close to the complementary bit line, and the first end of the complementary bit line refers to an end of the complementary bit line away from the sensing line; The sensing lines in the second conductive line group are mirror-symmetrical to the sensing lines in the first conductive line group.

5. The semiconductor structure according to claim 3, wherein: The first conductive layer is a single conductive layer, the first conductive line is a complementary bit line, and the second conductive line is a sensing line.

6. The semiconductor structure according to claim 5, wherein: The sensing line of the first conductive line group includes a first sub-segment, a second sub-segment, and a third sub-segment; the complementary bit line of the first conductive line group includes a fourth sub-segment and a fifth sub-segment; the first sub-segment to the fifth sub-segment all extend along the second direction; The first sub-segment, the fifth sub-segment and the third sub-segment are arranged in sequence along the second direction; The fourth sub-segment, the second sub-segment and the complementary sensing lines of the first conductive line group are arranged in sequence along the second direction; The third sub-segment and the complementary sensing wires of the first conductive line group are arranged adjacent to each other along the first direction; The first sub-segment is located on a side of the fourth sub-segment away from the second wire group; The second conductive line group and the first conductive line group are mirror-symmetrical.

7. The semiconductor structure according to claim 6, wherein: The complementary sensing lines of the first conductive line group, the complementary bit lines of the third conductive line group, the complementary bit lines of the fourth conductive line group, and the complementary sensing lines of the second conductive line group are sequentially arranged along the first direction; The sensing amplifier circuit corresponding to the third wire group and the sensing amplifier circuit corresponding to the first wire group respectively belong to the sensing amplifier circuit groups adjacent to each other along the second direction, and the sensing amplifier circuit corresponding to the fourth wire group and the sensing amplifier circuit corresponding to the second wire group respectively belong to the sensing amplifier circuit groups adjacent to each other along the second direction.

8. The semiconductor structure according to claim 6, wherein: The first sub-segment and the second sub-segment are connected via a connection structure of the same conductive layer, and the second sub-segment and the third sub-segment are connected via a connection structure of the same conductive layer; The fourth sub-segment and the fifth sub-segment are connected via a connection structure spanning different conductive layers or via a gate layer.

9. The semiconductor structure according to claim 3, wherein: The first conductive layer includes a first conductive sublayer and a second conductive sublayer stacked along a third direction; The sensing lines and the complementary sensing lines of the same wire group are twisted, and the third direction is perpendicular to the plane where the semiconductor structure is located.

10. The semiconductor structure according to claim 3, wherein: The sensing line of the second conductive line group is twisted with the complementary bit line of the second conductive line group.

11. The semiconductor structure according to claim 9, wherein: The complementary bit lines, sensing lines, and at least a portion of the complementary sensing lines of the first conductive line group and the complementary bit lines, sensing lines, and at least a portion of the complementary sensing lines of the second conductive line group are all located in the first conductive sublayer; The sensing line of the first conductive line group includes a first subsegment and a second subsegment, the complementary sensing line of the first conductive line group includes a third subsegment and a fourth subsegment, the sensing line of the second conductive line group includes a fifth subsegment, a sixth subsegment, and a seventh subsegment, the complementary sensing line of the second conductive line group includes an eighth subsegment and a ninth subsegment, and the complementary bit line of the second conductive line group includes a tenth subsegment and an eleventh subsegment; the first to eleventh subsegments all extend along the second direction; The third sub-segment and the second sub-segment are aligned along the second direction; The first sub-segment, the fourth sub-segment, and the complementary bit lines of the first conductive line group are aligned along the second direction; The eighth sub-segment, the sixth sub-segment, and the tenth sub-segment are aligned along the second direction; The fifth sub-segment, the ninth sub-segment, the eleventh sub-segment and the seventh sub-segment are aligned along the second direction; The third sub-segment, the first sub-segment, the eighth sub-segment and the fifth sub-segment are arranged in sequence along the first direction; The second sub-segment, the fourth sub-segment, the sixth sub-segment, and the ninth sub-segment are arranged in sequence along the first direction.

12. The semiconductor structure according to claim 11, wherein: The complementary bit lines of the third conductive line group and the complementary bit lines of the fourth conductive line group are located in the second conductive sublayer; The projections of the complementary bit lines of the third conductive line group and the complementary bit lines of the first conductive line group along the third direction at least partially overlap; the projections of the complementary bit lines of the fourth conductive line group and the complementary bit lines of the second conductive line group along the third direction at least partially overlap; The sensing amplifier circuit corresponding to the third wire group and the sensing amplifier circuit corresponding to the first wire group respectively belong to the sensing amplifier circuit groups adjacent to each other along the second direction, and the sensing amplifier circuit corresponding to the fourth wire group and the sensing amplifier circuit corresponding to the second wire group respectively belong to the sensing amplifier circuit groups adjacent to each other along the second direction.

13. The semiconductor structure according to claim 11, wherein: The first sub-segment and the second sub-segment are connected via a connection structure of the same conductive sub-layer, the fifth sub-segment and the sixth sub-segment are connected via a connection structure of the same conductive layer, and the sixth sub-segment and the seventh sub-segment are connected via a connection structure of the same conductive layer. The third sub-segment and the fourth sub-segment are connected via a connection structure spanning different conductive layers or via a gate layer; The eighth sub-segment and the ninth sub-segment are connected via a connection structure spanning different conductive layers or via the gate layer; The tenth sub-segment and the eleventh sub-segment are connected via a connection structure spanning different conductive layers or via the gate layer.

14. The semiconductor structure according to claim 6, wherein: The projection of the first sub-segment in the third direction is located on the N-type amplifier tube of the sensing amplifier circuit; A projection of the fifth subsegment in the third direction is located on a bias cancellation transistor or a precharge transistor of the sense amplifier circuit.

15. The semiconductor structure according to claim 11, wherein: The projection of the seventh sub-segment in the third direction is located on the N-type amplifier tube of the sensing amplifier circuit; The projection of the eleventh subsegment in the third direction is located on the isolation transistor or the pre-charge transistor of the sense amplifier circuit; Projections of the fourth sub-segment and the ninth sub-segment in the third direction are located on the P-type amplifier tube of the sense amplifier circuit.

16. An electronic device, characterized in that: include: A semiconductor structure as claimed in any one of claims 1 to 15.

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