Memory management unit

Abstract

A technique for determining the number of times a memory is actually rewritten is provided. A memory management unit is configured to control a storage destination of data to which a write request has been made from a host for each predetermined storage unit, the memory management unit comprising: a storage destination control unit that controls the storage destination of the data to which the write request has been made from the host; selecting a storage destination of the data of each of the memory cells from a main memory having a rewritable number of less than 1015 and a cache memory capable of performing copy-back of writing the data of each of the memory cells into the main memory according to a predetermined trigger; and a copy-back detection unit that detects, for each of the memory cells, that the copy-back has been executed.

Description

Technical Field

[0001] The present invention relates to a memory management unit. Background Art

[0002] Previously, information processing systems using MRAMs with a relatively low guaranteed rewrite count have been known. For example, Patent Document 1 discloses a structure in which data for which write requests are made is retained in a data retention circuit, and data that meets specified conditions is stored in the MRAM. In Patent Document 1, the data retention circuit retains data for each block and also stores information indicating the frequency of write requests for that block. Furthermore, if there are no free blocks in the data retention circuit, data from blocks with a low frequency of write requests is stored in the MRAM.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2010-97655.

[0004] Conventional technology reduces the number of write operations to the MRAM by transferring data from blocks with low write request frequencies. However, conventional technology makes it impossible to determine the actual number of times the MRAM is rewritten. Summary of the Invention

[0005] The present invention has been made in view of the above-mentioned problem, and an object of the present invention is to provide a technology for determining the number of times a memory is actually rewritten.

[0006] In order to achieve the above object, a memory management unit is constructed which controls the storage destination of data requested to be written by a host for each predetermined storage unit, wherein the storage destination control unit is provided with a storage destination control unit which controls the storage destination of data requested to be written by a host for each predetermined storage unit. 15 a main memory and a cache memory capable of executing a copy back of the data of each storage unit to the main memory according to a prescribed trigger, selecting a storage destination of the data of each storage unit; and a copy back detection unit for detecting whether the copy back has been executed for each storage unit.

[0007] The main memory can be rewritten less than 10 times 15 , and the number of rewrites can be reached during use. When using such a main memory, it is preferable to perform various controls, such as adjusting the main memory usage area or delaying the time when the number of rewrites is reached, depending on whether the number of rewrites has been reached. To perform various controls, it is necessary to determine whether each predetermined storage unit corresponding to the data rewrite unit in the main memory has been rewritten.

[0008] In an information processing system using a cache memory with a copy-back function, cached data is written to the cache memory when a write request is received from the host. The copy-back function writes data stored in the cache memory to the main memory based on a specified trigger. Therefore, in a system with a copy-back function, not all cached data is necessarily written to the main memory. In other words, if data stored in the cache memory is overwritten before a specified trigger occurs, that data is not stored in the main memory.

[0009] Conventional information processing systems cannot detect whether the main memory has been overwritten, making it impossible to perform control related to the main memory's expiration date. Therefore, the memory management unit is configured to detect whether the main memory has been overwritten by detecting when a copy-back has been performed. This configuration makes it possible to determine whether the memory has actually been overwritten, enabling control related to the expiration date, such as estimating the expiration date and controlling the expiration date. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a diagram showing an information processing system to which a memory management unit is applied.

[0011] Figure 2 This is a flowchart of the counting process.

[0012] Description of Reference Numerals

[0013] 1 Information processing system, 10 Host, 20 Memory management unit, 20a Non-volatile memory, 20b Control circuit, 20b1 Counter, 30 Cache memory, 30a Storage unit, 30b Control circuit, 30b1 Memory control unit, 30b2 Copy-back request signal output unit, 40 Main memory, 50 Bus. DETAILED DESCRIPTION

[0014] Here, the embodiments of the present invention will be described in the following order: (1) Configuration of the information processing system, (2) Counting processing, (3) Other embodiments, etc.

[0015] (1) Structure of information processing system:

[0016] Figure 1This figure shows an information processing system 1 to which a memory management unit according to one embodiment is applied. The information processing system 1 includes a host 10, a memory management unit 20, a cache memory 30, and a main memory 40. The host 10 is a processor that executes various programs stored in the main memory 40, and is composed of, for example, a CPU (Central Processing Unit). In this embodiment, the main memory 40 is composed of a memory that can be rewritten less than 10 times. 15 (As an example, including less than 10 10 For example, 10 6 The memory management unit 20 , the cache memory 30 , and the main memory 40 are connected via a bus 50 .

[0017] The memory management unit 20 manages and controls data for each specified memory cell. To perform this management and control, the memory management unit 20 of this embodiment includes a nonvolatile memory 20a and a control circuit 20b. In this specification, a specified memory cell is also referred to as a page.

[0018] The control circuit 20b is a device for managing and controlling the memory management unit 20 and can be implemented by various processors. The control circuit 20b also has a function of counting the number of copy-backs performed in the cache memory 30 (counter 20b1).

[0019] The nonvolatile memory 20a can store setting data, or page settings, for each predetermined memory cell, or page. Furthermore, the nonvolatile memory 20a counts and stores the number of times the storage location of each page of data is rewritten when the data is stored in the main memory 40. Furthermore, the nonvolatile memory 20a can be configured using various types of memory, such as MRAM.

[0020] The page settings include a conversion table between virtual addresses and physical addresses, a specified storage unit, i.e., the page size, a setting value indicating whether data is valid / invalid, a setting value indicating whether reading / writing is allowed, and a setting value indicating whether to use a cache memory as a storage destination for data.

[0021] The translation table is data used to convert the virtual address of the storage destination of data specified by the host 10 into the physical address of the main memory 40. Details will be described later. The page size is a value indicating the size of a specified storage unit. That is, in this embodiment, the specified storage unit size is variable. The setting value indicating whether the data is valid or invalid is used to set whether the data of the corresponding page is valid or invalid. If set to invalid, the data of the page is not written to the cache memory 30 or main memory 40. The setting value indicating whether to allow reading or writing is used to respectively allow or prohibit reading and writing of the data of the corresponding page.

[0022] The setting value indicating whether to use the cache memory as the storage destination for data is a value used to specify whether the data of each page is a cache target. That is, when the cache memory is specified as the storage destination for a certain page of data, the memory management unit 20 selects the cache memory 30 as the storage destination for the data of that page. On the other hand, when the cache memory is not specified as the storage destination for a certain page of data, the memory management unit 20 selects the main memory 40 as the storage destination for the data of that page. In addition, the rewrite frequency of data for which the cache memory is specified as the storage destination is higher than the rewrite frequency of data for which the cache memory is not specified as the storage destination. Therefore, in this embodiment, it is considered that the storage destination for data that is a cache target is rewritten more frequently than the storage destination for data that is not a cache target.

[0023] Here, the control of the storage destination of data in each specified storage unit is described. In this embodiment, the host 10 is configured to specify the storage destination of data using a virtual address. This virtual address refers to a continuous, specified storage unit beginning with the virtual address. Therefore, when a virtual address is specified, the data in the continuous, specified storage units starting from the virtual address is specified. In this embodiment, this specified storage unit is referred to as a page. In this embodiment, the above-mentioned page settings are defined corresponding to each of the continuous, specified storage units, i.e., pages, determined by the virtual addresses.

[0024] The memory management unit 20 manages addresses related to reading and writing data. Focusing on data writing, the memory management unit 20 controls the storage destination of data requested by the host 10 for each specified storage unit. When a data write request is made from the host 10, the memory management unit 20 manages the write destination address based on the write request from the host 10. Specifically, the write request includes information indicating the data to be written and the virtual address of the write destination. The memory management unit 20 converts the virtual address into a physical address in the main memory 40. The memory management unit 20 then associates the physical address with the data as the storage destination.

[0025] In this embodiment, the memory management unit 20 selects and outputs the data storage destination from the cache memory 30 and main memory 40 based on the data's virtual address. Specifically, the memory management unit 20 refers to a setting indicating whether to use the cache memory as the data storage destination and selects the storage destination indicated by the setting value.

[0026] When the storage destination is the cache memory 30, the memory management unit 20 outputs the data to the cache memory 30 in association with the physical address corresponding to the virtual address specified by the host 10. The cache memory 30 includes a storage unit 30a, and stores the data in the storage unit 30a together with the physical address specified as the storage destination by the memory management unit 20.

[0027] When the storage destination is the main memory 40, the memory management unit 20 outputs data to the main memory 40 in association with the physical address corresponding to the virtual address designated from the host 10. The main memory 40 stores data for the physical address designated from the memory management unit 20 as the storage destination.

[0028] The cache memory 30 is a memory that stores cache target data before storing it in the main memory 40. Specifically, the cache memory 30 includes a storage unit 30a that stores data for each storage unit output from the memory management unit 20. The storage unit 30a can be composed of, for example, an SRAM (Static Random Access Memory).

[0029] In this embodiment, the cache memory 30 has a copy-back function. To implement the copy-back function, the cache memory 30 includes a control circuit 30b that executes a copy-back operation to write the data of each specified storage unit to the main memory 40 based on a specified trigger. The control circuit 30b includes a memory control unit 30b1 and a copy-back request signal output unit 30b2. The memory control unit 30b1 causes the data output by the memory management unit 20 to be stored at a specified address of the storage unit 30a for each specified storage unit, i.e., page. When the copy-back function is executed, the physical address of the storage destination is specified by the copy-back request signal output unit 30b2 (described later). The memory control unit 30b1 extracts the data corresponding to the specified physical address from the storage unit 30a, specifies the physical address as the storage destination, and transfers it to the main memory 40. As a result, the main memory 40 stores the data of each page at the corresponding physical address.

[0030] Furthermore, when executing a copy-back, the memory control unit 30b1 transfers the data for each page stored in the storage unit 30a to the main memory 40. However, it does not process pages that do not store data or that have been invalidated. That is, the memory control unit 30b1 does not instruct the user to write to pages that are cache targets, pages that do not store data in the storage unit 30a, or pages that have been invalidated. Furthermore, the memory control unit 30b1 does not perform duplicate writes. Specifically, the memory control unit 30b1 does not rewrite data to pages that were already written to the main memory 40 during the previous copy-back and that have not been updated in the storage unit 30a until the current copy-back.

[0031] The copy-back request signal output unit 30b2 is a circuit that determines whether a predetermined trigger has occurred and, if so, outputs a signal requesting the execution of a copy-back. In this embodiment, the predetermined trigger is "the capacity of data stored in the storage unit 30a exceeds a threshold." Therefore, the copy-back request signal output unit 30b2 measures the capacity of data stored in the storage unit 30a after the last copy-back execution and outputs a copy-back request signal if the capacity exceeds the threshold.

[0032] The copy-back request signal output unit 30b2 is connected to the memory control unit 30b1 and the control circuit 20b, described later. When a predetermined trigger is generated, the copy-back request signal output unit 30b2 outputs a signal indicating the physical address (the storage destination) of the data to be copied back, along with a copy-back request signal. This signal is provided to the memory control unit 30b1 and the control circuit 20b. When the copy-back request signal is output to the memory control unit 30b1, the memory control unit 30b1 executes a copy-back operation, storing the data to be copied back at the designated physical address.

[0033] When using main memory 40, which has a relatively low rewritable limit and may reach its upper limit during use, the copy-back function is effective in extending the lifespan of main memory 40. Specifically, when using the copy-back function, all data requested for write access is not written to main memory 40, but rather temporarily stored in cache memory 30. Furthermore, unless a predetermined trigger occurs, data stored in cache memory 30 may be overwritten by other data without being stored in main memory 40. Therefore, compared to a configuration in which all data is written to main memory 40, the lifespan of main memory 40 is extended.

[0034] However, if the number of times the main memory 40 has been written to cannot be accurately determined, it is impossible to perform processing to extend the usage period, such as storing data whose address in a storage area nearing its usage period is designated as the storage destination at another address. Therefore, in this embodiment, the memory management unit 20 has a function of counting the number of times the main memory 40 has been rewritten for each specified storage unit.

[0035] The memory management unit 20 implements this function using the nonvolatile memory 20a and the control circuit 20b. Specifically, as described above, the nonvolatile memory 20a includes an area for recording the number of times the storage location of each page of data is rewritten when storing it in the main memory 40.

[0036] The control circuit 20b manages data on each page based on the page settings stored in the nonvolatile memory 20a. Specifically, the control circuit 20b sets the storage unit based on the page size indicated by the page settings. Furthermore, the control circuit 20b converts the virtual address indicating the storage destination of data specified by the host 10 into a physical address based on the conversion table indicated by the page settings.

[0037] The control circuit 20b also sets the data in pages set to invalid to not be read or written. Furthermore, the control circuit 20b reads or writes data based on a setting indicating whether to allow or disable reading or writing. Furthermore, the control circuit 20b selects a data storage destination from the main memory 40 and cache memory 30 based on a setting indicating whether to use the cache memory as the data storage destination. In other words, the control circuit 20b functions as a storage destination control unit.

[0038] The control circuit 20b also includes a counter 20b1. When a copy-back request signal and the physical address of the storage destination of the data to be copied back are output from the copy-back request signal output unit 30b2, the counter 20b1 counts the number of times each page of data is stored in the main memory 40 based on the signal. Furthermore, the counter 20b1 updates the number of overwrites stored in the nonvolatile memory 20a based on the count result.

[0039] More specifically, counter 20b1 references nonvolatile memory 20a to obtain the number of rewrites to the physical address, the storage destination of the data to be copied back. Furthermore, counter 20b1 updates nonvolatile memory 20a with the value obtained by adding 1 to this number of rewrites. Specifically, when counter 20b1 detects a copy back request signal, it increments the number of rewrites to the page to be copied back. With the above configuration, the actual number of rewrites to main memory 40 can be determined and counted for each page. Furthermore, since counter 20b1 detects the execution of a copy back by receiving the copy back request signal, it functions as a copy back detection unit.

[0040] The main memory 40 in this embodiment is an MRAM with a rewritable number of 10 6 Therefore, the number of times the rewrite limit is reached during use. When using such a main memory 40, it is preferable to perform various controls, such as adjusting the used area of ​​the main memory 40 according to whether the number of times the rewrite limit is reached. For example, in the main memory 40, if the number of times a storage area corresponding to a specific page has been rewritten exceeds a threshold, the use of that storage area can be prohibited and the data of the specific page can be stored in another storage area. With such controls, the service life of the main memory 40 can be extended compared to a case where no controls are performed.

[0041] In this embodiment, the number of rewrites is stored in the nonvolatile memory 20a. Therefore, even if the information processing system 1 is powered off and then on again, the number of rewrites stored in the nonvolatile memory 20a is maintained. Therefore, even if the power is turned off, the number of rewrites of the main memory 40 can be confirmed when the power is turned on again.

[0042] Furthermore, in this embodiment, the page settings are stored in the non-volatile memory 20a. Therefore, there is no need to operate with the initial settings each time the power is turned on; operation can be resumed with the settings in place before the power was turned off. In this embodiment, the correspondence between virtual addresses and physical addresses is defined by a translation table. Furthermore, since the page size is variable, if these settings change, there is a possibility that they will not match the record of the number of overwrites. However, in this embodiment, since the page settings are stored in the non-volatile memory 20a, even if the power is turned off, the information processing system 1 can operate with the same settings when the power is turned on. Therefore, counting based on the number of overwrites can continue.

[0043] (2) Counting processing:

[0044] Next, the counting process executed by the control circuit 20b will be described. When the information processing system 1 is started, the host 10, the memory management unit 20, etc. start processing. In parallel with these processes, the control circuit 20b executes Figure 2 When the counting process starts, the counter 20b1 of the control circuit 20b waits until a copy-back request signal is detected (step S100).

[0045] When the copy-back request signal is output from the copy-back request signal output unit 30b2 and the counter 20b1 detects the copy-back request signal in step S100, the counter 20b1 determines the page of the storage destination (step S105). Specifically, since the copy-back request signal is output along with the physical address of the storage destination of the data to be copied back, the counter 20b1 refers to the virtual-to-physical address conversion table and converts the physical address into a virtual address. As a result, the counter 20b1 can determine the virtual address of the data to be copied back.

[0046] Next, the counter 20b1 obtains the number of rewrites of the destination page from the nonvolatile memory 20a (step S110). That is, the counter 20b1 refers to the nonvolatile memory 20a and obtains the number of rewrites associated with the page specified by the virtual address determined in step S105.

[0047] Next, the counter 20b1 increments the rewrite count and stores it in the nonvolatile memory (step S115). Specifically, the counter 20b1 increments the rewrite count obtained in step S110 by 1 and uses this incremented value to update the rewrite count for each page in the nonvolatile memory 20a. As a result, the number of times data has been written since the start of main memory 40 operation is stored in the nonvolatile memory 20a as the rewrite count.

[0048] (3) Other implementation methods, etc.:

[0049] The above embodiment is an example for implementing the present invention, and various other embodiments may also be adopted. The memory management unit only needs to be able to control the storage destination of the data requested to be written from the host for each specified storage unit. That is, the address (virtual address) representing the storage destination of the data of each specified storage unit indicated from the host and the address (physical address) representing the storage destination of the main memory (or cache memory) where the data is written may be inconsistent. The memory management unit only needs to be able to convert the virtual address into the physical address. In addition, as an example, the memory management unit is composed of a plurality of circuits formed in an integrated circuit and does not constitute an integrated chip, but it can also be constituted as an integrated chip.

[0050] The host is the device that issues data write requests and can be composed of various processors. Of course, in addition to write requests, the host can also perform various other requests, such as read requests, and perform other computations. The specified storage unit has a predetermined data capacity, and data can be written and read from each storage unit.

[0051] Cache memory stores data output from the memory management unit for each memory cell and, based on a specified trigger, executes a copy-back function to write the data from each memory cell to the main memory. Specifically, cache memory is a memory capable of storing data and generally operates at a higher speed than the main memory. Furthermore, because cache memory has a copy-back function, not all data requested for write is necessarily written to the main memory. Therefore, compared to a configuration in which all data is written to the main memory, the time until the main memory reaches its end of life can be extended.

[0052] The cache memory stores data for each storage cell. Specifically, when a data write request is made from the host to each specified storage cell, the data is also written to each specified storage cell in the cache memory. A predetermined trigger can be any condition for executing the process of copying data from the cache memory back to the main memory. In addition to the triggers described above, various other conditions can serve as triggers. For example, the passage of a certain time can serve as a predetermined trigger, or an external request can serve as a predetermined trigger. Furthermore, the cache memory can be either volatile or non-volatile.

[0053] The memory management unit only needs to be able to detect when a copy-back operation has occurred. Therefore, in addition to a configuration that counts the number of copy-back operations, various configurations can be employed. For example, a system can be used to detect when a copy-back operation has occurred and to count the intervals and frequency of copy-back operations. Using this information, various controls related to the lifespan of the main memory can be implemented.

[0054] The storage medium that stores the count of the number of times copy-back executions are detected can be any storage medium that counts the number of times copy-back executions are detected for each storage cell and stores the count for each storage cell. Specifically, when copy-back is executed, the data stored in each storage cell of the cache memory is written to the main memory, and therefore, each storage cell is overwritten. Therefore, for storage cells that store data in the cache memory, the data is overwritten at the corresponding storage destination in the main memory, while for storage cells that do not store data, the data is not overwritten in the main memory. Therefore, the memory management unit counts the number of times copy-back is performed for each storage cell and counts this as the number of overwrites.

[0055] The structure for counting the number of copy-back operations can be various. For example, a counter can be provided for each page set for each memory cell to count the number of copies performed to the address storing the data of each page. Alternatively, a structure can be employed in which a single counter is controlled in a time-sharing manner to count the number of copies performed to the address corresponding to each page. Of course, the number of counters can also be two or more.

[0056] Furthermore, the structure for detecting that the copy-back is executed is not limited to the structure of outputting the copy-back request signal from the cache memory to the memory management unit. Figure 1 In the illustrated configuration, the memory management unit 20 may detect a signal indicating completion of access to the bus 50 in communication between the cache memory 30 and the main memory 40 and regard the execution of the copy-back.

[0057] Furthermore, the storage medium for storing the count value is preferably a non-volatile memory, but a volatile memory may also be used. Specifically, a trigger indicating that a copy-back has been performed and the number of times a copy-back has been performed may be stored in a register, and the value in the non-volatile memory may be incremented based on the value of the register.

[0058] In the above embodiment, the main memory is MRAM, but it may be other memories. That is, compared with other known memories, MRAM has a relatively long guaranteed period for data retention, but a relatively small number of guaranteed times for data rewriting (e.g., 10 6Thus, even if the MRAM characteristic is that the guaranteed number of rewrites is relatively small, by detecting that copy-back has been performed or counting the number of copy-backs, various controls such as controls for extending the useful life can be implemented.

[0059] In addition, the main memory is a memory whose rewritable number may become a limitation in use. 15 That is, the rewritable times of SRAM and DRAM (Dynamic Random Access Memory) is 10 15 In fact, the number of times that can be rewritten will not be a limitation in use. On the other hand, the number of times that MRAM can be rewritten is 10 6 As such a memory, there are other examples of a memory with a rewritable number of 10. 6 ReRAM (Resistive Random Access Memory) and so on.

[0060] In addition, the method of the present invention can also be applied as a program or method. In addition, the above-mentioned systems, programs, and methods may be implemented as a single device or as multiple devices, including various methods. In addition, part of the system may be software, part of the system may be hardware, etc., and these may be changed appropriately. In addition, the invention also exists as a recording medium for a program for controlling a system. Of course, the recording medium for the program may be a magnetic recording medium or a semiconductor memory, and any recording medium developed in the future may be considered in exactly the same way.

Claims

1. A memory management unit that controls a storage destination of data requested to be written by a host for each predetermined storage unit, wherein: have: The storage destination control unit is set to be less than 10 times the rewritable number 15 a main memory and a cache memory capable of executing a copy-back operation of writing the data of each storage unit to the main memory according to a predetermined trigger, and selecting a storage destination of the data of each storage unit; as well as The copy-back detection unit detects, for each of the storage units, whether the copy-back has been executed.

2. The memory management unit according to claim 1, wherein: Also features: The storage medium counts the number of times the copy-back is detected for each storage unit and stores the count value for each storage unit.

3. The memory management unit according to claim 1 or 2, wherein: The main memory is a magnetoresistive random access memory. The memory management unit according to claim 2 , wherein: The storage medium is a non-volatile memory.

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