Memory device and memory system

Abstract

The embodiment of the invention discloses a memory device and a memory system. The memory device includes: a first stack; wherein the first stack comprises a first channel structure; a plurality of first storage units formed along the length direction of the first channel structure; a plurality of first word lines coupled to the plurality of first memory cells one by one; a plurality of first string drivers coupled to the plurality of first word lines one by one; wherein the grid width of the first string driver in the plurality of first string drivers is set according to the critical dimension of the sub-channel structure in the first channel structure corresponding to the first string driver; and the control circuit is coupled with the plurality of first string drivers, and is configured to respond to a received first operation command, control the corresponding first string drivers, provide corresponding first operation voltages for the corresponding first word lines, and enable the first storage units coupled with the corresponding first word lines to execute corresponding operations.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and more particularly to a memory device and a memory system. Background Art

[0002] Memory devices are used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has become a mainstream product in the memory market due to its high storage density, manageable production costs, suitable programming and erasing speeds, and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems. Summary of the Invention

[0004] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: a first stack; wherein the first stack comprises: a first channel structure; a plurality of first storage cells formed along the length direction of the first channel structure; a plurality of first word lines coupled one by one to the plurality of first storage cells; a plurality of first string drivers coupled one by one to the plurality of first word lines; wherein a gate width of a first string driver among the plurality of first string drivers is set according to a critical dimension of a sub-channel structure in the first channel structure corresponding to the first string driver; and a control circuit coupled to the plurality of first string drivers and configured to: in response to a received first operation command, control the corresponding first string driver to provide a corresponding first operation voltage to its corresponding first word line, so that the first storage cell coupled to the corresponding first word line performs a corresponding operation.

[0005] In the above scheme, the larger the critical dimension of the sub-channel structure in the first channel structure, the larger the gate width of the corresponding first string driver; conversely, the smaller the critical dimension of the sub-channel structure in the first channel structure, the smaller the gate width of the corresponding first string driver.

[0006] In the above solution, the plurality of first storage cells are divided into a plurality of first storage groups; wherein the gate widths of the first string drivers corresponding to the first word lines coupled to the first storage cells in different first storage groups are different.

[0007] In the above solution, the gate widths of the first string drivers corresponding to the first word lines coupled to the first memory cells in the same first memory group are the same.

[0008] The above scheme also includes: multiple second stacks; wherein each second stack in the multiple second stacks includes: a second channel structure; multiple second storage cells formed along the length direction of the second channel; multiple second word lines coupled one by one to the multiple second storage cells; multiple second string drivers coupled one by one to the second word lines; wherein the gate width of the second string driver in the multiple second string drivers is set according to the critical dimension of the sub-channel structure in the second channel structure corresponding to the second string driver; the control circuit is coupled to the multiple second string drivers and is configured to: in response to the received second operation command, control the corresponding second string driver to provide the corresponding operation voltage to its corresponding second word line, so that the second storage cell coupled to the corresponding second word line performs the corresponding operation.

[0009] In the above scheme, the larger the critical dimension of the sub-channel structure in the second channel structure, the larger the gate width of the corresponding second string driver; conversely, the smaller the critical dimension of the sub-channel structure in the second channel structure, the smaller the gate width of the corresponding second string driver.

[0010] In the above scheme, the multiple second storage cells are divided into multiple second storage groups; wherein, the gate widths of the second string drivers corresponding to the second word lines coupled to the second storage cells in different second storage groups are different; the gate widths of the second string drivers corresponding to the second word lines coupled to the second storage cells in the same second storage group are the same.

[0011] In the above solution, the number of the plurality of first storage groups is the same as the number of the plurality of second storage groups.

[0012] In the above solution, the plurality of second stacks are arranged above the first stack, or the plurality of second stacks are arranged below the first stack.

[0013] In the above solution, the corresponding operation includes one of the following: a read operation, a write operation, and an erase operation.

[0014] In the above solution, the control circuit includes: control logic, voltage generator, and row decoder, wherein:

[0015] The control logic is configured to: receive a first operation command and input address information; generate a voltage control signal in response to the first operation command, and transmit the voltage control signal to the voltage generator, and transmit the input address information to the row decoder; the voltage generator is configured to: generate an operation voltage corresponding to the first operation command according to the voltage control signal; the row decoder is coupled to the voltage generator and the multiple first string drivers, and is configured to: parse the input address information to obtain an operation address; transmit the operation voltage to the first string driver corresponding to the operation address; the corresponding first string driver is configured to: provide the operation voltage to the first word line coupled to it.

[0016] According to another aspect of an embodiment of the present application, a memory system is provided, comprising: one or more memory devices as described in any one of the above; and a memory controller coupled to and controlling the memory devices.

[0017] In the above solution, the memory system is included in a solid state drive (SSD) or a memory card.

[0018] Embodiments of the present application provide a memory device and a memory system. The memory device includes: a first stack; the first stack includes: a first channel structure; a plurality of first memory cells formed along the length of the first channel structure; a plurality of first word lines coupled to the plurality of first memory cells; a plurality of first string drivers coupled to the plurality of first word lines; a gate width of a first string driver in the plurality of first string drivers is set according to a critical dimension of a sub-channel structure in the first channel structure corresponding to the first string driver; and a control circuit coupled to the plurality of first string drivers and configured to, in response to a received first operation command, control the corresponding first string driver to provide a corresponding first operating voltage to the corresponding first word line, thereby causing the first memory cell coupled to the corresponding first word line to perform a corresponding operation. The memory device provided by the embodiment of the present application correlates the gate width of the string driver with the critical dimension of the sub-channel structure of the channel structure, and sets the correlation to be positive. That is, when programming speed is high, the string driver size is larger; when programming speed is low, the string driver size is smaller. This ensures programming requirements and saves chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In the accompanying drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0020] Figure 1 A block diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0021] Figure 2 A schematic diagram of an exemplary memory card having a memory system provided in accordance with an embodiment of the present application;

[0022] Figure 3 A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0023] Figure 4 A schematic diagram of an exemplary memory device including a peripheral circuit provided in an embodiment of the present application;

[0024] Figure 5 A schematic cross-sectional view of an exemplary memory cell array including NAND memory strings provided in one embodiment of the present application;

[0025] Figure 6 Another cross-sectional diagram of an exemplary memory cell array 401 including NAND memory strings provided in one embodiment of the present application

[0026] Figure 7 A schematic diagram of a peripheral circuit of a memory device provided in one embodiment of the present application

[0027] Figures 8A to 8B A schematic diagram of the connection relationship between a row decoder / WL driver and a memory cell array provided in one embodiment of the present application;

[0028] Figure 9 A schematic structural diagram of a memory device provided in one embodiment of the present application;

[0029] Figure 10 Another cross-sectional schematic diagram of an exemplary memory cell array 401 including NAND memory strings provided in one embodiment of the present application;

[0030] Figure 11 An embodiment of the present application provides Figure 9 The memory cell array shown corresponds to a schematic diagram of the size arrangement of multiple string drivers;

[0031] Figure 12 A schematic diagram of the control logic flow of corresponding operations provided in an embodiment of the present application;

[0032] Figure 13 A schematic structural diagram of another memory device provided in one embodiment of the present application;

[0033] Figure 14 An embodiment of the present application provides Figure 13The memory cell array shown is a schematic diagram of the size arrangement of multiple string drivers. DETAILED DESCRIPTION

[0034] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0035] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0036] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0037] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0038] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0041] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0042] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0043] The embodiments of the present application are further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present application is shown. Figure 1 In the embodiment, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memory devices 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on chip (SoC), wherein the system on chip may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the memory device 104. Specifically, the memory device 104 may be any memory disclosed in this application, such as phase change random access memory (PCRAM), three-dimensional NAND flash memory, and the like.

[0045] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded Multi Media Card (eMMC), where the SSD or eMMC is used as data storage for mobile devices with high duty cycle environments such as smartphones, tablet computers, and laptop computers, as well as enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) on data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnection (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, etc.

[0046] In some embodiments, the memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2 In one example shown, the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. Memory cards may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card that connects the memory card to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 3 In another example shown, the memory controller 106 and the plurality of memory devices 104 may be integrated into a solid state drive (SSD) 302. The SSD may also include a computer that interfaces the SSD with a host (e.g., Figure 1 The memory controller 106 may further include an SSD connector 304 coupled to the host computer 108. In some embodiments, the SSD may have a greater storage capacity and / or operating speed than a memory card. Furthermore, the memory controller 106 may be configured to control erase, read, and write operations of the memory device 104.

[0047] Among them, Figure 4As shown, the memory device 104 may include a memory cell array 401 and a peripheral circuit 402 coupled to the memory cell array 401, wherein the memory cell array 401 may be a NAND flash memory array, wherein the memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the storage region of the memory cell 406. Each memory cell 406 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0048] In some embodiments, each memory cell 406 is a single-level cell (SLC) that has two possible data states and therefore can store one bit of data. For example, the first data state "0" can correspond to a first voltage range, and the second data state "1" can correspond to a second voltage range. In some embodiments, the first voltage range and the second voltage range can be referred to as the threshold voltage distribution of the memory cell. In some embodiments, each memory cell 406 can be a multi-level cell (MLC). For example, an MLC can store two bits per cell; for another example, it can store three bits per cell (also known as a tri-level cell (TLC); for another example, it can store four bits per cell (also known as a quadruple level cell (QLC)). Regardless of the type of memory cell, the data state includes an erased state and (one or more) programmed states. When a programming operation is performed on the memory cell, the memory cell in the erased state is programmed to a certain programmed state. Generally speaking, the voltage value in the voltage range corresponding to the programmed state of the memory cell is relatively large.

[0049] like Figure 4As shown, each NAND string 408 may include a source select gate (SSG) 410 at its source terminal and a drain select gate (DSG) 412 at its drain terminal. The SSG 410 and DSG 412 may be configured to activate a selected NAND string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND strings 408 in the same memory block 404 are coupled via the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND strings 408 in the same memory block 404 have an array common source (ACS). According to some embodiments, the DSG 412 of each NAND string 408 is coupled to a corresponding bit line 416, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having DSG 412) or a deselect voltage (e.g., 0 volts (V)) to the corresponding DSG 412 via one or more drain select lines (Drain Selective Line) or top select lines (Top Selective Line) 413 and / or applying a select voltage (e.g., higher than the threshold voltage of the transistor having SSG 410) or a deselect voltage (e.g., 0 V) ​​to the corresponding SSG 410 via one or more source select lines (Source Selective Line) or bottom select lines (Bottom Selective Line) 415.

[0050] like Figure 4 As shown, the NAND memory string 408 can be organized into a plurality of memory blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each memory block 404 is a basic data unit with an erase operation, that is, all memory cells 406 on the same memory block 404 are erased at the same time. In order to erase the memory cells 406 in the selected memory block 404, the source lines 414 coupled to the selected memory block 404 and the unselected memory blocks 404 in the same plane (Plane) as the selected memory block 404 can be biased with an erase voltage (Vers) (e.g., a high positive voltage of 20V or higher). It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of blocks or any suitable fraction of blocks. As shown Figure 4 As shown, the memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418 , that is, the same word line 418 can be coupled to memory cells at the same position in multiple memory strings (ie, corresponding memory cells).

[0051] Figure 5 1 shows a cross-sectional side view of an exemplary memory cell array 401 including NAND memory strings 408 according to some aspects of the present application. Figure 5 As shown in FIG, NAND memory string 408 may include a stacked structure 510, which includes multiple gate layers 511 and multiple insulating layers 512 that are alternately stacked in sequence, and a memory string 408 that vertically penetrates the gate layers 511 and the insulating layers 512. The gate layers 511 and the insulating layers 512 may be alternately stacked, with two adjacent gate layers 511 separated by a layer of insulating layer 512. The number of pairs of gate layers 511 and insulating layers 512 in the stacked structure 510 may determine the number of memory cells included in the memory cell array 401.

[0052] The gate layer 511 may be formed of a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 511 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 511 includes a doped polysilicon layer. Each gate layer 511 may include a control gate surrounding a memory cell. The gate layer 511 at the top of the stacked structure 510 can extend laterally to serve as an upper select gate line 513, also known as a TSG line 413. The upper select gate line 513 is also the lead line of the upper select gate (TSG) 412 described above, which can be connected to a corresponding select voltage or cancel voltage. The gate layer 511 at the bottom of the stacked structure 510 can extend laterally to serve as a lower select gate line 514, also known as a source select line (or bottom select line) 415. The lower select gate line 514 is also the lead line of the lower select gate (BSG) 410 described above, which can be connected to a corresponding select voltage or cancel voltage. The gate layer 511 extending laterally between the upper and lower select gate lines can serve as a word line layer 503. These word line layers 503 are also the word lines 418 described above.

[0053] In some embodiments, the stacked structure 510 may be disposed on a substrate 501. The substrate 501 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0054] In some embodiments, the NAND memory string 408 includes a channel structure (CH) 516 extending vertically through the stacked structure 510. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure can have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0055] Figure 6 FIG. 4 is a side view of another cross section of an exemplary memory cell array 401 including NAND memory strings 408 according to some aspects of the present application. In some embodiments, for storage performance or other considerations, the NAND memory strings 408 include multiple decks, such as Figure 6 As shown, the NAND storage string 408 includes three stacks. Each stack has the same or similar structure (there may be slight deviations in the process implementation, so the structure is similar), including Figure 5 The described stacked structures, alternating gate and insulating layers, channel structures, etc. will not be discussed for the sake of brevity except as necessary to discuss the embodiments of the present application.

[0056] Return Reference Figure 4 , the peripheral circuit 402 may be coupled to the memory cell array 401 via the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 401 by applying a voltage signal and / or a current signal to each target memory cell 406 and sensing a voltage signal and / or a current signal from each target memory cell 406 via the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 7Some exemplary peripheral circuits are shown, and the peripheral circuit 402 may include a page buffer / sense amplifier 704, a column decoder / bit line driver 706, a row decoder / word line driver 708, a voltage generator 710, a control logic 712, a register 714, an interface 716, and a data bus 718. It should be understood that in some examples, the peripheral circuit 402 may also include Figure 6 Additional circuitry not shown.

[0057] Specifically, the page buffer / sense amplifier 704 can be configured to read data from the memory cell array 401 and program (write) data to the memory cell array 401 based on control signals from the control logic 712. In one example, the page buffer / sense amplifier 704 can store program data (or write data) to be programmed into the memory cells coupled to a word line in the memory cell array 401. In another example, the page buffer / sense amplifier 704 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cells 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 704 can also sense low-power signals from the bit lines 416 representing the data bits stored in the memory cells 406 and amplify small voltage swings to recognizable logic levels during read operations. The column decoder / bit line driver 706 can be configured to be controlled by the control logic 712 and select one or more NAND memory strings 408 by applying bit line voltages generated by the voltage generator 710.

[0058] The row decoder / wordline driver 708 can be configured to be controlled by control logic 712 and to select / deselect memory blocks 404 of the memory cell array 401 and to select / deselect word lines 418 of the memory blocks 404. The row decoder / wordline driver 708 can also be configured to drive the word lines 418 using word line voltages generated from the voltage generator 710, and to perform programming and reading operations on the memory cells 406 coupled to the selected word line(s) 418. In some embodiments, the row decoder / wordline driver 708 can also select / deselect and drive the SSG lines 415 and DSG lines 413. The voltage generator 710 can be configured to be controlled by control logic 712 and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 401. The control logic 712 can be coupled to each of the circuits described above and configured to control the operation of each peripheral circuit. The register 714 may be coupled to the control logic 712 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 716 may be coupled to the control logic 712 and function as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 712, as well as to buffer status information received from the control logic 712 and relay it to the host. The interface 716 may also be coupled to the column decoder / bit line driver 706 via a data bus 718 and function as a data I / O interface and a data buffer to buffer data and relay it to or from the memory cell array 401.

[0059] Specifically, see Figures 8A to 8B As shown, the row decoder / word line driver 708 applies the word line voltage generated by the voltage generator 710 to the corresponding word line 418 through the string driver included therein to drive the corresponding word line 418. That is, the string driver is coupled to the word line for driving the corresponding word line. Figure 8A A simplified top view of the memory cell array of a 3D NAND flash memory. Figure 8B 2B-2B of a memory cell array 401 is shown. The memory cell array 401 of the 3D NAND flash memory can be connected to a plurality of bit lines 802 (e.g., bit lines 802a to 802n) and a plurality of word line groups 801 (e.g., word line groups 801a to 801n). Each of the bit lines 802 that can be activated by the column decoder / bit line driver 706 can be connected to one or more bit line pillars 803 extending into the memory cell array 401, as shown in FIG. Figure 8AAs shown. Each word line group 801 is connected to one or more corresponding row decoders 708, wherein the row decoder 708 may include a global word line driver 804 and a string driver 805 (e.g., string drivers 805a-n). The global word line driver 804 and the string driver 805, in combination with the column decoder, are configured to activate one or more memory cells 406 in the memory cell array 401 for performing corresponding operations. The global word line driver 804 and the string driver 805 may be arranged in a hierarchical circuit configuration, wherein the global word line driver 804 is connected to one or more local word line drivers of the string driver 805. The control logic of the row decoder 708 is known in the art and, therefore, for the sake of brevity, will not be discussed except as necessary to discuss the embodiments of the present application. In some embodiments, each word line group 801a-n may be operably connected to a corresponding string driver 805a-n. As Figure 8A and Figure 8B As shown in , the layout of the word line group 801 corresponds to the layout of the bit line pillars 803. For example, the word line group and the bit line pillars form a 3D grid pattern. Based on this, the memory cell array 401 can be arranged in a 3D grid structure. The 3D memory cell array 401 can be composed of alternating local word lines 806 and isolation layers 807, the local word lines can be polysilicon films, and the isolation layers 807 can be silicon oxide films. The memory cells 406 can be formed at the intersections of the bit line pillars 803 and the local word lines 806. The configuration of the memory cells 406 can be in the form of, for example, the aforementioned NAND configuration, wherein the local word lines 806 form the control gates in the transistor memory cells 406. Depending on the configuration, other types of configurations can also be used, such as NOR configurations, etc. Multiple memory cells 406 can be set between a DSG (drain side select gate) transistor 809 and an SSG (source side select gate) transistor 810 to form a memory string. DSG transistor 809 connects the memory string to the corresponding bit line 802, and SSG transistor 810 connects the memory string to source line 414. The memory cell array may include multiple memory strings, where each memory string corresponds to a respective bit line 802 along word line group 801a-n. Figure 8A and 8BAs shown, each local word line 806 corresponding to a single row of pillars 803 is shown. However, in some embodiments, each local word line can be a plate shared by more than one row of pillars 803. Each source line 414 can have a one-to-one correspondence with a bit line 802, or the source line 414 can be a plate shared by multiple bit lines 802. The exemplary embodiments of the present application are not limited to the above-mentioned memory cell array structure, and other types / configurations of memory cell array structures (2D / 3D) can be used. Since the memory cell array structure is known in the art, for the sake of brevity, a more detailed discussion is given of the string driver 805 that can be connected to each word line group 801. Each string driver 805 may include multiple local word line (LWL) drivers. Each LWL driver is connected to the corresponding global word line 812 of the global word line driver 804 to drive and activate the corresponding local word line in each word line group 801.

[0060] Based on the 3D memory devices discussed above, as the number of stacked layers increases, the number of word line (WL) layers increases, and subsequently, the number of SD transistors also increases. In this case, the area occupied by the SD transistors also increases.

[0061] To address one or more of the aforementioned issues, an embodiment of the present application provides a memory device that utilizes SD transistors of different sizes (i.e., gate widths) in the same memory string, thereby saving the area occupied by the SD transistors and simultaneously meeting the requirements for higher programming voltages for certain specific word lines WL.

[0062] Specifically, see Figure 9 As shown, the memory device 900 provided in the embodiment of the present application includes:

[0063] First stack 901; the first stack includes: a first channel structure; a plurality of first memory cells formed along the length direction of the first channel structure;

[0064] a plurality of first word lines 902 coupled one by one to the plurality of first memory cells;

[0065] a plurality of first string drivers 903 coupled one-to-one to the plurality of first word lines; wherein a gate width of a first string driver among the plurality of first string drivers is set according to a critical dimension of a sub-channel structure in the first channel structure corresponding to the first string driver;

[0066] And the control circuit 904 is coupled to the multiple first string drivers and is configured to: in response to the received first operation command, control the corresponding first string driver to provide the corresponding operation voltage to the corresponding first word line, so that the first storage unit coupled to the corresponding first word line performs the corresponding operation.

[0067] It should be noted that the first stack may refer to Figure 5 The exemplary stacking structure of the NAND memory string shown. In fact, the first stack includes multiple NAND memory strings, that is, multiple channel structures. Here, only one channel structure is used to illustrate this application, and it is not used to limit the structure of the memory device of this application. And, Figure 5 The cross-sectional schematic diagram of an exemplary memory cell array 401 including NAND memory strings 408 is shown, which illustrates an ideal channel structure with the same critical dimension (CD) at the top and bottom. The so-called CD refers to a specialized line pattern designed to reflect the width of the integrated circuit's characteristic lines, used to evaluate and control the pattern processing accuracy during integrated circuit photomask manufacturing and lithography processes. The physical size characteristic on a chip is called a characteristic dimension. Another term for characteristic dimension is the geometric dimension of a circuit, where the smallest characteristic dimension on a silicon wafer is called a critical dimension.

[0068] In practice, due to the limitations of process conditions, during the CH etching process of 3D NAND, the CD of the top CH is large and the CD of the bottom CH is small. Specifically, Figure 10 shown. Figure 10 In the figure, A is the CD of the top CH; A3 is the CD of the bottom CH. The CD at A is greater than the CD at A3. In actual applications, memory cells corresponding to CHs with different CDs have varying programming speeds. A larger CD indicates a slower programming speed, while a smaller CD indicates a faster programming speed. The programming speed can reflect how quickly a memory cell is programmed to a target data state. The programming speed is measured by the number of programming pulses used to program the memory cell to the target data state. A greater number of programming pulses indicates a slower programming speed, while a smaller number of programming pulses indicates a faster programming speed. The target data state here can refer to one of the aforementioned programming states: SLC, MLC, TLC, and QLC. The programming pulse can refer to the programming voltage applied to the corresponding word line. Specifically, for the same target data state, a greater number of programming pulses indicates a slower programming speed, while a smaller number of programming pulses indicates a faster programming speed.

[0069] Here, the sub-channel structure may refer to a channel in which the CH is divided into multiple segments. The critical dimension of the sub-channel structure may refer to the minimum dimension of the channel in the corresponding segment. For example, Figure 10As shown, A to A1 corresponds to a sub-channel structure; A1 to A2 corresponds to a sub-channel structure; and A2 to A3 corresponds to a sub-channel structure. Moreover, the CD of the CH corresponding to A to A1 is greater than the CD of the CH corresponding to A1 to A2, and the programming speed of the memory cell corresponding to A to A1 is slower than the programming speed of the memory cell corresponding to A1 to A2. The programming speed is also negatively correlated with the CD of CH. This is because the larger the CD of CH, the more time it takes to raise the channel potential during programming, that is, the slower the programming speed. Similarly, the programming speed of the memory cell corresponding to A1 to A2 is slower than the programming speed of the memory cell corresponding to A2 to A3. Combined with the previous description, that is, when programming the memory cell with a larger CD, more programming pulses are used to program the memory cell to the target data state, and the programming speed is slow; when programming the memory cell with a smaller CD, fewer programming pulses are used, and the programming speed is fast. In some embodiments, each sub-channel structure in the first channel structure can be as follows Figure 10 In some embodiments, each sub-channel structure in the first channel structure can also be divided in a uniform manner. Figure 11 shown.

[0070] In the present application, a gate width of a first string driver among the plurality of first string drivers coupled to the plurality of first word lines is set based on a critical dimension of a sub-channel structure within a first channel structure corresponding to the first string driver. Specifically, the larger the critical dimension of the sub-channel structure within the first channel structure, the larger the gate width of the corresponding first string driver; conversely, the smaller the critical dimension of the sub-channel structure within the first channel structure, the smaller the gate width of the corresponding first string driver.

[0071] For example, as mentioned above Figure 10 In the sub-channel structure shown, the gate width of the first string driver corresponding to the sub-channel structure between A to A1 is greater than the gate width of the first string driver corresponding to the sub-channel structure between A1 to A2; the gate width of the first string driver corresponding to the sub-channel structure between A1 to A2 is greater than the gate width of the first string driver corresponding to the sub-channel structure between A2 to A3.

[0072] To understand it in another way, it can also be said that the gate widths of the aforementioned multiple first string drivers can be set according to the programming speed of the memory cell coupled to the word line coupled to the sub-channel structure in the corresponding first channel structure. That is, the faster the programming speed of the corresponding memory cell, the smaller the gate width of the corresponding first string driver; the slower the programming speed of the corresponding memory cell, the larger the gate width of the corresponding first string driver.

[0073] In some embodiments, the plurality of first memory cells are divided into a plurality of first memory groups; wherein the gate widths of the first string drivers corresponding to the first word lines coupled to the first memory cells in different first memory groups are different.

[0074] In some embodiments, the gate widths of first string drivers corresponding to first word lines coupled to first memory cells in the same first memory group are the same.

[0075] For example, Figure 11 As shown, the first channel structure in the first stack is divided into three sections; based on this, the plurality of first memory cells formed along the first channel structure can be divided into three first memory groups, namely: the first group (also recorded as group1), the second group (also recorded as group2), and the third group (group3, wherein the CD of the CH corresponding to group1 is greater than the CD of the CH corresponding to group2; the CD of the CH corresponding to group2 is greater than the CD of the CH corresponding to group3. Here, the CD of the CH corresponding to group1 can refer to the smallest feature size in the CH corresponding to group1, for example, Figure 11 B in the diagram. The CDs corresponding to the remaining memory groups can be understood similarly. In this grouping, the gate width of the SD corresponding to group 1 is greater than that of the SD corresponding to group 2; and the gate width of the SD corresponding to group 2 is greater than that of the SD corresponding to group 3. Within group 1, the gate widths of the first strings of drivers coupled to different first word lines can be the same; within group 2, the gate widths of the first strings of drivers coupled to different first word lines can be the same; and within group 3, the gate widths of the first strings of drivers coupled to different first word lines can also be the same. This design saves area and simplifies the design.

[0076] In some embodiments, the corresponding operation includes one of the following: a read operation, a write operation, and an erase operation.

[0077] It should be noted that the function of the first string driver is to apply the corresponding operating voltage to the corresponding first word line. These operations are also called corresponding operations. The corresponding operations may include but are not limited to read operations, write operations, and erase operations.

[0078] In some embodiments, the control circuit includes: control logic, a voltage generator, and a row decoder, wherein the control logic is configured to: receive a first operation command and input address information; generate a voltage control signal in response to the first operation command, and transmit the voltage control signal to the voltage generator, and transmit the input address information to the row decoder;

[0079] The voltage generator is configured to: generate an operating voltage corresponding to the first operating command according to the voltage control signal;

[0080] The row decoder is coupled to the voltage generator and the plurality of first string drivers and is configured to: parse the input address information to obtain an operation address; and transmit the operation voltage to the first string driver corresponding to the operation address;

[0081] The corresponding first string driver is configured to provide the operating voltage to the first word line coupled thereto.

[0082] It should be noted that the control circuit described here may be part of the peripheral circuit described above. In other words, the control circuit described here only describes the structure of interest in the embodiments of this application, while other structures in the peripheral circuit and their functions are well known in the art and will not be discussed here. Based on the connection relationship and respective functions of the row decoder, string driver, and word line described above.

[0083] like Figure 12 As shown, it illustrates the control logic flow described above. Specifically, the control logic flow can be as follows: the control logic receives a first operation command (CMD) and input address information (ADDR), and generates a voltage control signal in response to the received first operation command, and transmits the voltage control signal to the voltage generator, and transmits the input address information to the row decoder; the voltage generator generates an operation voltage corresponding to the received operation command according to the voltage control signal; the row decoder parses the input address information, obtains the operation address, and transmits the corresponding operation voltage to the first string driver corresponding to the operation address; the corresponding first string driver provides the corresponding operation voltage to the first word line coupled thereto. Figure 12 Here, Vpass, Vread, and Vpgm may refer to a pass voltage, a read voltage, and a programming voltage, respectively.

[0084] In some embodiments, as Figure 13 As shown, the memory device may further include: a plurality of second stacks 905; wherein each of the plurality of second stacks includes:

[0085] a second channel structure; a plurality of second memory cells formed along the length direction of the second channel; and a plurality of second word lines coupled one-to-one with the plurality of second memory cells;

[0086] a plurality of second string drivers coupled one-to-one to the second word lines; wherein a gate width of a second string driver in the plurality of second string drivers is set according to a critical dimension of a sub-channel structure in the second channel structure corresponding to the second string driver;

[0087] The control circuit is coupled to the plurality of second string drivers and is configured to, in response to a received second operation command, control the corresponding second string driver to provide a corresponding operation voltage to its corresponding second word line, so that the second storage unit coupled to the corresponding second word line performs a corresponding operation.

[0088] In some embodiments, the larger the critical dimension of the sub-channel structure in the second channel structure, the larger the gate width of the corresponding second string driver; conversely, the smaller the critical dimension of the sub-channel structure in the second channel structure, the smaller the gate width of the corresponding second string driver.

[0089] In some embodiments, the multiple second storage cells are divided into multiple second storage groups; wherein, the gate widths of the second string drivers corresponding to the second word lines coupled to the second storage cells in different second storage groups are different; and the gate widths of the second string drivers corresponding to the second word lines coupled to the second storage cells in the same second storage group are the same.

[0090] In some embodiments, the plurality of first storage groups and the plurality of second storage groups are the same in number.

[0091] That is, the size of the second string drivers corresponding to each second stack in the plurality of second stacks is set in the same manner as the size of the first string drivers corresponding to the first stack. Figures 9 to 12 The description shown in FIG. 1 is omitted here. That is, the memory cell array of the memory device may further include a plurality of second stacks and a plurality of second string drivers corresponding to a plurality of second word lines coupled to a plurality of second memory cells included in each second stack. The structure of each second stack is the same as that of the first stack. For example, the structure of the second stack may also be as follows: Figure 10 Furthermore, the size setting method of the plurality of second string drivers corresponding to each second stack is also the same as the size setting method of the first string drivers corresponding to the first stack, such as Figure 11 The settings shown.

[0092] In addition, the plurality of second stacks may be arranged above the first stack, or the plurality of second stacks may be arranged below the first stack; or the first stack may be arranged between the plurality of second stacks. The positional relationship between the second stacks is not limited in this application.

[0093] In other words, for storage capacity or other considerations, the memory cell array may include multiple Figure 10The stack structure shown is a stack structure, and each stack is arranged in a vertical direction. The structure of each stack is the same, and the other devices corresponding to each stack (such as multiple string drivers) are arranged in the same way.

[0094] For example, Figure 14 , which shows another cross-sectional schematic diagram of an exemplary memory cell array 401 including a NAND memory string 408. Figure 14 , the NAND storage string 408 includes two stacks: an upper stack (including an upper channel structure, also known as UCH) and a lower stack (including a lower channel structure, also known as LCH). The structure of each stack is as follows Figure 10 As shown, the CD of CH is different from top to bottom; the gate width of multiple string drivers corresponding to each stack is set as follows Figure 11 As shown, three sizes are set. That is, from top to bottom, the UCH is as follows: the gate width of the SD corresponding to the first group (group 1) is larger than the gate width of the SD corresponding to the second group (group 2); the gate width of the SD corresponding to the second group (group 2) is larger than the gate width of the SD corresponding to the third group (group 3). Similarly, from top to bottom, the LCH is as follows: the gate width of the SD corresponding to the first group (group 1) is larger than the gate width of the SD corresponding to the second group (group 2); the gate width of the SD corresponding to the second group (group 2) is larger than the gate width of the SD corresponding to the third group (group 3).

[0095] Embodiments of the present application provide a memory device that associates the gate sizes of multiple string drivers with the programming speed of the memory cells coupled to their corresponding word lines, with a negative correlation. Specifically, faster programming speeds correspond to smaller string driver gate widths, while slower programming speeds correspond to larger string driver gate widths. This allows for a smaller string driver footprint in the memory device while still meeting the higher programming voltage requirements of specific word lines.

[0096] Based on the same inventive concept, an embodiment of the present application further provides a memory system, comprising: one or more memory devices as described in any one of the above; and a memory controller coupled to and controlling the memory devices.

[0097] In some embodiments, the memory system may be contained in a solid state drive (SSD) or a memory card.

[0098] It should be noted that the memory system includes the aforementioned memory device, and therefore, the two have the same technical features. The terms appearing in the memory system are explained in detail in the aforementioned memory device, and are also applicable here, and will not be repeated one by one. For other structures included in the memory system and the connection relationship with other devices such as the host, please refer to Figures 1 to 3 The accompanying drawings shown will not be described in detail here.

[0099] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments may be used, such as those available to a person of ordinary skill in the art upon reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to simplify the present invention. This should not be interpreted as meaning that unclaimed disclosed features are essential to any claim. On the contrary, the disclosed subject matter may be less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment, and it is expected that these embodiments may be combined with each other in various combinations or permutations. The scope of this application should be determined with reference to the appended claims and the full scope of equivalents to which these claims are assigned.

Claims

1. A memory device, characterized in that: include: A first stack; wherein the first stack comprises: a first channel structure; a plurality of first memory cells formed along a length direction of the first channel structure; a plurality of first word lines coupled one-to-one to the plurality of first memory cells; a plurality of first string drivers coupled one-to-one to the plurality of first word lines; wherein a gate width of a first string driver among the plurality of first string drivers is set according to a critical dimension of a sub-channel structure in the first channel structure corresponding to the first string driver; and a control circuit coupled to the plurality of first string drivers and configured to: in response to a received first operation command, control the corresponding first string driver to provide a corresponding operation voltage to its corresponding first word line, so that the first storage unit coupled to the corresponding first word line performs a corresponding operation.

2. The memory device according to claim 1, wherein The larger the critical dimension of the sub-channel structure in the first channel structure, the larger the gate width of the corresponding first string driver; conversely, the smaller the critical dimension of the sub-channel structure in the first channel structure, the smaller the gate width of the corresponding first string driver.

3. The memory device according to claim 1 or 2, wherein: The plurality of first memory cells are divided into a plurality of first memory groups; wherein the gate widths of the first string drivers corresponding to the first word lines coupled to the first memory cells in different first memory groups are different.

4. The memory device according to claim 3, wherein: The gate widths of the first string drivers corresponding to the first word lines coupled to the first memory cells in the same first memory group are the same.

5. The memory device according to claim 3, wherein: Also includes: A plurality of second stacks; wherein each of the plurality of second stacks comprises: a second channel structure; a plurality of second memory cells formed along the length direction of the second channel; and a plurality of second word lines coupled one-to-one with the plurality of second memory cells; a plurality of second string drivers coupled one-to-one to the second word lines; wherein a gate width of a second string driver in the plurality of second string drivers is set according to a critical dimension of a sub-channel structure in the second channel structure corresponding to the second string driver; The control circuit is coupled to the plurality of second string drivers and is configured to, in response to a received second operation command, control the corresponding second string driver to provide a corresponding operation voltage to its corresponding second word line, so that the second storage unit coupled to the corresponding second word line performs a corresponding operation.

6. The memory device according to claim 5, wherein: The larger the critical dimension of the sub-channel structure in the second channel structure, the larger the gate width of the corresponding second string driver; conversely, the smaller the critical dimension of the sub-channel structure in the second channel structure, the smaller the gate width of the corresponding second string driver.

7. The memory device according to claim 5 or 6, characterized in that The multiple second storage cells are divided into multiple second storage groups; wherein, the gate widths of the second string drivers corresponding to the second word lines coupled to the second storage cells in different second storage groups are different; and the gate widths of the second string drivers corresponding to the second word lines coupled to the second storage cells in the same second storage group are the same.

8. The memory device according to claim 7, wherein: The plurality of first storage groups and the plurality of second storage groups are the same in number.

9. The memory device according to claim 5, wherein: The plurality of second stacks are arranged above the first stack, or the plurality of second stacks are arranged below the first stack.

10. The memory device according to claim 1, wherein The corresponding operation includes one of the following: a read operation, a write operation, and an erase operation.

11. The memory device according to claim 1, wherein The control circuit includes: control logic, voltage generator, and row decoder, wherein: The control logic is configured to: receive a first operation command and input address information; generate a voltage control signal in response to the first operation command, and transmit the voltage control signal to the voltage generator and transmit the input address information to the row decoder; The voltage generator is configured to: generate an operating voltage corresponding to the first operating command according to the voltage control signal; The row decoder is coupled to the voltage generator and the plurality of first string drivers and is configured to: parse the input address information to obtain an operation address; and transmit the operation voltage to the first string driver corresponding to the operation address; The corresponding first string driver is configured to provide the operating voltage to the first word line coupled thereto.

12. A memory system, characterized in that: include: One or more memory devices according to any one of claims 1 to 11; and a memory controller coupled to the memory device and controlling the memory device.

13. The memory system according to claim 12, wherein: The memory system is included in a solid state drive SSD or a memory card.

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