Semiconductor structure
By forming a sealed through hole in the semiconductor structure and using a sealing ring structure as an etch stop layer, the problem of cracks in the dielectric structure during the etching process is solved, thereby ensuring the integrity of the semiconductor structure.
Patent Information
- Application Number
- CN202410315683.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-06
- Filing Date
- 2024-03-19
- Publication Date
- 2025-09-09
AI Technical Summary
In semiconductor structures, the etching process of the seal ring structure causes cracks in the dielectric structure, which in turn causes damage to the semiconductor structure during subsequent thermal processes.
By forming a sealing through hole in the dielectric structure so as to directly contact the sealing ring structure, and using the sealing ring structure as an etch stop layer, cracks in the dielectric structure are prevented from being generated during the etching process.
It effectively prevents cracks in the dielectric structure during the etching process, protects the semiconductor structure from damage, and improves the reliability of the manufacturing process.
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Figure CN120613312A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly to a semiconductor structure including a seal ring structure and a seal via and a manufacturing method thereof. Background Art
[0002] In semiconductor structures, moisture and stress are isolated by seal rings and slit structures. The slit structure is located above the seal ring. However, the etching process used to form the slit structure often causes cracks in the dielectric structure. When the cracks extend to the underlying conductive layer (e.g., metal layer), subsequent thermal processes can cause expansion of the conductive layer and damage the semiconductor structure (e.g., peeling). Summary of the Invention
[0003] The invention provides a semiconductor structure and a manufacturing method thereof, which can prevent the semiconductor structure from being damaged.
[0004] The present invention provides a semiconductor structure comprising a substrate, a dielectric structure, a first sealing ring structure, and a first sealing via. The substrate includes a component region. The dielectric structure is located on the substrate. The first sealing ring structure is located within the dielectric structure. The first sealing ring structure surrounds the component region. A first sealing via is located within the dielectric structure. The first sealing via surrounds the component region. The first sealing via is located on the first sealing ring structure. The first sealing via directly contacts the first sealing ring structure.
[0005] According to an embodiment of the present invention, in the semiconductor structure, the device region may be an active device region or a passive device region.
[0006] According to an embodiment of the present invention, in the semiconductor structure, the device region may be a memory region.
[0007] According to an embodiment of the present invention, in the semiconductor structure, the memory region may be a 3D AND flash memory region.
[0008] According to an embodiment of the present invention, in the semiconductor structure, the substrate may further include a scribe line region. The scribe line region may surround the device region. The seal ring structure may be located between the device region and the scribe line region.
[0009] According to an embodiment of the present invention, in the semiconductor structure, the first sealing via may be located directly above the first sealing ring structure.
[0010] According to an embodiment of the present invention, in the semiconductor structure, the maximum width of the first sealing via may be smaller than the maximum width of the first sealing ring structure.
[0011] According to an embodiment of the present invention, in the semiconductor structure, the material of the first sealing ring structure may include metal. The material of the first sealing via may include metal.
[0012] According to an embodiment of the present invention, in the semiconductor structure, the top view pattern of the first sealing via may be a solid ring shape.
[0013] According to one embodiment of the present invention, the semiconductor structure may further include a second seal ring structure and a second seal via. The second seal ring structure is located within the dielectric structure. The second seal ring structure may surround the first seal ring structure. The second seal via is located within the dielectric structure. The second seal via may surround the first seal via. The second seal via is located on the second seal ring structure. The second seal via may directly contact the second seal ring structure.
[0014] According to an embodiment of the present invention, in the semiconductor structure, the top view pattern of the first sealing via may be a solid line ring, and the top view pattern of the second sealing via may be a solid line ring.
[0015] According to an embodiment of the present invention, in the semiconductor structure, the top view pattern of the first sealing via may be a solid ring shape, and the top view pattern of the second sealing via may be a dashed ring shape.
[0016] According to an embodiment of the present invention, in the semiconductor structure, the top view pattern of the first sealing via may be a dotted ring shape, and the top view pattern of the second sealing via may be a solid ring shape.
[0017] According to an embodiment of the present invention, in the semiconductor structure, the top view pattern of the first sealing via may be a dotted ring shape, and the top view pattern of the second sealing via may be a dotted ring shape.
[0018] According to one embodiment of the present invention, in the semiconductor structure described above, a top view pattern of the first sealed via may include a plurality of first line portions and a plurality of first openings arranged alternately. A top view pattern of the second sealed via may include a plurality of second line portions and a plurality of second openings arranged alternately. The plurality of first line portions may be aligned with the plurality of second openings. The length of each first line portion may be greater than or equal to the length of each second opening. The plurality of second line portions may be aligned with the plurality of first openings. The length of each second line portion may be greater than or equal to the length of each first opening.
[0019] The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps: providing a substrate. The substrate includes a component region. Forming a dielectric structure on the substrate. Forming a first seal ring structure in the dielectric structure. The first seal ring structure surrounds the component region. Forming a first seal via in the dielectric structure. The first seal via surrounds the component region. The first seal via is located on the first seal ring structure. The first seal via directly contacts the first seal ring structure.
[0020] According to one embodiment of the present invention, the method for manufacturing the semiconductor structure may further include the following steps: forming a stacked structure in the dielectric structure in the device region. The stacked structure may include a plurality of dielectric layers and a plurality of conductor layers arranged alternately. The stacked structure may have a stepped portion. forming a plurality of contact windows in the dielectric structure. The plurality of contact windows may be electrically connected to the plurality of conductor layers in the stepped portion.
[0021] According to an embodiment of the present invention, in the method for manufacturing the semiconductor structure, the plurality of contact windows and the first sealing vias can be formed simultaneously by the same process.
[0022] According to one embodiment of the present invention, in the manufacturing method of the above-mentioned semiconductor structure, the substrate may further include a sealing ring area. The first sealing ring structure and the first sealing through-hole are located in the sealing ring area. The method for forming multiple contact windows and first sealing through-holes may include the following steps. A plurality of first openings are formed in the dielectric structure. The multiple first openings are located in the component area and expose multiple conductor layers. A second opening is formed in the dielectric structure. The second opening is located in the sealing ring area and exposes the first sealing ring structure. A conductor material layer is formed in the multiple first openings and the second openings and on the dielectric structure. The conductor material layer located outside the multiple first openings and outside the second openings is removed to form multiple contact windows and the first sealing through-hole.
[0023] According to an embodiment of the present invention, the method for manufacturing the semiconductor structure may further include the following steps: forming a second seal ring structure in the dielectric structure. The second seal ring structure may surround the first seal ring structure. forming a second seal through-hole in the dielectric structure. The second seal through-hole may surround the first seal through-hole. The second seal through-hole is located on the second seal ring structure. The second seal through-hole may directly contact the second seal ring structure.
[0024] Based on the foregoing, in the semiconductor structure and manufacturing method proposed in the present invention, the first sealing via is located on the first sealing ring structure and directly contacts the first sealing ring structure. Thus, during the formation of the first sealing via, the first sealing ring structure can be used as an etch stop layer to etch the dielectric structure, thereby forming an opening to accommodate the first sealing via. This prevents cracks in the dielectric structure during the etching process, thereby preventing damage to the semiconductor structure.
[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figures 1A to 1E 1 is a cross-sectional view of a manufacturing process of a semiconductor structure according to some embodiments of the present invention.
[0027] Figure 2A FIG. 1 is a top view of a semiconductor structure according to some embodiments of the present invention.
[0028] Figure 2B 1 and 2 are top views of semiconductor structures according to some other embodiments of the present invention.
[0029] Figure 2C 1 and 2 are top views of semiconductor structures according to some other embodiments of the present invention.
[0030] Figure 2D 1 and 2 are top views of semiconductor structures according to some other embodiments of the present invention.
[0031] Figure 3A FIG. 4 is a circuit diagram of a 3D AND flash memory array according to some embodiments of the present invention.
[0032] Figure 3B for Figure 3A A partial perspective view of the memory array in the middle section.
[0033] Figure 3C and Figure 3D To follow Figure 3B Cross-sectional view along section line II-II'.
[0034] Figure 3E for Figure 3B 、 Figure 3C and Figure 3D Top view of section line III-III'.
[0035] Description of reference numerals:
[0036] 10, A (i) , A (i+1) : Memory array
[0037] 12: Charge storage layer
[0038] 14: Tunneling layer
[0039] 16: Channel Column
[0040] 20: Storage unit
[0041] 24: Insulation filling layer
[0042] 28: Insulation column
[0043] 32a: Conductor column / source column
[0044] 32b: Conductor column / drain column
[0045] 36: Barrier layer
[0046] 38: Gate layer / word line / conductor layer
[0047] 40: Charge storage structure
[0048] 50: Dielectric substrate / dielectric layer
[0049] 50s: Surface
[0050] 53, 108, 114: Conductor layer
[0051] 54: Insulation layer
[0052] 60: Arrow
[0053] 100: Base
[0054] 102, 112, 118, 120, 122: Dielectric layer
[0055] 104, 106: Sealing ring structure
[0056] 110: Stacked structure
[0057] 116: Dielectric stack structure
[0058] 124: Dielectric Structure
[0059] 126: Conductor material layer
[0060] 126a, 126b: Contact window
[0061] 126c, 126d: Sealed through-holes
[0062] BLOCK (i) , BLOCK (i+1) : Block
[0063] BL n , BL n+i : Bit line
[0064] GSK: Gate stack structure
[0065] H1: Height
[0066] H2: Height
[0067] L1, L2, L3, L4: Length
[0068] OP1, OP2, OP3, OP4, OP5, OP6: opening
[0069] R1: Component area
[0070] R2: Cutting area
[0071] R3: Sealing ring area
[0072] S1: Semiconductor Structure
[0073] SCP: Stairway
[0074] SL n , SL n+1 : Source line
[0075] SP (i) n , Sp (i) n+1 , Sp (i+1) n , Sp (i+1) 1n+1 :Source column
[0076] DL1, DL2: Open
[0077] DP (i) n , DP (i) n+1 , DP (i+1) n , DP (i+ 1 ) n+1 : Drain column
[0078] WL (i) m , WL (i) m+i , WL (i+1) m , WL (i+1) m+1 :Word line
[0079] W1, W2, W3, W4: Maximum width
[0080] X, Y, Z: direction DETAILED DESCRIPTION
[0081] The following examples are illustrated in detail with accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, identical components will be designated by the same reference numerals throughout the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Furthermore, features in the top views are not drawn to the same scale as those in the cross-sectional views. Indeed, the dimensions of various features may be arbitrarily increased or decreased for clarity.
[0082] Figures 1A to 1E 1 is a cross-sectional view of a manufacturing process of a semiconductor structure according to some embodiments of the present invention. Figure 2A is a top view of a semiconductor structure according to some embodiments of the present invention. Figure 2A in, omit Figure 1E To clearly illustrate some of the components in Figure 2A The relationship between components in the setting. Figures 1A to 1E To follow Figure 2A Sectional view along section line I-I'. Figure 2B 1 and 2 are top views of semiconductor structures according to some other embodiments of the present invention. Figure 2C 1 and 2 are top views of semiconductor structures according to some other embodiments of the present invention. Figure 2D 1 and 2 are top views of semiconductor structures according to some other embodiments of the present invention.
[0083] Please refer to Figure 1A 2 , a substrate 100 is provided. The substrate 100 includes a device region R1. The device region R1 may be a region for forming semiconductor devices (e.g., active devices or passive devices). In some embodiments, the substrate 100 may further include a scribe line region R2. The scribe line region R2 may surround the device region R1. In some embodiments, the substrate 100 may further include a seal ring region R3. The seal ring region R3 may be located between the device region R1 and the scribe line region R2. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate.
[0084] In some embodiments, a dielectric layer 102 may be formed on the substrate 100. In some embodiments, the dielectric layer 102 may have a multi-layer structure. In some embodiments, desired semiconductor devices (e.g., active devices (e.g., transistors) and / or passive devices) and / or interconnect structures may be formed on the substrate 100 and / or in the dielectric layer 102, and their description is omitted herein.
[0085] In some embodiments, a seal ring structure 104 may be formed in the dielectric layer 102 in the seal ring region R3. The seal ring structure 104 surrounds the device region R1. In some embodiments, the seal ring structure 104 may be a multi-layer structure. In some embodiments, the material of the seal ring structure 104 may include a metal, such as tungsten, titanium, titanium nitride, or a combination thereof. In some embodiments, a seal ring structure 106 may be formed in the dielectric layer 102 in the seal ring region R3. The seal ring structure 106 may surround the seal ring structure 104. In some embodiments, the seal ring structure 106 may be a multi-layer structure. In some embodiments, the material of the seal ring structure 106 may include a metal, such as tungsten, titanium, titanium nitride, or a combination thereof. In some embodiments, a conductor layer 108 may be formed on the dielectric layer 102. In some embodiments, the material of the conductor layer 108 may be, for example, doped polysilicon.
[0086] In some embodiments, a stacked structure 110 may be formed on the dielectric layer 102 in the device region R1. A conductive layer 108 may be located between the stacked structure 110 and the dielectric layer 102. The conductive layer 108 may be used for grounding. The material of the conductive layer 108 may be doped polysilicon. The stacked structure 110 may include a plurality of dielectric layers 112 and a plurality of conductive layers 114 alternately arranged. The stacked structure 110 may have a stepped portion SCP. In some embodiments, the material of the dielectric layer 112 is, for example, silicon oxide. In some embodiments, the conductive layer 114 may be used as a word line. In some embodiments, the material of the conductive layer 114 may include a metal such as tungsten, titanium, titanium nitride, or a combination thereof.
[0087] Furthermore, a dielectric stack structure 116 is formed on the dielectric layer 102 in the seal ring region R3. The dielectric stack structure 116 may include a plurality of dielectric layers 118 and a plurality of dielectric layers 120 arranged alternately. In some embodiments, the material of the dielectric layer 118 is silicon oxide, for example. In some embodiments, the material of the dielectric layer 120 is silicon nitride, for example.
[0088] In addition, a dielectric layer 122 may be formed on the stacked structure 110 and the dielectric stacked structure 116. The dielectric layer 122 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the dielectric layer 122 is, for example, silicon oxide.
[0089] Through the above method, a dielectric structure 124 may be formed on the substrate 100, a seal ring structure 104 may be formed in the dielectric structure 124, a seal ring structure 106 may be formed in the dielectric structure 124, and a stacked structure 110 may be formed in the dielectric structure 124 in the device region R1. The dielectric structure 124 may include the dielectric layer 102 and the dielectric layer 122 in the device region R1, and the dielectric layer 102, the dielectric stacked structure 116, and the dielectric layer 122 in the seal ring region R3.
[0090] Please refer to Figure 1B , a plurality of openings OP1 may be formed in the dielectric structure 124. The plurality of openings OP1 are located in the device region R1 and expose the plurality of conductive layers 114. The openings OP1 may pass through the dielectric layer 112. In some embodiments, an opening OP2 may be formed in the dielectric structure 124. The opening OP2 is located in the device region R1 and exposes the conductive layer 108. The opening OP2 may pass through the dielectric layer 112. In some embodiments, the dielectric structure 124 and the dielectric layer 112 may be patterned by photolithography and etching processes to form the openings OP1 and OP2.
[0091] Please refer to Figure 1C , an opening OP3 may be formed in the dielectric structure 124. The opening OP3 is located in the seal ring region R3 and exposes the seal ring structure 104. In some embodiments, an opening OP4 may be formed in the dielectric structure 124. The opening OP4 is located in the seal ring region R3 and exposes the seal ring structure 106. In some embodiments, the dielectric structure 124 may be patterned by photolithography and etching processes to form the openings OP3 and OP4. In the etching process used to form the openings OP3 and OP4, the seal ring structure 104 and the seal ring structure 106 may be used as etch stop layers. Therefore, cracks in the dielectric structure 124 may be prevented during the etching process.
[0092] Please refer to Figure 1D A conductive material layer 126 may be formed in the plurality of openings OP1, OP2, OP3, and OP4 and on the dielectric structure 124. In some embodiments, the conductive material layer 126 may be made of a metal such as tungsten, titanium, titanium nitride, or a combination thereof. In some embodiments, the conductive material layer 126 may be formed by physical vapor deposition or chemical vapor deposition.
[0093] Please refer to Figure 1EThe conductive material layer 126 located outside the plurality of openings OP1, OP2, OP3, and OP4 is removed to form a plurality of contact windows 126a, 126b, sealing vias 126c, and 126d. Thus, a plurality of contact windows 126a, 126b, sealing vias 126c, and 126d are formed in the dielectric structure 124. The plurality of contact windows 126a can be electrically connected to the plurality of conductive layers 114 in the stepped portion SCP. The contact window 126b can be electrically connected to the conductive layer 108. The seal ring structure 104, the seal ring structure 106, the sealing vias 126c, and the sealing vias 126d are located in the seal ring region R3. The sealing via 126c directly contacts the seal ring structure 104. The sealing via 126d directly contacts the seal ring structure 106. In some embodiments, the sealing vias 126c and 126d may be slot vias. In some embodiments, the conductive material layer 126 located outside the plurality of openings OP1, OP2, OP3, and OP4 is removed by, for example, chemical mechanical polishing. In the above embodiment, the plurality of contact windows 126a, 126b, sealing vias 126c, and sealing vias 126d may be formed simultaneously using the same process.
[0094] Below, through Figure 1E In addition, although the method for forming the semiconductor structure S1 is described using the above method as an example, the present invention is not limited thereto.
[0095] Please refer to Figure 1E and Figure 2A The semiconductor structure S1 includes a substrate 100, a dielectric structure 124, a sealing ring structure 104, and a sealing through-hole 126c. The substrate 100 includes a device region R1. The device region R1 can be an active device region or a passive device region. In some embodiments, the device region R1 can be a memory region. In some embodiments, the memory region can be a three-dimensional flash memory region, but the present invention is not limited thereto. In some embodiments, the substrate 100 can further include a cutting path region R2. The cutting path region can surround the device region R1. In some embodiments, the substrate 100 can further include a sealing ring region R3. The sealing ring region R3 can be located between the device region R1 and the cutting path region R2.
[0096] The dielectric structure 124 is located on the substrate 100. The seal ring structure 104 is located in the dielectric structure 124. In some embodiments, the seal ring structure 104 may be a die seal ring structure. The seal ring structure 104 surrounds the device region R1. The seal ring structure 104 may be located in the seal ring region R3. The seal ring structure 104 may be located between the device region R1 and the saw street region R2. In some embodiments, the material of the seal ring structure 104 may include a metal such as tungsten, titanium, titanium nitride, or a combination thereof. The seal via 126c is located in the dielectric structure 124. In some embodiments, the seal via 126c may be a die seal via (DSV). The seal via 126c surrounds the device region R1. The seal via 126c is located on the seal ring structure 104. The seal via 126c may be located directly above the seal ring structure 104. The seal via 126c directly contacts the seal ring structure 104. In some embodiments, the maximum width W1 of the sealing through hole 126c may be smaller than the maximum width W2 of the sealing ring structure 104. Figure 2A As shown, the top view pattern of the sealing through hole 126c can be a solid ring. In some embodiments, the material of the sealing through hole 126c can include metal, such as tungsten, titanium, titanium nitride, or a combination thereof.
[0097] In some embodiments, semiconductor structure S1 may further include a seal ring structure 106 and a seal via 126d. Seal ring structure 106 is located within dielectric structure 124. In some embodiments, seal ring structure 106 may be a die seal ring structure. Seal ring structure 106 may surround seal ring structure 104. Seal ring structure 106 may be located within seal ring region R3. Seal ring structure 106 may be located between device region R1 and scribe line region R2. In some embodiments, seal ring structure 106 may be made of a metal such as tungsten, titanium, titanium nitride, or a combination thereof. Seal via 126d is located within dielectric structure 124. In some embodiments, seal via 126d may be a die seal via. Seal via 126d may surround seal via 126c. Seal via 126d is located above seal ring structure 106. Seal via 126d may be located directly above seal ring structure 106. Seal via 126d may directly contact seal ring structure 106. In some embodiments, the maximum width W3 of the sealing via 126d may be smaller than the maximum width W4 of the sealing ring structure 106. In some embodiments, the material of the sealing via 126d may include metal, such as tungsten, titanium, titanium nitride, or a combination thereof.
[0098] In this embodiment, if Figure 2A As shown, the top view pattern of the sealing through hole 126c can be a solid line ring, and the top view pattern of the sealing through hole 126d can be a solid line ring, but the present invention is not limited thereto. In other embodiments, such as Figure 2BAs shown, the top view pattern of the sealing through hole 126c can be a solid line ring, and the top view pattern of the sealing through hole 126d can be a dotted line ring. Figure 2C As shown, the top view pattern of the sealing through hole 126c can be a dotted ring, and the top view pattern of the sealing through hole 126d can be a solid ring. Figure 2D As shown, the top view pattern of the sealing through hole 126 c may be a dotted ring shape, and the top view pattern of the sealing through hole 126 d may be a dotted ring shape.
[0099] In addition, Figure 2D In an embodiment, the top view pattern of the sealed through-hole 126c may include a plurality of line portions DL1 and a plurality of openings OP5 arranged alternately. The top view pattern of the sealed through-hole 126d may include a plurality of line portions DL2 and a plurality of openings OP6 arranged alternately. The plurality of line portions DL1 may align with the plurality of openings OP6. The length L1 of each line portion DL1 may be greater than or equal to the length L2 of each opening OP6. The plurality of line portions DL2 may align with the plurality of openings OP5. The length L3 of each line portion DL2 may be greater than or equal to the length L4 of each opening OP5.
[0100] In some embodiments, the semiconductor structure S1 may further include a conductor layer 108. In this embodiment, Figure 1E As shown, the conductive layer 108 is located between the stacked structure 110 and the dielectric layer 102 in the device region R1, but the present invention is not limited thereto. In other embodiments, although not shown in the figure, the conductive layer 108 may also be located between the dielectric stacked structure 116 and the dielectric layer 102 in the seal ring region R3. The sealing vias 126c and 126d pass through the conductive layer 108 in the seal ring region R3, and a dielectric material is provided between the conductive layer 108 and the sealing vias 126c and 126d, thereby isolating the conductive layer 108 from the sealing vias 126c and 126d.
[0101] In addition, the remaining components in the semiconductor structure S1 can refer to the description of the above embodiment. In addition, the details of each component in the semiconductor structure S1 (such as materials and formation methods, etc.) have been fully described in the above embodiment and will not be repeated here.
[0102] Based on the above embodiments, it can be seen that in the semiconductor structure S1 and its manufacturing method, the sealing via 126c is located on the sealing ring structure 104, and the sealing via 126c directly contacts the sealing ring structure 104. As a result, during the formation of the sealing via 126c, the sealing ring structure 104 can be used as an etch stop layer to perform an etching process on the dielectric structure 124, thereby forming an opening OP3 for accommodating the sealing via 126c. Therefore, cracks in the dielectric structure 124 can be prevented during the etching process, thereby preventing damage to the semiconductor structure S1.
[0103] The semiconductor structure and manufacturing method of the above embodiment can be applied to memory such as three-dimensional AND flash memory or three-dimensional NOR flash memory. Figures 3A to 3E To illustrate three-dimensional AND flash memory.
[0104] Figure 3A FIG. 4 is a circuit diagram of a 3D AND flash memory array according to some embodiments of the present invention. Figure 3B for Figure 3A A partial perspective view of the memory array in the middle section. Figure 3C and Figure 3D To follow Figure 3B Cross-sectional view along section line II-II'. Figure 3E for Figure 3B 、 Figure 3C and Figure 3D Top view of section line III-III'.
[0105] In some embodiments, the components in the component region R1 of the semiconductor structure S1 may be replaced with components such as Figures 3A to 3E The memory array 10 is shown.
[0106] Figure 3A The vertical AND memory array 10 includes two blocks BLOCK arranged in rows and columns. (i) With BLOCK (i+1) Schematic diagram of the block. (i) Including memory array A (i) Memory array A (i) A row (for example, the m+1th row) has a common word line (for example, WL (i) m+1 ) of AND storage cells 20. Memory array A( i ) of each column (eg, the m+1th column) corresponds to a common word line (eg, WL (i) m+1 ) and coupled to different source columns (eg SP (i) n With SP (i) n+1 ) and the drain column (eg DP (i) n With DP (i) n+1 ), so that the AND memory cell 20 is along a common word line (eg WL (i) m+1 ) are logically arranged into a column.
[0107] Memory array A (i) A row (eg, the nth row) has a common source column (eg, SP(i) n ) and a common drain column (such as DP (i) n ) of AND storage cells 20. Memory array A (i) Each row (eg, the nth row) of AND storage cells 20 corresponds to a different word line (eg, WL (i) m+1 With WL (i) m ) and coupled to a common source column (eg SP (i) n ) with a common drain column (e.g. DP (i) n ). Therefore, memory array A (i) AND memory cell 20 along a common source column (eg SP (i) n ) and a common drain column (such as DP (i) n ) are logically arranged in a row. In the physical layout, depending on the fabrication method used, the rows or columns may be twisted, arranged in a honeycomb pattern or otherwise for high density or other reasons.
[0108] exist Figure 3A In the block BLOCK (i) In the memory array A (i) The AND memory cells 20 in the nth row share a common source column (eg Sp (i) n ) with a common drain column (e.g. DP (i) n ). The AND storage cells 20 in the n+1th row share a common source column (eg SP (i) n+1 ) with a common drain column (e.g. DP (i) n+1 ).
[0109] Common source column (such as SP (i) n ) is coupled to a common source line (eg, SL n ); a common drain column (eg DP (i) n ) is coupled to a common bit line (eg, BL n ). Common source column (such as SP (i) n+1 ) is coupled to a common source line (eg, SL n+1 ); a common drain column (eg DP (i) n+1 ) is coupled to a common bit line (eg, BL n+1).
[0110] Similarly, BLOCK (i+1) Including memory array A (i+1) , which is the same as in the block BLOCK (i) Memory array A in (i) Similar. Memory array A (i+1) A row (for example, the m+1th row) has a common word line (for example, WL (i+1) m+1 ) of AND storage cells 20. Memory array A (i+1) Each column (eg, the m+1th column) of AND memory cells 20 corresponds to a common word line (eg, WL (i+1) m+1 ) and coupled to different source columns (eg SP (i+1) n With SP (i+1) n+1 ) and the drain column (eg Dp (i+1) n With DP (i+1) n+1 ). Memory array A (i+1) A row (eg, the nth row) has a common source column (eg, SP (i +1) n ) and a common drain column (such as DP (i+1) n ) of AND storage cells 20. Memory array A (i+1) Each row (eg, the nth row) of AND storage cells 20 corresponds to a different word line (eg, WL (i+1) m+1 With WL (i+1) m ) and coupled to a common source column (eg SP (i+1) n ) with a common drain column (e.g. DP (i+1) n ). Therefore, memory array A (i+1) AND memory cell 20 along a common source column (eg SP (i+1) n ) and a common drain column (such as DP (i+1) n ) are logically configured into one row.
[0111] BLOCK (i+1) Shares a source line (e.g., SL) with block BLOCK(i) n With SL n+1 ) and bit lines (such as BL n With BL n+1). Therefore, the source line SL n and bit line BL n Coupled to block BLOCK (i) AND memory array A (i) The nth row of AND memory cells 20 is coupled to the block BLOCK (i+1) AND memory array A in (i+1) The nth row AND memory cell 20 in the same manner as the source line SL n+1 and bit line BL n+1 AND memory array A coupled to block BLOCK(i) (i) The AND memory cell 20 in the n+1th row is coupled to the block BLOCK (i+1) AND memory array A in (i+1) The AND storage unit 20 in the n+1th row.
[0112] Please refer to Figures 3B to 3D Memory array 10 may be disposed on an interconnect structure of a semiconductor die, such as one or more active devices (e.g., transistors) formed on a semiconductor substrate. Therefore, dielectric substrate (or dielectric layer) 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed on a silicon substrate over a metal interconnect structure. Memory array 10 may include a stacked structure GSK, a plurality of channel pillars 16, a plurality of first conductive pillars (also referred to as source pillars) 32a, a plurality of second conductive pillars (also referred to as drain pillars) 32b, and a plurality of charge storage structures 40.
[0113] Please refer to Figure 3B , a stacked structure GSK is formed on a dielectric substrate 50. The stacked structure GSK includes a plurality of gate layers (also called word lines or conductor layers) 38 and a plurality of insulating layers 54 vertically stacked on a surface 50s of the dielectric substrate 50. In the Z direction, these gate layers 38 are electrically isolated by insulating layers 54 disposed therebetween. The gate layers 38 extend in a direction parallel to the surface of the dielectric substrate 50. The gate layers 38 in the stepped region may have a stepped structure. Therefore, the lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38. Contact windows (not shown) for connecting the gate layers 38 may land at the ends of the gate layers 38 to connect each layer of the gate layers 38 to each wire.
[0114] Please refer to Figures 3B to 3DMemory array 10 further includes a plurality of channel pillars 16. Channel pillars 16 extend continuously through stacked structure GSK and to conductive layer 53 between dielectric substrate 50 and stacked structure GSK. Conductive layer 53 may be made of doped polysilicon. For example, conductive layer 53 may be made of P-type doped polysilicon. In some embodiments, channel pillars 16 may have an annular profile when viewed from above. Channel pillars 16 may be made of a semiconductor, such as undoped polysilicon.
[0115] Please refer to Figures 3B to 3D The memory array 10 further includes a plurality of insulating pillars 28, a plurality of first conductor pillars 32a, and a plurality of second conductor pillars 32b. In this example, the first conductor pillar 32a serves as a source pillar. The second conductor pillar 32b serves as a drain pillar. The first conductor pillar 32a, the second conductor pillar 32b, and the insulating pillar 28 each extend in a direction (i.e., the Z direction) perpendicular to the surface (i.e., the XY plane) of the gate layer 38. The first conductor pillar 32a and the second conductor pillar 32b are separated by the insulating pillar 28 and surrounded by the insulating filling layer 24. The first conductor pillar 32a and the second conductor pillar 32b are electrically connected to the channel pillar 16. The first conductor pillar 32a and the second conductor pillar 32b include doped polysilicon or metal material. The insulating pillar 28 includes silicon nitride or silicon oxide, and the insulating filling layer 24 includes silicon oxide.
[0116] Please refer to Figure 3C and Figure 3D The charge storage structure 40 is disposed between the channel pillar 16 and the plurality of gate layers (or conductor layers) 38. The charge storage structure 40 may include a tunneling layer (or energy gap engineered tunneling oxide layer) 14, a charge storage layer 12, and a blocking layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36. In some embodiments, the tunneling layer 14 and the blocking layer 36 comprise silicon oxide. The charge storage layer 12 comprises silicon nitride or other materials capable of capturing charges. In some embodiments, as Figure 3C As shown, a portion of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the Z direction), while another portion of the charge storage structure 40 (the blocking layer 36) surrounds the gate layer 38. In other embodiments, such as Figure 3D As shown, the charge storage structure 40 (tunneling layer 14 , charge storage layer 12 and blocking layer 36 ) surrounds the gate layer 38 .
[0117] Please refer to Figure 3EThe charge storage structure 40, channel pillar 16, and source and drain pillars 32a and 32b are surrounded by a gate layer 38 and define a memory cell 20. The memory cell 20 can perform 1-bit or 2-bit operations using different operation methods. For example, when a voltage is applied to the source and drain pillars 32a and 32b, electrons can be transferred along the channel pillar 16 and stored in the charge storage structure 40 because the source and drain pillars 32a and 32b are connected to the channel pillar 16, thereby performing a 1-bit operation on the memory cell 20. Furthermore, for operations utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source and drain pillars 32a and 32b. For source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection operations, electrons or holes can be locally trapped in the charge storage structure 40 adjacent to one of the source pillar 32 a and the drain pillar 32 b. This allows the memory cell 20 to perform single-bit (SLC, 1 bit) or multi-bit (MLC, greater than or equal to 2 bits) operations.
[0118] During operation, a voltage is applied to the selected word line (gate layer) 38, for example, when a voltage higher than the corresponding starting voltage (Vth) of the corresponding memory cell 20 is applied, the channel region of the channel pillar 16 intersecting the selected word line 38 is turned on, allowing current to flow from the bit line BL. n or BL n+1 (Shown in Figure 3B ) enters the drain column 32b and flows through the conductive channel region to the source column 32a (eg, in the direction indicated by arrow 60), and finally flows to the source line SL n or SL n+1 (Shown in Figure 3B ).
[0119] In summary, in the semiconductor structure and its manufacturing method according to the above-described embodiments, the sealing via is located on the sealing ring structure, and the sealing via directly contacts the sealing ring structure. Thus, during the formation of the sealing via, the sealing ring structure can be used as an etch stop layer to etch the dielectric structure, thereby forming an opening to accommodate the sealing via. This prevents cracks in the dielectric structure during the etching process, thereby preventing damage to the semiconductor structure.
[0120] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Those skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
Claims
1. A semiconductor structure comprising: a substrate including a component region; a dielectric structure located on the substrate; a first sealing ring structure located in the dielectric structure and surrounding the device region; as well as A first sealing through hole is located in the dielectric structure and surrounds the device region, wherein the first sealing through hole is located on the first sealing ring structure and directly contacts the first sealing ring structure. The semiconductor structure according to claim 1 , wherein the device region comprises a memory region. 3 . The semiconductor structure according to claim 1 , wherein the substrate further comprises a scribe line region, the scribe line region surrounds the device region, and the seal ring structure is located between the device region and the scribe line region. The semiconductor structure according to claim 1 , wherein the first sealing via is located directly above the first sealing ring structure.
5. The semiconductor structure according to claim 1 , further comprising: a second sealing ring structure located in the dielectric structure and surrounding the first sealing ring structure; as well as A second sealing through hole is located in the dielectric structure and surrounds the first sealing through hole, wherein the second sealing through hole is located on the second sealing ring structure and directly contacts the second sealing ring structure. 6 . The semiconductor structure according to claim 5 , wherein a top view pattern of the first sealing via is a solid line ring shape, and a top view pattern of the second sealing via is a solid line ring shape. 7 . The semiconductor structure according to claim 5 , wherein a top view pattern of the first sealing via is a solid ring shape, and a top view pattern of the second sealing via is a dotted ring shape. 8 . The semiconductor structure according to claim 5 , wherein a top view pattern of the first sealing via is a dotted ring shape, and a top view pattern of the second sealing via is a solid ring shape. 9 . The semiconductor structure according to claim 5 , wherein a top view pattern of the first sealing via is a dotted ring shape, and a top view pattern of the second sealing via is also a dotted ring shape.
10. The semiconductor structure according to claim 9, wherein The top view of the first sealing through hole includes a plurality of first line portions and a plurality of first openings arranged alternately. The top view of the second sealing through hole includes a plurality of second line portions and a plurality of second openings arranged alternately. A plurality of the first line portions are aligned with a plurality of the second openings, The length of each first line portion is greater than or equal to the length of each second opening, The plurality of second line portions are aligned with the plurality of first openings, and The length of each of the second line portions is greater than or equal to the length of each of the first openings.