Semiconductor package

Abstract

Disclosed is a semiconductor package including: a first redistribution substrate; a first semiconductor chip and a second semiconductor chip mounted on a top surface of the first redistribution substrate and horizontally spaced apart; a molding layer disposed on a top surface of the first redistribution substrate and surrounding the first semiconductor chip and the second semiconductor chip; a second redistribution substrate disposed on a top surface of the molding layer; an upper package mounted on a top surface of the second redistribution substrate; a vertical electrical connection structure disposed at one side of the first semiconductor chip and the second semiconductor chip and connecting the first redistribution substrate to the second redistribution substrate; a plurality of external connection terminals disposed on a bottom surface of the first redistribution substrate; and a bridge chip and a capacitor chip mounted on a bottom surface of the first redistribution substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0033370 filed on March 8, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package including a bridge chip and a method of manufacturing the same. Background Art

[0004] As the electronics industry continues to evolve, the demand for high performance, high speed, and compact size in electronic products continues to increase. One approach developed as part of the effort to meet these increasing demands is packaging technology that mounts multiple semiconductor chips in a single package.

[0005] A semiconductor package is provided to implement integrated circuit chips used in electronic products. Typically, a semiconductor package is configured such that the semiconductor chip is mounted on a printed circuit board (PCB), and bonding wires or bumps are used to electrically connect the semiconductor chip to the PCB. Compact size, low weight, and / or low manufacturing cost are typical goals in semiconductor package design. With technological advancements, the use of semiconductor packages has expanded to new applications, such as mass storage devices.

[0006] As the degree of integration of semiconductor chips has increased, their size has decreased, making it increasingly difficult to form and test electrical connections between pads on the chip and external connection pads of the semiconductor package containing the chip. Additionally, the reduction in size of semiconductor chips may pose a challenge to obtaining a variety of mounting boards depending on the size of the semiconductor chip. Fan-out panel-level packaging is one way to solve the above-mentioned problem. However, in the case of fan-out panel semiconductor packaging, the area of ​​the redistribution line is inevitably larger than the area of ​​the semiconductor chip. Therefore, there is a problem of giving the semiconductor chip an area that is too large compared to the utilization rate of the semiconductor chip. Summary of the Invention

[0007] Some embodiments of the inventive concept provide a compact-sized semiconductor package.

[0008] Some embodiments of the inventive concept provide a semiconductor package having improved electrical characteristics and improved heat radiation.

[0009] The objects of the present inventive concept are not limited to the above-mentioned objects, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0010] According to some embodiments conceived in the present invention, a semiconductor package may include: a first redistribution substrate; a first semiconductor chip and a second semiconductor chip, mounted on the top surface of the first redistribution substrate and horizontally spaced apart from each other; a molding layer, disposed on the top surface of the first redistribution substrate and surrounding the first semiconductor chip and the second semiconductor chip; a second redistribution substrate, disposed on the top surface of the molding layer; an upper package, mounted on the top surface of the second redistribution substrate; a vertical electrical connection structure, disposed on one side of the first semiconductor chip and the second semiconductor chip, and connecting the first redistribution substrate to the second redistribution substrate; a plurality of external connection terminals, disposed on the bottom surface of the first redistribution substrate; and a bridge chip and a capacitor chip, mounted on the bottom surface of the first redistribution substrate and disposed between the first group of external connection terminals and the second group of external connection terminals.

[0011] According to some embodiments of the present invention, a semiconductor package may include a lower package and an upper package mounted on the lower package. The lower package may include: a first redistribution substrate; a first logic chip and a second logic chip mounted on a top surface of the first redistribution substrate in a first region of the semiconductor package; a molding layer disposed on the top surface of the first redistribution substrate and surrounding the first logic chip and the second logic chip; a vertical electrical connection structure disposed on the top surface of the first redistribution substrate in a second region of the semiconductor package, the second region being horizontally spaced apart from the first region; and a bridge chip mounted on the bottom surface of the first redistribution substrate. The upper package may include: an upper package substrate; a memory chip mounted on the top surface of the upper package substrate; and an upper molding layer disposed on the top surface of the upper package substrate and covering the top surface of the memory chip. The upper package may be disposed in the second region of the semiconductor package.

[0012] According to some embodiments conceived in the present invention, a semiconductor package may include: a first redistribution substrate; a first semiconductor chip and a second semiconductor chip, which are mounted on the top surface of the first redistribution substrate in a first region of the semiconductor package; a second redistribution substrate, which is arranged above the first semiconductor chip and the second semiconductor chip; a vertical electrical connection structure, which is arranged on the top surface of the first redistribution substrate in the second region of the semiconductor package and connects the first redistribution substrate to the second redistribution substrate, the second region being horizontally spaced apart from the first region; an upper package, which is mounted on the top surface of the second redistribution substrate in the second region; a heat radiation member, which is attached to the top surface of the second redistribution substrate in the first region; a plurality of external connection terminals, which are arranged on the bottom surface of the first redistribution substrate; and a bridge chip, which is mounted on the bottom surface of the first redistribution substrate in the first region and is arranged between the first group of external connection terminals and the second group of external connection terminals. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1 to 14 Cross-sectional views illustrating semiconductor packages according to some embodiments of the inventive concept are shown. DETAILED DESCRIPTION

[0014] Throughout this specification, when a component is described as "comprising" a particular element or group of elements, it should be understood that the component consists of only that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component, unless the context indicates otherwise. On the other hand, the term "consisting of" indicates that the component is formed of only the listed elements.

[0015] Ordinal numbers such as "first," "second," and "third" may simply be used as labels for certain elements, steps, etc. to distinguish them from one another. Terms not described with "first," "second," etc. in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a particular ordinal number (e.g., "first" in a particular claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0016] It will be understood that when an element is referred to as being “connected” or “coupled” to another element or being “on” another element, the element can be directly connected or coupled to or directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element or “contacting” or “in contact with” another element (or any form of the word “contacting” is used), there are no intervening elements at the point of contact.

[0017] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as limited to the example embodiments set forth herein. These example embodiments are merely examples, and many implementations and variations that do not require the details provided herein are possible. It should also be emphasized that the present disclosure provides details of alternative examples, but this enumeration of alternatives is not exhaustive. Furthermore, any consistency in details between the various examples should not be construed as requiring such details, and it is impractical to list every possible variation of every feature described herein. Reference should be made to the language of the claims in determining the requirements of the present invention.

[0018] Hereinafter, a semiconductor package according to the inventive concept will be described with reference to the accompanying drawings.

[0019] Figure 1 and Figure 2 Cross-sectional views illustrating semiconductor packages according to some embodiments of the inventive concept are shown.

[0020] Reference Figure 1 The lower package may include a first redistribution substrate 100 , a first semiconductor chip 210 , a second semiconductor chip 220 , a conductive pillar 300 , a molding layer 350 , a second redistribution substrate 400 , a bridge chip 500 , and a passive device chip 600 .

[0021] The first redistribution substrate 100 may include one or more first substrate wiring layers stacked one on top of the other. Each first substrate wiring layer may include a first substrate dielectric pattern 110 and a first substrate wiring pattern 120 within the first substrate dielectric pattern 110. The first substrate wiring pattern 120 of one first substrate wiring layer may be electrically connected to the first substrate wiring pattern 120 of another adjacent first substrate wiring layer. As used herein, components described as "electrically connected" are configured such that electrical signals can be transmitted from one component to another (although such electrical signals may be attenuated in strength during transmission and may be selectively transmitted).

[0022] Any particular first substrate dielectric pattern 110 may comprise a dielectric polymer or a photoimageable dielectric (PID). For example, the photoimageable dielectric may comprise at least one selected from photosensitive polyimide, polybenzoxazole (PBO), phenolic polymer, and benzocyclobutene polymer. Alternatively, the first substrate dielectric pattern 110 may comprise a dielectric material. For example, the first substrate dielectric pattern 110 may comprise silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a dielectric polymer.

[0023] Any specific first substrate wiring pattern 120 can be disposed on the first substrate dielectric pattern 110. The first substrate wiring pattern 120 can extend horizontally on the first substrate dielectric pattern 110. The first substrate wiring pattern 120 can be disposed on the top surface of the first substrate dielectric pattern 110. The first substrate wiring pattern 120 can protrude above the top surface of the first substrate dielectric pattern 110. On the first substrate dielectric pattern 110, the first substrate wiring pattern 120 can be covered by another first substrate dielectric pattern 110 disposed thereon. The first substrate wiring pattern 120 disposed on the uppermost first substrate wiring layer can serve as a substrate pad to which the first semiconductor chip 210, the second semiconductor chip 220, and the conductive pillars 300 discussed below are coupled. For example, a portion of the first substrate wiring pattern 120 disposed on the uppermost first substrate wiring layer may be a first substrate pad 122 on which the first semiconductor chip 210 and the second semiconductor chip 220 are mounted, as described below, and another portion of the first substrate wiring pattern 120 disposed on the uppermost first substrate wiring layer may be a second substrate pad 124 coupled to the conductive pillar 300. As described above, the first substrate wiring pattern 120 may be a pad or line portion of the first substrate wiring layer. For example, the first substrate wiring pattern 120 may be a component used for horizontal redistribution in the first redistribution substrate 100. The first substrate wiring pattern 120 may include a conductive material. For example, the first substrate wiring pattern 120 may include a metal, such as copper (Cu).

[0024] The first substrate wiring pattern 120 may have a mosaic structure. For example, the first substrate wiring pattern 120 may have a via protruding from its bottom surface. The via may be a component used to vertically connect the first substrate wiring patterns 120 of adjacent first substrate wiring layers. Alternatively, the via may be a component used to connect the first substrate wiring pattern 120 of the lowermost first substrate wiring layer to the external pad 130 discussed below. For example, the via may extend from the bottom surface of the first substrate wiring pattern 120 to penetrate the first substrate dielectric pattern 110, thereby coupling to the top surface of the first substrate wiring pattern 120 of the lowermost first substrate wiring layer. For another example, the via may extend from the bottom surface of the first substrate wiring pattern 120 to penetrate the lowermost first substrate dielectric pattern 110, thereby coupling to the top surface of the external pad 130. In this configuration, the upper portion of the first substrate wiring pattern 120 located on the first substrate dielectric pattern 110 may serve as a header, serving as a horizontal line or pad, and the via of the first substrate wiring pattern 120 may serve as a tail. The tail may have a width smaller than that of the header. The width of the tail portion may decrease as the distance from the head portion of the first substrate wiring pattern 120 increases. For example, the tail portion may have a tapered shape. The first substrate wiring pattern 120 may have a T-shape.

[0025] The external pad 130 may be provided on the bottom surface of the lowermost first substrate wiring layer. The external pad 130 may be electrically connected to the first substrate wiring pattern 120. The external pad 130 may serve as a pad to which the external terminal 150 is coupled.

[0026] A substrate protective layer 140 may be provided. The substrate protective layer 140 may cover the bottom surface of the lowermost first substrate wiring layer and expose the external pads 130. External terminals 150 may be provided on the exposed bottom surfaces of the external pads 130. The external terminals 150 may include solder balls or solder bumps, and based on the type and arrangement of the external terminals 150, the semiconductor package may be provided in the form of one of a ball grid array (BGA) type, a fine ball grid array (FBGA) type, and a land grid array (LGA) type.

[0027] The first redistribution substrate 100 may be provided as described above. However, the present invention is not limited thereto. The first redistribution substrate 100 may be a printed circuit board (PCB). For example, the first redistribution substrate 100 may have a core layer and peripheral portions for interconnection on the top and bottom of the core layer.

[0028] The first semiconductor chip 210 and the second semiconductor chip 220 are mounted on the top surface of the first redistribution substrate 100 in the first region R1 of the semiconductor package. The conductive pillars 300 are provided on the top surface of the first redistribution substrate 100 in the second region R2 of the semiconductor package. The second region R2 may be located to one side of the first region R1. The first region R1 and the second region R2 may be provided to be horizontally spaced apart from each other.

[0029] The first semiconductor chip 210 and the second semiconductor chip 220 may be disposed on the top surface of the first redistribution substrate 100. The first semiconductor chip 210 and the second semiconductor chip 220 may be disposed on the top surface of the first redistribution substrate 100 in the first region R1.

[0030] The first semiconductor chip 210 may include a first chip base layer 212 and a first chip wiring layer 214 .

[0031] The first chip base layer 212 may include or may be a semiconductor substrate, such as a semiconductor wafer. The first chip base layer 212 may be a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium (SiGe) substrate, a III-V semiconductor substrate, or an epitaxial film substrate obtained by performing selective epitaxial growth (SEG). For example, the first chip base layer 212 may include at least one selected from silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof. The first integrated circuit may be disposed on the bottom surface of the first chip base layer 212. The first integrated circuit may include a logic circuit. For example, the first semiconductor chip 210 may be a logic chip including the first integrated circuit, and the first integrated circuit may include a logic circuit. In some examples, the first semiconductor chip 210 may include a logic chip including memory elements, a logic semiconductor chip including various integrated elements, or a passive device chip. The bottom surface of the first semiconductor chip 210 may be an active surface, and the top surface of the first semiconductor chip 210 may be an inactive surface. For example, the first semiconductor chip 210 may be disposed face-down on the first redistribution substrate 100.

[0032] The first chip wiring layer 214 may be disposed on the bottom surface of the first chip base layer 212. For example, the first chip wiring layer 214 may include a first chip dielectric pattern and a first chip wiring pattern formed on the bottom surface of the first chip base layer 212.

[0033] On the bottom surface of the first chip base layer 212 , a first chip dielectric pattern may cover the first integrated circuit. The first chip dielectric pattern may include a dielectric material. For example, the first chip dielectric pattern may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or a dielectric polymer. Alternatively, the first chip dielectric pattern may include a dielectric polymer or a photoimageable dielectric (PID). For example, the photoimageable dielectric may include at least one selected from photosensitive polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer.

[0034] The first chip wiring pattern may be disposed in the first chip dielectric pattern. The first chip wiring pattern may be electrically connected to the first integrated circuit on the bottom surface of the first chip base layer 212. The first chip wiring pattern may include a conductive material. For example, the first chip wiring pattern may include copper (Cu) or aluminum (Al).

[0035] The first semiconductor chip 210 may include a first chip pad 216 disposed on a bottom surface of the first semiconductor chip 210. The first chip pad 216 may be disposed on a bottom surface of the first chip wiring layer 214. The first chip pad 216 may be electrically connected to the first integrated circuit on the bottom surface of the first chip base layer 212 through a first chip wiring pattern in the first chip wiring layer 214.

[0036] In some examples, the first chip wiring layer 214 may further include a circuit pattern or a protection layer.

[0037] The first semiconductor chip 210 may be mounted on the top surface of the first redistribution substrate 100. For example, the first semiconductor chip 210 may be a flip chip mounted on the top surface of the first redistribution substrate 100. In this configuration, the first semiconductor chip 210 may be electrically connected to a set of first substrate pads 122 of the first redistribution substrate 100 through first connection terminals 218. The first connection terminals 218 may be provided between the first chip pads 216 of the first semiconductor chip 210 and the set of first substrate pads 122 of the first redistribution substrate 100.

[0038] The second semiconductor chip 220 may also be mounted on the top surface of the first redistribution substrate 100 and may be disposed horizontally spaced apart from the first semiconductor chip 210. The second semiconductor chip 220 may include a second chip base layer 222 and a second chip wiring layer 224.

[0039] The second chip base layer 222 may include or may be a semiconductor substrate, such as a semiconductor wafer. The second chip base layer 222 may be a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium (SiGe) substrate, a III-V semiconductor substrate, or an epitaxial film substrate obtained by performing selective epitaxial growth (SEG). For example, the second chip base layer 222 may include at least one selected from silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof. A second integrated circuit may be disposed on the bottom surface of the second chip base layer 222. The second integrated circuit may include a logic circuit. For example, the second semiconductor chip 220 may be a logic chip including the second integrated circuit, and the second integrated circuit may include a logic circuit. The first semiconductor chip 210 and the second semiconductor chip 220 may be chiplets that constitute the logic circuit in the semiconductor package. In some examples, the first semiconductor chip 210 and the second semiconductor chip 220 may be small chips in a semiconductor package for a semiconductor device (e.g., a central processing unit (CPU) device, a graphics processing unit (GPU) device, a display serial interface (DSI) device, a camera serial interface (CSI) device, a modulator and demodulator (MODEM) device, or a power management integrated circuit (PMIC) device). In some examples, the second semiconductor chip 220 may include a logic chip including a memory element, a logic semiconductor chip including various integrated elements, or a passive device chip. The bottom surface of the second semiconductor chip 220 may be an active surface, and the top surface of the second semiconductor chip 220 may be an inactive surface. For example, the second semiconductor chip 220 may be disposed face-down on the first redistribution substrate 100.

[0040] The second chip wiring layer 224 may be disposed on the bottom surface of the second chip base layer 222. For example, the second chip wiring layer 224 may include a second chip dielectric pattern and a second chip wiring pattern formed on the bottom surface of the second chip base layer 222.

[0041] On the bottom surface of the second chip base layer 222 , a second chip dielectric pattern may cover the second integrated circuit. The second chip dielectric pattern may include a dielectric material. For example, the second chip dielectric pattern may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or a dielectric polymer. Alternatively, the second chip dielectric pattern may include a dielectric polymer or a photoimageable dielectric (PID). For example, the photoimageable dielectric may include at least one selected from photosensitive polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer.

[0042] The second chip wiring pattern may be disposed in the second chip dielectric pattern. The second chip wiring pattern may be electrically connected to the second integrated circuit on the bottom surface of the second chip base layer 222. The second chip wiring pattern may include a conductive material. For example, the second chip wiring pattern may include copper (Cu) or aluminum (Al).

[0043] The second semiconductor chip 220 may include a second chip pad 226 disposed on the bottom surface of the second semiconductor chip 220. The second chip pad 226 may be disposed on the bottom surface of the second chip wiring layer 224. The second chip pad 226 may be electrically connected to the second integrated circuit on the bottom surface of the second chip base layer 222 through a second chip wiring pattern in the second chip wiring layer 224.

[0044] In some examples, the second chip wiring layer 224 may further include a circuit pattern or a protection layer.

[0045] The second semiconductor chip 220 may be mounted on the top surface of the first redistribution substrate 100. For example, the second semiconductor chip 220 may be a flip chip mounted on the top surface of the first redistribution substrate 100. In this configuration, the second semiconductor chip 220 may be electrically connected to a set of first substrate pads 122 of the first redistribution substrate 100 through second connection terminals 228. The second connection terminals 228 may be provided between the second chip pads 226 of the second semiconductor chip 220 and the set of first substrate pads 122 of the first redistribution substrate 100.

[0046] The bridge chip 500 may be disposed on the bottom surface of the first redistribution substrate 100. The bridge chip 500 may be disposed on the bottom surface of the first redistribution substrate 100 in the first region R1 of the semiconductor package. The bridge chip 500 may have a front surface and a rear surface. In the following description, the term "front surface" may be defined as indicating an active surface of an integrated element in a semiconductor chip, a surface on which a wiring line is formed, or a surface on which a pad of a semiconductor chip is formed, and the term "rear surface" may be defined as indicating a surface opposite to the front surface. The front surface of the bridge chip 500 may point to the first redistribution substrate 100. For example, the bridge chip 500 may be disposed face down on the bottom surface of the first redistribution substrate 100. The bridge chip 500 may be located between some external terminals 150 and other external terminals 150 on the bottom of the first redistribution substrate 100. The bridge chip 500 may have a thickness that is smaller than the thickness of the external terminals 150. A vertical distance from the bottom surface of the first redistribution substrate 100 to the bottom surface of the bridge chip 500 may be smaller than a vertical distance from the bottom surface of the first redistribution substrate 100 to the lowermost end of the external terminal 150 .

[0047] When viewed in a plan view, the bridge chip 500 may be disposed adjacent to the first semiconductor chip 210 and the second semiconductor chip 220. For example, Figure 1 As shown, the bridge chip 500 may overlap not only a portion of the first semiconductor chip 210 but also a portion of the second semiconductor chip 220. However, the present invention is not limited thereto. When viewed in a plan view, the bridge chip 500 may be located between the first semiconductor chip 210 and the second semiconductor chip 220, or may overlap only one of the first semiconductor chip 210 and the second semiconductor chip 220.

[0048] The bridge chip 500 may include a bridge base layer 502 and a bridge wiring layer 504. The bridge base layer 502 may include or may be a semiconductor substrate, such as a semiconductor wafer. The bridge base layer 502 may be a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium (SiGe) substrate, a III-V semiconductor substrate, or an epitaxial film substrate obtained by performing selective epitaxial growth (SEG). For example, the bridge base layer 502 may include at least one selected from silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof.

[0049] The bridge wiring layer 504 may be disposed on the top surface of the bridge base layer 502. For example, the bridge wiring layer 504 may include a bridge dielectric pattern and a bridge wiring pattern formed on the top surface of the bridge base layer 502. In some examples, the bridge wiring layer 504 may further include a circuit pattern or a protective layer.

[0050] The bridging dielectric pattern may include a dielectric material. For example, the bridging dielectric pattern may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or a dielectric polymer. Alternatively, the bridging dielectric pattern may include a dielectric polymer or a photoimageable dielectric (PID).

[0051] The bridge wiring pattern may be provided in the bridge dielectric pattern. The bridge wiring pattern may include a structure for providing an electrical connection between the first semiconductor chip 210 and the second semiconductor chip 220. The bridge wiring pattern may include a conductive material. For example, the bridge wiring pattern may include copper (Cu) or aluminum (Al).

[0052] A portion of the bridge wiring pattern may be exposed on the top surface of the bridge wiring layer 504. The portion of the bridge wiring pattern exposed on the top surface of the bridge wiring layer 504 may be a bridge chip pad 506 of the bridge chip 500. Some of the bridge chip pads 506 may be electrically connected to other bridge chip pads 506 through the bridge wiring pattern in the bridge wiring layer 504.

[0053] Figure 1 The bridging dielectric pattern is depicted as a single layer, but the inventive concept is not limited thereto. According to some embodiments, the bridging dielectric pattern may have a plurality of dielectric layers, and the bridging wiring pattern may be a wiring pattern disposed in the plurality of dielectric layers.

[0054] The bridge chip 500 may be mounted on the bottom surface of the first redistribution substrate 100. For example, the bridge chip 500 may be a flip chip mounted on the bottom surface of the first redistribution substrate 100. The bridge chip 500 may be electrically connected to a set of external pads 130 of the first redistribution substrate 100 through bridge connection terminals 508. The bridge connection terminals 508 may be provided between the bridge chip pads 506 of the bridge chip 500 and the set of external pads 130 of the first redistribution substrate 100.

[0055] The first and second semiconductor chips 210 and 220 may be electrically connected to each other through the first redistribution substrate 100 and the bridge chip 500 .

[0056] According to some embodiments of the present inventive concept, the first redistribution substrate 100 may not include horizontal wiring lines for connecting the first semiconductor chip 210 to the second semiconductor chip 220. For example, the first redistribution substrate 100 may include wiring lines for connecting the first semiconductor chip 210 to the bridge chip 500 and for connecting the second semiconductor chip 220 to the bridge chip 500, but may not include horizontal wiring lines for connecting the first semiconductor chip 210 to the second semiconductor chip 220. Therefore, the number of wiring lines used in the first redistribution substrate 100 can be reduced, and the first redistribution substrate 100 can be provided with a smaller number of first substrate wiring layers. This can reduce the thickness of the first redistribution substrate 100 and the size of the semiconductor package including the first redistribution substrate 100.

[0057] The bridge chip 500 can provide horizontal wiring lines for connecting the first semiconductor chip 210 and the second semiconductor chip 220. The bridge wiring pattern in the bridge wiring layer 504 of the bridge chip 500 can be a wiring pattern manufactured on a chip scale and can have a smaller scale (e.g., line width, height, and thickness) than the first substrate wiring pattern 120 of the first redistribution substrate 100. For example, the bridge wiring layer 504 of the bridge chip 500 can have a higher wiring integration than the wiring integration of the first redistribution substrate 100. Therefore, a semiconductor package with a smaller size and improved electrical characteristics can be used to provide electrical connection between the first semiconductor chip 210 and the second semiconductor chip 220.

[0058] Still refer to Figure 1 , the passive device chip 600 may be disposed on the bottom surface of the first redistribution substrate 100. The passive device chip 600 may be disposed on the bottom surface of the first redistribution substrate 100 in the first region R1 of the semiconductor package or in the second region R2 of the semiconductor package. The passive device chip 600 may be disposed horizontally spaced apart from the bridge chip 500. The passive device chip 600 may be located between some external terminals 150 and other external terminals 150 on the bottom of the first redistribution substrate 100. The passive device chip 600 may have a thickness smaller than that of the external terminals 150. The vertical distance from the bottom surface of the first redistribution substrate 100 to the bottom surface of the passive device chip 600 may be smaller than the vertical distance from the bottom surface of the first redistribution substrate 100 to the bottom end of the external terminals 150.

[0059] The passive device chip 600 may include passive devices. For example, the passive device may include a resistor, a capacitor, or an inductor. The passive device may be a capacitor including a first electrode and a second electrode spaced apart from each other, and further including a dielectric filling the space between the first electrode and the second electrode. The first electrode and the second electrode may be connected to a passive device pad 606 of the passive device chip 600. The passive device pad 606 may be a wiring line or a pad formed on the front surface of the passive device chip 600.

[0060] The passive device chip 600 may be mounted on the bottom surface of the first redistribution substrate 100. For example, the passive device chip 600 may be a flip chip mounted on the bottom surface of the first redistribution substrate 100. The passive device chip 600 may be electrically connected to a set of external pads 130 of the first redistribution substrate 100 through passive device connection terminals 608. The passive device connection terminals 608 may be provided between the passive device pads 606 of the passive device chip 600 and the set of external pads 130 of the first redistribution substrate 100.

[0061] The conductive pillars 300 may be disposed on the top surface of the first redistribution substrate 100. The conductive pillars 300 may be disposed on the top surface of the first redistribution substrate 100 in the second region R2 of the semiconductor package. The conductive pillars 300 may be disposed horizontally spaced apart from the first semiconductor chip 210 and the second semiconductor chip 220. The conductive pillars 300 may be disposed on the second substrate pads 124 of the first redistribution substrate 100. For example, each conductive pillar 300 may contact the top surface of one of the second substrate pads 124 included in the first redistribution substrate 100. The conductive pillars 300 may be vertical electrical connection structures for connecting the first redistribution substrate 100 to the second redistribution substrate 400, which will be discussed below. For example, the conductive pillars 300 may correspond to vertical electrical connection terminals. The conductive pillars 300 may each have a pillar shape extending in a vertical direction relative to the top surface of the first redistribution substrate 100. However, the present inventive concept is not limited thereto, and the conductive pillars 300 may be provided in various shapes for vertical connection. In some examples, the conductive pillars 300 may each have a constant width in the vertical direction. For example, each conductive pillar 300 may have a pillar shape with a constant width. In other examples, each conductive pillar 300 may have a non-constant width in the vertical direction, for example, a width that decreases as the distance from the first redistribution substrate 100 decreases. The conductive pillars 300 may include a conductive material. The conductive pillars 300 may include a metal material, for example, copper (Cu) or tungsten (W).

[0062] Although not shown, each conductive pillar 300 may further include a seed layer surrounding the side surface of the conductive pillar 300. The seed layer may conformally cover the bottom and side surface of the conductive pillar 300. The seed layer may include a metal, for example, gold (Au).

[0063] The mold layer 350 may be disposed on the top surface of the first redistribution substrate 100. On the first redistribution substrate 100, the mold layer 350 may surround the first semiconductor chip 210, the second semiconductor chip 220, and the conductive pillars 300. The mold layer 350 may cover the first semiconductor chip 210 and the second semiconductor chip 220. The conductive pillars 300 may vertically penetrate the mold layer 350 and may be exposed through the top surface of the mold layer 350. The mold layer 350 and the conductive pillars 300 may have substantially flat and coplanar top surfaces. The mold layer 350 may include a molding member. The molding member may include a dielectric polymer material, such as epoxy molding compound (EMC) or Ajinomoto buildup film (ABF).

[0064] The second redistribution substrate 400 may be disposed on the top surface of the mold layer 350. The second redistribution substrate 400 may be in contact with the top surface of the conductive pillar 300 and the top surface of the mold layer 350.

[0065] The second redistribution substrate 400 may include one or more second substrate wiring layers stacked one on top of the other. Each second substrate wiring layer may include a second substrate dielectric pattern 410 and a second substrate wiring pattern 420 in the second substrate dielectric pattern 410. The second substrate wiring pattern 420 of one second substrate wiring layer may be electrically connected to the second substrate wiring pattern 420 of another adjacent second substrate wiring layer.

[0066] Any particular second substrate dielectric pattern 410 may include a dielectric polymer or a photoimageable dielectric (PID). For example, the photoimageable dielectric may include at least one selected from photosensitive polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer.

[0067] Any particular second substrate wiring pattern 420 may be disposed on the second substrate dielectric pattern 410. The second substrate wiring pattern 420 may extend horizontally on the second substrate dielectric pattern 410. The second substrate wiring pattern 420 may be disposed on the top surface of the second substrate dielectric pattern 410. The second substrate wiring pattern 420 may protrude above the top surface of the second substrate dielectric pattern 410. On the second substrate dielectric pattern 410, the second substrate wiring pattern 420 may be covered by another second substrate dielectric pattern 410 stacked thereon. The second substrate wiring pattern 420 disposed on the uppermost second substrate wiring layer may serve as a substrate pad for coupling to an upper package, discussed below. As described above, the second substrate wiring pattern 420 may be a pad or a line portion of the second substrate wiring layer. For example, the second substrate wiring pattern 420 may be a component used for horizontal redistribution in the second redistribution substrate 400. The second substrate wiring pattern 420 may include a conductive material. For example, the second substrate wiring pattern 420 may include a metal, such as copper (Cu).

[0068] The second substrate wiring pattern 420 may have a mosaic structure. For example, the second substrate wiring pattern 420 may have a via protruding from its bottom surface. The via may be a component of the second substrate wiring pattern 420 used to vertically connect adjacent second substrate wiring layers. For example, the via may extend from the bottom surface of the second substrate wiring pattern 420 to penetrate the second substrate dielectric pattern 410, thereby coupling to the top surface of the second substrate wiring pattern 420 of the second substrate wiring layer below. Alternatively, the via may be a component of the second substrate wiring pattern 420 used to connect the conductive pillar 300 to the lowermost second substrate wiring layer. For example, the via may extend from the bottom surface of the second substrate wiring pattern 420 to penetrate the lowermost second substrate dielectric pattern 410, thereby coupling to the top surface of the conductive pillar 300. In this configuration, the upper portion of the second substrate wiring pattern 420 located on the second substrate dielectric pattern 410 may serve as a header portion serving as a horizontal line or pad, and the via of the second substrate wiring pattern 420 may be a tail portion. The tail portion may have a width smaller than that of the header portion. The width of the tail portion may decrease as the distance from the head portion of the second substrate wiring pattern 420 increases. For example, the tail portion may have a tapered shape. The second substrate wiring pattern 420 may have a T-shape.

[0069] The upper package 700 may be disposed on the lower package. For example, Figure 1 The illustrated semiconductor package may be a package-on-package (POP) in which an upper package 700 is mounted on a lower package. The upper package may be mounted on the top surface of the second redistribution substrate 400. The upper package 700 may be located on the top surface of the second redistribution substrate 400 in the second region R2. When viewed in plan, the upper package 700 may be spaced apart from the first region R1. When viewed in plan, the upper package 700 may be spaced apart from the first semiconductor chip 210 and the second semiconductor chip 220. For example, the upper package 700 may not cover any of the first semiconductor chips 210 and may not cover any of the second semiconductor chips 220. Figure 1 The upper package 700 is depicted and described as being horizontally spaced apart from the first region R1, but the present inventive concept is not limited thereto. Figure 2 As shown, a portion of the upper package 700 may extend into the first region R1. In this case, the upper package 700 may be disposed horizontally spaced apart from the second semiconductor chip 220, may cover a portion of the first semiconductor chip 210, and may not cover the remaining portion of the first semiconductor chip 210, such that it does not completely cover the first semiconductor chip 210. The following description will focus on Figure 1 Example of .

[0070] The upper package 700 may include an upper package substrate 710, an upper package chip 720, and an upper molding layer 730. The upper package substrate 710 may be a printed circuit board (PCB). Alternatively, the upper package substrate 710 may be a redistribution substrate. The upper package substrate 710 may be provided with an upper substrate pad 712 on its bottom surface.

[0071] The upper package chip 720 may be disposed on the top surface of the upper package substrate 710. The upper package chip 720 may include an integrated circuit, and the integrated circuit may include a memory circuit, a logic circuit, or a combination thereof. The upper package chip 720 may be a semiconductor chip of a different type from the first semiconductor chip 210 and the second semiconductor chip 220. For example, the upper package chip 720 may be a memory chip. The upper package chip 720 may be electrically connected to the upper package substrate 710 via upper connection terminals 722. Figure 1 The upper package chip 720 is depicted as being flip-chip mounted, but the upper package chip 720 may be mounted in a wire bonding manner or any other suitable manner.

[0072] The upper molding layer 730 may be disposed on the top surface of the upper package substrate 710. On the upper package substrate 710, the upper molding layer 730 may surround the upper package chip 720. The upper molding layer 730 may cover the top surface of the upper package chip 720. The upper molding layer 730 may include a dielectric polymer, for example, an epoxy-based polymer.

[0073] The intermediate connecting terminals 714 may be provided between the lower package and the upper package 700. The intermediate connecting terminals 714 may be interposed between the uppermost second substrate wiring patterns 420 of the second redistribution substrate 400 and the upper substrate pads 712 of the upper package substrate 710, thereby electrically connecting the second substrate wiring patterns 420 to the upper substrate pads 712. Thus, the upper package 700 may be electrically connected to the first and second semiconductor chips 210 and 220, as well as the external terminals 150, through the intermediate connecting terminals 714, the second redistribution substrate 400, the conductive pillars 300, and the first redistribution substrate 100.

[0074] A heat radiation member 800 may be provided on the lower package. The heat radiation member may be a heat radiator. The heat radiation member 800 may be provided on the top surface of the second redistribution substrate 400. The heat radiation member 800 may be provided horizontally spaced apart from the upper package 700. The heat radiation member 800 may be located on the top surface of the second redistribution substrate in the first region R1. The heat radiation member 800 may be provided above the first semiconductor chip 210 and the second semiconductor chip 220. The heat radiation member 800 may be connected to the top surface of the second redistribution substrate 400. For example, the heat radiation member 800 may be attached to the second redistribution substrate 400 via an adhesive film 802. The adhesive film 802 may include a thermal interface material (TIM), such as thermal grease. The heat radiation member 800 may radiate heat generated from the first semiconductor chip 210 and the second semiconductor chip 220. The heat radiation member 800 may include a heat sink. The heat radiation member 800 may include a thermally conductive material, such as metal. For example, the heat radiation member 800 may include copper (Cu) or aluminum (Al).

[0075] According to some embodiments of the present inventive concept, another semiconductor chip or package (e.g., upper package 700) may not be disposed above the first and second semiconductor chips 210 and 220. Therefore, heat generated from the first and second semiconductor chips 210 and 220 in the lower package may not be blocked (dissipated) by the other semiconductor chip or package, and heat generated by the other semiconductor chip or package may not be transmitted to the first and second semiconductor chips 210 and 220. Due to the presence of the heat radiation member 800 attached to the top surface of the second redistribution substrate 400 above the first and second semiconductor chips 210 and 220, heat generated from the first and second semiconductor chips 210 and 220 can be effectively discharged. Consequently, the semiconductor package can benefit from increased heat radiation efficiency and improved electrical characteristics.

[0076] In the following examples, Figure 1 and Figure 2 The same elements as those discussed in the embodiments of the present invention are assigned the same reference numerals, and for the sake of convenience, their repeated descriptions will be omitted or abridged. Figure 1 and Figure 2 The differences between the embodiment and other embodiments described below.

[0077] Figure 3 Cross-sectional views illustrating semiconductor packages according to some embodiments of the inventive concept are shown.

[0078] Reference Figure 3The lower package includes a first redistribution substrate 100 , a first semiconductor chip 210 and a second semiconductor chip 220 , a conductive pillar 300 , a molding layer 350 , a second redistribution substrate 400 , a bridge chip 500 and a passive device chip 600 .

[0079] The upper package 700 may be disposed on the lower package. The upper package 700 may be located on the top surface of the second redistribution substrate 400 in the second region R2. When viewed in a plan view, the upper package 700 may be spaced apart from the first region R1. For example, the upper package 700 may not cover any of the first semiconductor chips 210 and may not cover any of the second semiconductor chips 220.

[0080] The semiconductor package may not have a heat radiation member.In the first region R1, a top surface of the second redistribution substrate 400 may be exposed.

[0081] According to some embodiments of the present inventive concept, another semiconductor chip or package (e.g., upper package 700) may not be disposed in the first region R1 on the top surface of the second redistribution substrate 400 above the first semiconductor chip 210 and the second semiconductor chip 220. Therefore, heat generated from the first semiconductor chip 210 and the second semiconductor chip 220 in the lower package may not be blocked (dissipated) by the another semiconductor chip or package, and heat generated by the another semiconductor chip or package may not be transferred to the first semiconductor chip 210 and the second semiconductor chip 220. Therefore, even if the upper package 700 is not included, the heat generated from the first semiconductor chip 210 and the second semiconductor chip 220 in the lower package may not be blocked (dissipated). Figure 1 With the heat radiation member 800 , the semiconductor package may also benefit from increased heat radiation efficiency and improved electrical characteristics.

[0082] Figure 4 Cross-sectional views illustrating semiconductor packages according to some embodiments of the inventive concept are shown.

[0083] The upper package 700 is horizontally spaced apart from the first region R1. Figure 3 on the contrary, Figure 4 A portion of the upper package 700 is depicted extending into the first region R1. In this case, the upper package 700 may be disposed horizontally spaced apart from the second semiconductor chip 220. In some examples, the upper package 700 may cover the first semiconductor chip 210 and may not cover the second semiconductor chip 220. In some such examples, the first semiconductor chip 210 may be a small chip that generates a relatively small amount of heat, and the second semiconductor chip 220 may be a small chip that generates a large amount of heat.

[0084] According to some embodiments of the present inventive concept, a semiconductor package can be provided with an upper package 700 having a large size so that it covers at least a portion of the chiplets in the lower package that together constitute the logic circuit. The second semiconductor chip 220, which can generate a large amount of heat, can be located outside the lower package so that the upper package 700 does not cover the second semiconductor chip 220. Therefore, the upper package 700 can be prevented from blocking the heat generated from the second semiconductor chip 220, and the heat generated from the second semiconductor chip 220 can be effectively discharged. As a result, the semiconductor package can benefit from increased heat radiation efficiency and improved electrical characteristics.

[0085] Figure 5 Cross-sectional views illustrating semiconductor packages according to some embodiments of the inventive concept are shown.

[0086] The first semiconductor chip 210 and the second semiconductor chip 220 are mounted on the first redistribution substrate 100 through the first connection terminal 218 and the second connection terminal 228. Figure 1 on the contrary, Figure 5 It is depicted that the first chip attach pads 216 of the first semiconductor chip 210 and the second chip attach pads 226 of the second semiconductor chip 220 are directly connected to the first substrate wiring pattern 120 of the first redistribution substrate 100 .

[0087] As in Figure 5 In the embodiment of the present invention, the lower package includes a first redistribution substrate 100, a first semiconductor chip 210 and a second semiconductor chip 220, a mold layer 350 covering the top surfaces of the first semiconductor chip 210 and the second semiconductor chip 220, conductive pillars 300 vertically penetrating the mold layer 350 on one side of the first semiconductor chip 210 and the second semiconductor chip 220, and a second redistribution substrate 400 on the mold layer 350. In this case, the bottom surfaces of the first semiconductor chip 210, the second semiconductor chip 220, and the conductive pillars 300 can be exposed on the bottom surface of the mold layer 350. The bottom surfaces of the first semiconductor chip 210, the second semiconductor chip 220, the conductive pillars 300, and the mold layer 350 can be substantially flat and coplanar with each other.

[0088] The first redistribution substrate 100 may be disposed below the mold layer 350. The first redistribution substrate 100 may include one or more first substrate wiring layers stacked one on top of the other. Each first substrate wiring layer may include a first substrate dielectric pattern 110 and a first substrate wiring pattern 120 within the first substrate dielectric pattern 110. The first substrate dielectric pattern 110 may cover the bottom surface of the first semiconductor chip 210, the bottom surface of the second semiconductor chip 220, the bottom surface of the conductive pillar 300, and the bottom surface of the mold layer 350.

[0089] The first substrate wiring pattern 120 may have a damascene structure. For example, the first substrate wiring pattern 120 may have a via protruding from its top surface. The via may be a component used to vertically connect the first substrate wiring patterns 120 of adjacent first substrate wiring layers. Alternatively, the via may be a component used to connect the first substrate wiring pattern 120 of the uppermost first substrate wiring layer to the first die pad 216, the second die pad 226, or the conductive pillar 300. For example, the via may extend from the top surface of the first substrate wiring pattern 120 to penetrate the first substrate dielectric pattern 110, thereby coupling to the bottom surface of the first substrate wiring pattern 120 of the overlying first substrate wiring layer. For another example, the via may extend from the top surface of the first substrate wiring pattern 120 to penetrate the uppermost first substrate dielectric pattern 110, thereby coupling to the bottom surface of the first die pad 216, the bottom surface of the second die pad 226, or the bottom surface of the conductive pillar 300. The first substrate wiring pattern 120 may have an inverted T-shape.

[0090] On the lowermost of the first substrate wiring layers, the first substrate wiring patterns 120 may be exposed on the bottom surface of the first substrate dielectric pattern 110. The lowermost first substrate wiring patterns 120 may serve as external pads 130 of the first redistribution substrate 100.

[0091] The bridge chip 500 and the passive device chip 600 may be mounted on a portion of the lowermost first substrate wiring pattern 120 in the first region R1 . The external terminal 150 may be coupled to other portions of the first substrate wiring pattern 120 .

[0092] Figure 6 Cross-sectional views illustrating semiconductor packages according to some embodiments of the inventive concept are shown.

[0093] Reference Figure 6 , the bridge chip 500 may further include a capacitor element 510. In some examples, such as Figure 6 As shown, the capacitor element 510 can be disposed or formed on the rear surface of the bridge chip 500. In some other examples, Figure 6 Unlike the example shown, the capacitor element 510 may be disposed or formed in the bridge substrate 502. Although not shown in detail, the capacitor element 510 may include electrodes spaced apart from each other and may also include a dielectric filling the space between the electrodes. The electrodes may be connected to the bridge chip pad 506 via the bridge wiring layer 504 of the bridge chip 500.

[0094] According to some embodiments of the present inventive concept, including the capacitor element 510 in the bridge chip 500 can reduce the size of the passive device chip 600. For example, including the capacitor element 510 in the bridge chip 500 can enable the use of smaller capacitors as the passive device chip 600. In some examples, including the capacitor element 510 in the bridge chip 500 can allow the passive device chip 600 to be omitted from the semiconductor package. The reduced size (or omission) of the passive device chip 600 can correspondingly reduce the amount of surface area of ​​the first redistribution substrate 100 occupied by the passive device chip 600. As a result, a more compact semiconductor package can be achieved.

[0095] Figure 7 and Figure 8 Cross-sectional views illustrating semiconductor packages according to some embodiments of the inventive concept are shown.

[0096] Figure 7 An example in which the lower package does not include the second redistribution substrate 400 is depicted.

[0097] exist Figure 7 In the embodiment of the present invention, the lower package includes a first redistribution substrate 100, a first semiconductor chip 210 and a second semiconductor chip 220, a mold layer 350 covering the top surfaces of the first semiconductor chip 210 and the second semiconductor chip 220, and a conductive pillar 300 vertically penetrating the mold layer 350 on one side of the first semiconductor chip 210 and the second semiconductor chip 220. The conductive pillar 300 may have a top surface exposed on the top surface of the mold layer 350. The top surface of the conductive pillar 300 and the top surface of the mold layer 350 may be substantially flat and coplanar with each other. However, the present invention is not limited to this. For example, in the second region R2, the top surface of the mold layer 350 may have a recess facing the first redistribution substrate 100, and the top surface of the conductive pillar 300 may extend only to the bottom of the recess. In this case, the top surface of the conductive pillar 300 may be located at a level lower than the level of the top surface of the mold layer 350.

[0098] The upper package 700 may be disposed on the lower package. The upper package 700 may be located on the top surface of the mold layer 350 in the second region R2. When viewed in a plan view, the upper package 700 may be spaced apart from the first region R1. The upper package 700 may not cover any of the first semiconductor chips 210 and may not cover any of the second semiconductor chips 220.

[0099] The intermediate connecting terminals 714 may be provided between the lower package and the upper package 700. The intermediate connecting terminals 714 may be interposed between the top surfaces of the conductive pillars 300 and the bottom surfaces of the upper substrate pads 712 of the upper package substrate 710, thereby electrically connecting the conductive pillars 300 to the upper substrate pads 712. Thus, the upper package 700 may be electrically connected to the first and second semiconductor chips 210 and 220, as well as the external terminals 150, through the intermediate connecting terminals 714, the conductive pillars 300, and the first redistribution substrate 100.

[0100] A heat radiation member 800 may be provided on the lower package. The heat radiation member 800 may be provided on the top surface of the mold layer 350. The heat radiation member 800 may be provided horizontally spaced apart from the upper package 700. The heat radiation member 800 may be located on the top surface of the mold layer 350 in the first region R1. The heat radiation member 800 may be provided above the first semiconductor chip 210 and the second semiconductor chip 220. The heat radiation member 800 may be provided in contact with the top surface of the mold layer 350. The heat radiation member 800 may be attached to the mold layer 350 via an adhesive film 802. The heat radiation member 800 may radiate heat generated from the first semiconductor chip 210 and the second semiconductor chip 220 outward.

[0101] According to some embodiments of the present inventive concept, since the heat radiation member 800 is directly attached to the mold layer 350, heat generated from the first semiconductor chip 210 and the second semiconductor chip 220 can be easily discharged to the outside through the heat radiation member 800. Therefore, the semiconductor package can benefit from increased heat radiation efficiency and improved electrical characteristics.

[0102] Figure 7 It is depicted that the mold layer 350 covers the top surfaces of the first and second semiconductor chips 210 and 220 , but the inventive concept is not limited thereto.

[0103] Figure 8 An example is depicted in which the mold layer 350 does not cover the top surfaces of the first semiconductor chip 210 and the second semiconductor chip 220. Figure 8, the lower package includes a first redistribution substrate 100, a first semiconductor chip 210 and a second semiconductor chip 220, a mold layer 350, and a conductive pillar 300 vertically penetrating the mold layer 350 on one side of the first semiconductor chip 210 and the second semiconductor chip 220. The mold layer 350 may surround the first semiconductor chip 210 and the second semiconductor chip 220 but does not cover the top surfaces of the first semiconductor chip 210 and the second semiconductor chip 220. The conductive pillar 300, the first semiconductor chip 210 and the second semiconductor chip 220 may have top surfaces exposed at the top surface of the mold layer 350. The top surfaces of the conductive pillar 300, the first semiconductor chip 210, the second semiconductor chip 220, and the mold layer 350 may be substantially flat and coplanar with each other.

[0104] A heat radiation member 800 may be provided on the lower package. The heat radiation member 800 may be provided on the top surface of the mold layer 350. The heat radiation member 800 may be located on the top surface of the mold layer 350 in the first region R1. The heat radiation member 800 may be provided above the first semiconductor chip 210 and the second semiconductor chip 220. The heat radiation member 800 may be provided in contact with the top surface of the mold layer 350. The heat radiation member 800 may be attached to the mold layer 350 and the top surfaces of the first and second semiconductor chips 210 and 220 exposed at the top surface of the mold layer 350 via an adhesive film 802. The heat radiation member 800 may radiate heat generated from the first and second semiconductor chips 210 and 220 outward.

[0105] According to some embodiments of the present inventive concept, since the heat radiation member 800 is directly attached to the top surfaces of the first and second semiconductor chips 210 and 220, heat generated from the first and second semiconductor chips 210 and 220 can be easily discharged to the outside through the heat radiation member 800. Therefore, the semiconductor package can benefit from increased heat radiation efficiency and improved electrical characteristics.

[0106] Figure 9 Cross-sectional views illustrating semiconductor packages according to some embodiments of the inventive concept are shown.

[0107] exist Figure 9 In FIG. 3 , the lower package includes a connection substrate 310 instead of the conductive pillars 300 .

[0108] The connection substrate 310 may be disposed on the top surface of the first redistribution substrate 100. The connection substrate 310 may be disposed on the top surface of the first redistribution substrate in the second region R2. The connection substrate 310 may have a top surface vertically spaced apart from the top surface of the first redistribution substrate 100. The connection substrate 310 may provide a vertical electrical connection structure through which the first redistribution substrate 100 and the second redistribution substrate 400 are connected on one side of the first semiconductor chip 210 and the second semiconductor chip 220.

[0109] The connection substrate 310 may include a base layer 312 and a conductive member as a wiring pattern provided in the base layer 312. For example, the base layer 312 may include a dielectric material.

[0110] The conductive member may include an upper pad 314, a via 318, and a lower pad 316. The upper pad 314 may be provided on the top surface of the connection substrate 310. The lower pad 316 may be provided on the bottom surface of the connection substrate 310. The via 318 may be a through-electrode that penetrates the base layer 312 and electrically connects the upper pad 314 to the lower pad 316.

[0111] The connection substrate 310 may be mounted on the top surface of the first redistribution substrate 100. In some examples, the connection substrate 310 may be electrically connected to the first redistribution substrate 100 through the connection substrate terminals 320. The connection substrate terminals 320 may be disposed between the lower pads 316 of the connection substrate 310 and a set of second substrate pads 124 of the first redistribution substrate 100.

[0112] On the first redistribution substrate 100, a mold layer 350 may cover the connection substrate 310, the first semiconductor chip 210, and the second semiconductor chip 220. The mold layer 350 may fill the space between the connection substrate 310 and the first and second semiconductor chips 210 and 220. The mold layer 350 may cover the top surface of the connection substrate 310, the top surface of the first semiconductor chip 210, and the top surface of the second semiconductor chip 220. The upper pads 314 of the connection substrate 310 may be electrically connected to the second substrate wiring patterns 420 of the second redistribution substrate 400. For example, the second substrate wiring patterns 420 of the second redistribution substrate 400 may penetrate the second substrate dielectric pattern 410 and the mold layer 350 to electrically couple with the upper pads 314.

[0113] Figure 9 It is depicted that the first and second semiconductor chips 210 and 220 are mounted on the first redistribution substrate 100 through the first and second connection terminals 218 and 228 , and the connection substrate 310 is mounted on the first redistribution substrate 100 through the connection substrate terminals 320 , but the inventive concept is not limited thereto.

[0114] Figure 10 1 shows a cross-sectional view illustrating a semiconductor package according to some embodiments of the present inventive concept. Figure 10 , the first chip pads 216 of the first semiconductor chip 210 , the second chip pads 226 of the second semiconductor chip 220 , and the lower pads 316 of the connection substrate 310 may be directly connected to corresponding portions of the first substrate wiring patterns 120 of the first redistribution substrate 100 .

[0115] The lower package includes a first redistribution substrate 100, a first semiconductor chip 210 and a second semiconductor chip 220, a connection substrate 310 disposed on one side of the first semiconductor chip 210 and the second semiconductor chip 220, a mold layer 350 covering the top surfaces of the first semiconductor chip 210, the second semiconductor chip 220 and the connection substrate 310, and a second redistribution substrate 400 on the mold layer 350. The bottom surfaces of the first semiconductor chip 210, the second semiconductor chip 220, and the connection substrate 310 may be exposed on the bottom surface of the mold layer 350. The bottom surfaces of the first semiconductor chip 210, the second semiconductor chip 220, the connection substrate 310, and the mold layer 350 may be substantially flat and coplanar with each other.

[0116] The first redistribution substrate 100 may be disposed below the mold layer 350. The first redistribution substrate 100 may include one or more first substrate wiring layers stacked on each other. Each first substrate wiring layer may include a first substrate dielectric pattern 110 and a first substrate wiring pattern 120 in the first substrate dielectric pattern 110. The first substrate dielectric pattern 110 and the first substrate wiring pattern 120 may be connected to the reference substrate. Figure 5 The first substrate dielectric pattern 110 and the first substrate wiring pattern 120 are substantially the same or similar. The first substrate dielectric pattern 110 may cover the bottom surfaces of the first semiconductor chip 210, the second semiconductor chip 220, the connection substrate 310, and the mold layer 350.

[0117] The first substrate wiring pattern 120 may have a via protruding from its top surface. The via may be a component for vertically connecting the first substrate wiring pattern 120 of an adjacent first substrate wiring layer, or a component for vertically connecting the first substrate wiring pattern 120 of the uppermost first substrate wiring layer to the first die pad 216, the second die pad 226, and the lower pad 316 of the connection substrate 310. For example, the via may extend from the top surface of the first substrate wiring pattern 120 to penetrate the uppermost first substrate dielectric pattern 110, thereby coupling to the bottom surface of the first die pad 216, the bottom surface of the second die pad 226, or the bottom surface of the lower pad 316 of the connection substrate 310.

[0118] Figure 11Cross-sectional views illustrating semiconductor packages according to some embodiments of the inventive concept are shown.

[0119] exist Figure 11 , the first region R1 may be a central portion of the first redistribution substrate 100 , and the second region R2 may include left and right edge portions of the first redistribution substrate 100 such that the second region R2 horizontally surrounds the first region R1 .

[0120] The first semiconductor chip 210 and the second semiconductor chip 220 may be disposed on the first redistribution substrate 100. The first semiconductor chip 210 and the second semiconductor chip 220 may be disposed on a top surface of the first redistribution substrate 100 in the first region R1.

[0121] The connection substrate 310 may also be provided on the first redistribution substrate 100. The connection substrate 310 may be provided on the top surface of the first redistribution substrate 100 in the second region R2. The connection substrate 310 may have an opening OP extending therethrough. For example, the opening OP may be shaped as an opening connecting the top and bottom surfaces of the connection substrate 310. The opening OP may be provided on the top surface of the first redistribution substrate 100 in the first region R1. The connection substrate 310 may provide a vertical electrical connection structure through which the first redistribution substrate 100 and the second redistribution substrate 400 are connected on one side of the first semiconductor chip 210 and the second semiconductor chip 220. The connection substrate 310 may include a base layer 312 and a conductive member as a wiring pattern provided in the base layer 312. The conductive member may occupy the outer side of the connection substrate 310, and the opening OP may occupy the inner side of the connection substrate 310. The conductive member may include an upper pad 314, a via 318, and a lower pad 316.

[0122] The first semiconductor chip 210 and the second semiconductor chip 220 may be disposed in the opening OP of the connection substrate 310. When viewed in a plan view, the first semiconductor chip 210 and the second semiconductor chip 220 may have a planar shape smaller than the planar shape of the opening OP. For example, the first semiconductor chip 210 and the second semiconductor chip 220 may be spaced apart from the inner sidewall of the opening OP.

[0123] On the first redistribution substrate 100, a mold layer 350 may cover the connection substrate 310, the first semiconductor chip 210, and the second semiconductor chip 220. The mold layer 350 may fill the space between the connection substrate 310 and the first and second semiconductor chips 210 and 220. For example, the mold layer 350 may fill the unoccupied portion of the opening OP of the connection substrate 310. The mold layer 350 may cover the top surface of the connection substrate 310, the top surface of the first semiconductor chip 210, and the top surface of the second semiconductor chip 220. The upper pads 314 of the connection substrate 310 may be electrically connected to the second substrate wiring patterns 420 of the second redistribution substrate 400. For example, the second substrate wiring patterns 420 of the second redistribution substrate 400 may penetrate the second substrate dielectric pattern 410 and the mold layer 350 to electrically couple with the upper pads 314.

[0124] Figure 12 and Figure 13 Cross-sectional views illustrating semiconductor packages according to some embodiments of the inventive concept are shown.

[0125] exist Figure 12 In the embodiment, the lower package includes a first redistribution substrate 100 , a first semiconductor chip 210 and a second semiconductor chip 220 , a conductive pillar 300 , a molding layer 350 , a second redistribution substrate 400 , a bridge chip 500 and a passive device chip 600 .

[0126] As in Figure 11 In the embodiment, the first region R1 may include a central portion of the first redistribution substrate 100 , and the second region R2 may include left and right edge portions of the first redistribution substrate 100 horizontally surrounding the central portion of the first redistribution substrate 100 .

[0127] The first semiconductor chip 210 and the second semiconductor chip 220 may be disposed on the first redistribution substrate 100. The first semiconductor chip 210 and the second semiconductor chip 220 may be disposed on a top surface of the first redistribution substrate 100 in the first region R1.

[0128] Conductive pillars 300 may also be provided on the first redistribution substrate 100. The conductive pillars 300 may be provided on the top surface of the first redistribution substrate 100 in the second region R2. The conductive pillars 300 may be provided horizontally spaced apart from the first semiconductor chip 210 and the second semiconductor chip 220. The conductive pillars 300 may be provided on the second substrate pads 124 of the first redistribution substrate 100. The conductive pillars 300 may each have a pillar shape extending in a vertical direction relative to the top surface of the first redistribution substrate 100.

[0129] On the first redistribution substrate 100 , the mold layer 350 may cover the first and second semiconductor chips 210 and 220 . The conductive pillars 300 may be exposed on a top surface of the mold layer 350 .

[0130] The second redistribution substrate 400 may be disposed on the top surface of the mold layer 350. The second redistribution substrate 400 may contact the top surface of the conductive pillar 300 and the top surface of the mold layer 350. The second redistribution substrate 400 may include one or more second substrate wiring layers stacked on each other. Each second substrate wiring layer may include a second substrate dielectric pattern 410 and a second substrate wiring pattern 420 in the second substrate dielectric pattern 410. The second substrate wiring pattern 420 disposed on the uppermost second substrate wiring layer may serve as a substrate pad coupled to the upper package 700-1 to be discussed below. The second substrate wiring pattern 420 disposed on the lowermost second substrate wiring layer may extend from the bottom surface of the second substrate wiring pattern 420 to penetrate the second substrate dielectric pattern 410, thereby coupling to the top surface of the conductive pillar 300.

[0131] The upper package 700-1 can be placed on the lower package. Figure 12 The semiconductor package shown may be a package-on-package (POP) in which an upper package 700-1 is mounted on a lower package. The upper package 700-1 may be located on the top surface of the second redistribution substrate 400 and may overlap part or all of the first region R1 and part or all of the second region R2 in a plan view. Figure 12 The example in which the upper package 700-1 overlaps the entire first region R1 and the entire second region R2 is depicted, but the present invention is not limited thereto. The upper package 700-1 may have a width that is the same as or similar to that of the lower package. Alternatively, the width of the upper package 700-1 may be smaller than that of the lower package. The upper package 700-1 may include an upper package substrate 710, a first upper package chip 720-1, a second upper package chip 720-2, and an upper molding layer 730.

[0132] A chip stack including a first upper package chip 720-1 and a second upper package chip 720-2 may be disposed on the upper surface of the upper package substrate 710. The first upper package chip 720-1 and the second upper package chip 720-2 may be stacked alternately with each other. The first upper package chip 720-1 may be aligned in a direction perpendicular to the top surface of the upper package substrate 710. In some examples, the side surfaces of the first upper package chip 720-1 may be located in the same plane. The second upper package chip 720-2 may also be aligned in a direction perpendicular to the top surface of the upper package substrate 710. In some examples, the side surfaces of the second upper package chip 720-2 may be located in the same plane horizontally spaced apart from the plane in which the side surfaces of the first upper package chip 720-1 are located. The first upper package chip 720-1 may protrude from the adjacent second upper package chip 720-2 in a direction parallel to the top surface of the upper package substrate 710. For example, as Figure 12 As shown, the first upper package chip 720-1 may protrude from the adjacent second upper package chip 720-2 in the left direction. The second upper package chip 720-2 may protrude from the adjacent first upper package chip 720-1 in the direction opposite to the direction in which the first upper package chip 720-1 protrudes. For example, Figure 12 As shown, the second upper package chip 720-2 may protrude from the adjacent first upper package chip 720-1 in the right direction. The first upper package chip 720-1 and the second upper package chip 720-2 may be of the same type. The first upper package chip 720-1 and the second upper package chip 720-2 may include integrated circuits, and the integrated circuits may include memory circuits, logic circuits, or a combination thereof. The first upper package chip 720-1 and the second upper package chip 720-2 may be of different types from the first semiconductor chip 210 and the second semiconductor chip 220. For example, the first upper package chip 720-1 and the second upper package chip 720-2 may be memory chips. The first upper package chip 720-1 and the second upper package chip 720-2 may be electrically connected to the upper package substrate 710 via bonding wires 724. Figure 12 An example in which the first upper package chip 720 - 1 and the second upper package chip 720 - 2 are stacked and mounted is illustrated, but the inventive concept is not limited thereto.

[0133] The upper molding layer 730 may be disposed on the top surface of the upper package substrate 710. The upper molding layer 730 may surround the first upper package chip 720-1 and the second upper package chip 720-2 on the upper package substrate 710. The upper molding layer 730 may cover the top surfaces of the first upper package chip 720-1 and the second upper package chip 720-2.

[0134] The intermediate connection terminal 714 may be provided between the lower package and the upper package 700 - 1 , and may be interposed between the uppermost second substrate wiring pattern 420 of the second redistribution substrate 400 and the upper substrate pad 712 of the upper package substrate 710 , thereby electrically connecting the second substrate wiring pattern 420 to the upper substrate pad 712 .

[0135] Figure 13 An example in which the lower package does not include the second redistribution substrate 400 is depicted.

[0136] exist Figure 13 In the embodiment of the present invention, the lower package includes a first redistribution substrate 100, a first semiconductor chip 210 and a second semiconductor chip 220, a mold layer 350 covering the top surfaces of the first semiconductor chip 210 and the second semiconductor chip 220, and a conductive pillar 300 vertically penetrating the mold layer 350 on one side of the first semiconductor chip 210 and the second semiconductor chip 220. The conductive pillar 300 may have a top surface exposed on the top surface of the mold layer 350. The top surface of the conductive pillar 300 and the top surface of the mold layer 350 may be substantially flat and coplanar with each other. However, the present invention is not limited to this. For example, in the second region R2, the top surface of the mold layer 350 may have a recess facing the first redistribution substrate 100, and the top surface of the conductive pillar 300 may extend only to the bottom of the recess. In this case, the top surface of the conductive pillar 300 may be located at a level lower than the level of the top surface of the mold layer 350.

[0137] Figure 13 The mold layer 350 is depicted as covering the top surfaces of the first semiconductor chip 210 and the second semiconductor chip 220, but the present inventive concept is not limited thereto. In some examples, the conductive pillars 300, the first semiconductor chip 210, and the second semiconductor chip 220 may each have a top surface exposed at the top surface of the mold layer 350. In such examples, the top surfaces of the conductive pillars 300, the first semiconductor chip 210, the second semiconductor chip 220, and the mold layer 350 may be substantially flat and coplanar with each other.

[0138] exist Figure 13 In, as in Figure 12 In the embodiment, the upper package 700-1 can be set on the lower package. The upper package 700-1 can be Figure 12 The upper package 700 - 1 discussed above is the same or similar.

[0139] Intermediate connecting terminals 714 may be provided between the lower package and the upper package 700-1. The intermediate connecting terminals 714 may be interposed between the top surface of the conductive pillars 300 and the bottom surface of the upper substrate pads 712 of the upper package substrate 710, thereby electrically connecting the conductive pillars 300 to the upper substrate pads 712. Thus, the upper package 700-1 may be electrically connected to the first and second semiconductor chips 210 and 220, as well as the external terminals 150, through the intermediate connecting terminals 714, the conductive pillars 300, and the first redistribution substrate 100.

[0140] Figure 14 Cross-sectional views illustrating semiconductor packages according to some embodiments of the inventive concept are shown.

[0141] Reference Figure 14 , which can be provided with reference Figure 11 The lower package discussed is substantially the same or similar to the lower package. For example, the lower package may include a first redistribution substrate 100 , first and second semiconductor chips 210 and 220 , a connection substrate 310 , a molding layer 350 , a second redistribution substrate 400 , a bridge chip 500 , and a passive device chip 600 .

[0142] exist Figure 14 In, as in Figure 11 In the embodiment, the first region R1 may include a central portion of the first redistribution substrate 100 , and the second region R2 may include left and right edge portions of the first redistribution substrate 100 horizontally surrounding the central portion of the first redistribution substrate 100 .

[0143] The first and second semiconductor chips 210 and 220 may be disposed on the top surface of the first redistribution substrate 100 in the first region R1 .

[0144] The connection substrate 310 may be disposed on the top surface of the first redistribution substrate 100 in the second region R2 .

[0145] On the first redistribution substrate 100 , the mold layer 350 may cover the connection substrate 310 , the first semiconductor chip 210 , and the second semiconductor chip 220 . The mold layer 350 may fill a space between the connection substrate 310 and the first and second semiconductor chips 210 and 220 .

[0146] The second redistribution substrate 400 may cover the mold layer 350 . The second substrate wiring patterns 420 of the second redistribution substrate 400 may penetrate the second substrate dielectric patterns 410 and the mold layer 350 to be electrically coupled with the upper pads 314 .

[0147] The upper package 700-1 can be set on the lower package. Figure 12 or Figure 13The upper package 700-1 discussed is substantially the same or similar. The upper package 700-1 can be located on the top surface of the second redistribution substrate 400 and can overlap part or all of the first region R1 and part or all of the second region R2 in a plan view. The upper package 700-1 can have a width that is the same as or similar to that of the lower package. Alternatively, the width of the upper package 700-1 can be less than the width of the lower package. The upper package 700-1 may include an upper package substrate 710, a first upper package chip 720-1 and a second upper package chip 720-2, and an upper molding layer 730.

[0148] Figure 14 It is depicted that the lower package includes the second redistribution substrate 400 and the upper package 700-1 is mounted on the second redistribution substrate 400, but the present inventive concept is not limited thereto. According to some embodiments, Figure 13 Similar to the embodiment of , the lower package may not have the second redistribution substrate 400. In this case, the upper pads 314 of the connection substrate 310 may be exposed on the mold layer 350, and the upper package 700-1 may be directly mounted on the upper pads 314 of the connection substrate 310.

[0149] In semiconductor packages according to some embodiments of the present invention, the first redistribution substrate may include only wiring lines for connecting the first and second semiconductor chips to a bridge chip, and the bridge chip may provide horizontal wiring lines for redistributing the first and second semiconductor chips. Therefore, even when using a first redistribution substrate for connecting an upper package mounted on a mold layer to the first or second semiconductor chip, the number of wiring lines required for the first redistribution substrate and the number of substrate wiring layers of the first redistribution substrate can be reduced. This can reduce the thickness of the first redistribution substrate and the size of the semiconductor package including the first redistribution substrate.

[0150] Furthermore, according to some embodiments of the present invention, another semiconductor chip or package may not be disposed above the first and second semiconductor chips, and a heat radiation member may be disposed above the first and second semiconductor chips. Thus, heat generated from the first and second semiconductor chips can be more efficiently discharged. Consequently, the semiconductor package can benefit from increased heat radiation efficiency and improved electrical characteristics.

[0151] Although the present invention has been described in conjunction with some embodiments of the inventive concept shown in the drawings, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and essential characteristics of the inventive concept. Therefore, the embodiments disclosed above should be considered as illustrative rather than restrictive.

Claims

1. A semiconductor package, comprising: a first redistribution substrate; a first semiconductor chip and a second semiconductor chip mounted on a top surface of the first redistribution substrate and horizontally spaced apart from each other; a molding layer disposed on the top surface of the first redistribution substrate and surrounding the first semiconductor chip and the second semiconductor chip; a second redistribution substrate disposed on the top surface of the molding layer; an upper package mounted on a top surface of the second redistribution substrate; a vertical electrical connection structure disposed on one side of the first semiconductor chip and the second semiconductor chip and connecting the first redistribution substrate to the second redistribution substrate; a plurality of external connection terminals provided on the bottom surface of the first redistribution substrate; as well as A bridge chip and a capacitor chip are mounted on the bottom surface of the first redistribution substrate and disposed between the first group of external connection terminals and the second group of external connection terminals.

2. The semiconductor package according to claim 1, wherein the first semiconductor chip and the second semiconductor chip being mounted on the top surface of the first redistribution substrate in a first region of the semiconductor package, The vertical electrical connection structure is disposed on the top surface of the first redistribution substrate in the second region of the semiconductor package, and The second region is horizontally spaced apart from the first region.

3. The semiconductor package according to claim 2, further comprising: a heat radiation member attached to the top surface of the second redistribution substrate in the first region, The upper package is mounted on the top surface of the second redistribution substrate in the second region.

4. The semiconductor package according to claim 1, wherein The upper package is horizontally spaced apart from the second semiconductor chip.

5. The semiconductor package according to claim 4, wherein The upper package is horizontally spaced apart from the first semiconductor chip, or The upper package overlaps a portion of the first semiconductor chip and does not overlap another portion of the first semiconductor chip. The semiconductor package according to claim 1 , wherein: A vertical distance from the bottom surface of the first redistribution substrate to a bottom surface of the bridge chip is smaller than a vertical distance from the bottom surface of the first redistribution substrate to a lowermost end of the external connection terminal.

7. The semiconductor package according to claim 1, wherein At least one of the first semiconductor chip and the second semiconductor chip is a logic chip, and The upper package includes: upper package substrate; a memory chip mounted on the top surface of the upper package substrate; and An upper molding layer is disposed on the top surface of the upper package substrate and covers the top surface of the memory chip.

8. The semiconductor package according to claim 1, wherein The vertical electrical connection structure includes: a connection substrate disposed on the top surface of the first redistribution substrate, The first semiconductor chip and the second semiconductor chip are horizontally spaced apart from the connection substrate, and The mold layer fills a space between the connection substrate and the first and second semiconductor chips.

9. The semiconductor package according to claim 8, wherein The connection substrate has an opening penetrating the connection substrate, and the first semiconductor chip and the second semiconductor chip are provided in the opening, and In the opening, the mold layer fills the space between the connection substrate and the first and second semiconductor chips.

10. The semiconductor package according to claim 1, wherein The vertical electrical connection structure includes a conductive pillar horizontally spaced apart from the first semiconductor chip and the second semiconductor chip, the conductive pillar vertically penetrating the mold layer and connecting the first redistribution substrate to the second redistribution substrate.

11. The semiconductor package according to claim 1, wherein The bridge chip includes a capacitor element.

12. The semiconductor package according to claim 1, wherein The upper package is vertically spaced apart from the second redistribution substrate, and The upper package is mounted on the top surface of the second redistribution substrate with a plurality of intermediate connection terminals between the upper package and the second redistribution substrate.

13. A semiconductor package comprising: Lower package; as well as an upper package mounted on the lower package, Wherein, the lower package includes: a first redistribution substrate; a first logic chip and a second logic chip mounted on a top surface of the first redistribution substrate in a first region of the semiconductor package; a molding layer disposed on the top surface of the first redistribution substrate and surrounding the first logic chip and the second logic chip; a vertical electrical connection structure disposed on the top surface of the first redistribution substrate in a second region of the semiconductor package, the second region being horizontally spaced apart from the first region; and a bridge chip mounted on the bottom surface of the first redistribution substrate, Wherein, the upper package includes: upper package substrate; a memory chip mounted on the top surface of the upper package substrate; and an upper molding layer, disposed on the top surface of the upper package substrate and covering the top surface of the memory chip, Wherein, the upper package is arranged in the second area of ​​the semiconductor package.

14. The semiconductor package according to claim 13, wherein The lower package further includes: a second redistribution substrate disposed on the top surface of the mold layer and electrically connected to the vertical electrical connection structure, and The upper package is mounted on a top surface of the second redistribution substrate.

15. The semiconductor package according to claim 13, wherein The vertical electrical connection structure is exposed on the top surface of the molding layer, and The upper package is mounted on the vertical electrical connection structure through a plurality of intermediate connection terminals, which are provided on a bottom surface of the upper package substrate.

16. The semiconductor package according to claim 13, further comprising: a plurality of external connection terminals on the bottom surface of the first redistribution substrate, Wherein, the bridge chip is arranged between the first group of external connection terminals and the second group of external connection terminals.

17. The semiconductor package according to claim 13, further comprising: A heat radiation member is provided on a top surface of the lower package in the first region.

18. The semiconductor package according to claim 13, wherein The upper package is horizontally spaced apart from the first logic chip and the second logic chip.

19. The semiconductor package according to claim 13, wherein At least a portion of the upper package extends into the first region, The upper package is horizontally spaced apart from the first logic chip, and The upper package overlaps a portion of the second logic chip and does not overlap another portion of the second logic chip.

20. A semiconductor package comprising: a first redistribution substrate; a first semiconductor chip and a second semiconductor chip mounted on a top surface of the first redistribution substrate in a first region of the semiconductor package; a second redistribution substrate disposed above the first semiconductor chip and the second semiconductor chip; a vertical electrical connection structure disposed on the top surface of the first redistribution substrate in a second region of the semiconductor package and connecting the first redistribution substrate to the second redistribution substrate, the second region being horizontally spaced apart from the first region; an upper package mounted on a top surface of the second redistribution substrate in the second region; a heat radiation member attached to the top surface of the second redistribution substrate in the first region; a plurality of external connection terminals provided on the bottom surface of the first redistribution substrate; as well as A bridge chip is mounted on the bottom surface of the first redistribution substrate in the first region and is provided between the first group of external connection terminals and the second group of external connection terminals.

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